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# Verilog HDMI output IP. |
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This is a very simple HDMI output IP that is driven by a LCD IP. |
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Is accepting RGB 8 bit/color vertical and horizontal synchronization, data enable and a reference clock that is 5x the LCD clock. |
The outputs are the three serial channels the clock channel and the LCD clock that is equal to reference clock / 5. |
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The LCD clock provided by the HDMI IP is used to clocking the LCD IP. |
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The RGB and sinchronization signals are provided by an LCD IP. |
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The maximum obtained resolution is 1440x900 at less that 60 Hz, maximum 1 gigabit/second/line for Artix7 -1 grade device. |