URL
https://opencores.org/ocsvn/leros/leros/trunk
Subversion Repositories leros
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/leros/trunk/doc/design-blog.txt
0,0 → 1,22
Design Blog |
=========== |
|
A blog on the Leros implementation. Let's record how long it actually |
takes to get it running. The design has already been done (on a paper notebook) during a |
nice vacation in Greece in 2010. However, some details (most prominent the ISA definition) |
still needs to be flashed out. |
|
* 2011-02-20 2h: Start with the project setup. Trying to understand the library concept of VHDL, but gave up. Everything goes into work and the components are named leros_xxx to avoid name clashes. |
* 2011-02-20 4h: First VHDL files and setup Quartus to get an idea of fmax. Maximum clock frequency in a Cyclon 1 for a fully registered on-chip RAM is 255 MHz. Without output register and a small adder (ALU) towards the accu it is down to 148 MHz. Still a nice fmax ;-) |
* 2011-02-21 1.5h: Some decode, add ModelSim scripts plus test bench, load/add/sub immediate seems to work. Fmax is still at 145 MHz. LC count at 128. Can we do it below 3oo LC? |
* 2011-02-22 2.5h: Sketch the ISA (in a Bodega)- don't be too picky as 16 bit instructions for an accu machine as it has a lot of freedom in the ISA coding. Add more on the decoding. The LC count goes up to 142, but fmax is still at 145 MHz. |
* 2011-02-23 1h: Start with a conditional branch. |
* 2011-02-25 2h: Continue on conditional branch, add output port, adapt Makefile for the real FPGA compilation and download. The embedded "Hello World" - a blinking LED runs in the FPGA :-) (Just a little bit of cheating with the clock frequency as only simple 16 bit subtraction is supported). |
* 2011-03-04 2h: After a funding application writing break the next steps: start with an assembler (with a lot of copy from Jopa). Leros is now hosted on GitHub: https://github.com/schoeberl/leros |
* 2011-03-05 4h: Assembler knows most instructions and generates the ROM table. Instructions for load/store of variables added. Blinking LED now runs without frequency cheating. |
* 2011-03-07 2.5h: Optional work: add support for the Xilinx based Nexys2 board. |
* 2011-03-14 5h: Add Altera DE2-70 board, change instruction encoding. Add a minimalistic IO interface, shr instruction. |
* 2011-03-29 2h: Rewrite the assembler with a grammar for ANTLR. |
* 2011-05-29 2h: Add indirect load and store. |
* 2011-05-29 1.5h: Complete branches (unconditional and 4 conditional). |
* 2011-05-29 1h: Add jump and link instruction. Leros should now be complete and I stop counting the hours. |
leros/trunk/doc/design-blog.txt
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Index: leros/trunk/vhdl/.project
===================================================================
--- leros/trunk/vhdl/.project (revision 9)
+++ leros/trunk/vhdl/.project (revision 10)
@@ -10,8 +10,37 @@
+
+ org.eclipse.xtext.ui.shared.xtextBuilder
+
+
+
com.sigasi.hdt.core.hdlNature
+ com.sigasi.hdt.vhdl.ui.vhdlNature
+ org.eclipse.xtext.ui.shared.xtextNature
+
+
+ Common Libraries
+ 2
+ virtual:/virtual
+
+
+ Common Libraries/IEEE
+ 2
+ sigasiresource:/vhdl/93/IEEE
+
+
+ Common Libraries/IEEE Synopsys
+ 2
+ sigasiresource:/vhdl/93/IEEE%20Synopsys
+
+
+ Common Libraries/STD
+ 2
+ sigasiresource:/vhdl/93/STD
+
+