OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /light8080
    from Rev 81 to Rev 80
    ↔ Reverse comparison
  •

Rev 81 → Rev 80

/trunk/sw/demos/c2sb/c2sb_soc.vhdl.bak
0,0 → 1,318
--#############################################################################
-- Altair 4K Basic on DE-1 board demo
--#############################################################################
-- This is enough to run the Altair 4K Basic from internal FPGA RAM.
-- The output signals of the DE-1 board are unused except for a reset button,
-- a clock input and two seral pins (txd/rxd). it should be easy to port the
-- Altair Basic demo to any other FPGA starter kit.
--
-- The Altair Basic code is pre-loaded in an internal 4K RAM block. If the code
-- becomes corrupted, there's no way to restore it other than reloading the
-- FPGA -- a reset will not do.
--
-- Note there are a few unused registers here and there. They are remnants of
-- an unfinished CP/M-on-SD-card demo on which I based the Altair Basic demo.
-- You may just ignore them.
--#############################################################################
-- PORT ADDRESSES:
-- 00h : in status serial port
-- 01h : in/out data serial port
-- 23h : out HEX display, L (not used)
-- 24h : out HEX display, H (not used)
-- 40h : in switches (not used)
-- 40h : out green leds (not used)
--
-- Serial port status port:
-- 01h : '1' => serial port RX busy
-- 80h : '1' => serial port TX busy
--#############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use work.l80soc_pkg.all;
use work.obj_code_pkg.all;
 
-- Many of the board's i/o devices will go unused
entity c2sb_4kbasic_cpu is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
 
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
 
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
 
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
 
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
 
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
 
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
 
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end c2sb_4kbasic_cpu;
 
architecture minimal of c2sb_4kbasic_cpu is
 
--##############################################################################
-- light8080 SoC signals
 
signal data_in : std_logic_vector(7 downto 0);
signal vma : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal io : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal addr : std_logic_vector(15 downto 0);
signal inta : std_logic;
signal inte : std_logic;
signal intr : std_logic;
signal halt : std_logic;
 
-- signals for sram 'synchronization'
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg
signal sram_write : std_logic; -- sram we register
 
-- signals for debug
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus
 
signal rs_tx_data : std_logic_vector(7 downto 0);
 
--##############################################################################
-- General I/O control signals
 
signal io_q : std_logic;
signal rd_q : std_logic;
signal io_read : std_logic;
signal io_write : std_logic;
signal low_ram_we : std_logic;
 
--##############################################################################
-- RS232 signals
 
signal rx_rdy : std_logic;
signal tx_rdy : std_logic;
signal rs232_data_rx : std_logic_vector(7 downto 0);
signal rs232_status : std_logic_vector(7 downto 0);
signal data_io_out : std_logic_vector(7 downto 0);
signal io_port : std_logic_vector(7 downto 0);
signal read_rx : std_logic;
signal write_tx : std_logic;
 
 
--##############################################################################
-- Application signals
 
 
--##############################################################################
 
-- Quad 7-segment display (non multiplexed) & LEDS
signal display_data : std_logic_vector(15 downto 0);
 
-- i/o signals
signal p1in : std_logic_vector(7 downto 0);
signal p2out : std_logic_vector(7 downto 0);
 
-- Clock & reset signals
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal counter_1hz : std_logic_vector(25 downto 0);
signal reset : std_logic;
signal clk : std_logic;
 
-- SD control signals -- SD connector unused, unconnected
 
 
begin
 
mpu: entity work.l80soc
generic map (
OBJ_CODE => obj_code
)
port map (
clk => clk,
reset => reset,
rxd => rxd,
txd => txd,
extint => "0000",
p1in => p1in,
p2out => p2out
);
 
 
p1in <= X"12"; -- DUMMY
 
-- red leds (light with '1') -- some CPU control signals
red_leds <= (others => '0');
 
 
--##### Input ports ###########################################################
 
 
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD
--##############################################################################
 
--##############################################################################
-- FLASH (flash is unused in this demo)
--##############################################################################
 
flash_addr <= (others => '0');
 
flash_we_n <= '1'; -- all enable signals inactive
flash_oe_n <= '1';
flash_reset_n <= '1';
 
 
--##############################################################################
-- SRAM (used as 64K x 8)
--
-- NOTE: All writes go to SRAM independent of rom paging status
--##############################################################################
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
sram_addr <= "000000000000000000";
address_reg <= "0000000000000000";
sram_data_out <= X"00";
sram_write <= '0';
else
end if;
end if;
end process;
 
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out;
-- (the X"ZZ" will physically be the read input data)
 
-- sram access controlled by WE_N
sram_oe_n <= '0';
sram_ce_n <= '0';
sram_we_n <= not sram_write;
sram_ub_n <= '1'; -- always disable
sram_lb_n <= '0';
 
--##############################################################################
-- RESET, CLOCK
--##############################################################################
 
-- Use button 3 as reset
reset <= not buttons(3);
 
 
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
begin
if clk_50MHz'event and clk_50MHz='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if conv_integer(counter_1hz) = 50000000 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
 
-- Master clock is external 50MHz oscillator
clk <= clk_50MHz;
 
 
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
 
-- Display the contents of a debug register at the green leds bar
green_leds <= p2out;
 
 
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
 
display_data <= X"12AB";
 
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
with display_data(15 downto 12) select hex3 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
with display_data(11 downto 8) select hex2 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
with display_data(7 downto 4) select hex1 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
with display_data(3 downto 0) select hex0 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
--##############################################################################
-- SD card interface
--##############################################################################
 
-- SD card unused in this demo
sd_cs <= '0';
sd_cmd <= '0';
sd_clk <= '0';
sd_in <= '0';
 
 
--##############################################################################
-- SERIAL
--##############################################################################
 
-- UART is embedded in SoC entity, txd & rxd are connected straight to the SoC
 
end minimal;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.