URL
https://opencores.org/ocsvn/light8080/light8080/trunk
Subversion Repositories light8080
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- This comparison shows the changes necessary to convert path
/
- from Rev 66 to Rev 67
- ↔ Reverse comparison
Rev 66 → Rev 67
/light8080/trunk/tools/c80/c80.exe
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/light8080/trunk/tools/c80/c80.c
356,7 → 356,7
outname(cptr);col();nl(); |
// calculate number of bytes |
j = ((cptr[offset]&255) + ((cptr[offset+1]&255)<<8)); |
if ((cptr[type]==cint) | (cptr[ident]==pointer)) |
if ((cptr[type]==cint) | (cptr[ident]==pointer)) |
j=j+j; // 2 bytes for integer values |
// check if the global has an init value |
dptr = ((cptr[initptr]&255) + ((cptr[initptr+1]&255)<<8)); |
675,8 → 675,8
|
// save the values according to variable type |
if (typ==cint) { |
inittbq[inittbptr++] = (char)((num[0]>>16)&255); |
inittbq[inittbptr++] = (char)(num[0]&255); |
inittbq[inittbptr++] = (char)((num[0]>>8)&255); |
} |
else |
inittbq[inittbptr++] = (char)(num[0]&255); |
685,7 → 685,7
|
// init to end of array is more than one |
while (idx++ < k) { |
// fill the reset of the init list with zeros |
// fill the rest of the init list with zeros |
if (typ==cint) { |
inittbq[inittbptr++] = 0; |
inittbq[inittbptr++] = 0; |
2406,7 → 2406,7
} |
/* Swap the primary and secondary registers */ |
swap() |
{ ol("xchg"); |
{ ol("ex de,hl"); |
} |
/* Print partial instruction to get an immediate value */ |
/* into the primary register */ |
/light8080/trunk/c/hello.asm
778,16 → 778,12
;{ |
; // configure UART baud rate - set to 9600 for 30MHz clock |
; // BAUD = round(<clock>/<baud rate>/16) = round(30e6/9600/16) = 195 |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
;// UBAUDL = 195; |
; UBAUDL = 1; |
ld hl,1 |
; // Note: Usage of a minimum divider value of 1 will accelerate the RTL simulation. |
; UBAUDL = 195; |
ld hl,195 |
ld a,l |
out (129),a |
|
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
; UBAUDH = 0; |
ld hl,0 |
ld a,l |
823,7 → 819,6
; // enable CPU interrupt |
;#asm |
ei |
; |
; // print message |
; printstr("Hello World!!!"); nl(); |
ld hl,cc1+26 |
/light8080/trunk/c/HELLO.LST
74,7 → 74,7
|
63 labels used |
|
924 lines read, no errors in pass 1. |
919 lines read, no errors in pass 1. |
AS80 Assembler for i8080-Z180 [1.11]. Page 3 |
--------------------------------- HELLO.ASM ---------------------------------- |
|
894,16 → 894,12
;{ |
; // configure UART baud rate - set to 9600 for 30MHz |
; // BAUD = round(<clock>/<baud rate>/16) = round(30e6 |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT |
;// UBAUDL = 195; |
; UBAUDL = 1; |
0330 : 210100 ld hl,1 |
; // Note: Usage of a minimum divider value of 1 will |
; UBAUDL = 195; |
0330 : 21c300 ld hl,195 |
0333 : 7d ld a,l |
0334 : d381 out (129),a |
|
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT |
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT |
; UBAUDH = 0; |
0336 : 210000 ld hl,0 |
0339 : 7d ld a,l |
920,13 → 916,13
0345 : 7d ld a,l |
0346 : d385 out (133),a |
|
AS80 Assembler for i8080-Z180 [1.11]. Page 16 |
--------------------------------- HELLO.ASM ---------------------------------- |
|
; P2DATA = 0x00; |
0348 : 210000 ld hl,0 |
034b : 7d ld a,l |
034c : d386 out (134),a |
AS80 Assembler for i8080-Z180 [1.11]. Page 16 |
--------------------------------- HELLO.ASM ---------------------------------- |
|
|
; P2DIR = 0xff; |
034e : 21ff00 ld hl,255 |
942,7 → 938,6
; // enable CPU interrupt |
;#asm |
035a : fb ei |
; |
; // print message |
; printstr("Hello World!!!"); nl(); |
035b : 21ea03 ld hl,cc1+26 |
985,14 → 980,14
; // assert bit 0 of port 1 to test external interrupt |
; P1DATA = 0x01; |
03a0 : 210100 ld hl,1 |
AS80 Assembler for i8080-Z180 [1.11]. Page 17 |
--------------------------------- HELLO.ASM ---------------------------------- |
|
03a3 : 7d ld a,l |
03a4 : d384 out (132),a |
|
; |
; printstr("Echoing received bytes: "); nl(); |
AS80 Assembler for i8080-Z180 [1.11]. Page 17 |
--------------------------------- HELLO.ASM ---------------------------------- |
|
03a6 : 211304 ld hl,cc1+67 |
03a9 : e5 push hl |
03aa : cdc401 call __printstr |
/light8080/trunk/c/hello.c
132,12 → 132,8
{ |
// configure UART baud rate - set to 9600 for 30MHz clock |
// BAUD = round(<clock>/<baud rate>/16) = round(30e6/9600/16) = 195 |
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
// UBAUDL = 195; |
UBAUDL = 1; |
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI |
// Note: Usage of a minimum divider value of 1 will accelerate the RTL simulation. |
UBAUDL = 195; |
UBAUDH = 0; |
|
// configure both ports to output and digital outputs as zeros |
151,7 → 147,7
#asm |
ei |
#endasm |
|
|
// print message |
printstr("Hello World!!!"); nl(); |
printstr("Dec value: "); printdec(tstary[1]); nl(); |
/light8080/trunk/c/ram_image.v
224,7 → 224,7
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5; |
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1; |
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9; |
ram[816] = 8'h21; ram[817] = 8'h01; ram[818] = 8'h00; ram[819] = 8'h7d; |
ram[816] = 8'h21; ram[817] = 8'hc3; ram[818] = 8'h00; ram[819] = 8'h7d; |
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00; |
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82; |
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d; |
/light8080/trunk/c/HELLO.HEX
27,7 → 27,7
:2002C00021060039CD4800E521040039CD4800E5211000D1CDEE00D1CDDB00D1CD50002127 |
:2002E000000039CD4800E5210900D1CD77007CB5CA1003214100E521020039CD4800D119DC |
:20030000E5210A00D1CDDB00E5CD6C01C1C32203213000E521020039CD4800D119E5CD6CDD |
:2003200001C1C1C921D003E5CDC401C1CDB301C92101007DD3812100007DD3822100007D77 |
:2003200001C1C1C921D003E5CDC401C1CDB301C921C3007DD3812100007DD3822100007DB5 |
:20034000D38421FF007DD3852100007DD38621FF007DD3872101007DD388FB21EA03E5CDAE |
:20036000C401C1CDB30121F903E5CDC401C1212D04E521010029D119CD4800E5CDF501C137 |
:20038000CDB301210504E5CDC401C1212D04E521000029D119CD4800E5CD8A02C1CDB3017A |
/light8080/trunk/verilog/rtl/ram_image.v
224,7 → 224,7
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5; |
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1; |
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9; |
ram[816] = 8'h21; ram[817] = 8'h01; ram[818] = 8'h00; ram[819] = 8'h7d; |
ram[816] = 8'h21; ram[817] = 8'hc3; ram[818] = 8'h00; ram[819] = 8'h7d; |
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00; |
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82; |
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d; |