OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /light8080/trunk
    from Rev 84 to Rev 85
    ↔ Reverse comparison
  •

Rev 84 → Rev 85

/vhdl/demos/c2sb/c2sb_soc.vhdl
0,0 → 1,301
--##############################################################################
-- Light8080 SoC demo on DE-1 board
--##############################################################################
--
-- This is a minimal demo of the light8080 SoC targetting Terasic's DE-1
-- development board for Cyclone-2 FPGAs.
-- Since the demo uses little board resources other than the serial port it
-- should be easy to port it to other platforms.
-- This file is strictly for demonstration purposes and has not been tested
--
-- The SoC contains a block of RAM that is used for both program and data. The
-- BRAM is initialized at synthesis time with a constant taken from package
-- 'obj_code_pkg'. This package can be built from an object code file in Intel
-- HEX format with utility '/tools/obj2hdl' included with the project.
--
-- This demo has been built from a generic template for designs targetting the
-- DE-1 development board. The entity defines all the inputs and outputs present
-- in the actual board, whether or not they are used in the design at hand.
--##############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Package with utility functions for handling SoC object code.
use work.l80pkg.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
 
 
-- Define the entity outputs as they are connected in the DE-1 development
-- board. Many of the outputs will be left unused in this demo.
entity c2sb_soc is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
 
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
 
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
 
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
 
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
 
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
 
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
 
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end c2sb_soc;
 
architecture minimal of c2sb_soc is
 
--##############################################################################
-- Some of these signals are
 
-- light8080 SoC signals -------------------------------------------------------
signal p1in : std_logic_vector(7 downto 0);
signal p2out : std_logic_vector(7 downto 0);
signal uart_txd : std_logic;
signal uart_rxd : std_logic;
 
-- Signals for external SRAM synchronization -----------------------------------
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg
signal sram_write : std_logic; -- sram we register
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus
 
 
--##############################################################################
-- On-board device interface signals
 
-- Quad 7-segment display (non multiplexed) & LEDS -----------------------------
signal display_data : std_logic_vector(15 downto 0);
 
 
-- Clock & reset signals -------------------------------------------------------
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal reset : std_logic;
signal clk : std_logic;
signal counter_1hz : std_logic_vector(25 downto 0);
 
-- SD control signals ----------------------------------------------------------
-- SD connector unused, unconnected
 
 
--## Functions #################################################################
 
-- Converts hex nibble to 7-segment (sinthesizable).
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nibble is
when X"0" => return "0000001";
when X"1" => return "1001111";
when X"2" => return "0010010";
when X"3" => return "0000110";
when X"4" => return "1001100";
when X"5" => return "0100100";
when X"6" => return "0100000";
when X"7" => return "0001111";
when X"8" => return "0000000";
when X"9" => return "0000100";
when X"a" => return "0001000";
when X"b" => return "1100000";
when X"c" => return "0110001";
when X"d" => return "1000010";
when X"e" => return "0110000";
when X"f" => return "0111000";
when others => return "0111111"; -- can't happen
end case;
end function nibble_to_7seg;
 
begin
 
-- SOC instantiation
mpu: entity work.l80soc
generic map (
OBJ_CODE => work.obj_code_pkg.obj_code,
UART_HARDWIRED => false, -- UART baud rate is programmable in run time
UART_IRQ_LINE => 3 -- UART uses IRQ3 line of irq controller
)
port map (
clk => clk,
reset => reset,
rxd => uart_rxd,
txd => uart_txd,
extint => "0000", -- No external interrupts
p1in => p1in,
p2out => p2out
);
 
-- Input port connected to switches for lack of better use
p1in <= switches(7 downto 0);
 
 
--##### Input ports ###########################################################
 
 
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD
--##############################################################################
 
--##############################################################################
-- FLASH (flash is unused in this demo)
--##############################################################################
 
flash_addr <= (others => '0');
 
flash_we_n <= '1'; -- all enable signals inactive
flash_oe_n <= '1';
flash_reset_n <= '1';
 
 
--##############################################################################
-- SRAM (wired as 64K x 8)
-- The SRAM is unused in this demo.
--##############################################################################
 
-- These registera make the external, asynchronous SRAM behave like an
-- internal syncronous BRAM, except for the timing.
-- Since the SoC has no wait state capability, the SoC clock rate must
-- accomodate the SRAM timing -- including FPGA clock-to-output, RAM delays
-- and FPGA input setup and hold times. Setting up the synthesis constraints
-- is left to the user too.
sram_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
sram_addr <= "000000000000000000";
address_reg <= "0000000000000000";
sram_data_out <= X"00";
sram_write <= '0';
else
end if;
end if;
end process sram_registers;
 
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out;
-- (the X"ZZ" will physically be the read input data)
 
-- sram access controlled by WE_N
sram_oe_n <= '0';
sram_ce_n <= '0';
sram_we_n <= not sram_write;
sram_ub_n <= '1'; -- always disable
sram_lb_n <= '0';
 
--##############################################################################
-- RESET, CLOCK
--##############################################################################
 
-- Use button 0 as reset
reset <= not buttons(0);
 
 
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
begin
if clk_50MHz'event and clk_50MHz='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if conv_integer(counter_1hz) = 50000000 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
 
-- Master clock is external 50MHz oscillator
clk <= clk_50MHz;
 
 
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
 
-- Display the contents of an output port at the green leds bar
green_leds <= p2out;
 
-- Red leds unused except for 1-Hz clock
red_leds(9 downto 1) <= (others => '0');
red_leds(0) <= clk_1hz;
 
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
 
-- Display the contents of the output port at the hex displays.
display_data <= p2out & p1in;
 
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
hex3 <= nibble_to_7seg(display_data(15 downto 12));
hex2 <= nibble_to_7seg(display_data(11 downto 8));
hex1 <= nibble_to_7seg(display_data( 7 downto 4));
hex0 <= nibble_to_7seg(display_data( 3 downto 0));
 
--##############################################################################
-- SD card interface
--##############################################################################
 
-- SD card unused in this demo
sd_cs <= '0';
sd_cmd <= '0';
sd_clk <= '0';
--sd_in <= '0';
 
 
--##############################################################################
-- SERIAL
--##############################################################################
 
-- Txd & rxd connected straight to the SoC
txd <= uart_txd;
uart_rxd <= rxd;
end minimal;
/vhdl/demos/c2sb/readme.txt
0,0 → 1,6
 
The vhdl files in this directory are common to all the demos that run on the
DE-1 board from Terasic, and use the vhdl SoC.
 
An assignment file with all the pin definitions for the DE-1 board is included
(cs2b_pins.csv) than can be imported from Altera's Quartus 2.
/vhdl/demos/c2sb/c2sb_pins.csv
0,0 → 1,160
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
# Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# File: C:\altera\Kits\CycloneII_Starter_Kit-v1.0.0\proyectos\demo_tutorial\pin_assignment\c2sb_demo.csv
# Generated on: Sun Jul 19 05:05:49 2009
 
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.
 
To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Group,Current Strength,PCB layer
buttons[3],Input,PIN_T21,6,B6_N0,,,buttons[3..0],,
buttons[2],Input,PIN_T22,6,B6_N0,,,buttons[3..0],,
buttons[1],Input,PIN_R21,6,B6_N0,,,buttons[3..0],,
buttons[0],Input,PIN_R22,6,B6_N0,,,buttons[3..0],,
flash_addr[21],Output,PIN_R13,7,B7_N0,,,flash_addr[21..0],,
flash_addr[20],Output,PIN_U13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[19],Output,PIN_V14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[18],Output,PIN_U14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[17],Output,PIN_AA20,7,B7_N0,,,flash_addr[21..0],,
flash_addr[16],Output,PIN_AB12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[15],Output,PIN_AA12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[14],Output,PIN_AB13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[13],Output,PIN_AA13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[12],Output,PIN_AB14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[11],Output,PIN_T12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[10],Output,PIN_R12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[9],Output,PIN_Y13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[8],Output,PIN_R14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[7],Output,PIN_W15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[6],Output,PIN_V15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[5],Output,PIN_U15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[4],Output,PIN_T15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[3],Output,PIN_R15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[2],Output,PIN_Y16,7,B7_N0,,,flash_addr[21..0],,
flash_addr[1],Output,PIN_AA14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[0],Output,PIN_AB20,7,B7_N0,,,flash_addr[21..0],,
flash_data[7],Input,PIN_AA19,7,B7_N0,,,flash_data[7..0],,
flash_data[6],Input,PIN_AB19,7,B7_N0,,,flash_data[7..0],,
flash_data[5],Input,PIN_AA18,7,B7_N0,,,flash_data[7..0],,
flash_data[4],Input,PIN_AB18,7,B7_N0,,,flash_data[7..0],,
flash_data[3],Input,PIN_AA17,7,B7_N1,,,flash_data[7..0],,
flash_data[2],Input,PIN_AB17,7,B7_N1,,,flash_data[7..0],,
flash_data[1],Input,PIN_AA16,7,B7_N1,,,flash_data[7..0],,
flash_data[0],Input,PIN_AB16,7,B7_N1,,,flash_data[7..0],,
flash_oe_n,Output,PIN_AA15,7,B7_N1,,,,,
flash_reset_n,Output,PIN_W14,7,B7_N1,,,,,
flash_we_n,Output,PIN_Y14,7,B7_N0,,,,,
green_leds[7],Output,PIN_Y21,6,B6_N1,,,green_leds[7..0],,
green_leds[6],Output,PIN_Y22,6,B6_N1,,,green_leds[7..0],,
green_leds[5],Output,PIN_W21,6,B6_N1,,,green_leds[7..0],,
green_leds[4],Output,PIN_W22,6,B6_N1,,,green_leds[7..0],,
green_leds[3],Output,PIN_V21,6,B6_N1,,,green_leds[7..0],,
green_leds[2],Output,PIN_V22,6,B6_N1,,,green_leds[7..0],,
green_leds[1],Output,PIN_U21,6,B6_N1,,,green_leds[7..0],,
green_leds[0],Output,PIN_U22,6,B6_N1,,,green_leds[7..0],,
hex0[0],Output,PIN_J2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[1],Output,PIN_J1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[2],Output,PIN_H2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[3],Output,PIN_H1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[4],Output,PIN_F2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[5],Output,PIN_F1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[6],Output,PIN_E2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex1[0],Output,PIN_E1,2,B2_N1,3.3-V LVTTL,,hex1[0..6],,
hex1[1],Output,PIN_H6,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[2],Output,PIN_H5,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[3],Output,PIN_H4,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[4],Output,PIN_G3,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[5],Output,PIN_D2,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[6],Output,PIN_D1,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex2[0],Output,PIN_G5,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[1],Output,PIN_G6,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[2],Output,PIN_C2,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[3],Output,PIN_C1,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[4],Output,PIN_E3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[5],Output,PIN_E4,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[6],Output,PIN_D3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex3[0],Output,PIN_F4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[1],Output,PIN_D5,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[2],Output,PIN_D6,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[3],Output,PIN_J4,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[4],Output,PIN_L8,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[5],Output,PIN_F3,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[6],Output,PIN_D4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
red_leds[9],Output,PIN_R17,6,B6_N1,,,red_leds[9..0],,
red_leds[8],Output,PIN_R18,6,B6_N0,,,red_leds[9..0],,
red_leds[7],Output,PIN_U18,6,B6_N1,,,red_leds[9..0],,
red_leds[6],Output,PIN_Y18,6,B6_N1,,,red_leds[9..0],,
red_leds[5],Output,PIN_V19,6,B6_N1,,,red_leds[9..0],,
red_leds[4],Output,PIN_T18,6,B6_N1,,,red_leds[9..0],,
red_leds[3],Output,PIN_Y19,6,B6_N1,,,red_leds[9..0],,
red_leds[2],Output,PIN_U19,6,B6_N1,,,red_leds[9..0],,
red_leds[1],Output,PIN_R19,6,B6_N0,,,red_leds[9..0],,
red_leds[0],Output,PIN_R20,6,B6_N0,,,red_leds[9..0],,
rxd,Input,PIN_F14,4,B4_N1,,,,,
sd_clk,Output,PIN_V20,6,B6_N1,,,,,
sd_cmd,Output,PIN_Y20,6,B6_N1,,,,,
sd_cs,Output,PIN_U20,6,B6_N1,,,,,
sd_data,Input,PIN_W20,6,B6_N1,,,,,
sram_addr[17],Output,PIN_Y5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[16],Output,PIN_Y6,8,B8_N1,,,sram_addr[17..0],,
sram_addr[15],Output,PIN_T7,8,B8_N1,,,sram_addr[17..0],,
sram_addr[14],Output,PIN_R10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[13],Output,PIN_U10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[12],Output,PIN_Y10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[11],Output,PIN_T11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[10],Output,PIN_R11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[9],Output,PIN_W11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[8],Output,PIN_V11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[7],Output,PIN_AB11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[6],Output,PIN_AA11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[5],Output,PIN_AB10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[4],Output,PIN_AA5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[3],Output,PIN_AB4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[2],Output,PIN_AA4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[1],Output,PIN_AB3,8,B8_N1,,,sram_addr[17..0],,
sram_addr[0],Output,PIN_AA3,8,B8_N1,,,sram_addr[17..0],,
sram_ce_n,Output,PIN_AB5,8,B8_N1,,,,,
sram_data[15],Bidir,PIN_U8,8,B8_N1,,,sram_data[15..0],,
sram_data[14],Bidir,PIN_V8,8,B8_N1,,,sram_data[15..0],,
sram_data[13],Bidir,PIN_W8,8,B8_N1,,,sram_data[15..0],,
sram_data[12],Bidir,PIN_R9,8,B8_N0,,,sram_data[15..0],,
sram_data[11],Bidir,PIN_U9,8,B8_N0,,,sram_data[15..0],,
sram_data[10],Bidir,PIN_V9,8,B8_N1,,,sram_data[15..0],,
sram_data[9],Bidir,PIN_W9,8,B8_N0,,,sram_data[15..0],,
sram_data[8],Bidir,PIN_Y9,8,B8_N0,,,sram_data[15..0],,
sram_data[7],Bidir,PIN_AB9,8,B8_N0,,,sram_data[15..0],,
sram_data[6],Bidir,PIN_AA9,8,B8_N0,,,sram_data[15..0],,
sram_data[5],Bidir,PIN_AB8,8,B8_N0,,,sram_data[15..0],,
sram_data[4],Bidir,PIN_AA8,8,B8_N0,,,sram_data[15..0],,
sram_data[3],Bidir,PIN_AB7,8,B8_N1,,,sram_data[15..0],,
sram_data[2],Bidir,PIN_AA7,8,B8_N1,,,sram_data[15..0],,
sram_data[1],Bidir,PIN_AB6,8,B8_N1,,,sram_data[15..0],,
sram_data[0],Bidir,PIN_AA6,8,B8_N1,,,sram_data[15..0],,
sram_lb_n,Output,PIN_Y7,8,B8_N1,,,,,
sram_oe_n,Output,PIN_T8,8,B8_N1,,,,,
sram_ub_n,Output,PIN_W7,8,B8_N1,,,,,
sram_we_n,Output,PIN_AA10,8,B8_N0,,,,,
switches[9],Input,PIN_L2,2,B2_N1,,,switches[9..0],,
switches[8],Input,PIN_M1,1,B1_N0,,,switches[9..0],,
switches[7],Input,PIN_M2,1,B1_N0,,,switches[9..0],,
switches[6],Input,PIN_U11,8,B8_N0,,,switches[9..0],,
switches[5],Input,PIN_U12,8,B8_N0,,,switches[9..0],,
switches[4],Input,PIN_W12,7,B7_N1,,,switches[9..0],,
switches[3],Input,PIN_V12,7,B7_N1,,,switches[9..0],,
switches[2],Input,PIN_M22,6,B6_N0,,,switches[9..0],,
switches[1],Input,PIN_L21,5,B5_N1,,,switches[9..0],,
switches[0],Input,PIN_L22,5,B5_N1,,,switches[9..0],,
txd,Output,PIN_G12,4,B4_N1,,,,,
clk_50MHz,Unknown,PIN_L1,2,B2_N1,,,,,
/vhdl/demos/c2sb/c2sb_soc_tb.vhdl
0,0 → 1,93
--------------------------------------------------------------------------------
-- c2sb_soc_tb.vhdl -- Minimal test bench for c2sb_soc.
--
-- c2sb_soc is a light8080 SoC demo on a Cyclone 2 starter Board (C2SB). This
-- is a minimalistic simulation test bench. The test bench only drives the clock
-- and reset inputs.
--
-- This simulation test bench can be marginally useful for basic troubleshooting
-- of a C2SB board demo or as a starting point for a true test bench.
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
 
entity c2sb_soc_tb is
end entity c2sb_soc_tb;
 
architecture behavior of c2sb_soc_tb is
 
--------------------------------------------------------------------------------
-- Simulation parameters
 
-- T: simulated clock period
constant T : time := 100 ns;
 
-- MAX_SIM_LENGTH: maximum simulation time
constant MAX_SIM_LENGTH : time := T*7000000; -- enough for most purposes
 
 
--------------------------------------------------------------------------------
 
signal clk : std_logic := '0';
signal done : std_logic := '0';
signal buttons : std_logic_vector(3 downto 0);
signal green_leds : std_logic_vector(7 downto 0);
signal txd : std_logic;
 
begin
 
-- Instantiate the Unit Under Test (UUT)
-- The only mandatory signals are clk and buttons(3)
uut: entity work.c2sb_soc
port map (
clk_50MHz => clk,
buttons => buttons,
rxd => txd,
txd => txd,
flash_data => (others => '0'),
switches => (others => '0'),
sd_data => '0',
green_leds => green_leds
);
 
 
-- clock: run clock until test is done
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
 
 
-- Drive reset and done
main_test:
process
begin
-- Assert reset for at least one full clk period
buttons(0) <= '0';
wait until clk = '1';
wait for T/2;
buttons(0) <= '1';
 
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
 
-- Maximum sim time elapsed, stop the clk process asserting 'done' (which
-- will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
end process main_test;
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.