URL
https://opencores.org/ocsvn/light8080/light8080/trunk
Subversion Repositories light8080
Compare Revisions
- This comparison shows the changes necessary to convert path
/light8080/trunk
- from Rev 89 to Rev 90
- ↔ Reverse comparison
Rev 89 → Rev 90
/tools/c80/c80.exe
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/tools/c80/c80.c
1631,7 → 1631,7
|
q = n/10; |
if(q) outint(q); |
outbyte('0'-(n-q*10)); |
outbyte('0'+(n-q*10)); |
/* end outint */} |
|
/* return the length of a string */ |
/verilog/syn/xilinx_s3/xilinx_s3.xise
45,6 → 45,8
</files> |
|
<properties> |
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
51,6 → 53,7
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
64,8 → 67,8
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
80,6 → 83,7
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
86,30 → 90,46
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
120,6 → 140,8
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
138,6 → 160,7
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
159,6 → 182,8
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="Verilog" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
170,24 → 195,34
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/> |
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> |
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
208,13 → 243,16
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="l80soc_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="l80soc_timesim.v" xil_pn:valueState="default"/> |
221,7 → 259,9
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="l80soc_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="l80soc_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
232,10 → 272,13
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
253,6 → 296,7
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
266,7 → 310,10
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
281,8 → 328,9
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
295,7 → 343,7
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
308,20 → 356,25
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
330,7 → 383,7
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="xilinx_s3" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
/verilog/syn/xilinx_s3/l80soc_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>l80soc Project Status (04/28/2012 - 12:00:22)</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>l80soc Project Status (04/29/2012 - 17:48:33)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>xilinx_s3.xise</TD> |
17,7 → 17,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc3s200-4ft256</TD> |
<TD>xc6slx9-3tqg144</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
25,7 → 25,7
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs?&DataKey=Warning'>16 Warnings (7 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
57,82 → 57,334
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD> |
<TD ALIGN=RIGHT>237</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>6%</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>229</TD> |
<TD ALIGN=RIGHT>11,440</TD> |
<TD ALIGN=RIGHT>2%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> |
<TD ALIGN=RIGHT>384</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>10%</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
<TD ALIGN=RIGHT>229</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
<TD ALIGN=RIGHT>255</TD> |
<TD ALIGN=RIGHT>1,920</TD> |
<TD ALIGN=RIGHT>13%</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> |
<TD ALIGN=RIGHT>255</TD> |
<TD ALIGN=RIGHT>255</TD> |
<TD ALIGN=RIGHT>100%</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>255</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD> |
<TD ALIGN=RIGHT>385</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>10%</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>278</TD> |
<TD ALIGN=RIGHT>5,720</TD> |
<TD ALIGN=RIGHT>4%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
<TD ALIGN=RIGHT>368</TD> |
<TD ALIGN=RIGHT>269</TD> |
<TD ALIGN=RIGHT>5,720</TD> |
<TD ALIGN=RIGHT>4%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>220</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>49</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>1,440</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used for Dual Port RAMs</TD> |
<TD ALIGN=RIGHT>16</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
<TD ALIGN=RIGHT>106</TD> |
<TD ALIGN=RIGHT>1,430</TD> |
<TD ALIGN=RIGHT>7%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Nummber of MUXCYs used</TD> |
<TD ALIGN=RIGHT>36</TD> |
<TD ALIGN=RIGHT>2,860</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> |
<TD ALIGN=RIGHT>336</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> |
<TD ALIGN=RIGHT>122</TD> |
<TD ALIGN=RIGHT>336</TD> |
<TD ALIGN=RIGHT>36%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> |
<TD ALIGN=RIGHT>58</TD> |
<TD ALIGN=RIGHT>336</TD> |
<TD ALIGN=RIGHT>17%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>156</TD> |
<TD ALIGN=RIGHT>336</TD> |
<TD ALIGN=RIGHT>46%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> |
<TD ALIGN=RIGHT>24</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> |
<TD ALIGN=RIGHT>39</TD> |
<TD ALIGN=RIGHT>11,440</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TD ALIGN=RIGHT>24</TD> |
<TD ALIGN=RIGHT>173</TD> |
<TD ALIGN=RIGHT>13%</TD> |
<TD ALIGN=RIGHT>102</TD> |
<TD ALIGN=RIGHT>23%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> |
<TD ALIGN=RIGHT>3</TD> |
<TD ALIGN=RIGHT>12</TD> |
<TD ALIGN=RIGHT>25%</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>9%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>64</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>16</TD> |
<TD ALIGN=RIGHT>6%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>200</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>200</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>200</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>128</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>12%</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>16</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
<TD ALIGN=RIGHT>3.39</TD> |
<TD ALIGN=RIGHT>3.73</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
169,12 → 421,12
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Info'>7 Infos (1 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 12:00:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:46:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (10 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:46:39 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:47:37 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (6 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:48:11 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/par.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 12:00:18 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:48:31 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
183,5 → 435,5
</TABLE> |
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<br><center><b>Date Generated:</b> 04/28/2012 - 12:00:22</center> |
<br><center><b>Date Generated:</b> 04/29/2012 - 17:48:33</center> |
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