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/trunk/tools/ihex2vlog/ihex2vlog.exe
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trunk/tools/ihex2vlog/ihex2vlog.exe
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Index: trunk/tools/ihex2vlog/ihex2vlog.c
===================================================================
--- trunk/tools/ihex2vlog/ihex2vlog.c (nonexistent)
+++ trunk/tools/ihex2vlog/ihex2vlog.c (revision 65)
@@ -0,0 +1,286 @@
+//---------------------------------------------------------------------------------------
+//
+// ihex2vlog.c by Moti Litochevski, Nov 12, 2011
+// This program reads an Intel HEX file and generates memory Verilog module or
+// Xilinx RAMB16/RAMB4 verilog initialization vectors.
+//
+// This program uses the ihex.c functions by Paul Stoffregen.
+//
+// The project was compiled using the Tiny C Compiler using the following command line:
+// tcc ihex2vlog.c ihex.c
+//
+//---------------------------------------------------------------------------------------
+//
+// This file is released to the public domain under the BSD 2-clause license.
+//
+// Copyright (c) 2012, Moti Litochevski
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification, are
+// permitted provided that the following conditions are met:
+// o Redistributions of source code must retain the above copyright notice, this list
+// of conditions and the following disclaimer.
+// o Redistributions in binary form must reproduce the above copyright notice, this
+// list of conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+// IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+// INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//---------------------------------------------------------------------------------------
+
+#include
+#include
+#include
+
+// constants
+#define MAX_BUF_SIZE 65536
+
+/* this loads an intel hex file into the memory[] array */
+int load_file(char *filename);
+
+// the loaded memory is stored in a global variable with maximum size of 64K bytes
+int memory[MAX_BUF_SIZE];
+
+// Xilinx RAMB16 default parameters
+// total size of RAM memory block in bytes
+#define RAM_BLOCK_SIZE 2048
+// maxmimum number of memory blocks - each memory block contains RAM_BLOCK_SIZE bytes
+#define RAM_BLOCKS 8
+// number of rows in RAM block initialization vectors
+#define RAM_ROWS 64
+// number of bytes per row in RAM block initialization vectors
+#define RAM_BYTEPERROW 32
+// Xilinx RAMB4 parameters
+#define RAMB4_BLOCK_SIZE 512
+#define RAMB4_BLOCKS 32
+#define RAMB4_ROWS 16
+#define RAMB4_BYTEPERROW 32
+
+//------------------------------------------------------------------------------
+int main (int argc, char *argv[])
+{
+FILE *file;
+int index, hex_len, block_num, iblock, irow;
+int address, value, argi;
+int block_size, blocks_num, raws_num, bytes_num;
+char *argstr, modname[24];
+
+ // init block size to zero to sign generic Verilog code
+ block_size = 0;
+ // default address width
+ raws_num = 16;
+ bytes_num = 0;
+ // set default module name
+ strcpy(modname, "ram_image");
+
+ // announce program start
+ printf("ihex2vlog conversion tool:\n");
+
+ // check program usage
+ if (argc < 3) {
+ printf("\n");
+ printf("ERROR: incorrect usage of program.\n");
+ printf("\n");
+ printf("Usage: ihex2vlog [-a/s/m/4/16] \n");
+ printf("optional parameters:\n");
+ printf(" -a generate initialization vectors for generic Verilog\n");
+ printf(" code with specified address bus width. value should be\n");
+ printf(" in the range 8 to 16.\n");
+ printf(" this is the default option with width = 16\n");
+ printf(" -s set size of generic verilog memory size.\n");
+ printf(" value should be in the range 256 to 65536.\n");
+ printf(" default value is 2** (address width defined above).\n");
+ printf(" -m set module name for generic verilog memory.\n");
+ printf(" default value is \"ram_image\".\n");
+ printf(" -4 generate initialization vectors for Xilinx RAMB4.\n");
+ printf(" -16 generate initialization vectors for Xilinx RAMB16.\n");
+ printf("\n");
+ printf("Example: ihex2vlog test.ihx ram_image.v\n");
+ return -1;
+ }
+
+ // clear the memory array
+ for (index = 0; index < MAX_BUF_SIZE; index++) {
+ memory[index] = 0;
+ }
+
+ // check optional options
+ argi = 1;
+ argstr = argv[argi];
+ while (argstr[0]=='-') {
+ // check Xilinx RAMB4 option
+ if (argstr[1] == '4') {
+ // init block definition values for Xilinx RAMB4 block size
+ block_size = RAMB4_BLOCK_SIZE;
+ blocks_num = RAMB4_BLOCKS;
+ raws_num = RAMB4_ROWS;
+ bytes_num = RAMB4_BYTEPERROW;
+ }
+ else if ((argstr[1] == '1') & (argstr[2] == '6')) {
+ // init block definition values for Xilinx RAMB16 block size
+ block_size = RAM_BLOCK_SIZE;
+ blocks_num = RAM_BLOCKS;
+ raws_num = RAM_ROWS;
+ bytes_num = RAM_BYTEPERROW;
+ }
+ else if (argstr[1] == 'a') {
+ // for generic infered RAM Verilog code this option specifies the
+ // address bus width
+ sscanf(&argstr[2], "%d", &raws_num);
+ if ((raws_num < 8) | (raws_num > 16)) {
+ printf("\nERROR: Address width value error (%d)\n\n", raws_num);
+ return -1;
+ }
+ //check if memory length should be calculated
+ if (bytes_num == 0) {
+ // calculate the actual memory size
+ bytes_num=1;
+ for (index=0; index MAX_BUF_SIZE)) {
+ printf("\nERROR: Memory size value error (%d)\n\n", bytes_num);
+ return -1;
+ }
+ }
+ else if (argstr[1] == 'm') {
+ // set generic verilog memory module name
+ strcpy(modname, &argstr[2]);
+ }
+ else
+ printf("\nERROR: Unsupported option \"%s\"\n\n", argstr);
+ // update parameter index
+ argi++;
+ argstr = argv[argi];
+ }
+
+ // read input hex file into the memory array
+ hex_len = load_file(argv[argi]);
+ printf("HEX memory top address %d\n", hex_len);
+ // check if file loaded OK
+ if (hex_len < 1) {
+ printf("ERROR: Can't read '%s'!\n", argv[argi]);
+ return -1;
+ }
+
+ // announce output file name
+ printf("Writing output file to: %s\n", argv[argi+1]);
+ // open output file
+ file = fopen(argv[argi+1], "wt");
+ if (file == NULL) {
+ printf("ERROR: Can't write '%s'!\n", argv[argi+1]);
+ return -1;
+ }
+
+ // check if Xilinx RAMB memory is used or generic verilog RAM
+ if (block_size) {
+ // calculate the number of required RAM blocks
+ block_num = hex_len / block_size;
+ printf("HEX file requires %d RAM blocks\n", block_num+1);
+
+ // write file header
+ fprintf(file, "// RAM image for input code file: %s\n", argv[argi]);
+ // write memory block defines to enable only required memory blocks
+ fprintf(file, "// enable memory blocks \n");
+ fprintf(file, "`ifdef EN_ALL_BLOCKS\n");
+ for (iblock = 0; iblock < blocks_num; iblock++) {
+ fprintf(file, "`define EN_BLOCK%d 1 \n", iblock);
+ }
+ fprintf(file, "`else\n");
+ // write the memory block enable flags
+ for (iblock = 0; iblock < block_num+1; iblock++) {
+ fprintf(file, "`define EN_BLOCK%d 1 \n", iblock);
+ }
+ fprintf(file, "`endif\n");
+ fprintf(file, "\n");
+
+ // write memory blocks
+ for (iblock = 0; iblock <= block_num; iblock++) {
+ // write memory block header
+ fprintf(file, "// block %d \n", iblock);
+
+ // loop though block rows
+ for (irow = 0; irow < raws_num; irow++) {
+ // write start of line
+ fprintf(file, "defparam mem%d.INIT_%X%X = 256'h", iblock, irow/16, irow & 0xf);
+
+ // write memory bytes
+ for (index = 0; index < bytes_num; index++) {
+ address = iblock*block_size + irow*bytes_num + bytes_num - index - 1;
+
+ if (address < hex_len)
+ value = memory[address] & 0xff;
+ else
+ value = 0;
+
+ fprintf(file, "%x%x", value/16, value & 0xf);
+ }
+ fprintf(file, ";\n");
+ }
+ }
+ }
+ else {
+ // generate generic Verilog RAM code
+ printf("Generate generic Verilog RAM code.\n");
+
+ // write output file header
+ fprintf(file, "//-----------------------------------------------------------------------------\n");
+ fprintf(file, "//\n");
+ fprintf(file, "// RAM image for input code file: %s\n", argv[argi]);
+ fprintf(file, "//\n");
+ fprintf(file, "//-----------------------------------------------------------------------------\n");
+ fprintf(file, "module %s\n", modname);
+ fprintf(file, "(\n");
+ fprintf(file, " clk, addr, \n");
+ fprintf(file, " we, din, dout\n");
+ fprintf(file, ");\n");
+ fprintf(file, "//-----------------------------------------------------------------------------\n");
+ fprintf(file, "input clk;\n");
+ fprintf(file, "input [%d:0] addr;\n", raws_num-1);
+ fprintf(file, "input we;\n");
+ fprintf(file, "input [7:0] din;\n");
+ fprintf(file, "output [7:0] dout;\n");
+ fprintf(file, "//-----------------------------------------------------------------------------\n");
+ fprintf(file, "reg [7:0] dout;\n");
+ fprintf(file, "reg [7:0] ram [%d:0];\n", bytes_num-1);
+ fprintf(file, "//-----------------------------------------------------------------------------\n");
+ fprintf(file, "initial \n");
+ fprintf(file, "begin\n");
+ // dump memory values as RAM init values
+ for (index=0; index
+
+/* some ansi prototypes.. maybe ought to make a .h file */
+
+/* this loads an intel hex file into the memory[] array */
+int load_file(char *filename);
+
+/* this writes a part of memory[] to an intel hex file */
+void save_file(char *command);
+
+/* this is used by load_file to get each line of intex hex */
+int parse_hex_line(char *theline, int bytes[], int *addr, int *num, int *code);
+
+/* this does the dirty work of writing an intel hex file */
+/* caution, static buffering is used, so it is necessary */
+/* to call it with end=1 when finsihed to flush the buffer */
+/* and close the file */
+void hexout(FILE *fhex, int byte, int memory_location, int end);
+
+extern int memory[65536]; /* the memory is global */
+
+/* parses a line of intel hex code, stores the data in bytes[] */
+/* and the beginning address in addr, and returns a 1 if the */
+/* line was valid, or a 0 if an error occured. The variable */
+/* num gets the number of bytes that were stored into bytes[] */
+
+int parse_hex_line(theline, bytes, addr, num, code)
+char *theline;
+int *addr, *num, *code, bytes[];
+{
+ int sum, len, cksum;
+ char *ptr;
+
+ *num = 0;
+ if (theline[0] != ':') return 0;
+ if (strlen(theline) < 11) return 0;
+ ptr = theline+1;
+ if (!sscanf(ptr, "%02x", &len)) return 0;
+ ptr += 2;
+ if ( strlen(theline) < (11 + (len * 2)) ) return 0;
+ if (!sscanf(ptr, "%04x", addr)) return 0;
+ ptr += 4;
+ /* printf("Line: length=%d Addr=%d\n", len, *addr); */
+ if (!sscanf(ptr, "%02x", code)) return 0;
+ ptr += 2;
+ sum = (len & 255) + ((*addr >> 8) & 255) + (*addr & 255) + (*code & 255);
+ while(*num != len) {
+ if (!sscanf(ptr, "%02x", &bytes[*num])) return 0;
+ ptr += 2;
+ sum += bytes[*num] & 255;
+ (*num)++;
+ if (*num >= 256) return 0;
+ }
+ if (!sscanf(ptr, "%02x", &cksum)) return 0;
+ if ( ((sum & 255) + (cksum & 255)) & 255 ) return 0; /* checksum error */
+ return 1;
+}
+
+/* loads an intel hex file into the global memory[] array */
+/* filename is a string of the file to be opened */
+// the function returns the number of bytes read from the hex file
+int load_file (char *filename)
+{
+ char line[1000];
+ FILE *fin;
+ int addr, n, status, bytes[256];
+ int i, total=0, lineno=1;
+ int minaddr=65536, maxaddr=0;
+ int topaddr=0;
+
+ if (strlen(filename) == 0) {
+ printf("Can't load a file without the filename.");
+ printf(" '?' for help\n");
+ return 0;
+ }
+ fin = fopen(filename, "r");
+ if (fin == NULL) {
+ printf("Can't open file '%s' for reading.\n", filename);
+ return 0;
+ }
+
+ while (!feof(fin) && !ferror(fin)) {
+ line[0] = '\0';
+ fgets(line, 1000, fin);
+ if (line[strlen(line)-1] == '\n') line[strlen(line)-1] = '\0';
+ if (line[strlen(line)-1] == '\r') line[strlen(line)-1] = '\0';
+ if (parse_hex_line(line, bytes, &addr, &n, &status)) {
+ if (status == 0) { /* data */
+ for(i=0; i<=(n-1); i++) {
+ memory[addr] = bytes[i] & 255;
+ total++;
+ if (addr < minaddr) minaddr = addr;
+ if (addr > maxaddr) maxaddr = addr;
+ addr++;
+ }
+ if (addr >= topaddr) {
+ topaddr = addr;
+ }
+ }
+ if (status == 1) { /* end of file */
+ fclose(fin);
+ printf("Loaded %d bytes between:", total);
+ printf(" %04X to %04X\n", minaddr, maxaddr);
+ return (topaddr + 1);
+ }
+ if (status == 2) ; /* begin of file */
+ } else {
+ printf(" Error: '%s', line: %d\n", filename, lineno);
+ }
+ lineno++;
+ }
+ return (topaddr + 1);
+}
+
+
+/* the command string format is "S begin end filename" where */
+/* "begin" and "end" are the locations to dump to the intel */
+/* hex file, specified in hexidecimal. */
+
+void save_file(char *command)
+{
+ int begin, end, addr;
+ char *ptr, filename[200];
+ FILE *fhex;
+
+ ptr = command+1;
+ while (isspace(*ptr)) ptr++;
+ if (*ptr == '\0') {
+ printf(" Must specify address range and filename\n");
+ return;
+ }
+ if (sscanf(ptr, "%x%x%s", &begin, &end, filename) < 3) {
+ printf(" Invalid addresses or filename,\n");
+ printf(" usage: S begin_addr end_addr filename\n");
+ printf(" the addresses must be hexidecimal format\n");
+ return;
+ }
+ begin &= 65535;
+ end &= 65535;
+ if (begin > end) {
+ printf(" Begin address must be less than end address.\n");
+ return;
+ }
+ fhex = fopen(filename, "w");
+ if (fhex == NULL) {
+ printf(" Can't open '%s' for writing.\n", filename);
+ return;
+ }
+ for (addr=begin; addr <= end; addr++)
+ hexout(fhex, memory[addr], addr, 0);
+ hexout(fhex, 0, 0, 1);
+ printf("Memory %04X to %04X written to '%s'\n", begin, end, filename);
+}
+
+
+/* produce intel hex file output... call this routine with */
+/* each byte to output and it's memory location. The file */
+/* pointer fhex must have been opened for writing. After */
+/* all data is written, call with end=1 (normally set to 0) */
+/* so it will flush the data from its static buffer */
+
+#define MAXHEXLINE 32 /* the maximum number of bytes to put in one line */
+
+void hexout(fhex, byte, memory_location, end)
+FILE *fhex; /* the file to put intel hex into */
+int byte, memory_location, end;
+{
+ static int byte_buffer[MAXHEXLINE];
+ static int last_mem, buffer_pos, buffer_addr;
+ static int writing_in_progress=0;
+ register int i, sum;
+
+ if (!writing_in_progress) {
+ /* initial condition setup */
+ last_mem = memory_location-1;
+ buffer_pos = 0;
+ buffer_addr = memory_location;
+ writing_in_progress = 1;
+ }
+
+ if ( (memory_location != (last_mem+1)) || (buffer_pos >= MAXHEXLINE) \
+ || ((end) && (buffer_pos > 0)) ) {
+ /* it's time to dump the buffer to a line in the file */
+ fprintf(fhex, ":%02X%04X00", buffer_pos, buffer_addr);
+ sum = buffer_pos + ((buffer_addr>>8)&255) + (buffer_addr&255);
+ for (i=0; i < buffer_pos; i++) {
+ fprintf(fhex, "%02X", byte_buffer[i]&255);
+ sum += byte_buffer[i]&255;
+ }
+ fprintf(fhex, "%02X\n", (-sum)&255);
+ buffer_addr = memory_location;
+ buffer_pos = 0;
+ }
+
+ if (end) {
+ fprintf(fhex, ":00000001FF\n"); /* end of file marker */
+ fclose(fhex);
+ writing_in_progress = 0;
+ }
+
+ last_mem = memory_location;
+ byte_buffer[buffer_pos] = byte & 255;
+ buffer_pos++;
+}
+
+
Index: trunk/tools/c80/c80.lib
===================================================================
--- trunk/tools/c80/c80.lib (nonexistent)
+++ trunk/tools/c80/c80.lib (revision 65)
@@ -0,0 +1,312 @@
+#asm
+;
+;------------------------------------------------------------------
+; Small-C Run-time Librray
+;
+; V4d As of July 16, 1980 (gtf)
+; Added EXIT() function
+;------------------------------------------------------------------
+;
+;Fetch a single byte from the address in HL and sign extend into HL
+ccgchar:
+ ld a,(hl)
+ccsxt:
+ ld l,a
+ rlca
+ sbc a
+ ld h,a
+ ret
+;Fetch a full 16-bit integer from the address in HL
+ccgint:
+ ld a,(hl)
+ inc hl
+ ld h,(hl)
+ ld l,a
+ ret
+;Store a single byte from HL at the address in DE
+ccpchar:
+ ld a,l
+ ld (de),a
+ ret
+;Store a 16-bit integer in HL at the address in DE
+ccpint:
+ ld a,l
+ ld (de),a
+ inc de
+ ld a,h
+ ld (de),a
+ ret
+;Inclusive "or" HL and DE into HL
+ccor:
+ ld a,l
+ or e
+ ld l,a
+ ld a,h
+ or d
+ ld h,a
+ ret
+;Exclusive "or" HL and DE into HL
+ccxor:
+ ld a,l
+ xor e
+ ld l,a
+ ld a,h
+ xor d
+ ld h,a
+ ret
+;"And" HL and DE into HL
+ccand:
+ ld a,l
+ and e
+ ld l,a
+ ld a,h
+ and d
+ ld h,a
+ ret
+;Test if HL = DE and set HL = 1 if true else 0
+cceq:
+ call cccmp
+ ret z
+ dec hl
+ ret
+;Test if DE ~= HL
+ccne:
+ call cccmp
+ ret nz
+ dec hl
+ ret
+;Test if DE > HL (signed)
+ccgt:
+ ex de,hl
+ call cccmp
+ ret c
+ dec hl
+ ret
+;Test if DE <= HL (signed)
+ccle:
+ call cccmp
+ ret z
+ ret c
+ dec hl
+ ret
+;Test if DE >= HL (signed)
+ccge:
+ call cccmp
+ ret nc
+ dec hl
+ ret
+;Test if DE < HL (signed)
+cclt:
+ call cccmp
+ ret c
+ dec hl
+ ret
+; Signed compare of DE and HL
+; Performs DE - HL and sets the conditions:
+; Carry reflects sign of difference (set means DE < HL)
+; Zero/non-zero set according to equality.
+cccmp:
+ ld a,e
+ sub l
+ ld e,a
+ ld a,d
+ sbc h
+ ld hl,1
+ jp m,cccmp1
+ or e ;"OR" resets carry
+ ret
+cccmp1:
+ or e
+ scf ;set carry to signal minus
+ ret
+;Test if DE >= HL (unsigned)
+ccuge:
+ call ccucmp
+ ret nc
+ dec hl
+ ret
+;Test if DE < HL (unsigned)
+ccult:
+ call ccucmp
+ ret c
+ dec hl
+ ret
+;Test if DE > HL (unsigned)
+ccugt:
+ ex de,hl
+ call ccucmp
+ ret c
+ dec hl
+ ret
+;Test if DE <= HL (unsigned)
+ccule:
+ call ccucmp
+ ret z
+ ret c
+ dec hl
+ ret
+;Routine to perform unsigned compare
+;carry set if DE < HL
+;zero/nonzero set accordingly
+ccucmp:
+ ld a,d
+ cp h
+ jp nz,$+5
+ ld a,e
+ cp l
+ ld hl,1
+ ret
+;Shift DE arithmetically right by HL and return in HL
+ccasr:
+ ex de,hl
+ ld a,h
+ rla
+ ld a,h
+ rra
+ ld h,a
+ ld a,l
+ rra
+ ld l,a
+ dec e
+ jp nz,ccasr+1
+ ret
+;Shift DE arithmetically left by HL and return in HL
+ccasl:
+ ex de,hl
+ add hl,hl
+ dec e
+ jp nz,ccasl+1
+ ret
+;Subtract HL from DE and return in HL
+ccsub:
+ ld a,e
+ sub l
+ ld l,a
+ ld a,d
+ sbc h
+ ld h,a
+ ret
+;Form the two's complement of HL
+ccneg:
+ call cccom
+ inc hl
+ ret
+;Form the one's complement of HL
+cccom:
+ ld a,h
+ cpl
+ ld h,a
+ ld a,l
+ cpl
+ ld l,a
+ ret
+;Multiply DE by HL and return in HL
+ccmult:
+ ld b,h
+ ld c,l
+ ld hl,0
+ccmult1:
+ ld a,c
+ rrca
+ jp nc,$+4
+ add hl,de
+ xor a
+ ld a,b
+ rra
+ ld b,a
+ ld a,c
+ rra
+ ld c,a
+ or b
+ ret z
+ xor a
+ ld a,e
+ rla
+ ld e,a
+ ld a,d
+ rla
+ ld d,a
+ or e
+ ret z
+ jp ccmult1
+;Divide DE by HL and return quotient in HL, remainder in DE
+ccdiv:
+ ld b,h
+ ld c,l
+ ld a,d
+ xor b
+ push af
+ ld a,d
+ or a
+ call m,ccdeneg
+ ld a,b
+ or a
+ call m,ccbcneg
+ ld a,16
+ push af
+ ex de,hl
+ ld de,0
+ccdiv1:
+ add hl,hl
+ call ccrdel
+ jp z,ccdiv2
+ call cccmpbcde
+ jp m,ccdiv2
+ ld a,l
+ or 1
+ ld l,a
+ ld a,e
+ sub c
+ ld e,a
+ ld a,d
+ sbc b
+ ld d,a
+ccdiv2:
+ pop af
+ dec a
+ jp z,ccdiv3
+ push af
+ jp ccdiv1
+ccdiv3:
+ pop af
+ ret p
+ call ccdeneg
+ ex de,hl
+ call ccdeneg
+ ex de,hl
+ ret
+ccdeneg:
+ ld a,d
+ cpl
+ ld d,a
+ ld a,e
+ cpl
+ ld e,a
+ inc de
+ ret
+ccbcneg:
+ ld a,b
+ cpl
+ ld b,a
+ ld a,c
+ cpl
+ ld c,a
+ inc bc
+ ret
+ccrdel:
+ ld a,e
+ rla
+ ld e,a
+ ld a,d
+ rla
+ ld d,a
+ or e
+ ret
+cccmpbcde:
+ ld a,e
+ sub c
+ ld a,d
+ sbc b
+ ret
+
+#endasm
Index: trunk/tools/c80/c80_readme.txt
===================================================================
--- trunk/tools/c80/c80_readme.txt (nonexistent)
+++ trunk/tools/c80/c80_readme.txt (revision 65)
@@ -0,0 +1,51 @@
+Samll-C compiler adapted for embedded systems by Moti Litcochevski.
+(February 20, 2012)
+
+This compiler is an adapted version of the C80DOS compiler found on
+http://www.cpm.z80.de/small_c.html.
+
+After downloading the compiler I tried to generate some code for my FPGA SOC
+using the light8080 CPU. The generated assembler code presented a few issues:
+
+1. The compiler operates in interactive mode requesting the user to enter
+ filenames step by step. This is very inconvenient when compiling over and over
+ again.
+2. The generated assembly code did not compile using my preferred AS80 assembler.
+ Although other assemblers are available, they are not free to be used for all
+ purposes.
+3. The stack pointer was initialized to some constant value.
+4. Some coding extras where missing. For example, defining IO ports for CPU
+ peripherals (see below).
+
+The compiler version presented here provides some improvements to the above
+issues:
+
+1. Main routine was changed to enable command line operation of the compiler.
+ For command line options just run the compiler without any input options.
+2. Assembly code was changed to the syntax used by the Z80. This enables the
+ output assembly file to be compiled using the AS80 tool.
+3. Stack pointer initial value may be specified in the command line options.
+4. Supporting line comments "//". this is a must for me.
+5. Support for hexadecimal values defined with "0x" prefix.
+6. Defining IO ports using the following syntax:
+ // value in brackets is the port address
+ port (128) UDATA;
+ Address may be entered as hexadecimal value.
+7. Support for global variable init values either as strings or list.
+ For example:
+ // string init value
+ char tstring[10] = "Hello";
+ // value list init value
+ int tint[10] = {1,2,3,4,5,6,7,8,9,10};
+
+Note that one of the program source file must include the "c80.lib" assembler file
+which defines the library assembler functions used by the compiler. Currently all
+functions will be added to the output file even if not used. This will increase the
+size of the program memory by about 300 bytes.
+
+Features that are missing from the current release:
+1. Add "#ifdef" macro statements.
+2. Include only the library functions used by the program.
+
+Hope you find this application helpful,
+Moti
Index: trunk/tools/c80/AS80.txt
===================================================================
--- trunk/tools/c80/AS80.txt (nonexistent)
+++ trunk/tools/c80/AS80.txt (revision 65)
@@ -0,0 +1,769 @@
+Kingswood Software Development Tools AS80
+-------------------------------------------------------------------------
+
+NAME
+ as80 - assembler for 8080, 8085 and Z80 microprocessors.
+
+
+SYNOPSIS
+ as80 [-cdghilnopqstvwxz] file
+
+
+DESCRIPTION
+ This documentation is for as80 [1.10].
+ Copyright 1990-1994, Frank A. Vorstenbosch, Kingswood Software.
+
+ AS80 is an assembler for the Intel 8080/8085 and Zilog Z80
+ microprocessors. It reads input from an ASCII text file, assembles
+ this into memory, and then writes a listing and a binary or hex file.
+
+ AS80 is case sensitive, not only does it differentiate between the
+ labels XYZ and xyz, but it also requires all (pseudo) instruction and
+ register names to be lower case. This way, the listing is the most
+ readable. Option -i can be used to make the assembler case insensitive.
+ Alternatively, the included TOLOWER program can be used to convert
+ sources to lower case.
+
+
+OPTIONS
+ As80 recognizes the following options:
+
+ -c Show number of cycles per instruction in listing. This
+ decreases the number of columns available for listing by 5.
+ The number of cycles is printed between brackets [ and ].
+
+ -d
+ Define a label before the first source line is read. If
+ no name is specified, DEBUG is defined. The label is
+ EQUated to be 1.
+
+ -g Generate source-level debug information file. This file
+ can then be used in in-system debugging or a software
+ simulator.
+
+ -h
+ Specify height of page for listing. This option determines
+ the number of lines per printed page. Each page has a header
+ and is terminated by a form-feed character. The special
+ case -h0 indicates an infinite page length. In this case,
+ page breaks are only inserted between the two passes and
+ the symbol table (if present).
+
+ -i Ignore case in opcodes. In this way, the assembler does not
+ differentiate between 'add' and 'ADD', for example. Labels
+ are still case sensitive.
+
+ -l Generate pass 2 listing.
+
+ -l
+ Listing file name. The listing file is used for pass 1 and
+ pass 2 listing, for the symbol table (printed between the
+ two passes), and some statistics. When neither -p nor -t
+ is specified, and -l is given, then the assembler
+ automatically generates a pass 2 listing. When -p or -t is
+ specified, an additional -l should be given is a pass 2
+ listing is required. The filename - can be used to direct
+ the listing to standard output.
+
+ -l Generate pass 2 listing.
+
+ -m Show macro expansions in listing. Macro lines are prefixed
+ by a > sign.
+
+ -n Disable optimizations. When this option is specified no
+ optimizations will be done, even when the OPT pseudo-
+ instruction is used in the source code.
+
+ -o
+ Specify binary or s-records output file name. The assembler
+ automatically adds ".bin" for binary output or ".s19" for
+ s-records output when no extension is given.
+
+ -p Generate pass 1 listing. This may be used to examine any
+ optimizations/bugs generated in pass 2.
+
+ -q Quiet mode. No running line counter is displayed on standard
+ error output.
+
+ -s Write s-records instead of binary file. The s-records file
+ contains data for (only) the used memory; the binary file
+ begins at the lowest used address, and continues up to the
+ highest used address; filling unused memory between these
+ two addresses with either $ff or $00.
+
+ -s2 Write intel-hex file instead of binary file. The intel-hex
+ file contains data for (only) the used memory.
+
+ -t Generate symbol table. The symbol table is listed between
+ passes one and two, displaying the name, hexadecimal and
+ decimal value of each label, using 4-digit hexadecimal
+ numbers where possible, otherwise 8-digit numbers. The
+ decimal value is followed by an asterisk if the label is
+ redefinable (defined using SET instead of EQU).
+
+ -v Verbose mode. More information is displayed on standard
+ output.
+
+ -w
+ Specify column width. Normally, the listing is printed using
+ 79 columns for output to a 80-column screen or printer. If
+ the -w option is given without a number following it, then
+ the listing will be 131 columns wide, otherwise it will be
+ the number of colulmns specified (between 60 and 200).
+
+ -x1 Use 8085 extensions. The 8085 CPU has two additional
+ instructions and different cycle counts, but is otherwise
+ software compatible to the 8080. When this option is not
+ specified the assembler rejects the RIM and SIM instructions.
+
+ -x or
+ -x2
+ Use Z80 extensions. The Z80 has many additional instructions
+ and addressing modes, but is otherwise software compatible to
+ the 8080. When this option is not specified the assembler
+ rejects all Z80 new instructions and addressing modes.
+
+ -x3 Use Z80 extensions and index register byte instructions.
+ The IX and IY registers were originally intended to be
+ split in IXH/IXL and IYH/IYL register pairs. For some
+ reason (bug in original mask set?) these instructions were
+ not included by Zilog in the programming manuals, but
+ they do work on all CPUs I've seen. Your mileage may vary.
+ Note that these extensions do NOT work on the Z180/181 and
+ H64180, but they DO (and are documented) on the Z280.
+
+ -z Fill unused memory with zeros. Normally when a binary file
+ is generated, unused bytes between the lowest and highest
+ used addresses are filled with $ff, the unprogrammed state
+ of EPROMs. If this is not wanted, the -z option can be used
+ to initialize this memory to $00. With s-records, unused
+ memory is not output to the file, and this option forces the
+ creation of an S9 (start address) record instead, even if no
+ start address is specified in the file with the END pseudo-
+ instruction.
+
+ Commandline options can be catenated, but no other option can follow
+ one that may have a parameter. Thus:
+ -tlfile
+ is correct (specifying symbol table and pass 2 listing), but
+ -h5t
+ is not.
+
+ It is possible to discard any of the the output files by specifying
+ the name 'nul'.
+
+
+EXPRESSIONS
+
+ The assembler recognizes most C-language expressions. The operators
+ are listed here in order of precedence, highest first:
+
+ () braces to group subexpressions
+ * $ current location counter
+ unary + - ! ~ unary + (no-operation), negation, logical NOT,
+ binary NOT
+ * / % multiplication, division, modulo
+ + - addition, subtraction
+ << >> shift left, shift right
+ < > <= >= comparison for greater/less than
+ = != comparison for equality (== can be used for =)
+ & binary AND
+ ^ binary XOR
+ | binary OR
+ && logical AND
+ || logical OR
+ hi lo high byte, low byte
+
+ The logical NOT (!) evaluates to zero if the parameter is nonzero,
+ and vice versa. The binary NOT (~) complements all the bits in its
+ parameter. Logical AND (&&) and OR (||) operators evaluate to one
+ if both resp. at least one argument is nonzero. These two operators
+ evaluate both arguments, unlike the C-language versions.
+
+ Note: the asterisk is both used as the multiplication operator, and
+ as symbol for the current location. The assembler determines from
+ the context which is which. Thus:
+
+ 5**
+
+ is a valid expression, evaluating to five times the current location
+ counter, and:
+
+ 2+*/2
+
+ is too, evaluating to the current location counter divided by two, to
+ which two is added. In the same way, the % sign is both used as the
+ modulo operator and the prefix for binary numbers.
+
+ Numbers can be specified in any number base between 2 and 36.
+ Decimal numbers can be used without a prefix, hexadecimal numbers
+ can be prefixed by $, octal numbers by @, and binary numbers by %.
+ Other number bases can be used by using the following format:
+ ,
+ where the base is the number base to use (must be specified in
+ decimal), and number is the value. Thus:
+ 1000 - decimal number, value 10*10*10=1000
+ %1000 - binary number, value 2*2*2=8
+ @1000 - octal number, value 8*8*8=512
+ $1000 - hexadecimal number, value 16*16*16=4096
+ #1000 - hexadecimal number, value 16*16*16=4096
+ 0b1000 - binary number, value 2*2*2=8
+ 0x1000 - hexadecimal number, value 16*16*16=4096
+ 2#1000 - binary number, value 2*2*2=8
+ 4#1000 - base-4 number, value 4*4*4=64
+ 7#1000 - base-7 number, value 7*7*7=343
+ 36#1000 - base-36 number, value 36*36*36=444528
+ For number bases greater than 10, additional digits are represented
+ by letters, starting from A. Both lower and upper case letters can
+ be used.
+ 11#aa = 120
+ 16#ff = 255
+ 25#oo = 624
+ 36#zz = 1295
+
+
+PSEUDO-INSTRUCTIONS
+
+ align
+
+ Align fills zero or more bytes with zeros until the new address
+ modulo equals zero. If the expression is not present,
+ align fills zero or one bytes with zeros until the new address
+ is even.
+
+ Example 1:
+ align 256 ; continue assembly on the
+ ; next 256-byte page
+
+ Example 2:
+ align ; make sure table begins
+ Table dw 1,2,3 ; on an even address
+
+
+
+ bss
+
+ Put all following data in the bss segment. Only data pseudo-instructions
+ can be used in the bss segment, and these only increment the location
+ counter. It is up to the programmer to initialize the bss segment. The
+ bss segment is especially meaningful in a ROM based system where
+ variables must be placed in RAM, and RAM is not automatically initialized.
+
+ The assembler internally maintains three separate location counters,
+ one for the code segment, one for the data segment and one for the
+ uninitialized data segment. The user is responsible for not overlapping
+ the segments by setting appropriate origins. The code, data and bss
+ pseudo-instructions can be used to interleave code and data in the source
+ listing, while separating the three in the generated program. The
+ assembler starts with the code segment if none is specified.
+
+ Example:
+ code
+ org $f000 ; Assuming 4 kbyte code ROM
+ data ; with 2 kbyte program and
+ org $f800 ; 2 kbyte initialized data
+ bss
+ org 0 ; bss segment is in RAM
+
+ Buffer ds 100
+
+ code
+ Begin ld hl,Table
+ ld de,Buffer
+ ld bc,3
+ ldir
+ .
+ .
+ .
+
+ data
+ Table db 1,2,3
+
+ code
+ MyFunc ld ix,Table
+ .
+ .
+
+ code
+
+ Put all following assembled instructions and data in the code segment.
+ See BSS.
+
+
+ data
+
+ Put all following assembled instructions and data in the data segment.
+ See BSS.
+
+
+ db
+
+ Define bytes. The bytes may be specified as expressions or strings,
+ and are placed in the current (code or data) segment. This pseudo
+ instruction is similar to the Zilog-defined defb and defm pseudo-
+ instructions.
+
+ Example:
+ Message db "\aError\r\n",0
+
+
+ defb
+
+ Define bytes. The bytes may be specified only as expressions,
+ and are placed in the current (code or data) segment. This
+ pseudo-instruction is similar to the db pseudo-instruction.
+
+ Example:
+ Message defb 7
+ defm "Error"
+ defb 13,10,0
+
+
+ defm
+
+ Define message. The bytes may be specified only as a string, and
+ are placed in the current (code or data) segment. This pseudo-
+ instruction is similar to the db pseudo-instruction.
+
+
+ ds
+ defs
+
+ Define zero or more bytes empty space. The specified number of
+ bytes are filled with zeros. This pseudo-instruction is identical
+ to the Zilog-defined pseudo-instruction defs.
+
+ Example:
+ ds 100 ; reserve 100 bytes here
+
+
+ dw
+ defw
+
+ Define words. The words are placed in the current (code or data)
+ segment. This pseudo-instruction is identical to the Zilog-
+ defined defw pseudo-instruction.
+
+ Example:
+ ld a,2*Function ; number of function
+ ld hl,JumpTable
+ add a,l ; calculate HL+A
+ ld l,a
+ adc a,h
+ sub l
+ ld h,a
+ jp (hl) ; jump to function
+
+ JumpTable dw Function0
+ dw Function1
+ dw Function2
+
+
+ else
+
+ The else pseudo-instruction can be used for if-then-else
+ constructions. It must be placed between an if and an endif
+ instruction. For an example, see the if pseudo-instruction.
+
+
+ end
+
+ The end pseudo-instruction is optional, and need not be used. If
+ it is used, its optional operand specifies the staring address of
+ the program. This address is displayed when the program is
+ assembled, and is also placed in the s-record output file.
+
+ Example:
+ end Start
+
+ endif
+
+ The endif pseudo-instruction must be used to close an if-endif
+ or if-else-endif construction. For an example, see the if
+ pseudo-instruction.
+
+
+
trunk/tools/c80/c80.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/tools/c80/c80.c
===================================================================
--- trunk/tools/c80/c80.c (nonexistent)
+++ trunk/tools/c80/c80.c (revision 65)
@@ -0,0 +1,2627 @@
+//************************************************
+//
+// Small-C Compiler
+//
+// by Ron Cain
+//
+//************************************************
+
+// with minor mods by RDK
+#define BANNER " <><><> Small-C V1.2 DOS--CP/M Cross Compiler <><><>"
+#define VERSION " <><><><><> CP/M Large String Space Version <><><><><>"
+#define AUTHOR " <><><><><><><><><><> By Ron Cain <><><><><><><><><><>"
+#define TLINE " <><><><><><><><><><><><><><>X<><><><><><><><><><><><><><>"
+
+/* Define system dependent parameters */
+/* Stand-alone definitions */
+/* INCLUDE THE LIBRARY TO COMPILE THE COMPILER (RDK) */
+/* #include smallc.lib */ /* small-c library included in source now */
+/* IN DOS USE THE SMALL-C OBJ LIBRARY RATHER THAN IN-LINE ASSEMBLER */
+#define NULL 0
+#define eol 10 /* was 13 */
+
+#include "stdio.h" /* was */
+
+/* Define the symbol table parameters */
+#define symsiz 16
+#define symtbsz 5760
+#define numglbs 300
+#define startglb symtab
+#define endglb startglb+numglbs*symsiz
+#define startloc endglb+symsiz
+#define endloc symtab+symtbsz-symsiz
+
+/* Define symbol table entry format */
+#define name 0
+#define ident 9
+#define type 10
+#define storage 11
+#define offset 12
+#define initptr 14
+
+/* System wide name size (for symbols) */
+#define namesize 9
+#define namemax 8
+
+/* Define possible entries for "ident" */
+#define variable 1
+#define array 2
+#define pointer 3
+#define function 4
+
+/* Define possible entries for "type" */
+#define cchar 1
+#define cint 2
+#define cport 3
+
+/* Define possible entries for "storage" */
+#define statik 1
+#define stkloc 2
+
+/* Define the "while" statement queue */
+#define wqtabsz 300
+#define wqsiz 4
+#define wqmax wq+wqtabsz-wqsiz
+
+/* Define entry offsets in while queue */
+#define wqsym 0
+#define wqsp 1
+#define wqloop 2
+#define wqlab 3
+
+/* Define the literal pool */
+#define litabsz 8000
+#define litmax litabsz-1
+
+/* Define the input line */
+#define linesize 256
+#define linemax linesize-1
+#define mpmax linemax
+
+/* Define the macro (define) pool */
+#define macqsize 3000
+#define macmax macqsize-1
+
+/* Define statement types (tokens) */
+#define stif 1
+#define stwhile 2
+#define streturn 3
+#define stbreak 4
+#define stcont 5
+#define stasm 6
+#define stexp 7
+
+/* Define how to carve up a name too long for the assembler */
+#define asmpref 7
+#define asmsuff 7
+
+// define the global variable init values que size
+#define initqsz 8192
+
+/* Now reserve some storage words */
+char symtab[symtbsz]; /* symbol table */
+char *glbptr,*locptr; /* ptrs to next entries */
+
+int wq[wqtabsz]; /* while queue */
+int *wqptr; /* ptr to next entry */
+
+char litq[litabsz]; /* literal pool */
+int litptr; /* ptr to next entry */
+
+char macq[macqsize]; /* macro string buffer */
+int macptr; /* and its index */
+
+char inittbq[initqsz]; // init value buffer
+int inittbptr; // and its index
+
+char line[linesize]; /* parsing buffer */
+char mline[linesize]; /* temp macro buffer */
+int lptr,mptr; /* ptrs into each */
+
+/* Misc storage */
+int nxtlab, /* next avail label # */
+ litlab, /* label # assigned to literal pool */
+ Zsp, /* compiler relative stk ptr */
+ argstk, /* function arg sp */
+ ncmp, /* # open compound statements */
+ errcnt, /* # errors in compilation */
+ errstop, /* stop on error gtf 7/17/80 */
+ eof, /* set non-zero on final input eof */
+ input, /* iob # for input file */
+ output, /* iob # for output file (if any) */
+ outputv, /* output valid flag */
+ input2, /* iob # for "include" file */
+ glbflag, /* non-zero if internal globals */
+ ctext, /* non-zero to intermix c-source */
+ cmode, /* non-zero while parsing c-code */
+ /* zero when passing assembly code */
+ lastst, /* last executed statement type */
+ mainflg, /* output is to be first asm file gtf 4/9/80 */
+ saveout, /* holds output ptr when diverted to console */
+ /* gtf 7/16/80 */
+ fnstart, /* line# of start of current fn. gtf 7/2/80 */
+ lineno, /* line# in current file gtf 7/2/80 */
+ infunc, /* "inside function" flag gtf 7/2/80 */
+ savestart, /* copy of fnstart " " gtf 7/16/80 */
+ saveline, /* copy of lineno " " gtf 7/16/80 */
+ saveinfn; /* copy of infunc " " gtf 7/16/80 */
+
+char *currfn, /* ptr to symtab entry for current fn. gtf 7/17/80 */
+ *savecurr; /* copy of currfn for #include gtf 7/17/80 */
+char *cptr; /* work ptr to any char buffer */
+int *iptr; /* work ptr to any int buffer */
+
+// interactive mode flag
+int intmode;
+// pointer array to input files list from argv[]
+#define MAXINFILES 64
+char *infiles[MAXINFILES];
+int filesnum, filesidx;
+// initial stack pointer value
+int stackptr;
+
+/* >>>>> start cc1 <<<<<< */
+
+/* */
+/* Compiler begins execution here */
+/* */
+void main(int argc, char *argv[])
+{
+int argi, phelp;
+
+ glbptr=startglb; /* clear global symbols */
+ locptr=startloc; /* clear local symbols */
+ wqptr=wq;0; /* clear while queue */
+ macptr=0; /* clear the macro pool */
+ litptr=0; /* clear literal pool */
+ Zsp =0; /* stack ptr (relative) */
+ errcnt=0; /* no errors */
+ errstop=0; /* keep going after an error gtf 7/17/80 */
+ eof=0; /* not eof yet */
+ input=0; /* no input file */
+ input2=0; /* or include file */
+ output=0; /* no open units */
+ outputv=0; /* output is not valid */
+ saveout=0; /* no diverted output */
+ ncmp=0; /* no open compound states */
+ lastst=0; /* no last statement yet */
+ mainflg=0; /* not first file to asm gtf 4/9/80 */
+ fnstart=0; /* current "function" started at line 0 gtf 7/2/80 */
+ lineno=0; /* no lines read from file gtf 7/2/80 */
+ infunc=0; /* not in function now gtf 7/2/80 */
+ currfn=NULL; /* no function yet gtf 7/2/80 */
+ cmode=1; /* enable preprocessing */
+ stackptr=0; /* default value of stack pointer */
+ inittbptr=0; // clear pointer to init array
+
+ intmode = 1; // default mode is interactive mode
+ filesnum = 0; // no input files for now
+ filesidx = 0;
+
+ // print original banner
+ printf("\n");
+ printf(" <><><><><><><><><><><><><><>X<><><><><><><><><><><><><><>\n");
+ printf(" <><><> Small-C V1.2 DOS--CP/M Cross Compiler <><><>\n");
+ printf(" <><><><><><><><><><> By Ron Cain <><><><><><><><><><>\n");
+ printf(" <><><><><> CP/M Large String Space Version <><><><><>\n");
+ printf(" <><><><><><><><><><><><><><>X<><><><><><><><><><><><><><>\n");
+
+ // print adapted banner and usage
+ printf("\n");
+ printf(" <><><><><><><><><><><><><><>X<><><><><><><><><><><><><><>\n");
+ printf(" <><><> Small-C adapted for embedded systems by <><><><>\n");
+ printf(" <><><><><><><><><> Moti Litochevski <><><><><><><><><>\n");
+ printf(" <><><><><><> Version 0.1 (February 20, 2012) <><><><><><>\n");
+ printf(" <><><><><><><><><><><><><><>X<><><><><><><><><><><><><><>\n");
+ printf("\n");
+ // check if command line options where specified
+ if (argc <= 1) {
+ printf(" command line mode usage:\n");
+ printf(" c80 -s -o \n");
+ printf(" options:\n");
+ printf(" -s Initial stack pointer value in hex value.\n");
+ printf(" Example: -s800 will init the stack pointer\n");
+ printf(" to 0x800.\n");
+ printf(" -o Compiler output filename including extension.\n");
+ printf(" \n");
+ }
+
+ // start from the first valid argument
+ argi = 1;
+ phelp = 0;
+ // loop through input options
+ while (argi < argc) {
+ // copy pointer of the current option to the work buffer
+ cptr = argv[argi];
+ // loop through input options
+ if (cptr[0] == '-') {
+ // compiler options
+ if (cptr[1] == 's') {
+ // stack pointer address value
+ sscanf(&cptr[2], "%x", &stackptr);
+ } else if (cptr[1] == 'o') {
+ // copy the output filename to the line
+ strcpy(line, &cptr[2]);
+ // open output file
+ openout(0);
+ } else if ((cptr[1] == 'h') | (cptr[1] == '?')) {
+ // sign that only help should be printed
+ phelp = 1;
+ } else {
+ printf("error: illegal option.\n");
+ }
+ } else {
+ // after all other options the list of input files is given and
+ // compiler is operated in non-interactive mode
+ intmode = 0;
+
+ // copy the input files names pointers to the local array
+ for (filesnum=0; (argi < argc) && (filesnum < MAXINFILES); filesnum++) {
+ infiles[filesnum] = argv[argi];
+ argi++;
+ }
+ }
+ // update argument index
+ argi++;
+ }
+
+ // check if compiler should be started
+ if (!phelp) {
+ // announce interactive mode compiler
+ printf(" Starting compiler in interactive mode.\n\n");
+ // compiler body
+ ask(); /* get user options */
+ if (outputv == 0) openout(1); /* get an output file */
+ openin(); /* and initial input file */
+ header(); /* intro code */
+ parse(); /* process ALL input */
+ dumplits(); /* then dump literal pool */
+ dumpglbs(); /* and all static memory */
+ trailer(); /* follow-up code */
+ closeout(); /* close the output (if any) */
+ errorsummary(); /* summarize errors (on console!) */
+ }
+ return; /* then exit to system */
+}
+
+/* */
+/* Abort compilation */
+/* gtf 7/17/80 */
+zabort()
+{
+ if(input2)
+ endinclude();
+ if(input)
+ fclose(input);
+ closeout();
+ toconsole();
+ pl("Compilation aborted."); nl();
+ exit();
+/* end zabort */}
+
+/* */
+/* Process all input text */
+/* */
+/* At this level, only static declarations, */
+/* defines, includes, and function */
+/* definitions are legal... */
+parse()
+{
+ while (eof==0) /* do until no more input */
+ {
+ if(amatch("char",4)){declglb(cchar);ns();}
+ else if(amatch("int",3)){declglb(cint);ns();}
+ else if(amatch("port",4)){declglb(cport);ns();}
+ else if(match("#asm"))doasm();
+ else if(match("#include"))doinclude();
+ else if(match("#define"))addmac();
+ else newfunc();
+ blanks(); /* force eof if pending */
+ }
+}
+/* */
+/* Dump the literal pool */
+/* */
+dumplits()
+ {int j,k;
+ if (litptr==0) return; /* if nothing there, exit...*/
+ printlabel(litlab);col();nl(); /* print literal label */
+ k=0; /* init an index... */
+ while (k=litptr))
+ {nl(); /* need */
+ break;
+ }
+ outbyte(','); /* separate bytes */
+ }
+ }
+ }
+/* */
+/* Dump all static variables */
+/* */
+dumpglbs()
+{
+int j,dptr,idx;
+
+ if (glbflag==0) return; /* don't if user said no */
+ cptr=startglb;
+ while (cptr=inittbptr)) {
+ nl(); /* need */
+ break;
+ }
+ // every 10 values reopen the line
+ if (idx++ == 10) {
+ // add and restart byte definition
+ nl();
+ defbyte();
+ idx=1;
+ } else
+ // separate bytes
+ outbyte(',');
+ }
+ }
+ }
+ cptr=cptr+symsiz;
+ }
+}
+/* */
+/* Report errors for user */
+/* */
+errorsummary()
+{
+ /* see if anything left hanging... */
+ if (ncmp) error("missing closing bracket");
+ /* open compound statement ... */
+ printf("\nThere were %d errors in compilation.\n\n", errcnt);
+}
+
+/* Get options from user */
+ask()
+{
+int k,num[1];
+
+ kill(); /* clear input line */
+ // by default enabling C text in the output file in form of comments (for clarity)
+ ctext=1; /* user said yes */
+ // by default assuming all files are compiled together
+ glbflag=1; /* define globals */
+ mainflg=1; /* first file to assembler */
+ nxtlab =0; /* start numbers at lowest possible */
+ // compiler does noy pause on errors
+ errstop=0;
+
+ litlab=getlabel(); /* first label=literal pool */
+ kill(); /* erase line */
+}
+
+/* */
+/* Get output filename */
+/* */
+openout(char flag)
+{
+ if (flag) {
+ kill(); /* erase line */
+ output=0; /* start with none */
+ pl("Output filename? "); /* ask...*/
+ gets(line); /* get a filename */
+ }
+ if(ch()==0)return; /* none given... */
+ /* if given, open */
+ if((output=fopen(line,"w"))==NULL) {
+ output=0; /* can't open */
+ error("Open failure!");
+ } else
+ outputv = 1;
+ kill(); /* erase line */
+}
+/* */
+/* Get (next) input file */
+/* */
+openin()
+{
+ input=0; /* none to start with */
+ while (input==0) { /* any above 1 allowed */
+ kill(); /* clear line */
+ // check if we are using interactive mode or not
+ if (intmode) {
+ // use the old style input file from the user
+ if (eof) break; /* if user said none */
+ pl("Input filename? ");
+ gets(line); /* get a name */
+ if (ch()==0)
+ {eof=1;break;} /* none given... */
+ } else {
+ // copy the file names from the name array
+ if (filesidx < filesnum) {
+ strcpy(line, infiles[filesidx]);
+ printf("Processing Input file %d: %s\n", filesidx, line);
+ filesidx++;
+ } else {
+ // no more files
+ eof=1;
+ break;
+ }
+ }
+
+ if ((input=fopen(line,"r"))!=NULL)
+ newfile(); /* gtf 7/16/80 */
+ else {
+ input=0; /* can't open it */
+ pl("Open failure");
+ }
+ }
+ kill(); /* erase line */
+}
+
+/* */
+/* Reset line count, etc. */
+/* gtf 7/16/80 */
+newfile()
+{
+ lineno = 0; /* no lines read */
+ fnstart = 0; /* no fn. start yet. */
+ currfn = NULL; /* because no fn. yet */
+ infunc = 0; /* therefore not in fn. */
+/* end newfile */}
+
+/* */
+/* Open an include file */
+/* */
+doinclude()
+{
+ blanks(); /* skip over to name */
+
+ toconsole(); /* gtf 7/16/80 */
+ outstr("#include "); outstr(line+lptr); nl();
+ tofile();
+
+ if(input2) /* gtf 7/16/80 */
+ error("Cannot nest include files");
+ else if ((input2=fopen(line+lptr,"r"))==NULL) {
+ input2=0;
+ error("Open failure on include file");
+ }
+ else {
+ saveline = lineno;
+ savecurr = currfn;
+ saveinfn = infunc;
+ savestart= fnstart;
+ newfile();
+ }
+ kill(); /* clear rest of line */
+ /* so next read will come from */
+ /* new file (if open */
+}
+
+/* */
+/* Close an include file */
+/* gtf 7/16/80 */
+endinclude()
+{
+ toconsole();
+ outstr("#end include"); nl();
+ tofile();
+
+ input2 = 0;
+ lineno = saveline;
+ currfn = savecurr;
+ infunc = saveinfn;
+ fnstart = savestart;
+/* end endinclude */}
+
+/* */
+/* Close the output file */
+/* */
+closeout()
+{
+ tofile(); /* if diverted, return to file */
+ if(output)fclose(output); /* if open, close it */
+ output=0; /* mark as closed */
+}
+/* */
+/* Declare a static variable */
+/* (i.e. define for use) */
+/* */
+/* makes an entry in the symbol table so subsequent */
+/* references can call symbol by name */
+declglb(typ) /* typ is cchar or cint or cport (added by Moti Litchevski) */
+ int typ;
+{
+int k,j,iptr,idx,num[1];
+char sname[namesize];
+
+ while (1) {
+ while (1) {
+ if(endst())return; /* do line */
+ k=1; /* assume 1 element */
+ if(match("*")) /* pointer ? */
+ j=pointer; /* yes */
+ else
+ j=variable; /* no */
+
+ // added by Moti Litochevski
+ if (match("(")) {
+ // make sure this option is only used for port definition
+ if (typ != cport)
+ error("port address definition is only used for port type");
+ // get port address
+ k=portadr();
+ k=k&0xff;
+ } else if (typ == cport) {
+ error("port definition syntax error, need to define port address in brackets");
+ }
+
+ if (symname(sname)==0) /* name ok? */
+ illname(); /* no... */
+ if(findglb(sname)) /* already there? */
+ multidef(sname);
+ if (match("[")) { /* array? */
+ if (typ==cport) error("port cannot be defined as an array");
+ k=needsub(); /* get size */
+ if(k)j=array; /* !0=array */
+ else j=pointer; /* 0=ptr */
+ }
+
+ // check if the declared global has a default value
+ if (match("=")) {
+ // check if variable type supports init
+ if ((typ!=cchar) & (typ!=cint))
+ error("variable type does not support init value");
+
+ // set the init pointer to the current init pointer
+ iptr=inittbptr;
+ idx=0;
+
+ // new defined variable has a default init value
+ // check if the variable is defined as string, list of values {} or a
+ // single value
+ if (match("\"")) {
+ // init value is defined as a string
+ // copy the string values to the init buffer
+ while (idx++ < k) {
+ // check if new value is valid
+ if ((ch() != '"') & (ch() != 0))
+ inittbq[inittbptr++] = gch();
+ else
+ inittbq[inittbptr++] = 0;
+
+ // check that init buffer is full
+ if (inittbptr == initqsz) {
+ // clear the variable init pointer and print error message
+ iptr=0xffff;
+ error("init buffer is full, variable will not be initialized");
+ // sign that init is done
+ idx=k;
+ }
+ }
+ // look for matching quote mark
+ if (match("\"")==0) {
+ error("end of string expected");
+ }
+ }
+ else if (match("{")) {
+ // init value is defined as a list of values
+ // copy the list of values to the init buffer
+ while (idx++ < k) {
+ // check if new value is valid
+ if ((ch() != '}') & (ch() != 0)) {
+ // make sure that the next value is a number
+ if (!number(num) & !pstr(num))
+ error("could not find valid value in initialization list");
+ }
+ else
+ // use zero value as init
+ num[0]=0;
+
+ // save the values according to array type
+ if (typ==cint) {
+ inittbq[inittbptr++] = (char)(num[0]&255);
+ inittbq[inittbptr++] = (char)((num[0]>>8)&255);
+ }
+ else
+ inittbq[inittbptr++] = (char)(num[0]&255);
+
+ // check that init buffer is full
+ if (inittbptr == initqsz) {
+ // clear the variable init pointer and print error message
+ iptr=0xffff;
+ error("init buffer is full, variable will not be initialized");
+ // sign that init is done
+ idx=k;
+ }
+ // remove comma if it is there
+ match(",");
+ }
+ // look for ending brackets
+ if (match("}")==0) {
+ error("end of initialization list expected");
+ }
+ }
+ else {
+ // expecting a single input value
+ if (!number(num) & !pstr(num))
+ error("could not find initialization value");
+
+ // save the values according to variable type
+ if (typ==cint) {
+ inittbq[inittbptr++] = (char)((num[0]>>16)&255);
+ inittbq[inittbptr++] = (char)(num[0]&255);
+ }
+ else
+ inittbq[inittbptr++] = (char)(num[0]&255);
+ // update index
+ idx=1;
+
+ // init to end of array is more than one
+ while (idx++ < k) {
+ // fill the reset of the init list with zeros
+ if (typ==cint) {
+ inittbq[inittbptr++] = 0;
+ inittbq[inittbptr++] = 0;
+ }
+ else
+ inittbq[inittbptr++] = 0;
+
+ // check that init buffer is full
+ if (inittbptr == initqsz) {
+ // clear the variable init pointer and print error message
+ iptr=0xffff;
+ error("init buffer is full, variable will not be initialized");
+ // sign that init is done
+ idx=k;
+ }
+ }
+ }
+ } else {
+ // no default value point init pointer to null
+ iptr=0xffff;
+ }
+ // add symbol
+ addglb(sname,j,typ,k,iptr);
+ break;
+ }
+ if (match(",")==0) return; /* more? */
+ }
+}
+/* */
+/* Declare local variables */
+/* (i.e. define for use) */
+/* */
+/* works just like "declglb" but modifies machine stack */
+/* and adds symbol table entry with appropriate */
+/* stack offset to find it again */
+declloc(typ) /* typ is cchar or cint */
+ int typ;
+ {
+ int k,j;char sname[namesize];
+ while(1)
+ {while(1)
+ {if(endst())return;
+ if(match("*"))
+ j=pointer;
+ else j=variable;
+ if (symname(sname)==0)
+ illname();
+ if(findloc(sname))
+ multidef(sname);
+ if (match("["))
+ {k=needsub();
+ if(k)
+ {j=array;
+ if(typ==cint)k=k+k;
+ }
+ else
+ {j=pointer;
+ k=2;
+ }
+ }
+ else
+ if((typ==cchar)
+ &(j!=pointer))
+ k=1;else k=2;
+ /* change machine stack */
+ Zsp=modstk(Zsp-k);
+ addloc(sname,j,typ,Zsp);
+ break;
+ }
+ if (match(",")==0) return;
+ }
+ }
+/* >>>>>> start of cc2 <<<<<<<< */
+
+/* */
+/* Get required array size */
+/* */
+/* invoked when declared variable is followed by "[" */
+/* this routine makes subscript the absolute */
+/* size of the array. */
+needsub()
+{
+int num[1];
+
+ if(match("]"))return 0; /* null size */
+ if (number(num)==0) /* go after a number */
+ {error("must be constant"); /* it isn't */
+ num[0]=1; /* so force one */
+ }
+ if (num[0]<0)
+ {error("negative size illegal");
+ num[0]=(-num[0]);
+ }
+ needbrack("]"); /* force single dimension */
+ return num[0]; /* and return size */
+}
+//
+// get array size function changed to get a port address
+//
+portadr()
+{
+int num[1];
+
+ if(match(")")) {
+ error("port address value must be defined");
+ return 0; /* null size */
+ }
+ if (number(num)==0) { /* go after a number */
+ error("port address must be constant"); /* it isn't */
+ num[0]=1; /* so force one */
+ }
+ if (num[0]<0) {
+ error("negative port address illegal");
+ num[0]=(-num[0]);
+ }
+ needbrack(")"); /* force single dimension */
+ return num[0]; /* and return size */
+}
+
+/* */
+/* Begin a function */
+/* */
+/* Called from "parse" this routine tries to make a function */
+/* out of what follows. */
+newfunc()
+ {
+ char n[namesize]; /* ptr => currfn, gtf 7/16/80 */
+ if (symname(n)==0)
+ {error("illegal function or declaration");
+ kill(); /* invalidate line */
+ return;
+ }
+ fnstart=lineno; /* remember where fn began gtf 7/2/80 */
+ infunc=1; /* note, in function now. gtf 7/16/80 */
+ if(currfn=findglb(n)) /* already in symbol table ? */
+ {if(currfn[ident]!=function)multidef(n);
+ /* already variable by that name */
+ else if(currfn[offset]==function)multidef(n);
+ /* already function by that name */
+ else currfn[offset]=function;
+ /* otherwise we have what was earlier*/
+ /* assumed to be a function */
+ }
+ /* if not in table, define as a function now */
+ else currfn=addglb(n,function,cint,function,-1);
+
+ toconsole(); /* gtf 7/16/80 */
+ outstr("====== "); outstr(currfn+name); outstr("()"); nl();
+ tofile();
+
+ /* we had better see open paren for args... */
+ if(match("(")==0)error("missing open paren");
+ outname(n);col();nl(); /* print function name */
+ argstk=0; /* init arg count */
+ while(match(")")==0) /* then count args */
+ /* any legal name bumps arg count */
+ {if(symname(n))argstk=argstk+2;
+ else{error("illegal argument name");junk();}
+ blanks();
+ /* if not closing paren, should be comma */
+ if(streq(line+lptr,")")==0)
+ {if(match(",")==0)
+ error("expected comma");
+ }
+ if(endst())break;
+ }
+ locptr=startloc; /* "clear" local symbol table*/
+ Zsp=0; /* preset stack ptr */
+ while(argstk)
+ /* now let user declare what types of things */
+ /* those arguments were */
+ {if(amatch("char",4)){getarg(cchar);ns();}
+ else if(amatch("int",3)){getarg(cint);ns();}
+ else{error("wrong number args");break;}
+ }
+ if(statement()!=streturn) /* do a statement, but if */
+ /* it's a return, skip */
+ /* cleaning up the stack */
+ {modstk(0);
+ zret();
+ }
+ Zsp=0; /* reset stack ptr again */
+ locptr=startloc; /* deallocate all locals */
+ infunc=0; /* not in fn. any more gtf 7/2/80 */
+ }
+/* */
+/* Declare argument types */
+/* */
+/* called from "newfunc" this routine adds an entry in the */
+/* local symbol table for each named argument */
+getarg(t) /* t = cchar or cint */
+ int t;
+ {
+ char n[namesize],c;int j;
+ while(1)
+ {if(argstk==0)return; /* no more args */
+ if(match("*"))j=pointer;
+ else j=variable;
+ if(symname(n)==0) illname();
+ if(findloc(n))multidef(n);
+ if(match("[")) /* pointer ? */
+ /* it is a pointer, so skip all */
+ /* stuff between "[]" */
+ {while(inbyte()!=']')
+ if(endst())break;
+ j=pointer;
+ /* add entry as pointer */
+ }
+ addloc(n,j,t,argstk);
+ argstk=argstk-2; /* cnt down */
+ if(endst())return;
+ if(match(",")==0)error("expected comma");
+ }
+ }
+/* */
+/* Statement parser */
+/* */
+/* called whenever syntax requires */
+/* a statement. */
+/* this routine performs that statement */
+/* and returns a number telling which one */
+statement()
+{
+ /* NOTE (RDK) --- On DOS there is no CPM function so just try */
+ /* commenting it out for the first test compilation to see if */
+ /* the compiler basic framework works OK in the DOS environment */
+ /* if(cpm(11,0) & 1) /* check for ctrl-C gtf 7/17/80 */
+ /* if(getchar()==3) */
+ /* zabort(); */
+
+ if ((ch()==0) & (eof)) return;
+ else if(amatch("char",4))
+ {declloc(cchar);ns();}
+ else if(amatch("int",3))
+ {declloc(cint);ns();}
+ else if(match("{"))compound();
+ else if(amatch("if",2))
+ {doif();lastst=stif;}
+ else if(amatch("while",5))
+ {dowhile();lastst=stwhile;}
+ else if(amatch("return",6))
+ {doreturn();ns();lastst=streturn;}
+ else if(amatch("break",5))
+ {dobreak();ns();lastst=stbreak;}
+ else if(amatch("continue",8))
+ {docont();ns();lastst=stcont;}
+ else if(match(";"));
+ else if(match("#asm"))
+ {doasm();lastst=stasm;}
+ /* if nothing else, assume it's an expression */
+ else{expression();ns();lastst=stexp;}
+ return lastst;
+}
+/* */
+/* Semicolon enforcer */
+/* */
+/* called whenever syntax requires a semicolon */
+ns() {if(match(";")==0)error("missing semicolon");}
+/* */
+/* Compound statement */
+/* */
+/* allow any number of statements to fall between "{}" */
+compound()
+ {
+ ++ncmp; /* new level open */
+ while (match("}")==0) statement(); /* do one */
+ --ncmp; /* close current level */
+ }
+/* */
+/* "if" statement */
+/* */
+doif()
+ {
+ int flev,fsp,flab1,flab2;
+ flev=locptr; /* record current local level */
+ fsp=Zsp; /* record current stk ptr */
+ flab1=getlabel(); /* get label for false branch */
+ test(flab1); /* get expression, and branch false */
+ statement(); /* if true, do a statement */
+ Zsp=modstk(fsp); /* then clean up the stack */
+ locptr=flev; /* and deallocate any locals */
+ if (amatch("else",4)==0) /* if...else ? */
+ /* simple "if"...print false label */
+ {printlabel(flab1);col();nl();
+ return; /* and exit */
+ }
+ /* an "if...else" statement. */
+ jump(flab2=getlabel()); /* jump around false code */
+ printlabel(flab1);col();nl(); /* print false label */
+ statement(); /* and do "else" clause */
+ Zsp=modstk(fsp); /* then clean up stk ptr */
+ locptr=flev; /* and deallocate locals */
+ printlabel(flab2);col();nl(); /* print true label */
+ }
+/* */
+/* "while" statement */
+/* */
+dowhile()
+ {
+ int wq[4]; /* allocate local queue */
+ wq[wqsym]=locptr; /* record local level */
+ wq[wqsp]=Zsp; /* and stk ptr */
+ wq[wqloop]=getlabel(); /* and looping label */
+ wq[wqlab]=getlabel(); /* and exit label */
+ addwhile(wq); /* add entry to queue */
+ /* (for "break" statement) */
+ printlabel(wq[wqloop]);col();nl(); /* loop label */
+ test(wq[wqlab]); /* see if true */
+ statement(); /* if so, do a statement */
+ Zsp = modstk(wq[wqsp]); /* zap local vars: 9/25/80 gtf */
+ jump(wq[wqloop]); /* loop to label */
+ printlabel(wq[wqlab]);col();nl(); /* exit label */
+ locptr=wq[wqsym]; /* deallocate locals */
+ delwhile(); /* delete queue entry */
+ }
+/* */
+/* "return" statement */
+/* */
+doreturn()
+ {
+ /* if not end of statement, get an expression */
+ if(endst()==0)expression();
+ modstk(0); /* clean up stk */
+ zret(); /* and exit function */
+ }
+/* */
+/* "break" statement */
+/* */
+dobreak()
+ {
+ int *ptr;
+ /* see if any "whiles" are open */
+ if ((ptr=readwhile())==0) return; /* no */
+ modstk((ptr[wqsp])); /* else clean up stk ptr */
+ jump(ptr[wqlab]); /* jump to exit label */
+ }
+/* */
+/* "continue" statement */
+/* */
+docont()
+ {
+ int *ptr;
+ /* see if any "whiles" are open */
+ if ((ptr=readwhile())==0) return; /* no */
+ modstk((ptr[wqsp])); /* else clean up stk ptr */
+ jump(ptr[wqloop]); /* jump to loop label */
+ }
+/* */
+/* "asm" pseudo-statement */
+/* */
+/* enters mode where assembly language statement are */
+/* passed intact through parser */
+doasm()
+{
+ cmode=0; /* mark mode as "asm" */
+ while (1) {
+ finline(); /* get and print lines */
+ if (match("#endasm")) break; /* until... */
+ if(eof)break;
+ outstr(line);
+ nl();
+ }
+ kill(); /* invalidate line */
+ cmode=1; /* then back to parse level */
+}
+/* >>>>> start of cc3 <<<<<<<<< */
+
+/* */
+/* Perform a function call */
+/* */
+/* called from heir11, this routine will either call */
+/* the named function, or if the supplied ptr is */
+/* zero, will call the contents of HL */
+callfunction(ptr)
+ char *ptr; /* symbol table entry (or 0) */
+{ int nargs;
+ nargs=0;
+ blanks(); /* already saw open paren */
+ if(ptr==0)zpush(); /* calling HL */
+ while(streq(line+lptr,")")==0)
+ {if(endst())break;
+ expression(); /* get an argument */
+ if(ptr==0)swapstk(); /* don't push addr */
+ zpush(); /* push argument */
+ nargs=nargs+2; /* count args*2 */
+ if (match(",")==0) break;
+ }
+ needbrack(")");
+ if(ptr)zcall(ptr);
+ else callstk();
+ Zsp=modstk(Zsp+nargs); /* clean up arguments */
+}
+junk()
+{ if(an(inbyte()))
+ while(an(ch()))gch();
+ else while(an(ch())==0)
+ {if(ch()==0)break;
+ gch();
+ }
+ blanks();
+}
+endst()
+{ blanks();
+ return ((streq(line+lptr,";")|(ch()==0)));
+}
+illname()
+{ error("illegal symbol name");junk();}
+multidef(sname)
+ char *sname;
+{ error("already defined");
+ comment();
+ outstr(sname);nl();
+}
+needbrack(str)
+ char *str;
+{
+ if (match(str)==0) {
+ error("missing bracket");
+ comment();outstr(str);nl();
+ }
+}
+needlval()
+{ error("must be lvalue");
+}
+findglb(sname)
+ char *sname;
+{ char *ptr;
+ ptr=startglb;
+ while(ptr!=glbptr) {
+ if (astreq(sname,ptr,namemax)) return ptr;
+ ptr=ptr+symsiz;
+ }
+ return 0;
+}
+findloc(sname)
+ char *sname;
+{ char *ptr;
+ ptr=startloc;
+ while (ptr!=locptr) {
+ if(astreq(sname,ptr,namemax))return ptr;
+ ptr=ptr+symsiz;
+ }
+ return 0;
+}
+addglb(sname,id,typ,value,iptr)
+ char *sname,id,typ;
+ int value,iptr;
+{ char *ptr;
+ if(cptr=findglb(sname))return cptr;
+ if(glbptr>=endglb)
+ {error("global symbol table overflow");
+ return 0;
+ }
+ cptr=ptr=glbptr;
+ while (an(*ptr++ = *sname++)); /* copy name */
+ cptr[ident]=id;
+ cptr[type]=typ;
+ cptr[storage]=statik;
+ cptr[offset]=value;
+ cptr[offset+1]=value>>8;
+ cptr[initptr]=iptr&255;
+ cptr[initptr+1]=iptr>>8;
+ glbptr=glbptr+symsiz;
+ return cptr;
+}
+addloc(sname,id,typ,value)
+ char *sname,id,typ;
+ int value;
+{ char *ptr;
+ if(cptr=findloc(sname))return cptr;
+ if(locptr>=endloc)
+ {error("local symbol table overflow");
+ return 0;
+ }
+ cptr=ptr=locptr;
+ while(an(*ptr++ = *sname++)); /* copy name */
+ cptr[ident]=id;
+ cptr[type]=typ;
+ cptr[storage]=stkloc;
+ cptr[offset]=value;
+ cptr[offset+1]=value>>8;
+ locptr=locptr+symsiz;
+ return cptr;
+}
+/* Test if next input string is legal symbol name */
+symname(sname)
+ char *sname;
+{ int k;char c;
+ blanks();
+ if(alpha(ch())==0)return 0;
+ k=0;
+ while(an(ch()))sname[k++]=gch();
+ sname[k]=0;
+ return 1;
+ }
+/* Return next avail internal label number */
+getlabel()
+{ return(++nxtlab);
+}
+/* Print specified number as label */
+printlabel(label)
+ int label;
+{ outasm("cc");
+ outdec(label);
+}
+/* Test if given character is alpha */
+alpha(c)
+ char c;
+{ c=c&127;
+ return(((c>='a')&(c<='z'))|
+ ((c>='A')&(c<='Z'))|
+ (c=='_'));
+}
+// Test if given character is numeric
+numeric(c)
+ char c;
+{ c=c&127;
+ return ((c>='0')&(c<='9'));
+}
+// Test if given character is hexadecimal
+hexnum(c)
+ char c;
+{ c=c&127;
+ return (((c>='0')&(c<='9')) | ((c>='a')&(c<='f')) | ((c>='A')&(c<='F')));
+}
+/* Test if given character is alphanumeric */
+an(c)
+ char c;
+{ return((alpha(c))|(numeric(c)));
+}
+/* Print a carriage return and a string only to console */
+pl(str)
+ char *str;
+{ int k;
+ k=0;
+ putchar(eol);
+ while(str[k])putchar(str[k++]);
+}
+addwhile(ptr)
+ int ptr[];
+ {
+ int k;
+ if (wqptr==wqmax)
+ {error("too many active whiles");return;}
+ k=0;
+ while (k0)
+ {if((k==eol)|(lptr>=linemax))break;
+ line[lptr++]=k;
+ }
+ line[lptr]=0; /* append null */
+ lineno++; /* read one more line gtf 7/2/80 */
+ if(k<=0)
+ {fclose(unit);
+ if(input2)endinclude(); /* gtf 7/16/80 */
+ else input=0;
+ }
+ if(lptr)
+ {if((ctext)&(cmode))
+ {comment();
+ outstr(line);
+ nl();
+ }
+ lptr=0;
+ return;
+ }
+ }
+}
+/* >>>>>> start of cc4 <<<<<<< */
+
+keepch(c)
+ char c;
+{ mline[mptr]=c;
+ if(mptr=mpmax)error("line too long");
+ lptr=mptr=0;
+ while(line[lptr++]=mline[mptr++]);
+ lptr=0;
+ }
+addmac()
+{
+char sname[namesize];
+int k;
+
+ if (symname(sname)==0) {
+ illname();
+ kill();
+ return;
+ }
+ k=0;
+ while (putmac(sname[k++]));
+ while (ch()==' ' | ch()==9) gch();
+ while (putmac(gch()));
+ if (macptr>=macmax) error("macro table full");
+}
+putmac(c)
+ char c;
+{
+ macq[macptr]=c;
+ if(macptr='a') & (c<='z'))
+ c = c - 'a' + 'A';
+ return(c);
+/* end raise */}
+
+/* convert upper case to lower */
+/* ml 28/2/2012 */
+lower(c)
+char c;
+{
+ if((c>='A') & (c<='Z'))
+ c = c - 'A' + 'a';
+ return(c);
+/* end raise */}
+
+/* ------------------------------------------------------------- */
+
+/* >>>>>>> start of cc5 <<<<<<< */
+
+/* as of 5/5/81 rj */
+
+expression()
+{
+ int lval[2];
+ if(heir1(lval))rvalue(lval);
+}
+heir1(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir2(lval);
+ if (match("="))
+ {if(k==0){needlval();return 0;}
+ if (lval[1])zpush();
+ if(heir1(lval2))rvalue(lval2);
+ store(lval);
+ return 0;
+ }
+ else return k;
+}
+heir2(lval)
+ int lval[];
+{ int k,lval2[2];
+ k=heir3(lval);
+ blanks();
+ if(ch()!='|')return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("|"))
+ {zpush();
+ if(heir3(lval2)) rvalue(lval2);
+ zpop();
+ zor();
+ }
+ else return 0;
+ }
+}
+heir3(lval)
+ int lval[];
+{ int k,lval2[2];
+ k=heir4(lval);
+ blanks();
+ if(ch()!='^')return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("^"))
+ {zpush();
+ if(heir4(lval2))rvalue(lval2);
+ zpop();
+ zxor();
+ }
+ else return 0;
+ }
+}
+heir4(lval)
+ int lval[];
+{ int k,lval2[2];
+ k=heir5(lval);
+ blanks();
+ if(ch()!='&')return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("&"))
+ {zpush();
+ if(heir5(lval2))rvalue(lval2);
+ zpop();
+ zand();
+ }
+ else return 0;
+ }
+}
+heir5(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir6(lval);
+ blanks();
+ if((streq(line+lptr,"==")==0)&
+ (streq(line+lptr,"!=")==0))return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("=="))
+ {zpush();
+ if(heir6(lval2))rvalue(lval2);
+ zpop();
+ zeq();
+ }
+ else if (match("!="))
+ {zpush();
+ if(heir6(lval2))rvalue(lval2);
+ zpop();
+ zne();
+ }
+ else return 0;
+ }
+}
+heir6(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir7(lval);
+ blanks();
+ if((streq(line+lptr,"<")==0)&
+ (streq(line+lptr,">")==0)&
+ (streq(line+lptr,"<=")==0)&
+ (streq(line+lptr,">=")==0))return k;
+ if(streq(line+lptr,">>"))return k;
+ if(streq(line+lptr,"<<"))return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("<="))
+ {zpush();
+ if(heir7(lval2))rvalue(lval2);
+ zpop();
+ if(cptr=lval[0])
+ if(cptr[ident]==pointer)
+ {ule();
+ continue;
+ }
+ if(cptr=lval2[0])
+ if(cptr[ident]==pointer)
+ {ule();
+ continue;
+ }
+ zle();
+ }
+ else if (match(">="))
+ {zpush();
+ if(heir7(lval2))rvalue(lval2);
+ zpop();
+ if(cptr=lval[0])
+ if(cptr[ident]==pointer)
+ {uge();
+ continue;
+ }
+ if(cptr=lval2[0])
+ if(cptr[ident]==pointer)
+ {uge();
+ continue;
+ }
+ zge();
+ }
+ else if((streq(line+lptr,"<"))&
+ (streq(line+lptr,"<<")==0))
+ {inbyte();
+ zpush();
+ if(heir7(lval2))rvalue(lval2);
+ zpop();
+ if(cptr=lval[0])
+ if(cptr[ident]==pointer)
+ {ult();
+ continue;
+ }
+ if(cptr=lval2[0])
+ if(cptr[ident]==pointer)
+ {ult();
+ continue;
+ }
+ zlt();
+ }
+ else if((streq(line+lptr,">"))&
+ (streq(line+lptr,">>")==0))
+ {inbyte();
+ zpush();
+ if(heir7(lval2))rvalue(lval2);
+ zpop();
+ if(cptr=lval[0])
+ if(cptr[ident]==pointer)
+ {ugt();
+ continue;
+ }
+ if(cptr=lval2[0])
+ if(cptr[ident]==pointer)
+ {ugt();
+ continue;
+ }
+ zgt();
+ }
+ else return 0;
+ }
+}
+/* >>>>>> start of cc6 <<<<<< */
+
+heir7(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir8(lval);
+ blanks();
+ if((streq(line+lptr,">>")==0)&
+ (streq(line+lptr,"<<")==0))return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match(">>"))
+ {zpush();
+ if(heir8(lval2))rvalue(lval2);
+ zpop();
+ asr();
+ }
+ else if (match("<<"))
+ {zpush();
+ if(heir8(lval2))rvalue(lval2);
+ zpop();
+ asl();
+ }
+ else return 0;
+ }
+}
+heir8(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir9(lval);
+ blanks();
+ if((ch()!='+')&(ch()!='-'))return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("+"))
+ {zpush();
+ if(heir9(lval2))rvalue(lval2);
+ if(cptr=lval[0])
+ if((cptr[ident]==pointer)&
+ (cptr[type]==cint))
+ doublereg();
+ zpop();
+ zadd();
+ }
+ else if (match("-"))
+ {zpush();
+ if(heir9(lval2))rvalue(lval2);
+ if(cptr=lval[0])
+ if((cptr[ident]==pointer)&
+ (cptr[type]==cint))
+ doublereg();
+ zpop();
+ zsub();
+ }
+ else return 0;
+ }
+}
+heir9(lval)
+ int lval[];
+{
+ int k,lval2[2];
+ k=heir10(lval);
+ blanks();
+ if((ch()!='*')&(ch()!='/')&
+ (ch()!='%'))return k;
+ if(k)rvalue(lval);
+ while(1)
+ {if (match("*"))
+ {zpush();
+ if(heir9(lval2))rvalue(lval2);
+ zpop();
+ mult();
+ }
+ else if (match("/"))
+ {zpush();
+ if(heir10(lval2))rvalue(lval2);
+ zpop();
+ div();
+ }
+ else if (match("%"))
+ {zpush();
+ if(heir10(lval2))rvalue(lval2);
+ zpop();
+ zmod();
+ }
+ else return 0;
+ }
+}
+heir10(lval)
+ int lval[];
+{
+ int k;
+ char *ptr;
+ if(match("++"))
+ {if((k=heir10(lval))==0)
+ {needlval();
+ return 0;
+ }
+ if(lval[1])zpush();
+ rvalue(lval);
+ inc();
+ ptr=lval[0];
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ inc();
+ store(lval);
+ return 0;
+ }
+ else if(match("--"))
+ {if((k=heir10(lval))==0)
+ {needlval();
+ return 0;
+ }
+ if(lval[1])zpush();
+ rvalue(lval);
+ dec();
+ ptr=lval[0];
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ dec();
+ store(lval);
+ return 0;
+ }
+ else if (match("-"))
+ {k=heir10(lval);
+ if (k) rvalue(lval);
+ neg();
+ return 0;
+ }
+ else if(match("*"))
+ {k=heir10(lval);
+ if(k)rvalue(lval);
+ lval[1]=cint;
+ if(ptr=lval[0])lval[1]=ptr[type];
+ lval[0]=0;
+ return 1;
+ }
+ else if(match("&"))
+ {k=heir10(lval);
+ if(k==0)
+ {error("illegal address");
+ return 0;
+ }
+ else if(lval[1])return 0;
+ else
+ {immed();
+ outname(ptr=lval[0]);
+ nl();
+ lval[1]=ptr[type];
+ return 0;
+ }
+ }
+ else
+ {k=heir11(lval);
+ if(match("++"))
+ {if(k==0)
+ {needlval();
+ return 0;
+ }
+ if(lval[1])zpush();
+ rvalue(lval);
+ inc();
+ ptr=lval[0];
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ inc();
+ store(lval);
+ dec();
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ dec();
+ return 0;
+ }
+ else if(match("--"))
+ {if(k==0)
+ {needlval();
+ return 0;
+ }
+ if(lval[1])zpush();
+ rvalue(lval);
+ dec();
+ ptr=lval[0];
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ dec();
+ store(lval);
+ inc();
+ if((ptr[ident]==pointer)&
+ (ptr[type]==cint))
+ inc();
+ return 0;
+ }
+ else return k;
+ }
+ }
+/* >>>>>> start of cc7 <<<<<< */
+
+heir11(lval)
+ int *lval;
+{ int k;char *ptr;
+ k=primary(lval);
+ ptr=lval[0];
+ blanks();
+ if((ch()=='[')|(ch()=='('))
+ while(1)
+ {if(match("["))
+ {if(ptr==0)
+ {error("can't subscript");
+ junk();
+ needbrack("]");
+ return 0;
+ }
+ else if(ptr[ident]==pointer)rvalue(lval);
+ else if(ptr[ident]!=array)
+ {error("can't subscript");
+ k=0;
+ }
+ zpush();
+ expression();
+ needbrack("]");
+ if(ptr[type]==cint)doublereg();
+ zpop();
+ zadd();
+ lval[1]=ptr[type];
+ /* 4/1/81 - after subscripting, not ptr anymore */
+ lval[0]=0;
+ k=1;
+ }
+ else if(match("("))
+ {if(ptr==0)
+ {callfunction(0);
+ }
+ else if(ptr[ident]!=function)
+ {rvalue(lval);
+ callfunction(0);
+ }
+ else callfunction(ptr);
+ k=lval[0]=0;
+ }
+ else return k;
+ }
+ if(ptr==0)return k;
+ if(ptr[ident]==function)
+ {immed();
+ outname(ptr);
+ nl();
+ return 0;
+ }
+ return k;
+}
+primary(lval)
+ int *lval;
+{ char *ptr,sname[namesize];int num[1];
+ int k;
+ if(match("("))
+ {k=heir1(lval);
+ needbrack(")");
+ return k;
+ }
+ if(symname(sname))
+ {if(ptr=findloc(sname))
+ {getloc(ptr);
+ lval[0]=ptr;
+ lval[1]=ptr[type];
+ if(ptr[ident]==pointer)lval[1]=cint;
+ if(ptr[ident]==array)return 0;
+ else return 1;
+ }
+ if(ptr=findglb(sname))
+ if(ptr[ident]!=function)
+ {lval[0]=ptr;
+ lval[1]=0;
+ if(ptr[ident]!=array)return 1;
+ immed();
+ outname(ptr);nl();
+ lval[1]=ptr[type];
+ return 0;
+ }
+ ptr=addglb(sname,function,cint,0,-1);
+ lval[0]=ptr;
+ lval[1]=0;
+ return 0;
+ }
+ if(constant(num))
+ return(lval[0]=lval[1]=0);
+ else
+ {error("invalid expression");
+ immed();outdec(0);nl();
+ junk();
+ return 0;
+ }
+ }
+store(lval)
+ int *lval;
+{ if (lval[1]==0)putmem(lval[0]);
+ else putstk(lval[1]);
+}
+rvalue(lval)
+ int *lval;
+{ if((lval[0] != 0) & (lval[1] == 0))
+ getmem(lval[0]);
+ else indirect(lval[1]);
+}
+test(label)
+ int label;
+{
+ needbrack("(");
+ expression();
+ needbrack(")");
+ testjump(label);
+}
+constant(val)
+ int val[];
+{
+ if (number(val)) {
+ immed();
+ outdec(val[0]);
+ }
+ else if (pstr(val)) {
+ immed();
+ outdec(val[0]);
+ }
+ else if (qstr(val)) {
+ immed();
+ printlabel(litlab);
+ outbyte('+');
+ outdec(val[0]);
+ }
+ else
+ return 0;
+ nl();
+ return 1;
+}
+// get a numeric value from the source file
+number(val)
+int val[];
+{
+int k,minus;
+char c;
+
+ k=minus=1;
+ while (k) {
+ k=0;
+ if (match("+")) k=1;
+ if (match("-")) {
+ minus=(-minus);
+ k=1;
+ }
+ }
+ // check if hexadecimal value
+ if ((ch()=='0') & (nch()=='x')) {
+ // remove first two characters ("0x")
+ inchar();inchar();
+ // make sure the next value is legal
+ if (hexnum(ch())==0) return 0;
+ // continue to read hexadecimal value
+ while (hexnum(ch())) {
+ c=raise(inbyte());
+ if (numeric(c)!=0)
+ k=k*16+(c-'0');
+ else
+ k=k*16+(c-'A')+10;
+ }
+ if (minus<0) k=(-k);
+ val[0]=k;
+ return 1;
+ }
+ // check if decimal value
+ else if (numeric(ch())!=0) {
+ while (numeric(ch())) {
+ c=inbyte();
+ k=k*10+(c-'0');
+ }
+ if (minus<0) k=(-k);
+ val[0]=k;
+ return 1;
+ }
+ else
+ return 0;
+}
+pstr(val)
+int val[];
+{
+int k;
+char c;
+
+ k=0;
+ if (match("'")==0) return 0;
+ while((c=gch())!=39)
+ k=(k&255)*256 + (c&127);
+ val[0]=k;
+ return 1;
+}
+qstr(val)
+int val[];
+{
+char c;
+
+ if (match("\"")==0) return 0;
+ val[0]=litptr;
+ while (ch()!='"')
+ {if(ch()==0)break;
+ if(litptr>=litmax)
+ {error("string space exhausted");
+ while(match("\"")==0)
+ if(gch()==0)break;
+ return 1;
+ }
+ litq[litptr++]=gch();
+ }
+ gch();
+ litq[litptr++]=0;
+ return 1;
+}
+/* >>>>>> start of cc8 <<<<<<< */
+
+/* Begin a comment line for the assembler */
+comment()
+{ outbyte(';');
+}
+
+/* Put out assembler info before any code is generated */
+header()
+{ comment();
+ outstr(BANNER);
+ nl();
+ comment();
+ outstr(VERSION);
+ nl();
+ comment();
+ outstr(AUTHOR);
+ nl();
+ comment();
+ nl();
+ if (mainflg) { /* do stuff needed for first */
+ ol("code");
+ ol("org #0000"); /* assembler file. */
+ ot("ld hl,"); outdec(stackptr); nl(); /* set up stack */
+ ol("ld sp,hl");
+ zcall("main"); /* call the code generated by small-c */
+ }
+}
+/* Print any assembler stuff needed after all code */
+trailer()
+{ /* ol("END"); */ /*...note: commented out! */
+
+ nl(); /* 6 May 80 rj errorsummary() now goes to console */
+ comment();
+ outstr(" --- End of Compilation ---");
+ nl();
+}
+/* Print out a name such that it won't annoy the assembler */
+/* (by matching anything reserved, like opcodes.) */
+/* gtf 4/7/80 */
+outname(sname)
+char *sname;
+{ int len, i,j;
+
+ outasm("__");
+ len = strlen(sname);
+ if (len>(asmpref+asmsuff)) {
+ i = asmpref;
+ len = len-asmpref-asmsuff;
+ while(i-- > 0)
+ outbyte(lower(*sname++));
+ while(len-- > 0)
+ sname++;
+ while(*sname)
+ outbyte(lower(*sname++));
+ }
+ else outasm(sname);
+/* end outname */}
+/* Fetch a static memory cell into the primary register */
+getmem(sym)
+ char *sym;
+{
+int padr;
+
+ if ((sym[ident]!=pointer)&(sym[type]==cchar)) {
+ ot("ld a,(");
+ outname(sym+name);
+ outasm(")");
+ nl();
+ callrts("ccsxt");
+ } else if (sym[type]==cport) {
+ padr=sym[offset] & 0xff;
+ ot("in a,(");outdec(padr);outasm(")");nl();
+ callrts("ccsxt");
+ } else {
+ ot("ld hl,(");
+ outname(sym+name);
+ outasm(")");
+ nl();
+ }
+}
+/* Fetch the address of the specified symbol */
+/* into the primary register */
+getloc(sym)
+ char *sym;
+{
+int off_val;
+
+ immed();
+ off_val = ((sym[offset]&255)+((sym[offset+1]&255)<<8))-Zsp;
+ off_val &= 0xffff;
+ outdec(off_val);
+ nl();
+ ol("add hl,sp");
+}
+/* Store the primary register into the specified */
+/* static memory cell */
+putmem(sym)
+ char *sym;
+{
+int padr;
+
+ if((sym[ident]!=pointer)&(sym[type]==cchar)) {
+ ol("ld a,l");
+ ot("ld (");
+ outname(sym+name);
+ outasm("),a");
+ } else if (sym[type]==cport) {
+ padr=sym[offset] & 0xff;
+ ol("ld a,l");
+ ot("out (");outdec(padr);outasm("),a");nl();
+ } else {
+ ot("ld (");
+ outname(sym+name);
+ outasm("),hl");
+ }
+
+ nl();
+ }
+/* Store the specified object type in the primary register */
+/* at the address on the top of the stack */
+putstk(typeobj)
+char typeobj;
+{ zpop();
+ if(typeobj==cint)
+ callrts("ccpint");
+ else { ol("ld a,l"); /* per Ron Cain: gtf 9/25/80 */
+ ol("ld (de),a");
+ }
+ }
+/* Fetch the specified object type indirect through the */
+/* primary register into the primary register */
+indirect(typeobj)
+ char typeobj;
+{ if(typeobj==cchar)callrts("ccgchar");
+ else callrts("ccgint");
+}
+/* Swap the primary and secondary registers */
+swap()
+{ ol("xchg");
+}
+/* Print partial instruction to get an immediate value */
+/* into the primary register */
+immed()
+{ ot("ld hl,");
+}
+/* Push the primary register onto the stack */
+zpush()
+{ ol("push hl");
+ Zsp=Zsp-2;
+}
+/* Pop the top of the stack into the secondary register */
+zpop()
+{ ol("pop de");
+ Zsp=Zsp+2;
+}
+/* Swap the primary register and the top of the stack */
+swapstk()
+{ ol("ex (sp),hl");
+}
+/* Call the specified subroutine name */
+zcall(sname)
+ char *sname;
+{ ot("call ");
+ outname(sname);
+ nl();
+}
+/* Call a run-time library routine */
+callrts(sname)
+char *sname;
+{
+ ot("call ");
+ outasm(sname);
+ nl();
+/*end callrts*/}
+
+/* Return from subroutine */
+zret()
+{ ol("RET");
+}
+/* Perform subroutine call to value on top of stack */
+callstk()
+{ immed();
+ outasm("$+5");
+ nl();
+ swapstk();
+ ol("jp (hl)");
+ Zsp=Zsp+2; /* corrected 5 May 81 rj */
+ }
+/* Jump to specified internal label number */
+jump(label)
+ int label;
+{ ot("jp ");
+ printlabel(label);
+ nl();
+ }
+/* Test the primary register and jump if false to label */
+testjump(label)
+ int label;
+{ ol("ld a,h");
+ ol("or l");
+ ot("jp z,");
+ printlabel(label);
+ nl();
+ }
+/* Print pseudo-op to define a byte */
+defbyte()
+{ ot("db ");
+}
+/*Print pseudo-op to define storage */
+defstorage()
+{ ot("ds ");
+}
+/* Print pseudo-op to define a word */
+defword()
+{ ot("dw ");
+}
+/* Modify the stack pointer to the new value indicated */
+modstk(newsp)
+ int newsp;
+ { int k;
+ k=newsp-Zsp;
+ if(k==0)return newsp;
+ if(k>=0)
+ {if(k<7)
+ {if(k&1)
+ {ol("inc sp");
+ k--;
+ }
+ while(k)
+ {ol("pop bc");
+ k=k-2;
+ }
+ return newsp;
+ }
+ }
+ if(k<0)
+ {if(k>-7)
+ {if(k&1)
+ {ol("dec sp");
+ k++;
+ }
+ while(k)
+ {ol("push bc");
+ k=k+2;
+ }
+ return newsp;
+ }
+ }
+ swap();
+ immed();outdec(k);nl();
+ ol("add hl,sp");
+ ol("ld sp,hl");
+ swap();
+ return newsp;
+}
+/* Double the primary register */
+doublereg()
+{ ol("add hl,hl");
+}
+/* Add the primary and secondary registers */
+/* (results in primary) */
+zadd()
+{ ol("add hl,de");
+}
+/* Subtract the primary register from the secondary */
+/* (results in primary) */
+zsub()
+{ callrts("ccsub");
+}
+/* Multiply the primary and secondary registers */
+/* (results in primary */
+mult()
+{ callrts("ccmult");
+}
+/* Divide the secondary register by the primary */
+/* (quotient in primary, remainder in secondary) */
+div()
+{ callrts("ccdiv");
+}
+/* Compute remainder (mod) of secondary register divided */
+/* by the primary */
+/* (remainder in primary, quotient in secondary) */
+zmod()
+{ div();
+ swap();
+ }
+/* Inclusive 'or' the primary and the secondary registers */
+/* (results in primary) */
+zor()
+ {callrts("ccor");}
+/* Exclusive 'or' the primary and seconday registers */
+/* (results in primary) */
+zxor()
+ {callrts("ccxor");}
+/* 'And' the primary and secondary registers */
+/* (results in primary) */
+zand()
+ {callrts("ccand");}
+/* Arithmetic shift right the secondary register number of */
+/* times in primary (results in primary) */
+asr()
+ {callrts("ccasr");}
+/* Arithmetic left shift the secondary register number of */
+/* times in primary (results in primary) */
+asl()
+ {callrts("ccasl");}
+/* Form two's complement of primary register */
+neg()
+ {callrts("ccneg");}
+/* Form one's complement of primary register */
+com()
+ {callrts("cccom");}
+/* Increment the primary register by one */
+inc()
+ {ol("inc hl");}
+/* Decrement the primary register by one */
+dec()
+ {ol("dec hl");}
+
+/* Following are the conditional operators */
+/* They compare the secondary register against the primary */
+/* and put a literal 1 in the primary if the condition is */
+/* true, otherwise they clear the primary register */
+
+/* Test for equal */
+zeq()
+ {callrts("cceq");}
+/* Test for not equal */
+zne()
+ {callrts("ccne");}
+/* Test for less than (signed) */
+zlt()
+ {callrts("cclt");}
+/* Test for less than or equal to (signed) */
+zle()
+ {callrts("ccle");}
+/* Test for greater than (signed) */
+zgt()
+ {callrts("ccgt");}
+/* Test for greater than or equal to (signed) */
+zge()
+ {callrts("ccge");}
+/* Test for less than (unsigned) */
+ult()
+ {callrts("ccult");}
+/* Test for less than or equal to (unsigned) */
+ule()
+ {callrts("ccule");}
+/* Test for greater than (unsigned) */
+ugt()
+ {callrts("ccugt");}
+/* Test for greater than or equal to (unsigned) */
+uge()
+ {callrts("ccuge");}
+
+/* <<<<< End of small-c compiler >>>>> */
+
Index: trunk/tools/c80/AS80.EXE
===================================================================
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Index: trunk/tools/c80/AS80.EXE
===================================================================
--- trunk/tools/c80/AS80.EXE (nonexistent)
+++ trunk/tools/c80/AS80.EXE (revision 65)
trunk/tools/c80/AS80.EXE
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+application/octet-stream
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Index: trunk/tools/c80/C80DOS.txt
===================================================================
--- trunk/tools/c80/C80DOS.txt (nonexistent)
+++ trunk/tools/c80/C80DOS.txt (revision 65)
@@ -0,0 +1,524 @@
+
+
+ c80dos.doc
+
+ >>> Small-C Version 1-N Compiler Documentation <<<
+
+ NOTE: C80DOS.EXE is the MSDOS compiled binary for running on
+ a standard PC class machine which emits 8080 assembler
+ that can then be assembled and loaded on the PC using
+ lasm.cpm and load.cpm with the zrun.com CP/M emulator.
+ The final output (or any of the intermediate output in
+ 8080 assembler or Intel HEX format) can then be ported
+ to the CP/M machine by telecommunicating with a any of
+ a myriad of programs or by writing the disk directly
+ using something like the Uniform.exe program or its
+ equivalent. Hopefully, in the near future, a Z80
+ opcodeversion of the compiler as well as PC executable
+ versions of lasm and load will be finished. (RDK)
+
+
+ Available in the directory is a compiler for a
+ subset of the language C. It consists of the two files C80.C
+ (compiler) and C80LIB.I80 (runtime library) It is in source
+ form and is free to anyone wishing to use it.
+ Characteristics of the compiler are as follows:
+
+ (1) It supports a subset of the language C. (see the
+ book "C A Programming Language", by Brian Kernighan and
+ Dennis Ritchie.) (2) It is written in C itself. (3) It is
+ syntactically identical to the C on UNIX (unlike some other
+ small C compilers and interpreters). (4) It produces as
+ output a text file suitable for input to an 8080 assembler.
+ (5) It is a stand-alone single-pass compiler (which means it
+ does its own syntax checking and parsing and produces no
+ intermediate files). (6) It can compile itself. This means
+ any processor supporting C can be used to develop this small
+ C compiler for any other processor.
+
+ The intention behind the writing of this compiler was to
+ bring the C language to small computers. It was developed
+ primarily on a 8080 system with 40 K bytes and a single
+ mini-floppy. Consequently, an effort was made to keep the
+ compiler small in order to fit within limited memory, and
+ intermediate files were avoided in order to conserve floppy
+ space.
+
+
+ COMPILER SPECIFICATIONS
+
+ As of this writing, the compiler supports the following:
+
+ (1) Data type declarations can be:
+
+ - "char" (8 bits)
+ - "int" (16 bits)
+ - (by placing an "*" before the variable name, a pointer
+ can be formed to the respective type of
+ data element).
+
+ (2) Arrays:
+
+ - single dimension (vector) arrays can be
+ of type "char" or "int".
+
+ (3) Expressions:
+
+ - unary operators:
+ "-" (minus)
+ "*" (indirection)
+ "&" (address of)
+ "++" (increment, either prefix or postfix)
+ "--" (decrement, either prefix of postfix)
+ - binary operators:
+ "+" (addition)
+ "-" (subtraction)
+ "*" (multiplication)
+ "/" (division)
+ "%" (mod, i.e. remainder from division)
+ "|" (inclusive 'or')
+ "^" (exclusive 'or')
+ "&" (logical 'and')
+ "==" (test for equal)
+ "!=" (test for not equal)
+ "<" (test for less than)
+ "<=" (test for less than or equal to)
+ ">" (test for greater than)
+ ">=" (test for greater than or equal to)
+ "<<" (arithmetic left shift)
+ ">>" (arithmetic right shift)
+ - primaries:
+ -array[expression]
+ -function(arg1, arg2,...,argn)
+ -constant
+ -decimal number
+ -quoted string ("sample string")
+ -primed string ('a' or 'Z' or 'ab')
+ -local variable (or pointer)
+ -global (static) variable (or pointer)
+
+ (4) Program control:
+
+ -if(expression)statement;
+ -if(expression) statement;
+ else statement;
+ -while (expression) statement;
+ -break;
+ -continue;
+ -return;
+ -return expression;
+ -; (null statement)
+ -{statement; statement; ... statement;}
+ (compound statement)
+
+ (5) Pointers:
+
+ -local and static pointers can contain the
+ address of "char" or "int" data elements.
+
+ (6) Compiler commands:
+
+ - #define name string (pre-processor will replace
+ name by string throughout text.)
+ - #include filename (allows program to include other
+ files within this compilation.)
+ - #asm (not supported by standard C)
+ Allows all code between "#asm" and "#endasm"
+ to be passed unchanged to the target
+ assembler. This command is actually a statement
+ and may appear in the context:
+ "if (expression) #asm...#endasm else..."
+
+ (7) Miscellaneous:
+
+ -Expression evaluation maintains the same hierarchy
+ as standard C.
+
+ -Function calls are defined as
+ any primary followed by an open paren, so legal forms
+ include:
+
+ variable();
+ array[expression]();
+ constant();
+ function()();
+
+ -Pointer arithmetic takes into account the data
+ type of the destination (e.g. pointer++ will increment
+ by two if pointer was declared "int *pointer").
+
+ -Pointer compares generated unsigned
+ compares (since addresses are not signed numbers).
+
+ -Often used pieces of code
+ (i.e. storing the primary register indirect through the
+ top of the stack) generate calls to library routines to
+ shorten the amount of code generated.
+
+ -Generated code is "pure" (i.e. the code may be placed
+ in Read Only Memory). Code, literals, and variables
+ are kept in separate sections of memory.
+
+ -The generated code is re-entrant. Everytime a function
+ is called, its local variables refer to a new stack
+ frame. By way of example, the compiler uses
+ recursive-descent for most of its parsing, which relies
+ heavily on re-entrant (recursive) functions.
+
+
+ COMPILER RESTRICTIONS
+
+ Since recent stages of compiler check-out have been done
+ both on an 8080 system and on UNIX, language syntax appears
+ to be identical (within the given subset) between this small
+ C compiler and the standard UNIX compiler.
+
+
+ Not supported yet are:
+
+ (1) Structures.
+ (2) Multi-dimensional arrays.
+ (3) Floating point, long integer, or unsigned data types.
+ (4) Function calls returning anything but "int".
+ (5) The unaries "!", "~", and "sizeof".
+ (6) The control binary operators "&&", "||", and "?:".
+ (7) The declaration specifiers "auto", "static", "extern",
+ and "register".
+ (8) The statements "for", "switch", "case",
+ and "default."
+ (9) The use of arguments within a "#define" command.
+
+
+ Compiler restrictions include:
+
+ (1) Since it is a single-pass compiler, undefined names
+ are not detected and are assumed to be function names not yet
+ defined. If this assumption is incorrect, the undefined
+ reference will not appear until the compiled program is
+ assembled.
+
+ (2) No optimizing is done. The code produced is sound
+ and capable of re-entrancy, but no attempt is made to
+ optimize either for code size or speed. It was assumed a
+ post-processor optimizer would later be written for the
+ target machine.
+
+ (3) Since the target assembler is of unknown
+ characteristics, no attempt is made to produce pseudo-ops to
+ declare static variables as internal or external.
+
+ (4) Constants are not evaluated by the compiler. That
+ is, the line of code:
+
+ X = 1+2;
+
+ would generated code to add "1" and "2" at runtime. The
+ results are correct, but unnecessary code is the penalty.
+
+
+ ASSEMBLY LANGUAGE INTERFACE
+
+ Interfacing to assembly language is relatively
+ straight-forward. The "#asm ... #endasm" construct allows
+ the user to place assembly language code directly into the
+ control context. Since it is considered by the compiler to
+ be a single statement, it may appear in such forms as:
+
+ while(1) #asm ... #endasm
+
+ or
+
+ if (expression) #asm...#endasm else...
+
+ Due to the workings of the preprocessor which must be
+ suppressed in this construct, the pseudo-op "#asm" must be
+ the last item before the carriage return on the end of the
+ line (i.e. the text between #asm and the is thrown
+ away), and the "#endasm" pseudo-op must appear on a line by
+ itself (i.e. everything after #endasm is also thrown away).
+ Since the parser is completely free-format outside of these
+ execeptions, the expected format is as follows:
+
+ if (expression) #asm
+ ...
+ ...
+ #endasm
+ else statement;
+
+ Note a semicolon is not required after the #endasm since
+ the end of context is obvious to the compiler. Assembly
+ language code within the "#asm ... #endasm" context has
+ access to all global symbols and functions by name. It is up
+ to the programmer to know the data type of the symbol
+ (whether "char" or "int" implies a byte access or a word
+ access). Stack locals and arguments may be retrieved by
+ offset (see STACK FRAME). External assembly language
+ routines invoked by function calls from the c-code have
+ access to all registers and do not have to restore them prior
+ to exit. They may push items on the stack as well, but must
+ pop them off before exit. It is the responsibility of the
+ calling program to remove arguments from the stack after a
+ function call. This must not be done by the function itself.
+ There is no limit to the number of bytes the function may
+ push onto the stack, providing they are removed prior to
+ returning. Since parameters are passed by value, the
+ paramters on the stack may be modified by the called program.
+
+
+
+ STACK FRAME
+
+ The stack is used extensively by the compiler. Function
+ arguments are pushed onto the stack as they are encountered
+ between parentheses (note, this is opposite that of standard
+ C, which means routines expressly retrieving arguments from
+ the stack rather than declaring them by name must beware).
+ By the definition of the language, parameter passing is "call
+ by value". For example the following code would be produced
+ for the C statement:
+
+ function(X, Y, z());
+
+ LHLD X
+ PUSH H
+ LHLD Y
+ PUSH H
+ CALL z
+ PUSH H
+ CALL function
+ POP B
+ POP B
+ POP B
+
+ Notice, the compiler cleans up the stack after the call
+ using a simple algorithm to use the least number of bytes.
+
+ Local variables allocate as much stack space as is
+ needed, and are then assigned the current value of the stack
+ pointer (after the allocation) as their address.
+
+ int X;
+
+ would produce:
+
+ PUSH B
+
+ which merely allocates room on the stack for 2 bytes (not
+ initialized to any value). References to the local variable
+ X will now be made to the stack pointer + 0. If another
+ declaration is made:
+
+ char array[3];
+
+ the code would be:
+
+ DCX SP
+ PUSH B
+
+ Array[0] would be at SP+0, array[1] would be at SP+1,
+ array[2] would be at SP+2, and X would now be at SP+3. Thus,
+ assembly language code using "#asm...#endasm" cannot access
+ local variables by name, but must know how many intervening
+ bytes have been allocated between the declaration of the
+ variable and its use. It is worth pointing out local
+ declarations allocate only as much stack space as is
+ required, including an odd number of bytes, whereas function
+ arguments always consist of two bytes apiece. In the event
+ the argument was type "char" (8 bits), the most significant
+ byte of the 2-byte value is a sign-extension of the lower
+ byte.
+
+
+
+ OPERATING THE COMPILER
+
+ The small C compiler begins by asking the user for a
+ number of options regarding the expected compilation. Since
+ it was easier to ask questions than to pull arguments from a
+ command line (which is in no way similar between the 8080
+ developmental system and UNIX), this was the preferred
+ method.
+
+ The questions asked are as follows:
+
+ Do you want the c-text to appear?
+
+ This gives the user the option of interleaving the
+ source code into the output file. Response is Y or N. If Y,
+ a semicolon will be placed at the start of each input line
+ (to force a comment to the 8080 assembler) and the input
+ lines will be printed where appropriate. If the answer is N,
+ only the generated 8080 code will be output.
+
+ Do you wish the globals to be defined?
+
+ This question is primarily a developmental aid between
+ machines. If the answer is Y, all static symbols will
+ allocate storage within the module being compiled. This is
+ the normal method. If N, no storage will be allocated, but
+ symbol references will still be made in the normal way.
+ Essentially, this question allows the user to specify all or
+ none of the static symbols external. It is to be considered
+ a temporary measure.
+
+ Starting number for labels?
+
+ This lets the user supply the first label number
+ generated by the compiler for it internal labels (which will
+ typically be "ccXXXXX", where XXXXX is a decimal number
+ increasing with each label). This option allows modules to
+ be compiled separately and later appended on the source level
+ without generating multi-defined labels.
+
+ Output filename?
+
+ This question gets from the user the name of the file to
+ be created. A null line sends output to the user's terminal.
+
+ Input filename?
+
+ This question gets from the user the name of the C
+ module to use as input. The question will be repeated each
+ time a name is supplied, allowing the user to create an
+ output file consisting of many separate input files (it
+ behaves as if the user had appended them together and
+ submitted only the one file). A null line response ends the
+ compilation process.
+
+
+ COMPILING THE COMPILER
+
+ The power of the compiler lies in the fact it can
+ compile itself. This allows a user to "bootstrap" the
+ compiler onto a new machine without excessive recoding.
+
+ To compile the compiler under the UNIX operating system,
+ the appropriate command is:
+
+ % cc C80.c -lS
+
+ which will invoke the UNIX C-compiler and the UNIX linker to
+ create the runnable file "a.out". This file may be renamed
+ as needed and used. No other files are needed.
+
+ In order to create a compiler for a new machine, the
+ user will need to compile the compiler into the language of
+ the destination processor. The procedure currently used to
+ create the compiler for my 8080 system is as follows:
+
+ (1) Edit the file C80.c to modify two lines of code:
+
+ -change the line of code
+
+ #include
+ to
+ #define NULL 0
+
+ (this is done since the "stdio.h" I/O header file
+ contains unparsable lines for the small compiler, and the
+ line defining NULL is the only line of "stdio.h" needed by
+ the compiler).
+
+ -change the line of code
+
+ #define eol 10
+ to
+ #define eol 13
+
+ (this is done since my 8080 system uses for the end
+ of line character, and UNIX uses the "newline" character).
+
+
+ (2) Invoke the compiler (by typing "a.out" or whatever other
+ name it was given.
+
+ (3) Answer the questions by the compiler to use the file
+ C80.c as input and to produce the file C80.I80
+ as output.
+
+ (4) Append the files C80.I80 and C80LIB.I80 (the code for the
+ compiler and the code for the runtime library,
+ respectively).
+
+ (5) Assemble the combined file using some 8080 assembler.
+
+ (6) Execute the created run file.
+
+ Currently, the 8080 assembler used must possess the
+ abilities to handle symbol names unique to 8 characters and
+ to recognize lower-case symbol names as unique from their
+ upper-case equivalent. This is due to the fact the compiler
+ recognizes 8-character names and passes all static variable
+ and function names intact to the assembler. There are a few
+ symbol names within the compiler which are not unique until
+ the 7th character and which have "upper-case twins". These
+ discourage the use of the KL-10's MACN80 since it folds
+ lower-case to upper case and does not recognize 8-character
+ names. It may be used, however, if the user is aware of
+ these limitations and chooses symbol names within these
+ restrictions.
+
+
+ THE FUTURE OF THE COMPILER
+
+ That part of the compiler which produces code for the
+ 8080 is all together in the final section of the compiler.
+ Routines used by the compiler to produce code are kept short
+ and are commented. Changing this compiler to produce code
+ for any other machine is a matter of changing only these few
+ routines, and does not entail digging around through the
+ internals of the program. I would expect the change to
+ another machine could be made in an afternoon providing the
+ target machine had the following attributes:
+
+ (1) A stack, preferably running backwards as items
+ are pushed onto it.
+
+ (2) Two sixteen-bit registers. In the 8080 these
+ are the HL register pair (the primary register
+ to the compiler) and the DE register pair (the
+ secondary register).
+
+ (3) An assembler (or cross-assembler).
+
+
+ Since the compiler is just now on its feet and subject
+ to feedback from users, it is expected many changes will be
+ made to it. Already planned changes (in order of expected
+ addition) are:
+
+ (1) Constants will be pre-evaluated by the
+ compiler. Something like x=1+2*3 will become
+ x=7 prior to generating any code.
+
+ (2) Structures will be added. This is one of the
+ powers of C. Its omission has always been
+ considered temporary.
+
+ (3) Assignment operators (+=, &=, etc.) will be
+ added.
+
+ (4) Missing unary and binary operators and
+ statements will be added.
+
+ (5) The expression parser will create intermediate
+ tree-structures of the expressions and will
+ walk through them before generating any code.
+ This will allow some optimization and will
+ allow the function arguments to be passed on
+ the stack in the same sequence as UNIX.
+
+ (6) A peep-hole optimizer will be added to improve
+ the generated code.
+
+ Many of these things represent a wish-list. Time will
+ be spent only when it becomes available. Any volunteer help
+ in any of these areas would be appreciated.
+
+ Questions should be directed to Ron Cain here at SRI
+ either at extension 3860 or at CAIN@SRI-KL.
+
+
+
+
+
\ No newline at end of file
Index: trunk/c/hello.asm
===================================================================
--- trunk/c/hello.asm (nonexistent)
+++ trunk/c/hello.asm (revision 65)
@@ -0,0 +1,770 @@
+; <><><> Small-C V1.2 DOS--CP/M Cross Compiler <><><>
+; <><><><><> CP/M Large String Space Version <><><><><>
+; <><><><><><><><><><> By Ron Cain <><><><><><><><><><>
+;
+ code
+ org #0000
+ ld hl,3072
+ ld sp,hl
+ call __main
+;//---------------------------------------------------------------------------------------
+;// Project: light8080 SOC WiCores Solutions
+;//
+;// File name: hello.c (February 04, 2012)
+;//
+;// Writer: Moti Litochevski
+;//
+;// Description:
+;// This file contains a simple program written in Small-C that sends a string to
+;// the UART and then switches to echo received bytes.
+;//
+;// Revision History:
+;//
+;// Rev
+;//
+;//---------------------------------------------------------------------------------------
+;#include ..\tools\c80\c80.lib
+;#asm
+;
+;------------------------------------------------------------------
+; Small-C Run-time Librray
+;
+; V4d As of July 16, 1980 (gtf)
+; Added EXIT() function
+;------------------------------------------------------------------
+;
+;Fetch a single byte from the address in HL and sign extend into HL
+ccgchar:
+ ld a,(hl)
+ccsxt:
+ ld l,a
+ rlca
+ sbc a
+ ld h,a
+ ret
+;Fetch a full 16-bit integer from the address in HL
+ccgint:
+ ld a,(hl)
+ inc hl
+ ld h,(hl)
+ ld l,a
+ ret
+;Store a single byte from HL at the address in DE
+ccpchar:
+ ld a,l
+ ld (de),a
+ ret
+;Store a 16-bit integer in HL at the address in DE
+ccpint:
+ ld a,l
+ ld (de),a
+ inc de
+ ld a,h
+ ld (de),a
+ ret
+;Inclusive "or" HL and DE into HL
+ccor:
+ ld a,l
+ or e
+ ld l,a
+ ld a,h
+ or d
+ ld h,a
+ ret
+;Exclusive "or" HL and DE into HL
+ccxor:
+ ld a,l
+ xor e
+ ld l,a
+ ld a,h
+ xor d
+ ld h,a
+ ret
+;"And" HL and DE into HL
+ccand:
+ ld a,l
+ and e
+ ld l,a
+ ld a,h
+ and d
+ ld h,a
+ ret
+;Test if HL = DE and set HL = 1 if true else 0
+cceq:
+ call cccmp
+ ret z
+ dec hl
+ ret
+;Test if DE ~= HL
+ccne:
+ call cccmp
+ ret nz
+ dec hl
+ ret
+;Test if DE > HL (signed)
+ccgt:
+ ex de,hl
+ call cccmp
+ ret c
+ dec hl
+ ret
+;Test if DE <= HL (signed)
+ccle:
+ call cccmp
+ ret z
+ ret c
+ dec hl
+ ret
+;Test if DE >= HL (signed)
+ccge:
+ call cccmp
+ ret nc
+ dec hl
+ ret
+;Test if DE < HL (signed)
+cclt:
+ call cccmp
+ ret c
+ dec hl
+ ret
+; Signed compare of DE and HL
+; Performs DE - HL and sets the conditions:
+; Carry reflects sign of difference (set means DE < HL)
+; Zero/non-zero set according to equality.
+cccmp:
+ ld a,e
+ sub l
+ ld e,a
+ ld a,d
+ sbc h
+ ld hl,1
+ jp m,cccmp1
+ or e ;"OR" resets carry
+ ret
+cccmp1:
+ or e
+ scf ;set carry to signal minus
+ ret
+;Test if DE >= HL (unsigned)
+ccuge:
+ call ccucmp
+ ret nc
+ dec hl
+ ret
+;Test if DE < HL (unsigned)
+ccult:
+ call ccucmp
+ ret c
+ dec hl
+ ret
+;Test if DE > HL (unsigned)
+ccugt:
+ ex de,hl
+ call ccucmp
+ ret c
+ dec hl
+ ret
+;Test if DE <= HL (unsigned)
+ccule:
+ call ccucmp
+ ret z
+ ret c
+ dec hl
+ ret
+;Routine to perform unsigned compare
+;carry set if DE < HL
+;zero/nonzero set accordingly
+ccucmp:
+ ld a,d
+ cp h
+ jp nz,$+5
+ ld a,e
+ cp l
+ ld hl,1
+ ret
+;Shift DE arithmetically right by HL and return in HL
+ccasr:
+ ex de,hl
+ ld a,h
+ rla
+ ld a,h
+ rra
+ ld h,a
+ ld a,l
+ rra
+ ld l,a
+ dec e
+ jp nz,ccasr+1
+ ret
+;Shift DE arithmetically left by HL and return in HL
+ccasl:
+ ex de,hl
+ add hl,hl
+ dec e
+ jp nz,ccasl+1
+ ret
+;Subtract HL from DE and return in HL
+ccsub:
+ ld a,e
+ sub l
+ ld l,a
+ ld a,d
+ sbc h
+ ld h,a
+ ret
+;Form the two's complement of HL
+ccneg:
+ call cccom
+ inc hl
+ ret
+;Form the one's complement of HL
+cccom:
+ ld a,h
+ cpl
+ ld h,a
+ ld a,l
+ cpl
+ ld l,a
+ ret
+;Multiply DE by HL and return in HL
+ccmult:
+ ld b,h
+ ld c,l
+ ld hl,0
+ccmult1:
+ ld a,c
+ rrca
+ jp nc,$+4
+ add hl,de
+ xor a
+ ld a,b
+ rra
+ ld b,a
+ ld a,c
+ rra
+ ld c,a
+ or b
+ ret z
+ xor a
+ ld a,e
+ rla
+ ld e,a
+ ld a,d
+ rla
+ ld d,a
+ or e
+ ret z
+ jp ccmult1
+;Divide DE by HL and return quotient in HL, remainder in DE
+ccdiv:
+ ld b,h
+ ld c,l
+ ld a,d
+ xor b
+ push af
+ ld a,d
+ or a
+ call m,ccdeneg
+ ld a,b
+ or a
+ call m,ccbcneg
+ ld a,16
+ push af
+ ex de,hl
+ ld de,0
+ccdiv1:
+ add hl,hl
+ call ccrdel
+ jp z,ccdiv2
+ call cccmpbcde
+ jp m,ccdiv2
+ ld a,l
+ or 1
+ ld l,a
+ ld a,e
+ sub c
+ ld e,a
+ ld a,d
+ sbc b
+ ld d,a
+ccdiv2:
+ pop af
+ dec a
+ jp z,ccdiv3
+ push af
+ jp ccdiv1
+ccdiv3:
+ pop af
+ ret p
+ call ccdeneg
+ ex de,hl
+ call ccdeneg
+ ex de,hl
+ ret
+ccdeneg:
+ ld a,d
+ cpl
+ ld d,a
+ ld a,e
+ cpl
+ ld e,a
+ inc de
+ ret
+ccbcneg:
+ ld a,b
+ cpl
+ ld b,a
+ ld a,c
+ cpl
+ ld c,a
+ inc bc
+ ret
+ccrdel:
+ ld a,e
+ rla
+ ld e,a
+ ld a,d
+ rla
+ ld d,a
+ or e
+ ret
+cccmpbcde:
+ ld a,e
+ sub c
+ ld a,d
+ sbc b
+ ret
+;// UART IO registers
+;port (128) UDATA; // uart data register used for both transmit and receive
+;port (129) UBAUDL; // low byte of baud rate register
+;port (130) UBAUDH; // low byte of baud rate register
+;port (131) USTAT; // uart status register
+;// digital IO ports registers
+;port (132) P1REG; // output port1 - used as first attenuator control
+;port (133) P2REG; // output port2 - used as low digit LCD
+;port (134) P3REG; // output port3 - used as high digit LCD
+;port (135) P4REG; // output port4
+;// simulation end register
+;// writing any value to this port will end the verilog simulation when using tb_l80soc
+;// test bench.
+;port (255) SIMEND;
+;// registers bit fields definition
+;// uart status register decoding
+;#define UTXBUSY 1
+;#define URXFULL 16
+;// globals
+;char rxbyte; // byte received from the uart
+;int tstary[2] = {1234, 5678};
+;//---------------------------------------------------------------------------------------
+;// send a single byte to the UART
+;sendbyte(by)
+__sendbyte:
+;char by;
+;{
+; while (USTAT & UTXBUSY);
+cc2:
+ in a,(131)
+ call ccsxt
+ push hl
+ ld hl,1
+ pop de
+ call ccand
+ ld a,h
+ or l
+ jp z,cc3
+ jp cc2
+cc3:
+; UDATA = by;
+ ld hl,2
+ add hl,sp
+ call ccgchar
+ ld a,l
+ out (128),a
+
+;}
+ ret
+;// check if a byte was received by the uart
+;getbyte()
+__getbyte:
+;{
+; if (USTAT & URXFULL) {
+ in a,(131)
+ call ccsxt
+ push hl
+ ld hl,16
+ pop de
+ call ccand
+ ld a,h
+ or l
+ jp z,cc4
+; rxbyte = UDATA;
+ in a,(128)
+ call ccsxt
+ ld a,l
+ ld (__rxbyte),a
+; return 1;
+ ld hl,1
+ ret
+; }
+; else
+ jp cc5
+cc4:
+; return 0;
+ ld hl,0
+ ret
+cc5:
+;}
+ ret
+;// send new line to the UART
+;nl()
+__nl:
+;{
+; sendbyte(13);
+ ld hl,13
+ push hl
+ call __sendbyte
+ pop bc
+; sendbyte(10);
+ ld hl,10
+ push hl
+ call __sendbyte
+ pop bc
+;}
+ ret
+;// sends a string to the UART
+;printstr(sptr)
+__printstr:
+;char *sptr;
+;{
+; while (*sptr != 0)
+cc6:
+ ld hl,2
+ add hl,sp
+ call ccgint
+ call ccgchar
+ push hl
+ ld hl,0
+ pop de
+ call ccne
+ ld a,h
+ or l
+ jp z,cc7
+; sendbyte(*sptr++);
+ ld hl,2
+ add hl,sp
+ push hl
+ call ccgint
+ inc hl
+ pop de
+ call ccpint
+ dec hl
+ call ccgchar
+ push hl
+ call __sendbyte
+ pop bc
+ jp cc6
+cc7:
+;}
+ ret
+;// sends a decimal value to the UART
+;printdec(dval)
+__printdec:
+;int dval;
+;{
+; if (dval<0) {
+ ld hl,2
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,0
+ pop de
+ call cclt
+ ld a,h
+ or l
+ jp z,cc8
+; sendbyte('-');
+ ld hl,45
+ push hl
+ call __sendbyte
+ pop bc
+; dval = -dval;
+ ld hl,2
+ add hl,sp
+ push hl
+ ld hl,4
+ add hl,sp
+ call ccgint
+ call ccneg
+ pop de
+ call ccpint
+; }
+; outint(dval);
+cc8:
+ ld hl,2
+ add hl,sp
+ call ccgint
+ push hl
+ call __outint
+ pop bc
+;}
+ ret
+;// function copied from c80dos.c
+;outint(n)
+__outint:
+;int n;
+;{
+;int q;
+ push bc
+; q = n/10;
+ ld hl,0
+ add hl,sp
+ push hl
+ ld hl,6
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,10
+ pop de
+ call ccdiv
+ pop de
+ call ccpint
+; if (q) outint(q);
+ ld hl,0
+ add hl,sp
+ call ccgint
+ ld a,h
+ or l
+ jp z,cc9
+ ld hl,0
+ add hl,sp
+ call ccgint
+ push hl
+ call __outint
+ pop bc
+; sendbyte('0'+(n-q*10));
+cc9:
+ ld hl,48
+ push hl
+ ld hl,6
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,4
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,10
+ pop de
+ call ccmult
+ pop de
+ call ccsub
+ pop de
+ add hl,de
+ push hl
+ call __sendbyte
+ pop bc
+;}
+ pop bc
+ ret
+;// sends a hexadecimal value to the UART
+;printhex(hval)
+__printhex:
+;int hval;
+;{
+;int q;
+ push bc
+; q = hval/16;
+ ld hl,0
+ add hl,sp
+ push hl
+ ld hl,6
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,16
+ pop de
+ call ccdiv
+ pop de
+ call ccpint
+; if (q) printhex(q);
+ ld hl,0
+ add hl,sp
+ call ccgint
+ ld a,h
+ or l
+ jp z,cc10
+ ld hl,0
+ add hl,sp
+ call ccgint
+ push hl
+ call __printhex
+ pop bc
+; q = hval-q*16;
+cc10:
+ ld hl,0
+ add hl,sp
+ push hl
+ ld hl,6
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,4
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,16
+ pop de
+ call ccmult
+ pop de
+ call ccsub
+ pop de
+ call ccpint
+; if (q > 9)
+ ld hl,0
+ add hl,sp
+ call ccgint
+ push hl
+ ld hl,9
+ pop de
+ call ccgt
+ ld a,h
+ or l
+ jp z,cc11
+; sendbyte('A'+q-10);
+ ld hl,65
+ push hl
+ ld hl,2
+ add hl,sp
+ call ccgint
+ pop de
+ add hl,de
+ push hl
+ ld hl,10
+ pop de
+ call ccsub
+ push hl
+ call __sendbyte
+ pop bc
+; else
+ jp cc12
+cc11:
+; sendbyte('0'+q);
+ ld hl,48
+ push hl
+ ld hl,2
+ add hl,sp
+ call ccgint
+ pop de
+ add hl,de
+ push hl
+ call __sendbyte
+ pop bc
+cc12:
+;}
+ pop bc
+ ret
+;// program main routine
+;main()
+__main:
+;{
+; // configure UART baud rate - set to 9600 for 30MHz clock
+; // BAUD = round(//16) = round(30e6/9600/16) = 195
+; UBAUDL = 195;
+ ld hl,195
+ ld a,l
+ out (129),a
+
+; UBAUDH = 0;
+ ld hl,0
+ ld a,l
+ out (130),a
+
+; // print message
+; printstr("Hello World!!!"); nl();
+ ld hl,cc1+0
+ push hl
+ call __printstr
+ pop bc
+ call __nl
+; printstr("Dec value: "); printdec(tstary[1]); nl();
+ ld hl,cc1+15
+ push hl
+ call __printstr
+ pop bc
+ ld hl,__tstary
+ push hl
+ ld hl,1
+ add hl,hl
+ pop de
+ add hl,de
+ call ccgint
+ push hl
+ call __printdec
+ pop bc
+ call __nl
+; printstr("Hex value: 0x"); printhex(tstary[0]); nl();
+ ld hl,cc1+27
+ push hl
+ call __printstr
+ pop bc
+ ld hl,__tstary
+ push hl
+ ld hl,0
+ add hl,hl
+ pop de
+ add hl,de
+ call ccgint
+ push hl
+ call __printhex
+ pop bc
+ call __nl
+; printstr("Echoing received bytes: "); nl();
+ ld hl,cc1+41
+ push hl
+ call __printstr
+ pop bc
+ call __nl
+;
+; // loop forever
+; while (1) {
+cc13:
+ ld hl,1
+ ld a,h
+ or l
+ jp z,cc14
+; // check if a new byte was received
+; if (getbyte())
+ call __getbyte
+ ld a,h
+ or l
+ jp z,cc15
+; // echo the received byte to the UART
+; sendbyte(rxbyte);
+ ld a,(__rxbyte)
+ call ccsxt
+ push hl
+ call __sendbyte
+ pop bc
+; }
+cc15:
+ jp cc13
+cc14:
+;}
+ ret
+;//---------------------------------------------------------------------------------------
+;// Th.. Th.. Th.. Thats all folks !!!
+;//---------------------------------------------------------------------------------------
+cc1:
+ db 72,101,108,108,111,32,87,111,114,108
+ db 100,33,33,33,0,68,101,99,32,118
+ db 97,108,117,101,58,32,0,72,101,120
+ db 32,118,97,108,117,101,58,32,48,120
+ db 0,69,99,104,111,105,110,103,32,114
+ db 101,99,101,105,118,101,100,32,98,121
+ db 116,101,115,58,32,0
+__rxbyte:
+ ds 1
+__tstary:
+ db -46,4,46,22
+
+; --- End of Compilation ---
Index: trunk/c/HELLO.LST
===================================================================
--- trunk/c/HELLO.LST (nonexistent)
+++ trunk/c/HELLO.LST (revision 65)
@@ -0,0 +1,886 @@
+AS80 Assembler for i8080-Z180 [1.11]. Page 1
+--------------------------------- HELLO.ASM ----------------------------------
+
+-------------------------------- Symbol Table --------------------------------
+
+ Symbol Value Decimal
+
+ ccand : $0029 41
+ ccasl : $0099 153
+ ccasr : $008b 139
+ ccbcneg : $011c 284
+ cccmp : $0056 86
+ cccmpbcde : $012c 300
+ cccmp1 : $0063 99
+ cccom : $00ac 172
+ ccdeneg : $0114 276
+ ccdiv : $00d3 211
+ ccdiv1 : $00e9 233
+ ccdiv2 : $0100 256
+ ccdiv3 : $0109 265
+ cceq : $0030 48
+ ccgchar : $0007 7
+ ccge : $004a 74
+ ccgint : $000d 13
+ ccgt : $003c 60
+ ccle : $0043 67
+ cclt : $0050 80
+ ccmult : $00b3 179
+ ccmult1 : $00b8 184
+ ccne : $0036 54
+ ccneg : $00a7 167
+ ccor : $001b 27
+ ccpchar : $0012 18
+ ccpint : $0015 21
+ ccrdel : $0124 292
+ ccsub : $00a0 160
+ ccsxt : $0008 8
+ ccucmp : $0080 128
+ ccuge : $0066 102
+ ccugt : $0072 114
+ ccule : $0079 121
+ ccult : $006c 108
+ ccxor : $0022 34
+ cc1 : $035c 860
+ cc10 : $027a 634
+ cc11 : $02cf 719
+ cc12 : $02e1 737
+ cc13 : $033f 831
+ cc14 : $035b 859
+ cc15 : $0358 856
+ cc2 : $0131 305
+ cc3 : $0144 324
+ cc4 : $016d 365
+ cc5 : $0171 369
+ cc6 : $0183 387
+ cc7 : $01b3 435
+ cc8 : $01e3 483
+ cc9 : $0221 545
+ __getbyte : $014f 335
+ __main : $02e3 739
+ __nl : $0172 370
+ __outint : $01f0 496
+ __printdec : $01b4 436
+ __printhex : $0249 585
+ __printstr : $0183 387
+ AS80 Assembler for i8080-Z180 [1.11]. Page 2
+--------------------------------- HELLO.ASM ----------------------------------
+
+ __rxbyte : $039e 926
+ __sendbyte : $0131 305
+ __tstary : $039f 927
+ __8080__ : $0001 1
+
+62 labels used
+
+770 lines read, no errors in pass 1.
+ AS80 Assembler for i8080-Z180 [1.11]. Page 3
+--------------------------------- HELLO.ASM ----------------------------------
+
+ ; <><><> Small-C V1.2 DOS--CP/M Cross Compiler <
+ ; <><><><><> CP/M Large String Space Version <><><
+ ; <><><><><><><><><><> By Ron Cain <><><><><><><><
+ ;
+ code
+0000 = org #0000
+0000 : 21000c ld hl,3072
+0003 : f9 ld sp,hl
+0004 : cde302 call __main
+ ;//---------------------------------------------------
+ ;// Project: light8080 SOC WiCores Solutions
+ ;//
+ ;// File name: hello.c (February 04, 2012)
+ ;//
+ ;// Writer: Moti Litochevski
+ ;//
+ ;// Description:
+ ;// This file contains a simple program written in Sm
+ ;// the UART and then switches to echo received bytes
+ ;//
+ ;// Revision History:
+ ;//
+ ;// Rev
+ ;//
+ ;//---------------------------------------------------
+ ;#include ..\tools\c80\c80.lib
+ ;#asm
+ ;
+ ;-----------------------------------------------------
+ ; Small-C Run-time Librray
+ ;
+ ; V4d As of July 16, 1980 (gtf)
+ ; Added EXIT() function
+ ;-----------------------------------------------------
+ ;
+ ;Fetch a single byte from the address in HL and sign e
+0007 : ccgchar:
+0007 : 7e ld a,(hl)
+0008 : ccsxt:
+0008 : 6f ld l,a
+0009 : 07 rlca
+000a : 9f sbc a
+000b : 67 ld h,a
+000c : c9 ret
+ ;Fetch a full 16-bit integer from the address in HL
+000d : ccgint:
+000d : 7e ld a,(hl)
+000e : 23 inc hl
+000f : 66 ld h,(hl)
+0010 : 6f ld l,a
+0011 : c9 ret
+ ;Store a single byte from HL at the address in DE
+0012 : ccpchar:
+0012 : 7d ld a,l
+0013 : 12 ld (de),a
+0014 : c9 ret
+ ;Store a 16-bit integer in HL at the address in DE
+0015 : ccpint:
+0015 : 7d ld a,l
+0016 : 12 ld (de),a
+0017 : 13 inc de
+0018 : 7c ld a,h
+ AS80 Assembler for i8080-Z180 [1.11]. Page 4
+--------------------------------- HELLO.ASM ----------------------------------
+
+0019 : 12 ld (de),a
+001a : c9 ret
+ ;Inclusive "or" HL and DE into HL
+001b : ccor:
+001b : 7d ld a,l
+001c : b3 or e
+001d : 6f ld l,a
+001e : 7c ld a,h
+001f : b2 or d
+0020 : 67 ld h,a
+0021 : c9 ret
+ ;Exclusive "or" HL and DE into HL
+0022 : ccxor:
+0022 : 7d ld a,l
+0023 : ab xor e
+0024 : 6f ld l,a
+0025 : 7c ld a,h
+0026 : aa xor d
+0027 : 67 ld h,a
+0028 : c9 ret
+ ;"And" HL and DE into HL
+0029 : ccand:
+0029 : 7d ld a,l
+002a : a3 and e
+002b : 6f ld l,a
+002c : 7c ld a,h
+002d : a2 and d
+002e : 67 ld h,a
+002f : c9 ret
+ ;Test if HL = DE and set HL = 1 if true else 0
+0030 : cceq:
+0030 : cd5600 call cccmp
+0033 : c8 ret z
+0034 : 2b dec hl
+0035 : c9 ret
+ ;Test if DE ~= HL
+0036 : ccne:
+0036 : cd5600 call cccmp
+0039 : c0 ret nz
+003a : 2b dec hl
+003b : c9 ret
+ ;Test if DE > HL (signed)
+003c : ccgt:
+003c : eb ex de,hl
+003d : cd5600 call cccmp
+0040 : d8 ret c
+0041 : 2b dec hl
+0042 : c9 ret
+ ;Test if DE <= HL (signed)
+0043 : ccle:
+0043 : cd5600 call cccmp
+0046 : c8 ret z
+0047 : d8 ret c
+0048 : 2b dec hl
+0049 : c9 ret
+ ;Test if DE >= HL (signed)
+004a : ccge:
+004a : cd5600 call cccmp
+004d : d0 ret nc
+004e : 2b dec hl
+004f : c9 ret
+ ;Test if DE < HL (signed)
+ AS80 Assembler for i8080-Z180 [1.11]. Page 5
+--------------------------------- HELLO.ASM ----------------------------------
+
+0050 : cclt:
+0050 : cd5600 call cccmp
+0053 : d8 ret c
+0054 : 2b dec hl
+0055 : c9 ret
+ ; Signed compare of DE and HL
+ ; Performs DE - HL and sets the conditions:
+ ; Carry reflects sign of difference (set means DE < HL
+ ; Zero/non-zero set according to equality.
+0056 : cccmp:
+0056 : 7b ld a,e
+0057 : 95 sub l
+0058 : 5f ld e,a
+0059 : 7a ld a,d
+005a : 9c sbc h
+005b : 210100 ld hl,1
+005e : fa6300 jp m,cccmp1
+0061 : b3 or e ;"OR" resets carry
+0062 : c9 ret
+0063 : cccmp1:
+0063 : b3 or e
+0064 : 37 scf ;set carry to signal minus
+0065 : c9 ret
+ ;Test if DE >= HL (unsigned)
+0066 : ccuge:
+0066 : cd8000 call ccucmp
+0069 : d0 ret nc
+006a : 2b dec hl
+006b : c9 ret
+ ;Test if DE < HL (unsigned)
+006c : ccult:
+006c : cd8000 call ccucmp
+006f : d8 ret c
+0070 : 2b dec hl
+0071 : c9 ret
+ ;Test if DE > HL (unsigned)
+0072 : ccugt:
+0072 : eb ex de,hl
+0073 : cd8000 call ccucmp
+0076 : d8 ret c
+0077 : 2b dec hl
+0078 : c9 ret
+ ;Test if DE <= HL (unsigned)
+0079 : ccule:
+0079 : cd8000 call ccucmp
+007c : c8 ret z
+007d : d8 ret c
+007e : 2b dec hl
+007f : c9 ret
+ ;Routine to perform unsigned compare
+ ;carry set if DE < HL
+ ;zero/nonzero set accordingly
+0080 : ccucmp:
+0080 : 7a ld a,d
+0081 : bc cp h
+0082 : c28700 jp nz,$+5
+0085 : 7b ld a,e
+0086 : bd cp l
+0087 : 210100 ld hl,1
+008a : c9 ret
+ ;Shift DE arithmetically right by HL and return in HL
+008b : ccasr:
+ AS80 Assembler for i8080-Z180 [1.11]. Page 6
+--------------------------------- HELLO.ASM ----------------------------------
+
+008b : eb ex de,hl
+008c : 7c ld a,h
+008d : 17 rla
+008e : 7c ld a,h
+008f : 1f rra
+0090 : 67 ld h,a
+0091 : 7d ld a,l
+0092 : 1f rra
+0093 : 6f ld l,a
+0094 : 1d dec e
+0095 : c28c00 jp nz,ccasr+1
+0098 : c9 ret
+ ;Shift DE arithmetically left by HL and return in HL
+0099 : ccasl:
+0099 : eb ex de,hl
+009a : 29 add hl,hl
+009b : 1d dec e
+009c : c29a00 jp nz,ccasl+1
+009f : c9 ret
+ ;Subtract HL from DE and return in HL
+00a0 : ccsub:
+00a0 : 7b ld a,e
+00a1 : 95 sub l
+00a2 : 6f ld l,a
+00a3 : 7a ld a,d
+00a4 : 9c sbc h
+00a5 : 67 ld h,a
+00a6 : c9 ret
+ ;Form the two's complement of HL
+00a7 : ccneg:
+00a7 : cdac00 call cccom
+00aa : 23 inc hl
+00ab : c9 ret
+ ;Form the one's complement of HL
+00ac : cccom:
+00ac : 7c ld a,h
+00ad : 2f cpl
+00ae : 67 ld h,a
+00af : 7d ld a,l
+00b0 : 2f cpl
+00b1 : 6f ld l,a
+00b2 : c9 ret
+ ;Multiply DE by HL and return in HL
+00b3 : ccmult:
+00b3 : 44 ld b,h
+00b4 : 4d ld c,l
+00b5 : 210000 ld hl,0
+00b8 : ccmult1:
+00b8 : 79 ld a,c
+00b9 : 0f rrca
+00ba : d2be00 jp nc,$+4
+00bd : 19 add hl,de
+00be : af xor a
+00bf : 78 ld a,b
+00c0 : 1f rra
+00c1 : 47 ld b,a
+00c2 : 79 ld a,c
+00c3 : 1f rra
+00c4 : 4f ld c,a
+00c5 : b0 or b
+00c6 : c8 ret z
+00c7 : af xor a
+ AS80 Assembler for i8080-Z180 [1.11]. Page 7
+--------------------------------- HELLO.ASM ----------------------------------
+
+00c8 : 7b ld a,e
+00c9 : 17 rla
+00ca : 5f ld e,a
+00cb : 7a ld a,d
+00cc : 17 rla
+00cd : 57 ld d,a
+00ce : b3 or e
+00cf : c8 ret z
+00d0 : c3b800 jp ccmult1
+ ;Divide DE by HL and return quotient in HL, remainder
+00d3 : ccdiv:
+00d3 : 44 ld b,h
+00d4 : 4d ld c,l
+00d5 : 7a ld a,d
+00d6 : a8 xor b
+00d7 : f5 push af
+00d8 : 7a ld a,d
+00d9 : b7 or a
+00da : fc1401 call m,ccdeneg
+00dd : 78 ld a,b
+00de : b7 or a
+00df : fc1c01 call m,ccbcneg
+00e2 : 3e10 ld a,16
+00e4 : f5 push af
+00e5 : eb ex de,hl
+00e6 : 110000 ld de,0
+00e9 : ccdiv1:
+00e9 : 29 add hl,hl
+00ea : cd2401 call ccrdel
+00ed : ca0001 jp z,ccdiv2
+00f0 : cd2c01 call cccmpbcde
+00f3 : fa0001 jp m,ccdiv2
+00f6 : 7d ld a,l
+00f7 : f601 or 1
+00f9 : 6f ld l,a
+00fa : 7b ld a,e
+00fb : 91 sub c
+00fc : 5f ld e,a
+00fd : 7a ld a,d
+00fe : 98 sbc b
+00ff : 57 ld d,a
+0100 : ccdiv2:
+0100 : f1 pop af
+0101 : 3d dec a
+0102 : ca0901 jp z,ccdiv3
+0105 : f5 push af
+0106 : c3e900 jp ccdiv1
+0109 : ccdiv3:
+0109 : f1 pop af
+010a : f0 ret p
+010b : cd1401 call ccdeneg
+010e : eb ex de,hl
+010f : cd1401 call ccdeneg
+0112 : eb ex de,hl
+0113 : c9 ret
+0114 : ccdeneg:
+0114 : 7a ld a,d
+0115 : 2f cpl
+0116 : 57 ld d,a
+0117 : 7b ld a,e
+0118 : 2f cpl
+0119 : 5f ld e,a
+ AS80 Assembler for i8080-Z180 [1.11]. Page 8
+--------------------------------- HELLO.ASM ----------------------------------
+
+011a : 13 inc de
+011b : c9 ret
+011c : ccbcneg:
+011c : 78 ld a,b
+011d : 2f cpl
+011e : 47 ld b,a
+011f : 79 ld a,c
+0120 : 2f cpl
+0121 : 4f ld c,a
+0122 : 03 inc bc
+0123 : c9 ret
+0124 : ccrdel:
+0124 : 7b ld a,e
+0125 : 17 rla
+0126 : 5f ld e,a
+0127 : 7a ld a,d
+0128 : 17 rla
+0129 : 57 ld d,a
+012a : b3 or e
+012b : c9 ret
+012c : cccmpbcde:
+012c : 7b ld a,e
+012d : 91 sub c
+012e : 7a ld a,d
+012f : 98 sbc b
+0130 : c9 ret
+ ;// UART IO registers
+ ;port (128) UDATA; // uart data register used for bot
+ ;port (129) UBAUDL; // low byte of baud rate register
+ ;port (130) UBAUDH; // low byte of baud rate register
+ ;port (131) USTAT; // uart status register
+ ;// digital IO ports registers
+ ;port (132) P1REG; // output port1 - used as firs
+ ;port (133) P2REG; // output port2 - used as low digi
+ ;port (134) P3REG; // output port3 - used as high dig
+ ;port (135) P4REG; // output port4
+ ;// simulation end register
+ ;// writing any value to this port will end the verilo
+ ;// test bench.
+ ;port (255) SIMEND;
+ ;// registers bit fields definition
+ ;// uart status register decoding
+ ;#define UTXBUSY 1
+ ;#define URXFULL 16
+ ;// globals
+ ;char rxbyte; // byte received from the uart
+ ;int tstary[2] = {1234, 5678};
+ ;//---------------------------------------------------
+ ;// send a single byte to the UART
+ ;sendbyte(by)
+0131 : __sendbyte:
+ ;char by;
+ ;{
+ ; while (USTAT & UTXBUSY);
+0131 : cc2:
+0131 : db83 in a,(131)
+0133 : cf call ccsxt
+0134 : e5 push hl
+0135 : 210100 ld hl,1
+0138 : d1 pop de
+0139 : cd2900 call ccand
+013c : 7c ld a,h
+ AS80 Assembler for i8080-Z180 [1.11]. Page 9
+--------------------------------- HELLO.ASM ----------------------------------
+
+013d : b5 or l
+013e : ca4401 jp z,cc3
+0141 : c33101 jp cc2
+0144 : cc3:
+ ; UDATA = by;
+0144 : 210200 ld hl,2
+0147 : 39 add hl,sp
+0148 : cd0700 call ccgchar
+014b : 7d ld a,l
+014c : d380 out (128),a
+
+ ;}
+014e : c9 ret
+ ;// check if a byte was received by the uart
+ ;getbyte()
+014f : __getbyte:
+ ;{
+ ; if (USTAT & URXFULL) {
+014f : db83 in a,(131)
+0151 : cf call ccsxt
+0152 : e5 push hl
+0153 : 211000 ld hl,16
+0156 : d1 pop de
+0157 : cd2900 call ccand
+015a : 7c ld a,h
+015b : b5 or l
+015c : ca6d01 jp z,cc4
+ ; rxbyte = UDATA;
+015f : db80 in a,(128)
+0161 : cf call ccsxt
+0162 : 7d ld a,l
+0163 : 329e03 ld (__rxbyte),a
+ ; return 1;
+0166 : 210100 ld hl,1
+0169 : c9 ret
+ ; }
+ ; else
+016a : c37101 jp cc5
+016d : cc4:
+ ; return 0;
+016d : 210000 ld hl,0
+0170 : c9 ret
+0171 : cc5:
+ ;}
+0171 : c9 ret
+ ;// send new line to the UART
+ ;nl()
+0172 : __nl:
+ ;{
+ ; sendbyte(13);
+0172 : 210d00 ld hl,13
+0175 : e5 push hl
+0176 : cd3101 call __sendbyte
+0179 : c1 pop bc
+ ; sendbyte(10);
+017a : 210a00 ld hl,10
+017d : e5 push hl
+017e : cd3101 call __sendbyte
+0181 : c1 pop bc
+ ;}
+0182 : c9 ret
+ ;// sends a string to the UART
+ AS80 Assembler for i8080-Z180 [1.11]. Page 10
+--------------------------------- HELLO.ASM ----------------------------------
+
+ ;printstr(sptr)
+0183 : __printstr:
+ ;char *sptr;
+ ;{
+ ; while (*sptr != 0)
+0183 : cc6:
+0183 : 210200 ld hl,2
+0186 : 39 add hl,sp
+0187 : cd0d00 call ccgint
+018a : cd0700 call ccgchar
+018d : e5 push hl
+018e : 210000 ld hl,0
+0191 : d1 pop de
+0192 : cd3600 call ccne
+0195 : 7c ld a,h
+0196 : b5 or l
+0197 : cab301 jp z,cc7
+ ; sendbyte(*sptr++);
+019a : 210200 ld hl,2
+019d : 39 add hl,sp
+019e : e5 push hl
+019f : cd0d00 call ccgint
+01a2 : 23 inc hl
+01a3 : d1 pop de
+01a4 : cd1500 call ccpint
+01a7 : 2b dec hl
+01a8 : cd0700 call ccgchar
+01ab : e5 push hl
+01ac : cd3101 call __sendbyte
+01af : c1 pop bc
+01b0 : c38301 jp cc6
+01b3 : cc7:
+ ;}
+01b3 : c9 ret
+ ;// sends a decimal value to the UART
+ ;printdec(dval)
+01b4 : __printdec:
+ ;int dval;
+ ;{
+ ; if (dval<0) {
+01b4 : 210200 ld hl,2
+01b7 : 39 add hl,sp
+01b8 : cd0d00 call ccgint
+01bb : e5 push hl
+01bc : 210000 ld hl,0
+01bf : d1 pop de
+01c0 : cd5000 call cclt
+01c3 : 7c ld a,h
+01c4 : b5 or l
+01c5 : cae301 jp z,cc8
+ ; sendbyte('-');
+01c8 : 212d00 ld hl,45
+01cb : e5 push hl
+01cc : cd3101 call __sendbyte
+01cf : c1 pop bc
+ ; dval = -dval;
+01d0 : 210200 ld hl,2
+01d3 : 39 add hl,sp
+01d4 : e5 push hl
+01d5 : 210400 ld hl,4
+01d8 : 39 add hl,sp
+01d9 : cd0d00 call ccgint
+ AS80 Assembler for i8080-Z180 [1.11]. Page 11
+--------------------------------- HELLO.ASM ----------------------------------
+
+01dc : cda700 call ccneg
+01df : d1 pop de
+01e0 : cd1500 call ccpint
+ ; }
+ ; outint(dval);
+01e3 : cc8:
+01e3 : 210200 ld hl,2
+01e6 : 39 add hl,sp
+01e7 : cd0d00 call ccgint
+01ea : e5 push hl
+01eb : cdf001 call __outint
+01ee : c1 pop bc
+ ;}
+01ef : c9 ret
+ ;// function copied from c80dos.c
+ ;outint(n)
+01f0 : __outint:
+ ;int n;
+ ;{
+ ;int q;
+01f0 : c5 push bc
+ ; q = n/10;
+01f1 : 210000 ld hl,0
+01f4 : 39 add hl,sp
+01f5 : e5 push hl
+01f6 : 210600 ld hl,6
+01f9 : 39 add hl,sp
+01fa : cd0d00 call ccgint
+01fd : e5 push hl
+01fe : 210a00 ld hl,10
+0201 : d1 pop de
+0202 : cdd300 call ccdiv
+0205 : d1 pop de
+0206 : cd1500 call ccpint
+ ; if (q) outint(q);
+0209 : 210000 ld hl,0
+020c : 39 add hl,sp
+020d : cd0d00 call ccgint
+0210 : 7c ld a,h
+0211 : b5 or l
+0212 : ca2102 jp z,cc9
+0215 : 210000 ld hl,0
+0218 : 39 add hl,sp
+0219 : cd0d00 call ccgint
+021c : e5 push hl
+021d : cdf001 call __outint
+0220 : c1 pop bc
+ ; sendbyte('0'+(n-q*10));
+0221 : cc9:
+0221 : 213000 ld hl,48
+0224 : e5 push hl
+0225 : 210600 ld hl,6
+0228 : 39 add hl,sp
+0229 : cd0d00 call ccgint
+022c : e5 push hl
+022d : 210400 ld hl,4
+0230 : 39 add hl,sp
+0231 : cd0d00 call ccgint
+0234 : e5 push hl
+0235 : 210a00 ld hl,10
+0238 : d1 pop de
+0239 : cdb300 call ccmult
+ AS80 Assembler for i8080-Z180 [1.11]. Page 12
+--------------------------------- HELLO.ASM ----------------------------------
+
+023c : d1 pop de
+023d : cda000 call ccsub
+0240 : d1 pop de
+0241 : 19 add hl,de
+0242 : e5 push hl
+0243 : cd3101 call __sendbyte
+0246 : c1 pop bc
+ ;}
+0247 : c1 pop bc
+0248 : c9 ret
+ ;// sends a hexadecimal value to the UART
+ ;printhex(hval)
+0249 : __printhex:
+ ;int hval;
+ ;{
+ ;int q;
+0249 : c5 push bc
+ ; q = hval/16;
+024a : 210000 ld hl,0
+024d : 39 add hl,sp
+024e : e5 push hl
+024f : 210600 ld hl,6
+0252 : 39 add hl,sp
+0253 : cd0d00 call ccgint
+0256 : e5 push hl
+0257 : 211000 ld hl,16
+025a : d1 pop de
+025b : cdd300 call ccdiv
+025e : d1 pop de
+025f : cd1500 call ccpint
+ ; if (q) printhex(q);
+0262 : 210000 ld hl,0
+0265 : 39 add hl,sp
+0266 : cd0d00 call ccgint
+0269 : 7c ld a,h
+026a : b5 or l
+026b : ca7a02 jp z,cc10
+026e : 210000 ld hl,0
+0271 : 39 add hl,sp
+0272 : cd0d00 call ccgint
+0275 : e5 push hl
+0276 : cd4902 call __printhex
+0279 : c1 pop bc
+ ; q = hval-q*16;
+027a : cc10:
+027a : 210000 ld hl,0
+027d : 39 add hl,sp
+027e : e5 push hl
+027f : 210600 ld hl,6
+0282 : 39 add hl,sp
+0283 : cd0d00 call ccgint
+0286 : e5 push hl
+0287 : 210400 ld hl,4
+028a : 39 add hl,sp
+028b : cd0d00 call ccgint
+028e : e5 push hl
+028f : 211000 ld hl,16
+0292 : d1 pop de
+0293 : cdb300 call ccmult
+0296 : d1 pop de
+0297 : cda000 call ccsub
+029a : d1 pop de
+ AS80 Assembler for i8080-Z180 [1.11]. Page 13
+--------------------------------- HELLO.ASM ----------------------------------
+
+029b : cd1500 call ccpint
+ ; if (q > 9)
+029e : 210000 ld hl,0
+02a1 : 39 add hl,sp
+02a2 : cd0d00 call ccgint
+02a5 : e5 push hl
+02a6 : 210900 ld hl,9
+02a9 : d1 pop de
+02aa : cd3c00 call ccgt
+02ad : 7c ld a,h
+02ae : b5 or l
+02af : cacf02 jp z,cc11
+ ; sendbyte('A'+q-10);
+02b2 : 214100 ld hl,65
+02b5 : e5 push hl
+02b6 : 210200 ld hl,2
+02b9 : 39 add hl,sp
+02ba : cd0d00 call ccgint
+02bd : d1 pop de
+02be : 19 add hl,de
+02bf : e5 push hl
+02c0 : 210a00 ld hl,10
+02c3 : d1 pop de
+02c4 : cda000 call ccsub
+02c7 : e5 push hl
+02c8 : cd3101 call __sendbyte
+02cb : c1 pop bc
+ ; else
+02cc : c3e102 jp cc12
+02cf : cc11:
+ ; sendbyte('0'+q);
+02cf : 213000 ld hl,48
+02d2 : e5 push hl
+02d3 : 210200 ld hl,2
+02d6 : 39 add hl,sp
+02d7 : cd0d00 call ccgint
+02da : d1 pop de
+02db : 19 add hl,de
+02dc : e5 push hl
+02dd : cd3101 call __sendbyte
+02e0 : c1 pop bc
+02e1 : cc12:
+ ;}
+02e1 : c1 pop bc
+02e2 : c9 ret
+ ;// program main routine
+ ;main()
+02e3 : __main:
+ ;{
+ ; // configure UART baud rate - set to 9600 for 30MHz
+ ; // BAUD = round(//16) = round(30e6
+ ; UBAUDL = 195;
+02e3 : 21c300 ld hl,195
+02e6 : 7d ld a,l
+02e7 : d381 out (129),a
+
+ ; UBAUDH = 0;
+02e9 : 210000 ld hl,0
+02ec : 7d ld a,l
+02ed : d382 out (130),a
+
+ ; // print message
+ AS80 Assembler for i8080-Z180 [1.11]. Page 14
+--------------------------------- HELLO.ASM ----------------------------------
+
+ ; printstr("Hello World!!!"); nl();
+02ef : 215c03 ld hl,cc1+0
+02f2 : e5 push hl
+02f3 : cd8301 call __printstr
+02f6 : c1 pop bc
+02f7 : cd7201 call __nl
+ ; printstr("Dec value: "); printdec(tstary[1]); nl();
+02fa : 216b03 ld hl,cc1+15
+02fd : e5 push hl
+02fe : cd8301 call __printstr
+0301 : c1 pop bc
+0302 : 219f03 ld hl,__tstary
+0305 : e5 push hl
+0306 : 210100 ld hl,1
+0309 : 29 add hl,hl
+030a : d1 pop de
+030b : 19 add hl,de
+030c : cd0d00 call ccgint
+030f : e5 push hl
+0310 : cdb401 call __printdec
+0313 : c1 pop bc
+0314 : cd7201 call __nl
+ ; printstr("Hex value: 0x"); printhex(tstary[0]); nl()
+0317 : 217703 ld hl,cc1+27
+031a : e5 push hl
+031b : cd8301 call __printstr
+031e : c1 pop bc
+031f : 219f03 ld hl,__tstary
+0322 : e5 push hl
+0323 : 210000 ld hl,0
+0326 : 29 add hl,hl
+0327 : d1 pop de
+0328 : 19 add hl,de
+0329 : cd0d00 call ccgint
+032c : e5 push hl
+032d : cd4902 call __printhex
+0330 : c1 pop bc
+0331 : cd7201 call __nl
+ ; printstr("Echoing received bytes: "); nl();
+0334 : 218503 ld hl,cc1+41
+0337 : e5 push hl
+0338 : cd8301 call __printstr
+033b : c1 pop bc
+033c : cd7201 call __nl
+ ;
+ ; // loop forever
+ ; while (1) {
+033f : cc13:
+033f : 210100 ld hl,1
+0342 : 7c ld a,h
+0343 : b5 or l
+0344 : ca5b03 jp z,cc14
+ ; // check if a new byte was received
+ ; if (getbyte())
+0347 : cd4f01 call __getbyte
+034a : 7c ld a,h
+034b : b5 or l
+034c : ca5803 jp z,cc15
+ ; // echo the received byte to the UART
+ ; sendbyte(rxbyte);
+034f : 3a9e03 ld a,(__rxbyte)
+0352 : cf call ccsxt
+ AS80 Assembler for i8080-Z180 [1.11]. Page 15
+--------------------------------- HELLO.ASM ----------------------------------
+
+0353 : e5 push hl
+0354 : cd3101 call __sendbyte
+0357 : c1 pop bc
+ ; }
+0358 : cc15:
+0358 : c33f03 jp cc13
+035b : cc14:
+ ;}
+035b : c9 ret
+ ;//---------------------------------------------------
+ ;// Th.. Th.. Th.. Thats all folks !!!
+ ;//---------------------------------------------------
+035c : cc1:
+035c : 48656c6c6f2057.. db 72,101,108,108,111,32,87,111,114,108
+0366 : 64212121004465.. db 100,33,33,33,0,68,101,99,32,118
+0370 : 616c75653a2000.. db 97,108,117,101,58,32,0,72,101,120
+037a : 2076616c75653a.. db 32,118,97,108,117,101,58,32,48,120
+0384 : 004563686f696e.. db 0,69,99,104,111,105,110,103,32,114
+038e : 65636569766564.. db 101,99,101,105,118,101,100,32,98,121
+0398 : 7465733a2000 db 116,101,115,58,32,0
+039e : __rxbyte:
+039e : 00 ds 1
+039f : __tstary:
+039f : d2042e16 db -46,4,46,22
+
+ ; --- End of Compilation ---
+No errors in pass 2.
Index: trunk/c/hello.c
===================================================================
--- trunk/c/hello.c (nonexistent)
+++ trunk/c/hello.c (revision 65)
@@ -0,0 +1,142 @@
+//---------------------------------------------------------------------------------------
+// Project: light8080 SOC WiCores Solutions
+//
+// File name: hello.c (February 04, 2012)
+//
+// Writer: Moti Litochevski
+//
+// Description:
+// This file contains a simple program written in Small-C that sends a string to
+// the UART and then switches to echo received bytes.
+//
+// Revision History:
+//
+// Rev
+//
+//---------------------------------------------------------------------------------------
+
+#include ..\tools\c80\c80.lib
+
+// UART IO registers
+port (128) UDATA; // uart data register used for both transmit and receive
+port (129) UBAUDL; // low byte of baud rate register
+port (130) UBAUDH; // low byte of baud rate register
+port (131) USTAT; // uart status register
+// digital IO ports registers
+port (132) P1REG; // output port1 - used as first attenuator control
+port (133) P2REG; // output port2 - used as low digit LCD
+port (134) P3REG; // output port3 - used as high digit LCD
+port (135) P4REG; // output port4
+// simulation end register
+// writing any value to this port will end the verilog simulation when using tb_l80soc
+// test bench.
+port (255) SIMEND;
+
+// registers bit fields definition
+// uart status register decoding
+#define UTXBUSY 1
+#define URXFULL 16
+
+// globals
+char rxbyte; // byte received from the uart
+int tstary[2] = {1234, 5678};
+
+//---------------------------------------------------------------------------------------
+// send a single byte to the UART
+sendbyte(by)
+char by;
+{
+ while (USTAT & UTXBUSY);
+ UDATA = by;
+}
+
+// check if a byte was received by the uart
+getbyte()
+{
+ if (USTAT & URXFULL) {
+ rxbyte = UDATA;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+// send new line to the UART
+nl()
+{
+ sendbyte(13);
+ sendbyte(10);
+}
+
+// sends a string to the UART
+printstr(sptr)
+char *sptr;
+{
+ while (*sptr != 0)
+ sendbyte(*sptr++);
+}
+
+// sends a decimal value to the UART
+printdec(dval)
+int dval;
+{
+ if (dval<0) {
+ sendbyte('-');
+ dval = -dval;
+ }
+ outint(dval);
+}
+
+// function copied from c80dos.c
+outint(n)
+int n;
+{
+int q;
+
+ q = n/10;
+ if (q) outint(q);
+ sendbyte('0'+(n-q*10));
+}
+
+// sends a hexadecimal value to the UART
+printhex(hval)
+int hval;
+{
+int q;
+
+ q = hval/16;
+ if (q) printhex(q);
+ q = hval-q*16;
+ if (q > 9)
+ sendbyte('A'+q-10);
+ else
+ sendbyte('0'+q);
+}
+
+// program main routine
+main()
+{
+ // configure UART baud rate - set to 9600 for 30MHz clock
+ // BAUD = round(//16) = round(30e6/9600/16) = 195
+ UBAUDL = 195;
+ UBAUDH = 0;
+
+ // print message
+ printstr("Hello World!!!"); nl();
+ printstr("Dec value: "); printdec(tstary[1]); nl();
+ printstr("Hex value: 0x"); printhex(tstary[0]); nl();
+ printstr("Echoing received bytes: "); nl();
+
+ // loop forever
+ while (1) {
+ // check if a new byte was received
+ if (getbyte())
+ // echo the received byte to the UART
+ sendbyte(rxbyte);
+ }
+}
+
+//---------------------------------------------------------------------------------------
+// Th.. Th.. Th.. Thats all folks !!!
+//---------------------------------------------------------------------------------------
+
Index: trunk/c/ram_image.v
===================================================================
--- trunk/c/ram_image.v (nonexistent)
+++ trunk/c/ram_image.v (revision 65)
@@ -0,0 +1,1058 @@
+//-----------------------------------------------------------------------------
+//
+// RAM image for input code file: hello.hex
+//
+//-----------------------------------------------------------------------------
+module ram_image
+(
+ clk, addr,
+ we, din, dout
+);
+//-----------------------------------------------------------------------------
+input clk;
+input [11:0] addr;
+input we;
+input [7:0] din;
+output [7:0] dout;
+//-----------------------------------------------------------------------------
+reg [7:0] dout;
+reg [7:0] ram [4095:0];
+//-----------------------------------------------------------------------------
+initial
+begin
+ ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
+ ram[4] = 8'hcd; ram[5] = 8'he3; ram[6] = 8'h02; ram[7] = 8'h7e;
+ ram[8] = 8'h6f; ram[9] = 8'h07; ram[10] = 8'h9f; ram[11] = 8'h67;
+ ram[12] = 8'hc9; ram[13] = 8'h7e; ram[14] = 8'h23; ram[15] = 8'h66;
+ ram[16] = 8'h6f; ram[17] = 8'hc9; ram[18] = 8'h7d; ram[19] = 8'h12;
+ ram[20] = 8'hc9; ram[21] = 8'h7d; ram[22] = 8'h12; ram[23] = 8'h13;
+ ram[24] = 8'h7c; ram[25] = 8'h12; ram[26] = 8'hc9; ram[27] = 8'h7d;
+ ram[28] = 8'hb3; ram[29] = 8'h6f; ram[30] = 8'h7c; ram[31] = 8'hb2;
+ ram[32] = 8'h67; ram[33] = 8'hc9; ram[34] = 8'h7d; ram[35] = 8'hab;
+ ram[36] = 8'h6f; ram[37] = 8'h7c; ram[38] = 8'haa; ram[39] = 8'h67;
+ ram[40] = 8'hc9; ram[41] = 8'h7d; ram[42] = 8'ha3; ram[43] = 8'h6f;
+ ram[44] = 8'h7c; ram[45] = 8'ha2; ram[46] = 8'h67; ram[47] = 8'hc9;
+ ram[48] = 8'hcd; ram[49] = 8'h56; ram[50] = 8'h00; ram[51] = 8'hc8;
+ ram[52] = 8'h2b; ram[53] = 8'hc9; ram[54] = 8'hcd; ram[55] = 8'h56;
+ ram[56] = 8'h00; ram[57] = 8'hc0; ram[58] = 8'h2b; ram[59] = 8'hc9;
+ ram[60] = 8'heb; ram[61] = 8'hcd; ram[62] = 8'h56; ram[63] = 8'h00;
+ ram[64] = 8'hd8; ram[65] = 8'h2b; ram[66] = 8'hc9; ram[67] = 8'hcd;
+ ram[68] = 8'h56; ram[69] = 8'h00; ram[70] = 8'hc8; ram[71] = 8'hd8;
+ ram[72] = 8'h2b; ram[73] = 8'hc9; ram[74] = 8'hcd; ram[75] = 8'h56;
+ ram[76] = 8'h00; ram[77] = 8'hd0; ram[78] = 8'h2b; ram[79] = 8'hc9;
+ ram[80] = 8'hcd; ram[81] = 8'h56; ram[82] = 8'h00; ram[83] = 8'hd8;
+ ram[84] = 8'h2b; ram[85] = 8'hc9; ram[86] = 8'h7b; ram[87] = 8'h95;
+ ram[88] = 8'h5f; ram[89] = 8'h7a; ram[90] = 8'h9c; ram[91] = 8'h21;
+ ram[92] = 8'h01; ram[93] = 8'h00; ram[94] = 8'hfa; ram[95] = 8'h63;
+ ram[96] = 8'h00; ram[97] = 8'hb3; ram[98] = 8'hc9; ram[99] = 8'hb3;
+ ram[100] = 8'h37; ram[101] = 8'hc9; ram[102] = 8'hcd; ram[103] = 8'h80;
+ ram[104] = 8'h00; ram[105] = 8'hd0; ram[106] = 8'h2b; ram[107] = 8'hc9;
+ ram[108] = 8'hcd; ram[109] = 8'h80; ram[110] = 8'h00; ram[111] = 8'hd8;
+ ram[112] = 8'h2b; ram[113] = 8'hc9; ram[114] = 8'heb; ram[115] = 8'hcd;
+ ram[116] = 8'h80; ram[117] = 8'h00; ram[118] = 8'hd8; ram[119] = 8'h2b;
+ ram[120] = 8'hc9; ram[121] = 8'hcd; ram[122] = 8'h80; ram[123] = 8'h00;
+ ram[124] = 8'hc8; ram[125] = 8'hd8; ram[126] = 8'h2b; ram[127] = 8'hc9;
+ ram[128] = 8'h7a; ram[129] = 8'hbc; ram[130] = 8'hc2; ram[131] = 8'h87;
+ ram[132] = 8'h00; ram[133] = 8'h7b; ram[134] = 8'hbd; ram[135] = 8'h21;
+ ram[136] = 8'h01; ram[137] = 8'h00; ram[138] = 8'hc9; ram[139] = 8'heb;
+ ram[140] = 8'h7c; ram[141] = 8'h17; ram[142] = 8'h7c; ram[143] = 8'h1f;
+ ram[144] = 8'h67; ram[145] = 8'h7d; ram[146] = 8'h1f; ram[147] = 8'h6f;
+ ram[148] = 8'h1d; ram[149] = 8'hc2; ram[150] = 8'h8c; ram[151] = 8'h00;
+ ram[152] = 8'hc9; ram[153] = 8'heb; ram[154] = 8'h29; ram[155] = 8'h1d;
+ ram[156] = 8'hc2; ram[157] = 8'h9a; ram[158] = 8'h00; ram[159] = 8'hc9;
+ ram[160] = 8'h7b; ram[161] = 8'h95; ram[162] = 8'h6f; ram[163] = 8'h7a;
+ ram[164] = 8'h9c; ram[165] = 8'h67; ram[166] = 8'hc9; ram[167] = 8'hcd;
+ ram[168] = 8'hac; ram[169] = 8'h00; ram[170] = 8'h23; ram[171] = 8'hc9;
+ ram[172] = 8'h7c; ram[173] = 8'h2f; ram[174] = 8'h67; ram[175] = 8'h7d;
+ ram[176] = 8'h2f; ram[177] = 8'h6f; ram[178] = 8'hc9; ram[179] = 8'h44;
+ ram[180] = 8'h4d; ram[181] = 8'h21; ram[182] = 8'h00; ram[183] = 8'h00;
+ ram[184] = 8'h79; ram[185] = 8'h0f; ram[186] = 8'hd2; ram[187] = 8'hbe;
+ ram[188] = 8'h00; ram[189] = 8'h19; ram[190] = 8'haf; ram[191] = 8'h78;
+ ram[192] = 8'h1f; ram[193] = 8'h47; ram[194] = 8'h79; ram[195] = 8'h1f;
+ ram[196] = 8'h4f; ram[197] = 8'hb0; ram[198] = 8'hc8; ram[199] = 8'haf;
+ ram[200] = 8'h7b; ram[201] = 8'h17; ram[202] = 8'h5f; ram[203] = 8'h7a;
+ ram[204] = 8'h17; ram[205] = 8'h57; ram[206] = 8'hb3; ram[207] = 8'hc8;
+ ram[208] = 8'hc3; ram[209] = 8'hb8; ram[210] = 8'h00; ram[211] = 8'h44;
+ ram[212] = 8'h4d; ram[213] = 8'h7a; ram[214] = 8'ha8; ram[215] = 8'hf5;
+ ram[216] = 8'h7a; ram[217] = 8'hb7; ram[218] = 8'hfc; ram[219] = 8'h14;
+ ram[220] = 8'h01; ram[221] = 8'h78; ram[222] = 8'hb7; ram[223] = 8'hfc;
+ ram[224] = 8'h1c; ram[225] = 8'h01; ram[226] = 8'h3e; ram[227] = 8'h10;
+ ram[228] = 8'hf5; ram[229] = 8'heb; ram[230] = 8'h11; ram[231] = 8'h00;
+ ram[232] = 8'h00; ram[233] = 8'h29; ram[234] = 8'hcd; ram[235] = 8'h24;
+ ram[236] = 8'h01; ram[237] = 8'hca; ram[238] = 8'h00; ram[239] = 8'h01;
+ ram[240] = 8'hcd; ram[241] = 8'h2c; ram[242] = 8'h01; ram[243] = 8'hfa;
+ ram[244] = 8'h00; ram[245] = 8'h01; ram[246] = 8'h7d; ram[247] = 8'hf6;
+ ram[248] = 8'h01; ram[249] = 8'h6f; ram[250] = 8'h7b; ram[251] = 8'h91;
+ ram[252] = 8'h5f; ram[253] = 8'h7a; ram[254] = 8'h98; ram[255] = 8'h57;
+ ram[256] = 8'hf1; ram[257] = 8'h3d; ram[258] = 8'hca; ram[259] = 8'h09;
+ ram[260] = 8'h01; ram[261] = 8'hf5; ram[262] = 8'hc3; ram[263] = 8'he9;
+ ram[264] = 8'h00; ram[265] = 8'hf1; ram[266] = 8'hf0; ram[267] = 8'hcd;
+ ram[268] = 8'h14; ram[269] = 8'h01; ram[270] = 8'heb; ram[271] = 8'hcd;
+ ram[272] = 8'h14; ram[273] = 8'h01; ram[274] = 8'heb; ram[275] = 8'hc9;
+ ram[276] = 8'h7a; ram[277] = 8'h2f; ram[278] = 8'h57; ram[279] = 8'h7b;
+ ram[280] = 8'h2f; ram[281] = 8'h5f; ram[282] = 8'h13; ram[283] = 8'hc9;
+ ram[284] = 8'h78; ram[285] = 8'h2f; ram[286] = 8'h47; ram[287] = 8'h79;
+ ram[288] = 8'h2f; ram[289] = 8'h4f; ram[290] = 8'h03; ram[291] = 8'hc9;
+ ram[292] = 8'h7b; ram[293] = 8'h17; ram[294] = 8'h5f; ram[295] = 8'h7a;
+ ram[296] = 8'h17; ram[297] = 8'h57; ram[298] = 8'hb3; ram[299] = 8'hc9;
+ ram[300] = 8'h7b; ram[301] = 8'h91; ram[302] = 8'h7a; ram[303] = 8'h98;
+ ram[304] = 8'hc9; ram[305] = 8'hdb; ram[306] = 8'h83; ram[307] = 8'hcf;
+ ram[308] = 8'he5; ram[309] = 8'h21; ram[310] = 8'h01; ram[311] = 8'h00;
+ ram[312] = 8'hd1; ram[313] = 8'hcd; ram[314] = 8'h29; ram[315] = 8'h00;
+ ram[316] = 8'h7c; ram[317] = 8'hb5; ram[318] = 8'hca; ram[319] = 8'h44;
+ ram[320] = 8'h01; ram[321] = 8'hc3; ram[322] = 8'h31; ram[323] = 8'h01;
+ ram[324] = 8'h21; ram[325] = 8'h02; ram[326] = 8'h00; ram[327] = 8'h39;
+ ram[328] = 8'hcd; ram[329] = 8'h07; ram[330] = 8'h00; ram[331] = 8'h7d;
+ ram[332] = 8'hd3; ram[333] = 8'h80; ram[334] = 8'hc9; ram[335] = 8'hdb;
+ ram[336] = 8'h83; ram[337] = 8'hcf; ram[338] = 8'he5; ram[339] = 8'h21;
+ ram[340] = 8'h10; ram[341] = 8'h00; ram[342] = 8'hd1; ram[343] = 8'hcd;
+ ram[344] = 8'h29; ram[345] = 8'h00; ram[346] = 8'h7c; ram[347] = 8'hb5;
+ ram[348] = 8'hca; ram[349] = 8'h6d; ram[350] = 8'h01; ram[351] = 8'hdb;
+ ram[352] = 8'h80; ram[353] = 8'hcf; ram[354] = 8'h7d; ram[355] = 8'h32;
+ ram[356] = 8'h9e; ram[357] = 8'h03; ram[358] = 8'h21; ram[359] = 8'h01;
+ ram[360] = 8'h00; ram[361] = 8'hc9; ram[362] = 8'hc3; ram[363] = 8'h71;
+ ram[364] = 8'h01; ram[365] = 8'h21; ram[366] = 8'h00; ram[367] = 8'h00;
+ ram[368] = 8'hc9; ram[369] = 8'hc9; ram[370] = 8'h21; ram[371] = 8'h0d;
+ ram[372] = 8'h00; ram[373] = 8'he5; ram[374] = 8'hcd; ram[375] = 8'h31;
+ ram[376] = 8'h01; ram[377] = 8'hc1; ram[378] = 8'h21; ram[379] = 8'h0a;
+ ram[380] = 8'h00; ram[381] = 8'he5; ram[382] = 8'hcd; ram[383] = 8'h31;
+ ram[384] = 8'h01; ram[385] = 8'hc1; ram[386] = 8'hc9; ram[387] = 8'h21;
+ ram[388] = 8'h02; ram[389] = 8'h00; ram[390] = 8'h39; ram[391] = 8'hcd;
+ ram[392] = 8'h0d; ram[393] = 8'h00; ram[394] = 8'hcd; ram[395] = 8'h07;
+ ram[396] = 8'h00; ram[397] = 8'he5; ram[398] = 8'h21; ram[399] = 8'h00;
+ ram[400] = 8'h00; ram[401] = 8'hd1; ram[402] = 8'hcd; ram[403] = 8'h36;
+ ram[404] = 8'h00; ram[405] = 8'h7c; ram[406] = 8'hb5; ram[407] = 8'hca;
+ ram[408] = 8'hb3; ram[409] = 8'h01; ram[410] = 8'h21; ram[411] = 8'h02;
+ ram[412] = 8'h00; ram[413] = 8'h39; ram[414] = 8'he5; ram[415] = 8'hcd;
+ ram[416] = 8'h0d; ram[417] = 8'h00; ram[418] = 8'h23; ram[419] = 8'hd1;
+ ram[420] = 8'hcd; ram[421] = 8'h15; ram[422] = 8'h00; ram[423] = 8'h2b;
+ ram[424] = 8'hcd; ram[425] = 8'h07; ram[426] = 8'h00; ram[427] = 8'he5;
+ ram[428] = 8'hcd; ram[429] = 8'h31; ram[430] = 8'h01; ram[431] = 8'hc1;
+ ram[432] = 8'hc3; ram[433] = 8'h83; ram[434] = 8'h01; ram[435] = 8'hc9;
+ ram[436] = 8'h21; ram[437] = 8'h02; ram[438] = 8'h00; ram[439] = 8'h39;
+ ram[440] = 8'hcd; ram[441] = 8'h0d; ram[442] = 8'h00; ram[443] = 8'he5;
+ ram[444] = 8'h21; ram[445] = 8'h00; ram[446] = 8'h00; ram[447] = 8'hd1;
+ ram[448] = 8'hcd; ram[449] = 8'h50; ram[450] = 8'h00; ram[451] = 8'h7c;
+ ram[452] = 8'hb5; ram[453] = 8'hca; ram[454] = 8'he3; ram[455] = 8'h01;
+ ram[456] = 8'h21; ram[457] = 8'h2d; ram[458] = 8'h00; ram[459] = 8'he5;
+ ram[460] = 8'hcd; ram[461] = 8'h31; ram[462] = 8'h01; ram[463] = 8'hc1;
+ ram[464] = 8'h21; ram[465] = 8'h02; ram[466] = 8'h00; ram[467] = 8'h39;
+ ram[468] = 8'he5; ram[469] = 8'h21; ram[470] = 8'h04; ram[471] = 8'h00;
+ ram[472] = 8'h39; ram[473] = 8'hcd; ram[474] = 8'h0d; ram[475] = 8'h00;
+ ram[476] = 8'hcd; ram[477] = 8'ha7; ram[478] = 8'h00; ram[479] = 8'hd1;
+ ram[480] = 8'hcd; ram[481] = 8'h15; ram[482] = 8'h00; ram[483] = 8'h21;
+ ram[484] = 8'h02; ram[485] = 8'h00; ram[486] = 8'h39; ram[487] = 8'hcd;
+ ram[488] = 8'h0d; ram[489] = 8'h00; ram[490] = 8'he5; ram[491] = 8'hcd;
+ ram[492] = 8'hf0; ram[493] = 8'h01; ram[494] = 8'hc1; ram[495] = 8'hc9;
+ ram[496] = 8'hc5; ram[497] = 8'h21; ram[498] = 8'h00; ram[499] = 8'h00;
+ ram[500] = 8'h39; ram[501] = 8'he5; ram[502] = 8'h21; ram[503] = 8'h06;
+ ram[504] = 8'h00; ram[505] = 8'h39; ram[506] = 8'hcd; ram[507] = 8'h0d;
+ ram[508] = 8'h00; ram[509] = 8'he5; ram[510] = 8'h21; ram[511] = 8'h0a;
+ ram[512] = 8'h00; ram[513] = 8'hd1; ram[514] = 8'hcd; ram[515] = 8'hd3;
+ ram[516] = 8'h00; ram[517] = 8'hd1; ram[518] = 8'hcd; ram[519] = 8'h15;
+ ram[520] = 8'h00; ram[521] = 8'h21; ram[522] = 8'h00; ram[523] = 8'h00;
+ ram[524] = 8'h39; ram[525] = 8'hcd; ram[526] = 8'h0d; ram[527] = 8'h00;
+ ram[528] = 8'h7c; ram[529] = 8'hb5; ram[530] = 8'hca; ram[531] = 8'h21;
+ ram[532] = 8'h02; ram[533] = 8'h21; ram[534] = 8'h00; ram[535] = 8'h00;
+ ram[536] = 8'h39; ram[537] = 8'hcd; ram[538] = 8'h0d; ram[539] = 8'h00;
+ ram[540] = 8'he5; ram[541] = 8'hcd; ram[542] = 8'hf0; ram[543] = 8'h01;
+ ram[544] = 8'hc1; ram[545] = 8'h21; ram[546] = 8'h30; ram[547] = 8'h00;
+ ram[548] = 8'he5; ram[549] = 8'h21; ram[550] = 8'h06; ram[551] = 8'h00;
+ ram[552] = 8'h39; ram[553] = 8'hcd; ram[554] = 8'h0d; ram[555] = 8'h00;
+ ram[556] = 8'he5; ram[557] = 8'h21; ram[558] = 8'h04; ram[559] = 8'h00;
+ ram[560] = 8'h39; ram[561] = 8'hcd; ram[562] = 8'h0d; ram[563] = 8'h00;
+ ram[564] = 8'he5; ram[565] = 8'h21; ram[566] = 8'h0a; ram[567] = 8'h00;
+ ram[568] = 8'hd1; ram[569] = 8'hcd; ram[570] = 8'hb3; ram[571] = 8'h00;
+ ram[572] = 8'hd1; ram[573] = 8'hcd; ram[574] = 8'ha0; ram[575] = 8'h00;
+ ram[576] = 8'hd1; ram[577] = 8'h19; ram[578] = 8'he5; ram[579] = 8'hcd;
+ ram[580] = 8'h31; ram[581] = 8'h01; ram[582] = 8'hc1; ram[583] = 8'hc1;
+ ram[584] = 8'hc9; ram[585] = 8'hc5; ram[586] = 8'h21; ram[587] = 8'h00;
+ ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'he5; ram[591] = 8'h21;
+ ram[592] = 8'h06; ram[593] = 8'h00; ram[594] = 8'h39; ram[595] = 8'hcd;
+ ram[596] = 8'h0d; ram[597] = 8'h00; ram[598] = 8'he5; ram[599] = 8'h21;
+ ram[600] = 8'h10; ram[601] = 8'h00; ram[602] = 8'hd1; ram[603] = 8'hcd;
+ ram[604] = 8'hd3; ram[605] = 8'h00; ram[606] = 8'hd1; ram[607] = 8'hcd;
+ ram[608] = 8'h15; ram[609] = 8'h00; ram[610] = 8'h21; ram[611] = 8'h00;
+ ram[612] = 8'h00; ram[613] = 8'h39; ram[614] = 8'hcd; ram[615] = 8'h0d;
+ ram[616] = 8'h00; ram[617] = 8'h7c; ram[618] = 8'hb5; ram[619] = 8'hca;
+ ram[620] = 8'h7a; ram[621] = 8'h02; ram[622] = 8'h21; ram[623] = 8'h00;
+ ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h0d;
+ ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'hcd; ram[631] = 8'h49;
+ ram[632] = 8'h02; ram[633] = 8'hc1; ram[634] = 8'h21; ram[635] = 8'h00;
+ ram[636] = 8'h00; ram[637] = 8'h39; ram[638] = 8'he5; ram[639] = 8'h21;
+ ram[640] = 8'h06; ram[641] = 8'h00; ram[642] = 8'h39; ram[643] = 8'hcd;
+ ram[644] = 8'h0d; ram[645] = 8'h00; ram[646] = 8'he5; ram[647] = 8'h21;
+ ram[648] = 8'h04; ram[649] = 8'h00; ram[650] = 8'h39; ram[651] = 8'hcd;
+ ram[652] = 8'h0d; ram[653] = 8'h00; ram[654] = 8'he5; ram[655] = 8'h21;
+ ram[656] = 8'h10; ram[657] = 8'h00; ram[658] = 8'hd1; ram[659] = 8'hcd;
+ ram[660] = 8'hb3; ram[661] = 8'h00; ram[662] = 8'hd1; ram[663] = 8'hcd;
+ ram[664] = 8'ha0; ram[665] = 8'h00; ram[666] = 8'hd1; ram[667] = 8'hcd;
+ ram[668] = 8'h15; ram[669] = 8'h00; ram[670] = 8'h21; ram[671] = 8'h00;
+ ram[672] = 8'h00; ram[673] = 8'h39; ram[674] = 8'hcd; ram[675] = 8'h0d;
+ ram[676] = 8'h00; ram[677] = 8'he5; ram[678] = 8'h21; ram[679] = 8'h09;
+ ram[680] = 8'h00; ram[681] = 8'hd1; ram[682] = 8'hcd; ram[683] = 8'h3c;
+ ram[684] = 8'h00; ram[685] = 8'h7c; ram[686] = 8'hb5; ram[687] = 8'hca;
+ ram[688] = 8'hcf; ram[689] = 8'h02; ram[690] = 8'h21; ram[691] = 8'h41;
+ ram[692] = 8'h00; ram[693] = 8'he5; ram[694] = 8'h21; ram[695] = 8'h02;
+ ram[696] = 8'h00; ram[697] = 8'h39; ram[698] = 8'hcd; ram[699] = 8'h0d;
+ ram[700] = 8'h00; ram[701] = 8'hd1; ram[702] = 8'h19; ram[703] = 8'he5;
+ ram[704] = 8'h21; ram[705] = 8'h0a; ram[706] = 8'h00; ram[707] = 8'hd1;
+ ram[708] = 8'hcd; ram[709] = 8'ha0; ram[710] = 8'h00; ram[711] = 8'he5;
+ ram[712] = 8'hcd; ram[713] = 8'h31; ram[714] = 8'h01; ram[715] = 8'hc1;
+ ram[716] = 8'hc3; ram[717] = 8'he1; ram[718] = 8'h02; ram[719] = 8'h21;
+ ram[720] = 8'h30; ram[721] = 8'h00; ram[722] = 8'he5; ram[723] = 8'h21;
+ ram[724] = 8'h02; ram[725] = 8'h00; ram[726] = 8'h39; ram[727] = 8'hcd;
+ ram[728] = 8'h0d; ram[729] = 8'h00; ram[730] = 8'hd1; ram[731] = 8'h19;
+ ram[732] = 8'he5; ram[733] = 8'hcd; ram[734] = 8'h31; ram[735] = 8'h01;
+ ram[736] = 8'hc1; ram[737] = 8'hc1; ram[738] = 8'hc9; ram[739] = 8'h21;
+ ram[740] = 8'hc3; ram[741] = 8'h00; ram[742] = 8'h7d; ram[743] = 8'hd3;
+ ram[744] = 8'h81; ram[745] = 8'h21; ram[746] = 8'h00; ram[747] = 8'h00;
+ ram[748] = 8'h7d; ram[749] = 8'hd3; ram[750] = 8'h82; ram[751] = 8'h21;
+ ram[752] = 8'h5c; ram[753] = 8'h03; ram[754] = 8'he5; ram[755] = 8'hcd;
+ ram[756] = 8'h83; ram[757] = 8'h01; ram[758] = 8'hc1; ram[759] = 8'hcd;
+ ram[760] = 8'h72; ram[761] = 8'h01; ram[762] = 8'h21; ram[763] = 8'h6b;
+ ram[764] = 8'h03; ram[765] = 8'he5; ram[766] = 8'hcd; ram[767] = 8'h83;
+ ram[768] = 8'h01; ram[769] = 8'hc1; ram[770] = 8'h21; ram[771] = 8'h9f;
+ ram[772] = 8'h03; ram[773] = 8'he5; ram[774] = 8'h21; ram[775] = 8'h01;
+ ram[776] = 8'h00; ram[777] = 8'h29; ram[778] = 8'hd1; ram[779] = 8'h19;
+ ram[780] = 8'hcd; ram[781] = 8'h0d; ram[782] = 8'h00; ram[783] = 8'he5;
+ ram[784] = 8'hcd; ram[785] = 8'hb4; ram[786] = 8'h01; ram[787] = 8'hc1;
+ ram[788] = 8'hcd; ram[789] = 8'h72; ram[790] = 8'h01; ram[791] = 8'h21;
+ ram[792] = 8'h77; ram[793] = 8'h03; ram[794] = 8'he5; ram[795] = 8'hcd;
+ ram[796] = 8'h83; ram[797] = 8'h01; ram[798] = 8'hc1; ram[799] = 8'h21;
+ ram[800] = 8'h9f; ram[801] = 8'h03; ram[802] = 8'he5; ram[803] = 8'h21;
+ ram[804] = 8'h00; ram[805] = 8'h00; ram[806] = 8'h29; ram[807] = 8'hd1;
+ ram[808] = 8'h19; ram[809] = 8'hcd; ram[810] = 8'h0d; ram[811] = 8'h00;
+ ram[812] = 8'he5; ram[813] = 8'hcd; ram[814] = 8'h49; ram[815] = 8'h02;
+ ram[816] = 8'hc1; ram[817] = 8'hcd; ram[818] = 8'h72; ram[819] = 8'h01;
+ ram[820] = 8'h21; ram[821] = 8'h85; ram[822] = 8'h03; ram[823] = 8'he5;
+ ram[824] = 8'hcd; ram[825] = 8'h83; ram[826] = 8'h01; ram[827] = 8'hc1;
+ ram[828] = 8'hcd; ram[829] = 8'h72; ram[830] = 8'h01; ram[831] = 8'h21;
+ ram[832] = 8'h01; ram[833] = 8'h00; ram[834] = 8'h7c; ram[835] = 8'hb5;
+ ram[836] = 8'hca; ram[837] = 8'h5b; ram[838] = 8'h03; ram[839] = 8'hcd;
+ ram[840] = 8'h4f; ram[841] = 8'h01; ram[842] = 8'h7c; ram[843] = 8'hb5;
+ ram[844] = 8'hca; ram[845] = 8'h58; ram[846] = 8'h03; ram[847] = 8'h3a;
+ ram[848] = 8'h9e; ram[849] = 8'h03; ram[850] = 8'hcf; ram[851] = 8'he5;
+ ram[852] = 8'hcd; ram[853] = 8'h31; ram[854] = 8'h01; ram[855] = 8'hc1;
+ ram[856] = 8'hc3; ram[857] = 8'h3f; ram[858] = 8'h03; ram[859] = 8'hc9;
+ ram[860] = 8'h48; ram[861] = 8'h65; ram[862] = 8'h6c; ram[863] = 8'h6c;
+ ram[864] = 8'h6f; ram[865] = 8'h20; ram[866] = 8'h57; ram[867] = 8'h6f;
+ ram[868] = 8'h72; ram[869] = 8'h6c; ram[870] = 8'h64; ram[871] = 8'h21;
+ ram[872] = 8'h21; ram[873] = 8'h21; ram[874] = 8'h00; ram[875] = 8'h44;
+ ram[876] = 8'h65; ram[877] = 8'h63; ram[878] = 8'h20; ram[879] = 8'h76;
+ ram[880] = 8'h61; ram[881] = 8'h6c; ram[882] = 8'h75; ram[883] = 8'h65;
+ ram[884] = 8'h3a; ram[885] = 8'h20; ram[886] = 8'h00; ram[887] = 8'h48;
+ ram[888] = 8'h65; ram[889] = 8'h78; ram[890] = 8'h20; ram[891] = 8'h76;
+ ram[892] = 8'h61; ram[893] = 8'h6c; ram[894] = 8'h75; ram[895] = 8'h65;
+ ram[896] = 8'h3a; ram[897] = 8'h20; ram[898] = 8'h30; ram[899] = 8'h78;
+ ram[900] = 8'h00; ram[901] = 8'h45; ram[902] = 8'h63; ram[903] = 8'h68;
+ ram[904] = 8'h6f; ram[905] = 8'h69; ram[906] = 8'h6e; ram[907] = 8'h67;
+ ram[908] = 8'h20; ram[909] = 8'h72; ram[910] = 8'h65; ram[911] = 8'h63;
+ ram[912] = 8'h65; ram[913] = 8'h69; ram[914] = 8'h76; ram[915] = 8'h65;
+ ram[916] = 8'h64; ram[917] = 8'h20; ram[918] = 8'h62; ram[919] = 8'h79;
+ ram[920] = 8'h74; ram[921] = 8'h65; ram[922] = 8'h73; ram[923] = 8'h3a;
+ ram[924] = 8'h20; ram[925] = 8'h00; ram[926] = 8'h00; ram[927] = 8'hd2;
+ ram[928] = 8'h04; ram[929] = 8'h2e; ram[930] = 8'h16; ram[931] = 8'h00;
+ ram[932] = 8'h00; ram[933] = 8'h00; ram[934] = 8'h00; ram[935] = 8'h00;
+ ram[936] = 8'h00; ram[937] = 8'h00; ram[938] = 8'h00; ram[939] = 8'h00;
+ ram[940] = 8'h00; ram[941] = 8'h00; ram[942] = 8'h00; ram[943] = 8'h00;
+ ram[944] = 8'h00; ram[945] = 8'h00; ram[946] = 8'h00; ram[947] = 8'h00;
+ ram[948] = 8'h00; ram[949] = 8'h00; ram[950] = 8'h00; ram[951] = 8'h00;
+ ram[952] = 8'h00; ram[953] = 8'h00; ram[954] = 8'h00; ram[955] = 8'h00;
+ ram[956] = 8'h00; ram[957] = 8'h00; ram[958] = 8'h00; ram[959] = 8'h00;
+ ram[960] = 8'h00; ram[961] = 8'h00; ram[962] = 8'h00; ram[963] = 8'h00;
+ ram[964] = 8'h00; ram[965] = 8'h00; ram[966] = 8'h00; ram[967] = 8'h00;
+ ram[968] = 8'h00; ram[969] = 8'h00; ram[970] = 8'h00; ram[971] = 8'h00;
+ ram[972] = 8'h00; ram[973] = 8'h00; ram[974] = 8'h00; ram[975] = 8'h00;
+ ram[976] = 8'h00; ram[977] = 8'h00; ram[978] = 8'h00; ram[979] = 8'h00;
+ ram[980] = 8'h00; ram[981] = 8'h00; ram[982] = 8'h00; ram[983] = 8'h00;
+ ram[984] = 8'h00; ram[985] = 8'h00; ram[986] = 8'h00; ram[987] = 8'h00;
+ ram[988] = 8'h00; ram[989] = 8'h00; ram[990] = 8'h00; ram[991] = 8'h00;
+ ram[992] = 8'h00; ram[993] = 8'h00; ram[994] = 8'h00; ram[995] = 8'h00;
+ ram[996] = 8'h00; ram[997] = 8'h00; ram[998] = 8'h00; ram[999] = 8'h00;
+ ram[1000] = 8'h00; ram[1001] = 8'h00; ram[1002] = 8'h00; ram[1003] = 8'h00;
+ ram[1004] = 8'h00; ram[1005] = 8'h00; ram[1006] = 8'h00; ram[1007] = 8'h00;
+ ram[1008] = 8'h00; ram[1009] = 8'h00; ram[1010] = 8'h00; ram[1011] = 8'h00;
+ ram[1012] = 8'h00; ram[1013] = 8'h00; ram[1014] = 8'h00; ram[1015] = 8'h00;
+ ram[1016] = 8'h00; ram[1017] = 8'h00; ram[1018] = 8'h00; ram[1019] = 8'h00;
+ ram[1020] = 8'h00; ram[1021] = 8'h00; ram[1022] = 8'h00; ram[1023] = 8'h00;
+ ram[1024] = 8'h00; ram[1025] = 8'h00; ram[1026] = 8'h00; ram[1027] = 8'h00;
+ ram[1028] = 8'h00; ram[1029] = 8'h00; ram[1030] = 8'h00; ram[1031] = 8'h00;
+ ram[1032] = 8'h00; ram[1033] = 8'h00; ram[1034] = 8'h00; ram[1035] = 8'h00;
+ ram[1036] = 8'h00; ram[1037] = 8'h00; ram[1038] = 8'h00; ram[1039] = 8'h00;
+ ram[1040] = 8'h00; ram[1041] = 8'h00; ram[1042] = 8'h00; ram[1043] = 8'h00;
+ ram[1044] = 8'h00; ram[1045] = 8'h00; ram[1046] = 8'h00; ram[1047] = 8'h00;
+ ram[1048] = 8'h00; ram[1049] = 8'h00; ram[1050] = 8'h00; ram[1051] = 8'h00;
+ ram[1052] = 8'h00; ram[1053] = 8'h00; ram[1054] = 8'h00; ram[1055] = 8'h00;
+ ram[1056] = 8'h00; ram[1057] = 8'h00; ram[1058] = 8'h00; ram[1059] = 8'h00;
+ ram[1060] = 8'h00; ram[1061] = 8'h00; ram[1062] = 8'h00; ram[1063] = 8'h00;
+ ram[1064] = 8'h00; ram[1065] = 8'h00; ram[1066] = 8'h00; ram[1067] = 8'h00;
+ ram[1068] = 8'h00; ram[1069] = 8'h00; ram[1070] = 8'h00; ram[1071] = 8'h00;
+ ram[1072] = 8'h00; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
+ ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
+ ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
+ ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
+ ram[1088] = 8'h00; ram[1089] = 8'h00; ram[1090] = 8'h00; ram[1091] = 8'h00;
+ ram[1092] = 8'h00; ram[1093] = 8'h00; ram[1094] = 8'h00; ram[1095] = 8'h00;
+ ram[1096] = 8'h00; ram[1097] = 8'h00; ram[1098] = 8'h00; ram[1099] = 8'h00;
+ ram[1100] = 8'h00; ram[1101] = 8'h00; ram[1102] = 8'h00; ram[1103] = 8'h00;
+ ram[1104] = 8'h00; ram[1105] = 8'h00; ram[1106] = 8'h00; ram[1107] = 8'h00;
+ ram[1108] = 8'h00; ram[1109] = 8'h00; ram[1110] = 8'h00; ram[1111] = 8'h00;
+ ram[1112] = 8'h00; ram[1113] = 8'h00; ram[1114] = 8'h00; ram[1115] = 8'h00;
+ ram[1116] = 8'h00; ram[1117] = 8'h00; ram[1118] = 8'h00; ram[1119] = 8'h00;
+ ram[1120] = 8'h00; ram[1121] = 8'h00; ram[1122] = 8'h00; ram[1123] = 8'h00;
+ ram[1124] = 8'h00; ram[1125] = 8'h00; ram[1126] = 8'h00; ram[1127] = 8'h00;
+ ram[1128] = 8'h00; ram[1129] = 8'h00; ram[1130] = 8'h00; ram[1131] = 8'h00;
+ ram[1132] = 8'h00; ram[1133] = 8'h00; ram[1134] = 8'h00; ram[1135] = 8'h00;
+ ram[1136] = 8'h00; ram[1137] = 8'h00; ram[1138] = 8'h00; ram[1139] = 8'h00;
+ ram[1140] = 8'h00; ram[1141] = 8'h00; ram[1142] = 8'h00; ram[1143] = 8'h00;
+ ram[1144] = 8'h00; ram[1145] = 8'h00; ram[1146] = 8'h00; ram[1147] = 8'h00;
+ ram[1148] = 8'h00; ram[1149] = 8'h00; ram[1150] = 8'h00; ram[1151] = 8'h00;
+ ram[1152] = 8'h00; ram[1153] = 8'h00; ram[1154] = 8'h00; ram[1155] = 8'h00;
+ ram[1156] = 8'h00; ram[1157] = 8'h00; ram[1158] = 8'h00; ram[1159] = 8'h00;
+ ram[1160] = 8'h00; ram[1161] = 8'h00; ram[1162] = 8'h00; ram[1163] = 8'h00;
+ ram[1164] = 8'h00; ram[1165] = 8'h00; ram[1166] = 8'h00; ram[1167] = 8'h00;
+ ram[1168] = 8'h00; ram[1169] = 8'h00; ram[1170] = 8'h00; ram[1171] = 8'h00;
+ ram[1172] = 8'h00; ram[1173] = 8'h00; ram[1174] = 8'h00; ram[1175] = 8'h00;
+ ram[1176] = 8'h00; ram[1177] = 8'h00; ram[1178] = 8'h00; ram[1179] = 8'h00;
+ ram[1180] = 8'h00; ram[1181] = 8'h00; ram[1182] = 8'h00; ram[1183] = 8'h00;
+ ram[1184] = 8'h00; ram[1185] = 8'h00; ram[1186] = 8'h00; ram[1187] = 8'h00;
+ ram[1188] = 8'h00; ram[1189] = 8'h00; ram[1190] = 8'h00; ram[1191] = 8'h00;
+ ram[1192] = 8'h00; ram[1193] = 8'h00; ram[1194] = 8'h00; ram[1195] = 8'h00;
+ ram[1196] = 8'h00; ram[1197] = 8'h00; ram[1198] = 8'h00; ram[1199] = 8'h00;
+ ram[1200] = 8'h00; ram[1201] = 8'h00; ram[1202] = 8'h00; ram[1203] = 8'h00;
+ ram[1204] = 8'h00; ram[1205] = 8'h00; ram[1206] = 8'h00; ram[1207] = 8'h00;
+ ram[1208] = 8'h00; ram[1209] = 8'h00; ram[1210] = 8'h00; ram[1211] = 8'h00;
+ ram[1212] = 8'h00; ram[1213] = 8'h00; ram[1214] = 8'h00; ram[1215] = 8'h00;
+ ram[1216] = 8'h00; ram[1217] = 8'h00; ram[1218] = 8'h00; ram[1219] = 8'h00;
+ ram[1220] = 8'h00; ram[1221] = 8'h00; ram[1222] = 8'h00; ram[1223] = 8'h00;
+ ram[1224] = 8'h00; ram[1225] = 8'h00; ram[1226] = 8'h00; ram[1227] = 8'h00;
+ ram[1228] = 8'h00; ram[1229] = 8'h00; ram[1230] = 8'h00; ram[1231] = 8'h00;
+ ram[1232] = 8'h00; ram[1233] = 8'h00; ram[1234] = 8'h00; ram[1235] = 8'h00;
+ ram[1236] = 8'h00; ram[1237] = 8'h00; ram[1238] = 8'h00; ram[1239] = 8'h00;
+ ram[1240] = 8'h00; ram[1241] = 8'h00; ram[1242] = 8'h00; ram[1243] = 8'h00;
+ ram[1244] = 8'h00; ram[1245] = 8'h00; ram[1246] = 8'h00; ram[1247] = 8'h00;
+ ram[1248] = 8'h00; ram[1249] = 8'h00; ram[1250] = 8'h00; ram[1251] = 8'h00;
+ ram[1252] = 8'h00; ram[1253] = 8'h00; ram[1254] = 8'h00; ram[1255] = 8'h00;
+ ram[1256] = 8'h00; ram[1257] = 8'h00; ram[1258] = 8'h00; ram[1259] = 8'h00;
+ ram[1260] = 8'h00; ram[1261] = 8'h00; ram[1262] = 8'h00; ram[1263] = 8'h00;
+ ram[1264] = 8'h00; ram[1265] = 8'h00; ram[1266] = 8'h00; ram[1267] = 8'h00;
+ ram[1268] = 8'h00; ram[1269] = 8'h00; ram[1270] = 8'h00; ram[1271] = 8'h00;
+ ram[1272] = 8'h00; ram[1273] = 8'h00; ram[1274] = 8'h00; ram[1275] = 8'h00;
+ ram[1276] = 8'h00; ram[1277] = 8'h00; ram[1278] = 8'h00; ram[1279] = 8'h00;
+ ram[1280] = 8'h00; ram[1281] = 8'h00; ram[1282] = 8'h00; ram[1283] = 8'h00;
+ ram[1284] = 8'h00; ram[1285] = 8'h00; ram[1286] = 8'h00; ram[1287] = 8'h00;
+ ram[1288] = 8'h00; ram[1289] = 8'h00; ram[1290] = 8'h00; ram[1291] = 8'h00;
+ ram[1292] = 8'h00; ram[1293] = 8'h00; ram[1294] = 8'h00; ram[1295] = 8'h00;
+ ram[1296] = 8'h00; ram[1297] = 8'h00; ram[1298] = 8'h00; ram[1299] = 8'h00;
+ ram[1300] = 8'h00; ram[1301] = 8'h00; ram[1302] = 8'h00; ram[1303] = 8'h00;
+ ram[1304] = 8'h00; ram[1305] = 8'h00; ram[1306] = 8'h00; ram[1307] = 8'h00;
+ ram[1308] = 8'h00; ram[1309] = 8'h00; ram[1310] = 8'h00; ram[1311] = 8'h00;
+ ram[1312] = 8'h00; ram[1313] = 8'h00; ram[1314] = 8'h00; ram[1315] = 8'h00;
+ ram[1316] = 8'h00; ram[1317] = 8'h00; ram[1318] = 8'h00; ram[1319] = 8'h00;
+ ram[1320] = 8'h00; ram[1321] = 8'h00; ram[1322] = 8'h00; ram[1323] = 8'h00;
+ ram[1324] = 8'h00; ram[1325] = 8'h00; ram[1326] = 8'h00; ram[1327] = 8'h00;
+ ram[1328] = 8'h00; ram[1329] = 8'h00; ram[1330] = 8'h00; ram[1331] = 8'h00;
+ ram[1332] = 8'h00; ram[1333] = 8'h00; ram[1334] = 8'h00; ram[1335] = 8'h00;
+ ram[1336] = 8'h00; ram[1337] = 8'h00; ram[1338] = 8'h00; ram[1339] = 8'h00;
+ ram[1340] = 8'h00; ram[1341] = 8'h00; ram[1342] = 8'h00; ram[1343] = 8'h00;
+ ram[1344] = 8'h00; ram[1345] = 8'h00; ram[1346] = 8'h00; ram[1347] = 8'h00;
+ ram[1348] = 8'h00; ram[1349] = 8'h00; ram[1350] = 8'h00; ram[1351] = 8'h00;
+ ram[1352] = 8'h00; ram[1353] = 8'h00; ram[1354] = 8'h00; ram[1355] = 8'h00;
+ ram[1356] = 8'h00; ram[1357] = 8'h00; ram[1358] = 8'h00; ram[1359] = 8'h00;
+ ram[1360] = 8'h00; ram[1361] = 8'h00; ram[1362] = 8'h00; ram[1363] = 8'h00;
+ ram[1364] = 8'h00; ram[1365] = 8'h00; ram[1366] = 8'h00; ram[1367] = 8'h00;
+ ram[1368] = 8'h00; ram[1369] = 8'h00; ram[1370] = 8'h00; ram[1371] = 8'h00;
+ ram[1372] = 8'h00; ram[1373] = 8'h00; ram[1374] = 8'h00; ram[1375] = 8'h00;
+ ram[1376] = 8'h00; ram[1377] = 8'h00; ram[1378] = 8'h00; ram[1379] = 8'h00;
+ ram[1380] = 8'h00; ram[1381] = 8'h00; ram[1382] = 8'h00; ram[1383] = 8'h00;
+ ram[1384] = 8'h00; ram[1385] = 8'h00; ram[1386] = 8'h00; ram[1387] = 8'h00;
+ ram[1388] = 8'h00; ram[1389] = 8'h00; ram[1390] = 8'h00; ram[1391] = 8'h00;
+ ram[1392] = 8'h00; ram[1393] = 8'h00; ram[1394] = 8'h00; ram[1395] = 8'h00;
+ ram[1396] = 8'h00; ram[1397] = 8'h00; ram[1398] = 8'h00; ram[1399] = 8'h00;
+ ram[1400] = 8'h00; ram[1401] = 8'h00; ram[1402] = 8'h00; ram[1403] = 8'h00;
+ ram[1404] = 8'h00; ram[1405] = 8'h00; ram[1406] = 8'h00; ram[1407] = 8'h00;
+ ram[1408] = 8'h00; ram[1409] = 8'h00; ram[1410] = 8'h00; ram[1411] = 8'h00;
+ ram[1412] = 8'h00; ram[1413] = 8'h00; ram[1414] = 8'h00; ram[1415] = 8'h00;
+ ram[1416] = 8'h00; ram[1417] = 8'h00; ram[1418] = 8'h00; ram[1419] = 8'h00;
+ ram[1420] = 8'h00; ram[1421] = 8'h00; ram[1422] = 8'h00; ram[1423] = 8'h00;
+ ram[1424] = 8'h00; ram[1425] = 8'h00; ram[1426] = 8'h00; ram[1427] = 8'h00;
+ ram[1428] = 8'h00; ram[1429] = 8'h00; ram[1430] = 8'h00; ram[1431] = 8'h00;
+ ram[1432] = 8'h00; ram[1433] = 8'h00; ram[1434] = 8'h00; ram[1435] = 8'h00;
+ ram[1436] = 8'h00; ram[1437] = 8'h00; ram[1438] = 8'h00; ram[1439] = 8'h00;
+ ram[1440] = 8'h00; ram[1441] = 8'h00; ram[1442] = 8'h00; ram[1443] = 8'h00;
+ ram[1444] = 8'h00; ram[1445] = 8'h00; ram[1446] = 8'h00; ram[1447] = 8'h00;
+ ram[1448] = 8'h00; ram[1449] = 8'h00; ram[1450] = 8'h00; ram[1451] = 8'h00;
+ ram[1452] = 8'h00; ram[1453] = 8'h00; ram[1454] = 8'h00; ram[1455] = 8'h00;
+ ram[1456] = 8'h00; ram[1457] = 8'h00; ram[1458] = 8'h00; ram[1459] = 8'h00;
+ ram[1460] = 8'h00; ram[1461] = 8'h00; ram[1462] = 8'h00; ram[1463] = 8'h00;
+ ram[1464] = 8'h00; ram[1465] = 8'h00; ram[1466] = 8'h00; ram[1467] = 8'h00;
+ ram[1468] = 8'h00; ram[1469] = 8'h00; ram[1470] = 8'h00; ram[1471] = 8'h00;
+ ram[1472] = 8'h00; ram[1473] = 8'h00; ram[1474] = 8'h00; ram[1475] = 8'h00;
+ ram[1476] = 8'h00; ram[1477] = 8'h00; ram[1478] = 8'h00; ram[1479] = 8'h00;
+ ram[1480] = 8'h00; ram[1481] = 8'h00; ram[1482] = 8'h00; ram[1483] = 8'h00;
+ ram[1484] = 8'h00; ram[1485] = 8'h00; ram[1486] = 8'h00; ram[1487] = 8'h00;
+ ram[1488] = 8'h00; ram[1489] = 8'h00; ram[1490] = 8'h00; ram[1491] = 8'h00;
+ ram[1492] = 8'h00; ram[1493] = 8'h00; ram[1494] = 8'h00; ram[1495] = 8'h00;
+ ram[1496] = 8'h00; ram[1497] = 8'h00; ram[1498] = 8'h00; ram[1499] = 8'h00;
+ ram[1500] = 8'h00; ram[1501] = 8'h00; ram[1502] = 8'h00; ram[1503] = 8'h00;
+ ram[1504] = 8'h00; ram[1505] = 8'h00; ram[1506] = 8'h00; ram[1507] = 8'h00;
+ ram[1508] = 8'h00; ram[1509] = 8'h00; ram[1510] = 8'h00; ram[1511] = 8'h00;
+ ram[1512] = 8'h00; ram[1513] = 8'h00; ram[1514] = 8'h00; ram[1515] = 8'h00;
+ ram[1516] = 8'h00; ram[1517] = 8'h00; ram[1518] = 8'h00; ram[1519] = 8'h00;
+ ram[1520] = 8'h00; ram[1521] = 8'h00; ram[1522] = 8'h00; ram[1523] = 8'h00;
+ ram[1524] = 8'h00; ram[1525] = 8'h00; ram[1526] = 8'h00; ram[1527] = 8'h00;
+ ram[1528] = 8'h00; ram[1529] = 8'h00; ram[1530] = 8'h00; ram[1531] = 8'h00;
+ ram[1532] = 8'h00; ram[1533] = 8'h00; ram[1534] = 8'h00; ram[1535] = 8'h00;
+ ram[1536] = 8'h00; ram[1537] = 8'h00; ram[1538] = 8'h00; ram[1539] = 8'h00;
+ ram[1540] = 8'h00; ram[1541] = 8'h00; ram[1542] = 8'h00; ram[1543] = 8'h00;
+ ram[1544] = 8'h00; ram[1545] = 8'h00; ram[1546] = 8'h00; ram[1547] = 8'h00;
+ ram[1548] = 8'h00; ram[1549] = 8'h00; ram[1550] = 8'h00; ram[1551] = 8'h00;
+ ram[1552] = 8'h00; ram[1553] = 8'h00; ram[1554] = 8'h00; ram[1555] = 8'h00;
+ ram[1556] = 8'h00; ram[1557] = 8'h00; ram[1558] = 8'h00; ram[1559] = 8'h00;
+ ram[1560] = 8'h00; ram[1561] = 8'h00; ram[1562] = 8'h00; ram[1563] = 8'h00;
+ ram[1564] = 8'h00; ram[1565] = 8'h00; ram[1566] = 8'h00; ram[1567] = 8'h00;
+ ram[1568] = 8'h00; ram[1569] = 8'h00; ram[1570] = 8'h00; ram[1571] = 8'h00;
+ ram[1572] = 8'h00; ram[1573] = 8'h00; ram[1574] = 8'h00; ram[1575] = 8'h00;
+ ram[1576] = 8'h00; ram[1577] = 8'h00; ram[1578] = 8'h00; ram[1579] = 8'h00;
+ ram[1580] = 8'h00; ram[1581] = 8'h00; ram[1582] = 8'h00; ram[1583] = 8'h00;
+ ram[1584] = 8'h00; ram[1585] = 8'h00; ram[1586] = 8'h00; ram[1587] = 8'h00;
+ ram[1588] = 8'h00; ram[1589] = 8'h00; ram[1590] = 8'h00; ram[1591] = 8'h00;
+ ram[1592] = 8'h00; ram[1593] = 8'h00; ram[1594] = 8'h00; ram[1595] = 8'h00;
+ ram[1596] = 8'h00; ram[1597] = 8'h00; ram[1598] = 8'h00; ram[1599] = 8'h00;
+ ram[1600] = 8'h00; ram[1601] = 8'h00; ram[1602] = 8'h00; ram[1603] = 8'h00;
+ ram[1604] = 8'h00; ram[1605] = 8'h00; ram[1606] = 8'h00; ram[1607] = 8'h00;
+ ram[1608] = 8'h00; ram[1609] = 8'h00; ram[1610] = 8'h00; ram[1611] = 8'h00;
+ ram[1612] = 8'h00; ram[1613] = 8'h00; ram[1614] = 8'h00; ram[1615] = 8'h00;
+ ram[1616] = 8'h00; ram[1617] = 8'h00; ram[1618] = 8'h00; ram[1619] = 8'h00;
+ ram[1620] = 8'h00; ram[1621] = 8'h00; ram[1622] = 8'h00; ram[1623] = 8'h00;
+ ram[1624] = 8'h00; ram[1625] = 8'h00; ram[1626] = 8'h00; ram[1627] = 8'h00;
+ ram[1628] = 8'h00; ram[1629] = 8'h00; ram[1630] = 8'h00; ram[1631] = 8'h00;
+ ram[1632] = 8'h00; ram[1633] = 8'h00; ram[1634] = 8'h00; ram[1635] = 8'h00;
+ ram[1636] = 8'h00; ram[1637] = 8'h00; ram[1638] = 8'h00; ram[1639] = 8'h00;
+ ram[1640] = 8'h00; ram[1641] = 8'h00; ram[1642] = 8'h00; ram[1643] = 8'h00;
+ ram[1644] = 8'h00; ram[1645] = 8'h00; ram[1646] = 8'h00; ram[1647] = 8'h00;
+ ram[1648] = 8'h00; ram[1649] = 8'h00; ram[1650] = 8'h00; ram[1651] = 8'h00;
+ ram[1652] = 8'h00; ram[1653] = 8'h00; ram[1654] = 8'h00; ram[1655] = 8'h00;
+ ram[1656] = 8'h00; ram[1657] = 8'h00; ram[1658] = 8'h00; ram[1659] = 8'h00;
+ ram[1660] = 8'h00; ram[1661] = 8'h00; ram[1662] = 8'h00; ram[1663] = 8'h00;
+ ram[1664] = 8'h00; ram[1665] = 8'h00; ram[1666] = 8'h00; ram[1667] = 8'h00;
+ ram[1668] = 8'h00; ram[1669] = 8'h00; ram[1670] = 8'h00; ram[1671] = 8'h00;
+ ram[1672] = 8'h00; ram[1673] = 8'h00; ram[1674] = 8'h00; ram[1675] = 8'h00;
+ ram[1676] = 8'h00; ram[1677] = 8'h00; ram[1678] = 8'h00; ram[1679] = 8'h00;
+ ram[1680] = 8'h00; ram[1681] = 8'h00; ram[1682] = 8'h00; ram[1683] = 8'h00;
+ ram[1684] = 8'h00; ram[1685] = 8'h00; ram[1686] = 8'h00; ram[1687] = 8'h00;
+ ram[1688] = 8'h00; ram[1689] = 8'h00; ram[1690] = 8'h00; ram[1691] = 8'h00;
+ ram[1692] = 8'h00; ram[1693] = 8'h00; ram[1694] = 8'h00; ram[1695] = 8'h00;
+ ram[1696] = 8'h00; ram[1697] = 8'h00; ram[1698] = 8'h00; ram[1699] = 8'h00;
+ ram[1700] = 8'h00; ram[1701] = 8'h00; ram[1702] = 8'h00; ram[1703] = 8'h00;
+ ram[1704] = 8'h00; ram[1705] = 8'h00; ram[1706] = 8'h00; ram[1707] = 8'h00;
+ ram[1708] = 8'h00; ram[1709] = 8'h00; ram[1710] = 8'h00; ram[1711] = 8'h00;
+ ram[1712] = 8'h00; ram[1713] = 8'h00; ram[1714] = 8'h00; ram[1715] = 8'h00;
+ ram[1716] = 8'h00; ram[1717] = 8'h00; ram[1718] = 8'h00; ram[1719] = 8'h00;
+ ram[1720] = 8'h00; ram[1721] = 8'h00; ram[1722] = 8'h00; ram[1723] = 8'h00;
+ ram[1724] = 8'h00; ram[1725] = 8'h00; ram[1726] = 8'h00; ram[1727] = 8'h00;
+ ram[1728] = 8'h00; ram[1729] = 8'h00; ram[1730] = 8'h00; ram[1731] = 8'h00;
+ ram[1732] = 8'h00; ram[1733] = 8'h00; ram[1734] = 8'h00; ram[1735] = 8'h00;
+ ram[1736] = 8'h00; ram[1737] = 8'h00; ram[1738] = 8'h00; ram[1739] = 8'h00;
+ ram[1740] = 8'h00; ram[1741] = 8'h00; ram[1742] = 8'h00; ram[1743] = 8'h00;
+ ram[1744] = 8'h00; ram[1745] = 8'h00; ram[1746] = 8'h00; ram[1747] = 8'h00;
+ ram[1748] = 8'h00; ram[1749] = 8'h00; ram[1750] = 8'h00; ram[1751] = 8'h00;
+ ram[1752] = 8'h00; ram[1753] = 8'h00; ram[1754] = 8'h00; ram[1755] = 8'h00;
+ ram[1756] = 8'h00; ram[1757] = 8'h00; ram[1758] = 8'h00; ram[1759] = 8'h00;
+ ram[1760] = 8'h00; ram[1761] = 8'h00; ram[1762] = 8'h00; ram[1763] = 8'h00;
+ ram[1764] = 8'h00; ram[1765] = 8'h00; ram[1766] = 8'h00; ram[1767] = 8'h00;
+ ram[1768] = 8'h00; ram[1769] = 8'h00; ram[1770] = 8'h00; ram[1771] = 8'h00;
+ ram[1772] = 8'h00; ram[1773] = 8'h00; ram[1774] = 8'h00; ram[1775] = 8'h00;
+ ram[1776] = 8'h00; ram[1777] = 8'h00; ram[1778] = 8'h00; ram[1779] = 8'h00;
+ ram[1780] = 8'h00; ram[1781] = 8'h00; ram[1782] = 8'h00; ram[1783] = 8'h00;
+ ram[1784] = 8'h00; ram[1785] = 8'h00; ram[1786] = 8'h00; ram[1787] = 8'h00;
+ ram[1788] = 8'h00; ram[1789] = 8'h00; ram[1790] = 8'h00; ram[1791] = 8'h00;
+ ram[1792] = 8'h00; ram[1793] = 8'h00; ram[1794] = 8'h00; ram[1795] = 8'h00;
+ ram[1796] = 8'h00; ram[1797] = 8'h00; ram[1798] = 8'h00; ram[1799] = 8'h00;
+ ram[1800] = 8'h00; ram[1801] = 8'h00; ram[1802] = 8'h00; ram[1803] = 8'h00;
+ ram[1804] = 8'h00; ram[1805] = 8'h00; ram[1806] = 8'h00; ram[1807] = 8'h00;
+ ram[1808] = 8'h00; ram[1809] = 8'h00; ram[1810] = 8'h00; ram[1811] = 8'h00;
+ ram[1812] = 8'h00; ram[1813] = 8'h00; ram[1814] = 8'h00; ram[1815] = 8'h00;
+ ram[1816] = 8'h00; ram[1817] = 8'h00; ram[1818] = 8'h00; ram[1819] = 8'h00;
+ ram[1820] = 8'h00; ram[1821] = 8'h00; ram[1822] = 8'h00; ram[1823] = 8'h00;
+ ram[1824] = 8'h00; ram[1825] = 8'h00; ram[1826] = 8'h00; ram[1827] = 8'h00;
+ ram[1828] = 8'h00; ram[1829] = 8'h00; ram[1830] = 8'h00; ram[1831] = 8'h00;
+ ram[1832] = 8'h00; ram[1833] = 8'h00; ram[1834] = 8'h00; ram[1835] = 8'h00;
+ ram[1836] = 8'h00; ram[1837] = 8'h00; ram[1838] = 8'h00; ram[1839] = 8'h00;
+ ram[1840] = 8'h00; ram[1841] = 8'h00; ram[1842] = 8'h00; ram[1843] = 8'h00;
+ ram[1844] = 8'h00; ram[1845] = 8'h00; ram[1846] = 8'h00; ram[1847] = 8'h00;
+ ram[1848] = 8'h00; ram[1849] = 8'h00; ram[1850] = 8'h00; ram[1851] = 8'h00;
+ ram[1852] = 8'h00; ram[1853] = 8'h00; ram[1854] = 8'h00; ram[1855] = 8'h00;
+ ram[1856] = 8'h00; ram[1857] = 8'h00; ram[1858] = 8'h00; ram[1859] = 8'h00;
+ ram[1860] = 8'h00; ram[1861] = 8'h00; ram[1862] = 8'h00; ram[1863] = 8'h00;
+ ram[1864] = 8'h00; ram[1865] = 8'h00; ram[1866] = 8'h00; ram[1867] = 8'h00;
+ ram[1868] = 8'h00; ram[1869] = 8'h00; ram[1870] = 8'h00; ram[1871] = 8'h00;
+ ram[1872] = 8'h00; ram[1873] = 8'h00; ram[1874] = 8'h00; ram[1875] = 8'h00;
+ ram[1876] = 8'h00; ram[1877] = 8'h00; ram[1878] = 8'h00; ram[1879] = 8'h00;
+ ram[1880] = 8'h00; ram[1881] = 8'h00; ram[1882] = 8'h00; ram[1883] = 8'h00;
+ ram[1884] = 8'h00; ram[1885] = 8'h00; ram[1886] = 8'h00; ram[1887] = 8'h00;
+ ram[1888] = 8'h00; ram[1889] = 8'h00; ram[1890] = 8'h00; ram[1891] = 8'h00;
+ ram[1892] = 8'h00; ram[1893] = 8'h00; ram[1894] = 8'h00; ram[1895] = 8'h00;
+ ram[1896] = 8'h00; ram[1897] = 8'h00; ram[1898] = 8'h00; ram[1899] = 8'h00;
+ ram[1900] = 8'h00; ram[1901] = 8'h00; ram[1902] = 8'h00; ram[1903] = 8'h00;
+ ram[1904] = 8'h00; ram[1905] = 8'h00; ram[1906] = 8'h00; ram[1907] = 8'h00;
+ ram[1908] = 8'h00; ram[1909] = 8'h00; ram[1910] = 8'h00; ram[1911] = 8'h00;
+ ram[1912] = 8'h00; ram[1913] = 8'h00; ram[1914] = 8'h00; ram[1915] = 8'h00;
+ ram[1916] = 8'h00; ram[1917] = 8'h00; ram[1918] = 8'h00; ram[1919] = 8'h00;
+ ram[1920] = 8'h00; ram[1921] = 8'h00; ram[1922] = 8'h00; ram[1923] = 8'h00;
+ ram[1924] = 8'h00; ram[1925] = 8'h00; ram[1926] = 8'h00; ram[1927] = 8'h00;
+ ram[1928] = 8'h00; ram[1929] = 8'h00; ram[1930] = 8'h00; ram[1931] = 8'h00;
+ ram[1932] = 8'h00; ram[1933] = 8'h00; ram[1934] = 8'h00; ram[1935] = 8'h00;
+ ram[1936] = 8'h00; ram[1937] = 8'h00; ram[1938] = 8'h00; ram[1939] = 8'h00;
+ ram[1940] = 8'h00; ram[1941] = 8'h00; ram[1942] = 8'h00; ram[1943] = 8'h00;
+ ram[1944] = 8'h00; ram[1945] = 8'h00; ram[1946] = 8'h00; ram[1947] = 8'h00;
+ ram[1948] = 8'h00; ram[1949] = 8'h00; ram[1950] = 8'h00; ram[1951] = 8'h00;
+ ram[1952] = 8'h00; ram[1953] = 8'h00; ram[1954] = 8'h00; ram[1955] = 8'h00;
+ ram[1956] = 8'h00; ram[1957] = 8'h00; ram[1958] = 8'h00; ram[1959] = 8'h00;
+ ram[1960] = 8'h00; ram[1961] = 8'h00; ram[1962] = 8'h00; ram[1963] = 8'h00;
+ ram[1964] = 8'h00; ram[1965] = 8'h00; ram[1966] = 8'h00; ram[1967] = 8'h00;
+ ram[1968] = 8'h00; ram[1969] = 8'h00; ram[1970] = 8'h00; ram[1971] = 8'h00;
+ ram[1972] = 8'h00; ram[1973] = 8'h00; ram[1974] = 8'h00; ram[1975] = 8'h00;
+ ram[1976] = 8'h00; ram[1977] = 8'h00; ram[1978] = 8'h00; ram[1979] = 8'h00;
+ ram[1980] = 8'h00; ram[1981] = 8'h00; ram[1982] = 8'h00; ram[1983] = 8'h00;
+ ram[1984] = 8'h00; ram[1985] = 8'h00; ram[1986] = 8'h00; ram[1987] = 8'h00;
+ ram[1988] = 8'h00; ram[1989] = 8'h00; ram[1990] = 8'h00; ram[1991] = 8'h00;
+ ram[1992] = 8'h00; ram[1993] = 8'h00; ram[1994] = 8'h00; ram[1995] = 8'h00;
+ ram[1996] = 8'h00; ram[1997] = 8'h00; ram[1998] = 8'h00; ram[1999] = 8'h00;
+ ram[2000] = 8'h00; ram[2001] = 8'h00; ram[2002] = 8'h00; ram[2003] = 8'h00;
+ ram[2004] = 8'h00; ram[2005] = 8'h00; ram[2006] = 8'h00; ram[2007] = 8'h00;
+ ram[2008] = 8'h00; ram[2009] = 8'h00; ram[2010] = 8'h00; ram[2011] = 8'h00;
+ ram[2012] = 8'h00; ram[2013] = 8'h00; ram[2014] = 8'h00; ram[2015] = 8'h00;
+ ram[2016] = 8'h00; ram[2017] = 8'h00; ram[2018] = 8'h00; ram[2019] = 8'h00;
+ ram[2020] = 8'h00; ram[2021] = 8'h00; ram[2022] = 8'h00; ram[2023] = 8'h00;
+ ram[2024] = 8'h00; ram[2025] = 8'h00; ram[2026] = 8'h00; ram[2027] = 8'h00;
+ ram[2028] = 8'h00; ram[2029] = 8'h00; ram[2030] = 8'h00; ram[2031] = 8'h00;
+ ram[2032] = 8'h00; ram[2033] = 8'h00; ram[2034] = 8'h00; ram[2035] = 8'h00;
+ ram[2036] = 8'h00; ram[2037] = 8'h00; ram[2038] = 8'h00; ram[2039] = 8'h00;
+ ram[2040] = 8'h00; ram[2041] = 8'h00; ram[2042] = 8'h00; ram[2043] = 8'h00;
+ ram[2044] = 8'h00; ram[2045] = 8'h00; ram[2046] = 8'h00; ram[2047] = 8'h00;
+ ram[2048] = 8'h00; ram[2049] = 8'h00; ram[2050] = 8'h00; ram[2051] = 8'h00;
+ ram[2052] = 8'h00; ram[2053] = 8'h00; ram[2054] = 8'h00; ram[2055] = 8'h00;
+ ram[2056] = 8'h00; ram[2057] = 8'h00; ram[2058] = 8'h00; ram[2059] = 8'h00;
+ ram[2060] = 8'h00; ram[2061] = 8'h00; ram[2062] = 8'h00; ram[2063] = 8'h00;
+ ram[2064] = 8'h00; ram[2065] = 8'h00; ram[2066] = 8'h00; ram[2067] = 8'h00;
+ ram[2068] = 8'h00; ram[2069] = 8'h00; ram[2070] = 8'h00; ram[2071] = 8'h00;
+ ram[2072] = 8'h00; ram[2073] = 8'h00; ram[2074] = 8'h00; ram[2075] = 8'h00;
+ ram[2076] = 8'h00; ram[2077] = 8'h00; ram[2078] = 8'h00; ram[2079] = 8'h00;
+ ram[2080] = 8'h00; ram[2081] = 8'h00; ram[2082] = 8'h00; ram[2083] = 8'h00;
+ ram[2084] = 8'h00; ram[2085] = 8'h00; ram[2086] = 8'h00; ram[2087] = 8'h00;
+ ram[2088] = 8'h00; ram[2089] = 8'h00; ram[2090] = 8'h00; ram[2091] = 8'h00;
+ ram[2092] = 8'h00; ram[2093] = 8'h00; ram[2094] = 8'h00; ram[2095] = 8'h00;
+ ram[2096] = 8'h00; ram[2097] = 8'h00; ram[2098] = 8'h00; ram[2099] = 8'h00;
+ ram[2100] = 8'h00; ram[2101] = 8'h00; ram[2102] = 8'h00; ram[2103] = 8'h00;
+ ram[2104] = 8'h00; ram[2105] = 8'h00; ram[2106] = 8'h00; ram[2107] = 8'h00;
+ ram[2108] = 8'h00; ram[2109] = 8'h00; ram[2110] = 8'h00; ram[2111] = 8'h00;
+ ram[2112] = 8'h00; ram[2113] = 8'h00; ram[2114] = 8'h00; ram[2115] = 8'h00;
+ ram[2116] = 8'h00; ram[2117] = 8'h00; ram[2118] = 8'h00; ram[2119] = 8'h00;
+ ram[2120] = 8'h00; ram[2121] = 8'h00; ram[2122] = 8'h00; ram[2123] = 8'h00;
+ ram[2124] = 8'h00; ram[2125] = 8'h00; ram[2126] = 8'h00; ram[2127] = 8'h00;
+ ram[2128] = 8'h00; ram[2129] = 8'h00; ram[2130] = 8'h00; ram[2131] = 8'h00;
+ ram[2132] = 8'h00; ram[2133] = 8'h00; ram[2134] = 8'h00; ram[2135] = 8'h00;
+ ram[2136] = 8'h00; ram[2137] = 8'h00; ram[2138] = 8'h00; ram[2139] = 8'h00;
+ ram[2140] = 8'h00; ram[2141] = 8'h00; ram[2142] = 8'h00; ram[2143] = 8'h00;
+ ram[2144] = 8'h00; ram[2145] = 8'h00; ram[2146] = 8'h00; ram[2147] = 8'h00;
+ ram[2148] = 8'h00; ram[2149] = 8'h00; ram[2150] = 8'h00; ram[2151] = 8'h00;
+ ram[2152] = 8'h00; ram[2153] = 8'h00; ram[2154] = 8'h00; ram[2155] = 8'h00;
+ ram[2156] = 8'h00; ram[2157] = 8'h00; ram[2158] = 8'h00; ram[2159] = 8'h00;
+ ram[2160] = 8'h00; ram[2161] = 8'h00; ram[2162] = 8'h00; ram[2163] = 8'h00;
+ ram[2164] = 8'h00; ram[2165] = 8'h00; ram[2166] = 8'h00; ram[2167] = 8'h00;
+ ram[2168] = 8'h00; ram[2169] = 8'h00; ram[2170] = 8'h00; ram[2171] = 8'h00;
+ ram[2172] = 8'h00; ram[2173] = 8'h00; ram[2174] = 8'h00; ram[2175] = 8'h00;
+ ram[2176] = 8'h00; ram[2177] = 8'h00; ram[2178] = 8'h00; ram[2179] = 8'h00;
+ ram[2180] = 8'h00; ram[2181] = 8'h00; ram[2182] = 8'h00; ram[2183] = 8'h00;
+ ram[2184] = 8'h00; ram[2185] = 8'h00; ram[2186] = 8'h00; ram[2187] = 8'h00;
+ ram[2188] = 8'h00; ram[2189] = 8'h00; ram[2190] = 8'h00; ram[2191] = 8'h00;
+ ram[2192] = 8'h00; ram[2193] = 8'h00; ram[2194] = 8'h00; ram[2195] = 8'h00;
+ ram[2196] = 8'h00; ram[2197] = 8'h00; ram[2198] = 8'h00; ram[2199] = 8'h00;
+ ram[2200] = 8'h00; ram[2201] = 8'h00; ram[2202] = 8'h00; ram[2203] = 8'h00;
+ ram[2204] = 8'h00; ram[2205] = 8'h00; ram[2206] = 8'h00; ram[2207] = 8'h00;
+ ram[2208] = 8'h00; ram[2209] = 8'h00; ram[2210] = 8'h00; ram[2211] = 8'h00;
+ ram[2212] = 8'h00; ram[2213] = 8'h00; ram[2214] = 8'h00; ram[2215] = 8'h00;
+ ram[2216] = 8'h00; ram[2217] = 8'h00; ram[2218] = 8'h00; ram[2219] = 8'h00;
+ ram[2220] = 8'h00; ram[2221] = 8'h00; ram[2222] = 8'h00; ram[2223] = 8'h00;
+ ram[2224] = 8'h00; ram[2225] = 8'h00; ram[2226] = 8'h00; ram[2227] = 8'h00;
+ ram[2228] = 8'h00; ram[2229] = 8'h00; ram[2230] = 8'h00; ram[2231] = 8'h00;
+ ram[2232] = 8'h00; ram[2233] = 8'h00; ram[2234] = 8'h00; ram[2235] = 8'h00;
+ ram[2236] = 8'h00; ram[2237] = 8'h00; ram[2238] = 8'h00; ram[2239] = 8'h00;
+ ram[2240] = 8'h00; ram[2241] = 8'h00; ram[2242] = 8'h00; ram[2243] = 8'h00;
+ ram[2244] = 8'h00; ram[2245] = 8'h00; ram[2246] = 8'h00; ram[2247] = 8'h00;
+ ram[2248] = 8'h00; ram[2249] = 8'h00; ram[2250] = 8'h00; ram[2251] = 8'h00;
+ ram[2252] = 8'h00; ram[2253] = 8'h00; ram[2254] = 8'h00; ram[2255] = 8'h00;
+ ram[2256] = 8'h00; ram[2257] = 8'h00; ram[2258] = 8'h00; ram[2259] = 8'h00;
+ ram[2260] = 8'h00; ram[2261] = 8'h00; ram[2262] = 8'h00; ram[2263] = 8'h00;
+ ram[2264] = 8'h00; ram[2265] = 8'h00; ram[2266] = 8'h00; ram[2267] = 8'h00;
+ ram[2268] = 8'h00; ram[2269] = 8'h00; ram[2270] = 8'h00; ram[2271] = 8'h00;
+ ram[2272] = 8'h00; ram[2273] = 8'h00; ram[2274] = 8'h00; ram[2275] = 8'h00;
+ ram[2276] = 8'h00; ram[2277] = 8'h00; ram[2278] = 8'h00; ram[2279] = 8'h00;
+ ram[2280] = 8'h00; ram[2281] = 8'h00; ram[2282] = 8'h00; ram[2283] = 8'h00;
+ ram[2284] = 8'h00; ram[2285] = 8'h00; ram[2286] = 8'h00; ram[2287] = 8'h00;
+ ram[2288] = 8'h00; ram[2289] = 8'h00; ram[2290] = 8'h00; ram[2291] = 8'h00;
+ ram[2292] = 8'h00; ram[2293] = 8'h00; ram[2294] = 8'h00; ram[2295] = 8'h00;
+ ram[2296] = 8'h00; ram[2297] = 8'h00; ram[2298] = 8'h00; ram[2299] = 8'h00;
+ ram[2300] = 8'h00; ram[2301] = 8'h00; ram[2302] = 8'h00; ram[2303] = 8'h00;
+ ram[2304] = 8'h00; ram[2305] = 8'h00; ram[2306] = 8'h00; ram[2307] = 8'h00;
+ ram[2308] = 8'h00; ram[2309] = 8'h00; ram[2310] = 8'h00; ram[2311] = 8'h00;
+ ram[2312] = 8'h00; ram[2313] = 8'h00; ram[2314] = 8'h00; ram[2315] = 8'h00;
+ ram[2316] = 8'h00; ram[2317] = 8'h00; ram[2318] = 8'h00; ram[2319] = 8'h00;
+ ram[2320] = 8'h00; ram[2321] = 8'h00; ram[2322] = 8'h00; ram[2323] = 8'h00;
+ ram[2324] = 8'h00; ram[2325] = 8'h00; ram[2326] = 8'h00; ram[2327] = 8'h00;
+ ram[2328] = 8'h00; ram[2329] = 8'h00; ram[2330] = 8'h00; ram[2331] = 8'h00;
+ ram[2332] = 8'h00; ram[2333] = 8'h00; ram[2334] = 8'h00; ram[2335] = 8'h00;
+ ram[2336] = 8'h00; ram[2337] = 8'h00; ram[2338] = 8'h00; ram[2339] = 8'h00;
+ ram[2340] = 8'h00; ram[2341] = 8'h00; ram[2342] = 8'h00; ram[2343] = 8'h00;
+ ram[2344] = 8'h00; ram[2345] = 8'h00; ram[2346] = 8'h00; ram[2347] = 8'h00;
+ ram[2348] = 8'h00; ram[2349] = 8'h00; ram[2350] = 8'h00; ram[2351] = 8'h00;
+ ram[2352] = 8'h00; ram[2353] = 8'h00; ram[2354] = 8'h00; ram[2355] = 8'h00;
+ ram[2356] = 8'h00; ram[2357] = 8'h00; ram[2358] = 8'h00; ram[2359] = 8'h00;
+ ram[2360] = 8'h00; ram[2361] = 8'h00; ram[2362] = 8'h00; ram[2363] = 8'h00;
+ ram[2364] = 8'h00; ram[2365] = 8'h00; ram[2366] = 8'h00; ram[2367] = 8'h00;
+ ram[2368] = 8'h00; ram[2369] = 8'h00; ram[2370] = 8'h00; ram[2371] = 8'h00;
+ ram[2372] = 8'h00; ram[2373] = 8'h00; ram[2374] = 8'h00; ram[2375] = 8'h00;
+ ram[2376] = 8'h00; ram[2377] = 8'h00; ram[2378] = 8'h00; ram[2379] = 8'h00;
+ ram[2380] = 8'h00; ram[2381] = 8'h00; ram[2382] = 8'h00; ram[2383] = 8'h00;
+ ram[2384] = 8'h00; ram[2385] = 8'h00; ram[2386] = 8'h00; ram[2387] = 8'h00;
+ ram[2388] = 8'h00; ram[2389] = 8'h00; ram[2390] = 8'h00; ram[2391] = 8'h00;
+ ram[2392] = 8'h00; ram[2393] = 8'h00; ram[2394] = 8'h00; ram[2395] = 8'h00;
+ ram[2396] = 8'h00; ram[2397] = 8'h00; ram[2398] = 8'h00; ram[2399] = 8'h00;
+ ram[2400] = 8'h00; ram[2401] = 8'h00; ram[2402] = 8'h00; ram[2403] = 8'h00;
+ ram[2404] = 8'h00; ram[2405] = 8'h00; ram[2406] = 8'h00; ram[2407] = 8'h00;
+ ram[2408] = 8'h00; ram[2409] = 8'h00; ram[2410] = 8'h00; ram[2411] = 8'h00;
+ ram[2412] = 8'h00; ram[2413] = 8'h00; ram[2414] = 8'h00; ram[2415] = 8'h00;
+ ram[2416] = 8'h00; ram[2417] = 8'h00; ram[2418] = 8'h00; ram[2419] = 8'h00;
+ ram[2420] = 8'h00; ram[2421] = 8'h00; ram[2422] = 8'h00; ram[2423] = 8'h00;
+ ram[2424] = 8'h00; ram[2425] = 8'h00; ram[2426] = 8'h00; ram[2427] = 8'h00;
+ ram[2428] = 8'h00; ram[2429] = 8'h00; ram[2430] = 8'h00; ram[2431] = 8'h00;
+ ram[2432] = 8'h00; ram[2433] = 8'h00; ram[2434] = 8'h00; ram[2435] = 8'h00;
+ ram[2436] = 8'h00; ram[2437] = 8'h00; ram[2438] = 8'h00; ram[2439] = 8'h00;
+ ram[2440] = 8'h00; ram[2441] = 8'h00; ram[2442] = 8'h00; ram[2443] = 8'h00;
+ ram[2444] = 8'h00; ram[2445] = 8'h00; ram[2446] = 8'h00; ram[2447] = 8'h00;
+ ram[2448] = 8'h00; ram[2449] = 8'h00; ram[2450] = 8'h00; ram[2451] = 8'h00;
+ ram[2452] = 8'h00; ram[2453] = 8'h00; ram[2454] = 8'h00; ram[2455] = 8'h00;
+ ram[2456] = 8'h00; ram[2457] = 8'h00; ram[2458] = 8'h00; ram[2459] = 8'h00;
+ ram[2460] = 8'h00; ram[2461] = 8'h00; ram[2462] = 8'h00; ram[2463] = 8'h00;
+ ram[2464] = 8'h00; ram[2465] = 8'h00; ram[2466] = 8'h00; ram[2467] = 8'h00;
+ ram[2468] = 8'h00; ram[2469] = 8'h00; ram[2470] = 8'h00; ram[2471] = 8'h00;
+ ram[2472] = 8'h00; ram[2473] = 8'h00; ram[2474] = 8'h00; ram[2475] = 8'h00;
+ ram[2476] = 8'h00; ram[2477] = 8'h00; ram[2478] = 8'h00; ram[2479] = 8'h00;
+ ram[2480] = 8'h00; ram[2481] = 8'h00; ram[2482] = 8'h00; ram[2483] = 8'h00;
+ ram[2484] = 8'h00; ram[2485] = 8'h00; ram[2486] = 8'h00; ram[2487] = 8'h00;
+ ram[2488] = 8'h00; ram[2489] = 8'h00; ram[2490] = 8'h00; ram[2491] = 8'h00;
+ ram[2492] = 8'h00; ram[2493] = 8'h00; ram[2494] = 8'h00; ram[2495] = 8'h00;
+ ram[2496] = 8'h00; ram[2497] = 8'h00; ram[2498] = 8'h00; ram[2499] = 8'h00;
+ ram[2500] = 8'h00; ram[2501] = 8'h00; ram[2502] = 8'h00; ram[2503] = 8'h00;
+ ram[2504] = 8'h00; ram[2505] = 8'h00; ram[2506] = 8'h00; ram[2507] = 8'h00;
+ ram[2508] = 8'h00; ram[2509] = 8'h00; ram[2510] = 8'h00; ram[2511] = 8'h00;
+ ram[2512] = 8'h00; ram[2513] = 8'h00; ram[2514] = 8'h00; ram[2515] = 8'h00;
+ ram[2516] = 8'h00; ram[2517] = 8'h00; ram[2518] = 8'h00; ram[2519] = 8'h00;
+ ram[2520] = 8'h00; ram[2521] = 8'h00; ram[2522] = 8'h00; ram[2523] = 8'h00;
+ ram[2524] = 8'h00; ram[2525] = 8'h00; ram[2526] = 8'h00; ram[2527] = 8'h00;
+ ram[2528] = 8'h00; ram[2529] = 8'h00; ram[2530] = 8'h00; ram[2531] = 8'h00;
+ ram[2532] = 8'h00; ram[2533] = 8'h00; ram[2534] = 8'h00; ram[2535] = 8'h00;
+ ram[2536] = 8'h00; ram[2537] = 8'h00; ram[2538] = 8'h00; ram[2539] = 8'h00;
+ ram[2540] = 8'h00; ram[2541] = 8'h00; ram[2542] = 8'h00; ram[2543] = 8'h00;
+ ram[2544] = 8'h00; ram[2545] = 8'h00; ram[2546] = 8'h00; ram[2547] = 8'h00;
+ ram[2548] = 8'h00; ram[2549] = 8'h00; ram[2550] = 8'h00; ram[2551] = 8'h00;
+ ram[2552] = 8'h00; ram[2553] = 8'h00; ram[2554] = 8'h00; ram[2555] = 8'h00;
+ ram[2556] = 8'h00; ram[2557] = 8'h00; ram[2558] = 8'h00; ram[2559] = 8'h00;
+ ram[2560] = 8'h00; ram[2561] = 8'h00; ram[2562] = 8'h00; ram[2563] = 8'h00;
+ ram[2564] = 8'h00; ram[2565] = 8'h00; ram[2566] = 8'h00; ram[2567] = 8'h00;
+ ram[2568] = 8'h00; ram[2569] = 8'h00; ram[2570] = 8'h00; ram[2571] = 8'h00;
+ ram[2572] = 8'h00; ram[2573] = 8'h00; ram[2574] = 8'h00; ram[2575] = 8'h00;
+ ram[2576] = 8'h00; ram[2577] = 8'h00; ram[2578] = 8'h00; ram[2579] = 8'h00;
+ ram[2580] = 8'h00; ram[2581] = 8'h00; ram[2582] = 8'h00; ram[2583] = 8'h00;
+ ram[2584] = 8'h00; ram[2585] = 8'h00; ram[2586] = 8'h00; ram[2587] = 8'h00;
+ ram[2588] = 8'h00; ram[2589] = 8'h00; ram[2590] = 8'h00; ram[2591] = 8'h00;
+ ram[2592] = 8'h00; ram[2593] = 8'h00; ram[2594] = 8'h00; ram[2595] = 8'h00;
+ ram[2596] = 8'h00; ram[2597] = 8'h00; ram[2598] = 8'h00; ram[2599] = 8'h00;
+ ram[2600] = 8'h00; ram[2601] = 8'h00; ram[2602] = 8'h00; ram[2603] = 8'h00;
+ ram[2604] = 8'h00; ram[2605] = 8'h00; ram[2606] = 8'h00; ram[2607] = 8'h00;
+ ram[2608] = 8'h00; ram[2609] = 8'h00; ram[2610] = 8'h00; ram[2611] = 8'h00;
+ ram[2612] = 8'h00; ram[2613] = 8'h00; ram[2614] = 8'h00; ram[2615] = 8'h00;
+ ram[2616] = 8'h00; ram[2617] = 8'h00; ram[2618] = 8'h00; ram[2619] = 8'h00;
+ ram[2620] = 8'h00; ram[2621] = 8'h00; ram[2622] = 8'h00; ram[2623] = 8'h00;
+ ram[2624] = 8'h00; ram[2625] = 8'h00; ram[2626] = 8'h00; ram[2627] = 8'h00;
+ ram[2628] = 8'h00; ram[2629] = 8'h00; ram[2630] = 8'h00; ram[2631] = 8'h00;
+ ram[2632] = 8'h00; ram[2633] = 8'h00; ram[2634] = 8'h00; ram[2635] = 8'h00;
+ ram[2636] = 8'h00; ram[2637] = 8'h00; ram[2638] = 8'h00; ram[2639] = 8'h00;
+ ram[2640] = 8'h00; ram[2641] = 8'h00; ram[2642] = 8'h00; ram[2643] = 8'h00;
+ ram[2644] = 8'h00; ram[2645] = 8'h00; ram[2646] = 8'h00; ram[2647] = 8'h00;
+ ram[2648] = 8'h00; ram[2649] = 8'h00; ram[2650] = 8'h00; ram[2651] = 8'h00;
+ ram[2652] = 8'h00; ram[2653] = 8'h00; ram[2654] = 8'h00; ram[2655] = 8'h00;
+ ram[2656] = 8'h00; ram[2657] = 8'h00; ram[2658] = 8'h00; ram[2659] = 8'h00;
+ ram[2660] = 8'h00; ram[2661] = 8'h00; ram[2662] = 8'h00; ram[2663] = 8'h00;
+ ram[2664] = 8'h00; ram[2665] = 8'h00; ram[2666] = 8'h00; ram[2667] = 8'h00;
+ ram[2668] = 8'h00; ram[2669] = 8'h00; ram[2670] = 8'h00; ram[2671] = 8'h00;
+ ram[2672] = 8'h00; ram[2673] = 8'h00; ram[2674] = 8'h00; ram[2675] = 8'h00;
+ ram[2676] = 8'h00; ram[2677] = 8'h00; ram[2678] = 8'h00; ram[2679] = 8'h00;
+ ram[2680] = 8'h00; ram[2681] = 8'h00; ram[2682] = 8'h00; ram[2683] = 8'h00;
+ ram[2684] = 8'h00; ram[2685] = 8'h00; ram[2686] = 8'h00; ram[2687] = 8'h00;
+ ram[2688] = 8'h00; ram[2689] = 8'h00; ram[2690] = 8'h00; ram[2691] = 8'h00;
+ ram[2692] = 8'h00; ram[2693] = 8'h00; ram[2694] = 8'h00; ram[2695] = 8'h00;
+ ram[2696] = 8'h00; ram[2697] = 8'h00; ram[2698] = 8'h00; ram[2699] = 8'h00;
+ ram[2700] = 8'h00; ram[2701] = 8'h00; ram[2702] = 8'h00; ram[2703] = 8'h00;
+ ram[2704] = 8'h00; ram[2705] = 8'h00; ram[2706] = 8'h00; ram[2707] = 8'h00;
+ ram[2708] = 8'h00; ram[2709] = 8'h00; ram[2710] = 8'h00; ram[2711] = 8'h00;
+ ram[2712] = 8'h00; ram[2713] = 8'h00; ram[2714] = 8'h00; ram[2715] = 8'h00;
+ ram[2716] = 8'h00; ram[2717] = 8'h00; ram[2718] = 8'h00; ram[2719] = 8'h00;
+ ram[2720] = 8'h00; ram[2721] = 8'h00; ram[2722] = 8'h00; ram[2723] = 8'h00;
+ ram[2724] = 8'h00; ram[2725] = 8'h00; ram[2726] = 8'h00; ram[2727] = 8'h00;
+ ram[2728] = 8'h00; ram[2729] = 8'h00; ram[2730] = 8'h00; ram[2731] = 8'h00;
+ ram[2732] = 8'h00; ram[2733] = 8'h00; ram[2734] = 8'h00; ram[2735] = 8'h00;
+ ram[2736] = 8'h00; ram[2737] = 8'h00; ram[2738] = 8'h00; ram[2739] = 8'h00;
+ ram[2740] = 8'h00; ram[2741] = 8'h00; ram[2742] = 8'h00; ram[2743] = 8'h00;
+ ram[2744] = 8'h00; ram[2745] = 8'h00; ram[2746] = 8'h00; ram[2747] = 8'h00;
+ ram[2748] = 8'h00; ram[2749] = 8'h00; ram[2750] = 8'h00; ram[2751] = 8'h00;
+ ram[2752] = 8'h00; ram[2753] = 8'h00; ram[2754] = 8'h00; ram[2755] = 8'h00;
+ ram[2756] = 8'h00; ram[2757] = 8'h00; ram[2758] = 8'h00; ram[2759] = 8'h00;
+ ram[2760] = 8'h00; ram[2761] = 8'h00; ram[2762] = 8'h00; ram[2763] = 8'h00;
+ ram[2764] = 8'h00; ram[2765] = 8'h00; ram[2766] = 8'h00; ram[2767] = 8'h00;
+ ram[2768] = 8'h00; ram[2769] = 8'h00; ram[2770] = 8'h00; ram[2771] = 8'h00;
+ ram[2772] = 8'h00; ram[2773] = 8'h00; ram[2774] = 8'h00; ram[2775] = 8'h00;
+ ram[2776] = 8'h00; ram[2777] = 8'h00; ram[2778] = 8'h00; ram[2779] = 8'h00;
+ ram[2780] = 8'h00; ram[2781] = 8'h00; ram[2782] = 8'h00; ram[2783] = 8'h00;
+ ram[2784] = 8'h00; ram[2785] = 8'h00; ram[2786] = 8'h00; ram[2787] = 8'h00;
+ ram[2788] = 8'h00; ram[2789] = 8'h00; ram[2790] = 8'h00; ram[2791] = 8'h00;
+ ram[2792] = 8'h00; ram[2793] = 8'h00; ram[2794] = 8'h00; ram[2795] = 8'h00;
+ ram[2796] = 8'h00; ram[2797] = 8'h00; ram[2798] = 8'h00; ram[2799] = 8'h00;
+ ram[2800] = 8'h00; ram[2801] = 8'h00; ram[2802] = 8'h00; ram[2803] = 8'h00;
+ ram[2804] = 8'h00; ram[2805] = 8'h00; ram[2806] = 8'h00; ram[2807] = 8'h00;
+ ram[2808] = 8'h00; ram[2809] = 8'h00; ram[2810] = 8'h00; ram[2811] = 8'h00;
+ ram[2812] = 8'h00; ram[2813] = 8'h00; ram[2814] = 8'h00; ram[2815] = 8'h00;
+ ram[2816] = 8'h00; ram[2817] = 8'h00; ram[2818] = 8'h00; ram[2819] = 8'h00;
+ ram[2820] = 8'h00; ram[2821] = 8'h00; ram[2822] = 8'h00; ram[2823] = 8'h00;
+ ram[2824] = 8'h00; ram[2825] = 8'h00; ram[2826] = 8'h00; ram[2827] = 8'h00;
+ ram[2828] = 8'h00; ram[2829] = 8'h00; ram[2830] = 8'h00; ram[2831] = 8'h00;
+ ram[2832] = 8'h00; ram[2833] = 8'h00; ram[2834] = 8'h00; ram[2835] = 8'h00;
+ ram[2836] = 8'h00; ram[2837] = 8'h00; ram[2838] = 8'h00; ram[2839] = 8'h00;
+ ram[2840] = 8'h00; ram[2841] = 8'h00; ram[2842] = 8'h00; ram[2843] = 8'h00;
+ ram[2844] = 8'h00; ram[2845] = 8'h00; ram[2846] = 8'h00; ram[2847] = 8'h00;
+ ram[2848] = 8'h00; ram[2849] = 8'h00; ram[2850] = 8'h00; ram[2851] = 8'h00;
+ ram[2852] = 8'h00; ram[2853] = 8'h00; ram[2854] = 8'h00; ram[2855] = 8'h00;
+ ram[2856] = 8'h00; ram[2857] = 8'h00; ram[2858] = 8'h00; ram[2859] = 8'h00;
+ ram[2860] = 8'h00; ram[2861] = 8'h00; ram[2862] = 8'h00; ram[2863] = 8'h00;
+ ram[2864] = 8'h00; ram[2865] = 8'h00; ram[2866] = 8'h00; ram[2867] = 8'h00;
+ ram[2868] = 8'h00; ram[2869] = 8'h00; ram[2870] = 8'h00; ram[2871] = 8'h00;
+ ram[2872] = 8'h00; ram[2873] = 8'h00; ram[2874] = 8'h00; ram[2875] = 8'h00;
+ ram[2876] = 8'h00; ram[2877] = 8'h00; ram[2878] = 8'h00; ram[2879] = 8'h00;
+ ram[2880] = 8'h00; ram[2881] = 8'h00; ram[2882] = 8'h00; ram[2883] = 8'h00;
+ ram[2884] = 8'h00; ram[2885] = 8'h00; ram[2886] = 8'h00; ram[2887] = 8'h00;
+ ram[2888] = 8'h00; ram[2889] = 8'h00; ram[2890] = 8'h00; ram[2891] = 8'h00;
+ ram[2892] = 8'h00; ram[2893] = 8'h00; ram[2894] = 8'h00; ram[2895] = 8'h00;
+ ram[2896] = 8'h00; ram[2897] = 8'h00; ram[2898] = 8'h00; ram[2899] = 8'h00;
+ ram[2900] = 8'h00; ram[2901] = 8'h00; ram[2902] = 8'h00; ram[2903] = 8'h00;
+ ram[2904] = 8'h00; ram[2905] = 8'h00; ram[2906] = 8'h00; ram[2907] = 8'h00;
+ ram[2908] = 8'h00; ram[2909] = 8'h00; ram[2910] = 8'h00; ram[2911] = 8'h00;
+ ram[2912] = 8'h00; ram[2913] = 8'h00; ram[2914] = 8'h00; ram[2915] = 8'h00;
+ ram[2916] = 8'h00; ram[2917] = 8'h00; ram[2918] = 8'h00; ram[2919] = 8'h00;
+ ram[2920] = 8'h00; ram[2921] = 8'h00; ram[2922] = 8'h00; ram[2923] = 8'h00;
+ ram[2924] = 8'h00; ram[2925] = 8'h00; ram[2926] = 8'h00; ram[2927] = 8'h00;
+ ram[2928] = 8'h00; ram[2929] = 8'h00; ram[2930] = 8'h00; ram[2931] = 8'h00;
+ ram[2932] = 8'h00; ram[2933] = 8'h00; ram[2934] = 8'h00; ram[2935] = 8'h00;
+ ram[2936] = 8'h00; ram[2937] = 8'h00; ram[2938] = 8'h00; ram[2939] = 8'h00;
+ ram[2940] = 8'h00; ram[2941] = 8'h00; ram[2942] = 8'h00; ram[2943] = 8'h00;
+ ram[2944] = 8'h00; ram[2945] = 8'h00; ram[2946] = 8'h00; ram[2947] = 8'h00;
+ ram[2948] = 8'h00; ram[2949] = 8'h00; ram[2950] = 8'h00; ram[2951] = 8'h00;
+ ram[2952] = 8'h00; ram[2953] = 8'h00; ram[2954] = 8'h00; ram[2955] = 8'h00;
+ ram[2956] = 8'h00; ram[2957] = 8'h00; ram[2958] = 8'h00; ram[2959] = 8'h00;
+ ram[2960] = 8'h00; ram[2961] = 8'h00; ram[2962] = 8'h00; ram[2963] = 8'h00;
+ ram[2964] = 8'h00; ram[2965] = 8'h00; ram[2966] = 8'h00; ram[2967] = 8'h00;
+ ram[2968] = 8'h00; ram[2969] = 8'h00; ram[2970] = 8'h00; ram[2971] = 8'h00;
+ ram[2972] = 8'h00; ram[2973] = 8'h00; ram[2974] = 8'h00; ram[2975] = 8'h00;
+ ram[2976] = 8'h00; ram[2977] = 8'h00; ram[2978] = 8'h00; ram[2979] = 8'h00;
+ ram[2980] = 8'h00; ram[2981] = 8'h00; ram[2982] = 8'h00; ram[2983] = 8'h00;
+ ram[2984] = 8'h00; ram[2985] = 8'h00; ram[2986] = 8'h00; ram[2987] = 8'h00;
+ ram[2988] = 8'h00; ram[2989] = 8'h00; ram[2990] = 8'h00; ram[2991] = 8'h00;
+ ram[2992] = 8'h00; ram[2993] = 8'h00; ram[2994] = 8'h00; ram[2995] = 8'h00;
+ ram[2996] = 8'h00; ram[2997] = 8'h00; ram[2998] = 8'h00; ram[2999] = 8'h00;
+ ram[3000] = 8'h00; ram[3001] = 8'h00; ram[3002] = 8'h00; ram[3003] = 8'h00;
+ ram[3004] = 8'h00; ram[3005] = 8'h00; ram[3006] = 8'h00; ram[3007] = 8'h00;
+ ram[3008] = 8'h00; ram[3009] = 8'h00; ram[3010] = 8'h00; ram[3011] = 8'h00;
+ ram[3012] = 8'h00; ram[3013] = 8'h00; ram[3014] = 8'h00; ram[3015] = 8'h00;
+ ram[3016] = 8'h00; ram[3017] = 8'h00; ram[3018] = 8'h00; ram[3019] = 8'h00;
+ ram[3020] = 8'h00; ram[3021] = 8'h00; ram[3022] = 8'h00; ram[3023] = 8'h00;
+ ram[3024] = 8'h00; ram[3025] = 8'h00; ram[3026] = 8'h00; ram[3027] = 8'h00;
+ ram[3028] = 8'h00; ram[3029] = 8'h00; ram[3030] = 8'h00; ram[3031] = 8'h00;
+ ram[3032] = 8'h00; ram[3033] = 8'h00; ram[3034] = 8'h00; ram[3035] = 8'h00;
+ ram[3036] = 8'h00; ram[3037] = 8'h00; ram[3038] = 8'h00; ram[3039] = 8'h00;
+ ram[3040] = 8'h00; ram[3041] = 8'h00; ram[3042] = 8'h00; ram[3043] = 8'h00;
+ ram[3044] = 8'h00; ram[3045] = 8'h00; ram[3046] = 8'h00; ram[3047] = 8'h00;
+ ram[3048] = 8'h00; ram[3049] = 8'h00; ram[3050] = 8'h00; ram[3051] = 8'h00;
+ ram[3052] = 8'h00; ram[3053] = 8'h00; ram[3054] = 8'h00; ram[3055] = 8'h00;
+ ram[3056] = 8'h00; ram[3057] = 8'h00; ram[3058] = 8'h00; ram[3059] = 8'h00;
+ ram[3060] = 8'h00; ram[3061] = 8'h00; ram[3062] = 8'h00; ram[3063] = 8'h00;
+ ram[3064] = 8'h00; ram[3065] = 8'h00; ram[3066] = 8'h00; ram[3067] = 8'h00;
+ ram[3068] = 8'h00; ram[3069] = 8'h00; ram[3070] = 8'h00; ram[3071] = 8'h00;
+ ram[3072] = 8'h00; ram[3073] = 8'h00; ram[3074] = 8'h00; ram[3075] = 8'h00;
+ ram[3076] = 8'h00; ram[3077] = 8'h00; ram[3078] = 8'h00; ram[3079] = 8'h00;
+ ram[3080] = 8'h00; ram[3081] = 8'h00; ram[3082] = 8'h00; ram[3083] = 8'h00;
+ ram[3084] = 8'h00; ram[3085] = 8'h00; ram[3086] = 8'h00; ram[3087] = 8'h00;
+ ram[3088] = 8'h00; ram[3089] = 8'h00; ram[3090] = 8'h00; ram[3091] = 8'h00;
+ ram[3092] = 8'h00; ram[3093] = 8'h00; ram[3094] = 8'h00; ram[3095] = 8'h00;
+ ram[3096] = 8'h00; ram[3097] = 8'h00; ram[3098] = 8'h00; ram[3099] = 8'h00;
+ ram[3100] = 8'h00; ram[3101] = 8'h00; ram[3102] = 8'h00; ram[3103] = 8'h00;
+ ram[3104] = 8'h00; ram[3105] = 8'h00; ram[3106] = 8'h00; ram[3107] = 8'h00;
+ ram[3108] = 8'h00; ram[3109] = 8'h00; ram[3110] = 8'h00; ram[3111] = 8'h00;
+ ram[3112] = 8'h00; ram[3113] = 8'h00; ram[3114] = 8'h00; ram[3115] = 8'h00;
+ ram[3116] = 8'h00; ram[3117] = 8'h00; ram[3118] = 8'h00; ram[3119] = 8'h00;
+ ram[3120] = 8'h00; ram[3121] = 8'h00; ram[3122] = 8'h00; ram[3123] = 8'h00;
+ ram[3124] = 8'h00; ram[3125] = 8'h00; ram[3126] = 8'h00; ram[3127] = 8'h00;
+ ram[3128] = 8'h00; ram[3129] = 8'h00; ram[3130] = 8'h00; ram[3131] = 8'h00;
+ ram[3132] = 8'h00; ram[3133] = 8'h00; ram[3134] = 8'h00; ram[3135] = 8'h00;
+ ram[3136] = 8'h00; ram[3137] = 8'h00; ram[3138] = 8'h00; ram[3139] = 8'h00;
+ ram[3140] = 8'h00; ram[3141] = 8'h00; ram[3142] = 8'h00; ram[3143] = 8'h00;
+ ram[3144] = 8'h00; ram[3145] = 8'h00; ram[3146] = 8'h00; ram[3147] = 8'h00;
+ ram[3148] = 8'h00; ram[3149] = 8'h00; ram[3150] = 8'h00; ram[3151] = 8'h00;
+ ram[3152] = 8'h00; ram[3153] = 8'h00; ram[3154] = 8'h00; ram[3155] = 8'h00;
+ ram[3156] = 8'h00; ram[3157] = 8'h00; ram[3158] = 8'h00; ram[3159] = 8'h00;
+ ram[3160] = 8'h00; ram[3161] = 8'h00; ram[3162] = 8'h00; ram[3163] = 8'h00;
+ ram[3164] = 8'h00; ram[3165] = 8'h00; ram[3166] = 8'h00; ram[3167] = 8'h00;
+ ram[3168] = 8'h00; ram[3169] = 8'h00; ram[3170] = 8'h00; ram[3171] = 8'h00;
+ ram[3172] = 8'h00; ram[3173] = 8'h00; ram[3174] = 8'h00; ram[3175] = 8'h00;
+ ram[3176] = 8'h00; ram[3177] = 8'h00; ram[3178] = 8'h00; ram[3179] = 8'h00;
+ ram[3180] = 8'h00; ram[3181] = 8'h00; ram[3182] = 8'h00; ram[3183] = 8'h00;
+ ram[3184] = 8'h00; ram[3185] = 8'h00; ram[3186] = 8'h00; ram[3187] = 8'h00;
+ ram[3188] = 8'h00; ram[3189] = 8'h00; ram[3190] = 8'h00; ram[3191] = 8'h00;
+ ram[3192] = 8'h00; ram[3193] = 8'h00; ram[3194] = 8'h00; ram[3195] = 8'h00;
+ ram[3196] = 8'h00; ram[3197] = 8'h00; ram[3198] = 8'h00; ram[3199] = 8'h00;
+ ram[3200] = 8'h00; ram[3201] = 8'h00; ram[3202] = 8'h00; ram[3203] = 8'h00;
+ ram[3204] = 8'h00; ram[3205] = 8'h00; ram[3206] = 8'h00; ram[3207] = 8'h00;
+ ram[3208] = 8'h00; ram[3209] = 8'h00; ram[3210] = 8'h00; ram[3211] = 8'h00;
+ ram[3212] = 8'h00; ram[3213] = 8'h00; ram[3214] = 8'h00; ram[3215] = 8'h00;
+ ram[3216] = 8'h00; ram[3217] = 8'h00; ram[3218] = 8'h00; ram[3219] = 8'h00;
+ ram[3220] = 8'h00; ram[3221] = 8'h00; ram[3222] = 8'h00; ram[3223] = 8'h00;
+ ram[3224] = 8'h00; ram[3225] = 8'h00; ram[3226] = 8'h00; ram[3227] = 8'h00;
+ ram[3228] = 8'h00; ram[3229] = 8'h00; ram[3230] = 8'h00; ram[3231] = 8'h00;
+ ram[3232] = 8'h00; ram[3233] = 8'h00; ram[3234] = 8'h00; ram[3235] = 8'h00;
+ ram[3236] = 8'h00; ram[3237] = 8'h00; ram[3238] = 8'h00; ram[3239] = 8'h00;
+ ram[3240] = 8'h00; ram[3241] = 8'h00; ram[3242] = 8'h00; ram[3243] = 8'h00;
+ ram[3244] = 8'h00; ram[3245] = 8'h00; ram[3246] = 8'h00; ram[3247] = 8'h00;
+ ram[3248] = 8'h00; ram[3249] = 8'h00; ram[3250] = 8'h00; ram[3251] = 8'h00;
+ ram[3252] = 8'h00; ram[3253] = 8'h00; ram[3254] = 8'h00; ram[3255] = 8'h00;
+ ram[3256] = 8'h00; ram[3257] = 8'h00; ram[3258] = 8'h00; ram[3259] = 8'h00;
+ ram[3260] = 8'h00; ram[3261] = 8'h00; ram[3262] = 8'h00; ram[3263] = 8'h00;
+ ram[3264] = 8'h00; ram[3265] = 8'h00; ram[3266] = 8'h00; ram[3267] = 8'h00;
+ ram[3268] = 8'h00; ram[3269] = 8'h00; ram[3270] = 8'h00; ram[3271] = 8'h00;
+ ram[3272] = 8'h00; ram[3273] = 8'h00; ram[3274] = 8'h00; ram[3275] = 8'h00;
+ ram[3276] = 8'h00; ram[3277] = 8'h00; ram[3278] = 8'h00; ram[3279] = 8'h00;
+ ram[3280] = 8'h00; ram[3281] = 8'h00; ram[3282] = 8'h00; ram[3283] = 8'h00;
+ ram[3284] = 8'h00; ram[3285] = 8'h00; ram[3286] = 8'h00; ram[3287] = 8'h00;
+ ram[3288] = 8'h00; ram[3289] = 8'h00; ram[3290] = 8'h00; ram[3291] = 8'h00;
+ ram[3292] = 8'h00; ram[3293] = 8'h00; ram[3294] = 8'h00; ram[3295] = 8'h00;
+ ram[3296] = 8'h00; ram[3297] = 8'h00; ram[3298] = 8'h00; ram[3299] = 8'h00;
+ ram[3300] = 8'h00; ram[3301] = 8'h00; ram[3302] = 8'h00; ram[3303] = 8'h00;
+ ram[3304] = 8'h00; ram[3305] = 8'h00; ram[3306] = 8'h00; ram[3307] = 8'h00;
+ ram[3308] = 8'h00; ram[3309] = 8'h00; ram[3310] = 8'h00; ram[3311] = 8'h00;
+ ram[3312] = 8'h00; ram[3313] = 8'h00; ram[3314] = 8'h00; ram[3315] = 8'h00;
+ ram[3316] = 8'h00; ram[3317] = 8'h00; ram[3318] = 8'h00; ram[3319] = 8'h00;
+ ram[3320] = 8'h00; ram[3321] = 8'h00; ram[3322] = 8'h00; ram[3323] = 8'h00;
+ ram[3324] = 8'h00; ram[3325] = 8'h00; ram[3326] = 8'h00; ram[3327] = 8'h00;
+ ram[3328] = 8'h00; ram[3329] = 8'h00; ram[3330] = 8'h00; ram[3331] = 8'h00;
+ ram[3332] = 8'h00; ram[3333] = 8'h00; ram[3334] = 8'h00; ram[3335] = 8'h00;
+ ram[3336] = 8'h00; ram[3337] = 8'h00; ram[3338] = 8'h00; ram[3339] = 8'h00;
+ ram[3340] = 8'h00; ram[3341] = 8'h00; ram[3342] = 8'h00; ram[3343] = 8'h00;
+ ram[3344] = 8'h00; ram[3345] = 8'h00; ram[3346] = 8'h00; ram[3347] = 8'h00;
+ ram[3348] = 8'h00; ram[3349] = 8'h00; ram[3350] = 8'h00; ram[3351] = 8'h00;
+ ram[3352] = 8'h00; ram[3353] = 8'h00; ram[3354] = 8'h00; ram[3355] = 8'h00;
+ ram[3356] = 8'h00; ram[3357] = 8'h00; ram[3358] = 8'h00; ram[3359] = 8'h00;
+ ram[3360] = 8'h00; ram[3361] = 8'h00; ram[3362] = 8'h00; ram[3363] = 8'h00;
+ ram[3364] = 8'h00; ram[3365] = 8'h00; ram[3366] = 8'h00; ram[3367] = 8'h00;
+ ram[3368] = 8'h00; ram[3369] = 8'h00; ram[3370] = 8'h00; ram[3371] = 8'h00;
+ ram[3372] = 8'h00; ram[3373] = 8'h00; ram[3374] = 8'h00; ram[3375] = 8'h00;
+ ram[3376] = 8'h00; ram[3377] = 8'h00; ram[3378] = 8'h00; ram[3379] = 8'h00;
+ ram[3380] = 8'h00; ram[3381] = 8'h00; ram[3382] = 8'h00; ram[3383] = 8'h00;
+ ram[3384] = 8'h00; ram[3385] = 8'h00; ram[3386] = 8'h00; ram[3387] = 8'h00;
+ ram[3388] = 8'h00; ram[3389] = 8'h00; ram[3390] = 8'h00; ram[3391] = 8'h00;
+ ram[3392] = 8'h00; ram[3393] = 8'h00; ram[3394] = 8'h00; ram[3395] = 8'h00;
+ ram[3396] = 8'h00; ram[3397] = 8'h00; ram[3398] = 8'h00; ram[3399] = 8'h00;
+ ram[3400] = 8'h00; ram[3401] = 8'h00; ram[3402] = 8'h00; ram[3403] = 8'h00;
+ ram[3404] = 8'h00; ram[3405] = 8'h00; ram[3406] = 8'h00; ram[3407] = 8'h00;
+ ram[3408] = 8'h00; ram[3409] = 8'h00; ram[3410] = 8'h00; ram[3411] = 8'h00;
+ ram[3412] = 8'h00; ram[3413] = 8'h00; ram[3414] = 8'h00; ram[3415] = 8'h00;
+ ram[3416] = 8'h00; ram[3417] = 8'h00; ram[3418] = 8'h00; ram[3419] = 8'h00;
+ ram[3420] = 8'h00; ram[3421] = 8'h00; ram[3422] = 8'h00; ram[3423] = 8'h00;
+ ram[3424] = 8'h00; ram[3425] = 8'h00; ram[3426] = 8'h00; ram[3427] = 8'h00;
+ ram[3428] = 8'h00; ram[3429] = 8'h00; ram[3430] = 8'h00; ram[3431] = 8'h00;
+ ram[3432] = 8'h00; ram[3433] = 8'h00; ram[3434] = 8'h00; ram[3435] = 8'h00;
+ ram[3436] = 8'h00; ram[3437] = 8'h00; ram[3438] = 8'h00; ram[3439] = 8'h00;
+ ram[3440] = 8'h00; ram[3441] = 8'h00; ram[3442] = 8'h00; ram[3443] = 8'h00;
+ ram[3444] = 8'h00; ram[3445] = 8'h00; ram[3446] = 8'h00; ram[3447] = 8'h00;
+ ram[3448] = 8'h00; ram[3449] = 8'h00; ram[3450] = 8'h00; ram[3451] = 8'h00;
+ ram[3452] = 8'h00; ram[3453] = 8'h00; ram[3454] = 8'h00; ram[3455] = 8'h00;
+ ram[3456] = 8'h00; ram[3457] = 8'h00; ram[3458] = 8'h00; ram[3459] = 8'h00;
+ ram[3460] = 8'h00; ram[3461] = 8'h00; ram[3462] = 8'h00; ram[3463] = 8'h00;
+ ram[3464] = 8'h00; ram[3465] = 8'h00; ram[3466] = 8'h00; ram[3467] = 8'h00;
+ ram[3468] = 8'h00; ram[3469] = 8'h00; ram[3470] = 8'h00; ram[3471] = 8'h00;
+ ram[3472] = 8'h00; ram[3473] = 8'h00; ram[3474] = 8'h00; ram[3475] = 8'h00;
+ ram[3476] = 8'h00; ram[3477] = 8'h00; ram[3478] = 8'h00; ram[3479] = 8'h00;
+ ram[3480] = 8'h00; ram[3481] = 8'h00; ram[3482] = 8'h00; ram[3483] = 8'h00;
+ ram[3484] = 8'h00; ram[3485] = 8'h00; ram[3486] = 8'h00; ram[3487] = 8'h00;
+ ram[3488] = 8'h00; ram[3489] = 8'h00; ram[3490] = 8'h00; ram[3491] = 8'h00;
+ ram[3492] = 8'h00; ram[3493] = 8'h00; ram[3494] = 8'h00; ram[3495] = 8'h00;
+ ram[3496] = 8'h00; ram[3497] = 8'h00; ram[3498] = 8'h00; ram[3499] = 8'h00;
+ ram[3500] = 8'h00; ram[3501] = 8'h00; ram[3502] = 8'h00; ram[3503] = 8'h00;
+ ram[3504] = 8'h00; ram[3505] = 8'h00; ram[3506] = 8'h00; ram[3507] = 8'h00;
+ ram[3508] = 8'h00; ram[3509] = 8'h00; ram[3510] = 8'h00; ram[3511] = 8'h00;
+ ram[3512] = 8'h00; ram[3513] = 8'h00; ram[3514] = 8'h00; ram[3515] = 8'h00;
+ ram[3516] = 8'h00; ram[3517] = 8'h00; ram[3518] = 8'h00; ram[3519] = 8'h00;
+ ram[3520] = 8'h00; ram[3521] = 8'h00; ram[3522] = 8'h00; ram[3523] = 8'h00;
+ ram[3524] = 8'h00; ram[3525] = 8'h00; ram[3526] = 8'h00; ram[3527] = 8'h00;
+ ram[3528] = 8'h00; ram[3529] = 8'h00; ram[3530] = 8'h00; ram[3531] = 8'h00;
+ ram[3532] = 8'h00; ram[3533] = 8'h00; ram[3534] = 8'h00; ram[3535] = 8'h00;
+ ram[3536] = 8'h00; ram[3537] = 8'h00; ram[3538] = 8'h00; ram[3539] = 8'h00;
+ ram[3540] = 8'h00; ram[3541] = 8'h00; ram[3542] = 8'h00; ram[3543] = 8'h00;
+ ram[3544] = 8'h00; ram[3545] = 8'h00; ram[3546] = 8'h00; ram[3547] = 8'h00;
+ ram[3548] = 8'h00; ram[3549] = 8'h00; ram[3550] = 8'h00; ram[3551] = 8'h00;
+ ram[3552] = 8'h00; ram[3553] = 8'h00; ram[3554] = 8'h00; ram[3555] = 8'h00;
+ ram[3556] = 8'h00; ram[3557] = 8'h00; ram[3558] = 8'h00; ram[3559] = 8'h00;
+ ram[3560] = 8'h00; ram[3561] = 8'h00; ram[3562] = 8'h00; ram[3563] = 8'h00;
+ ram[3564] = 8'h00; ram[3565] = 8'h00; ram[3566] = 8'h00; ram[3567] = 8'h00;
+ ram[3568] = 8'h00; ram[3569] = 8'h00; ram[3570] = 8'h00; ram[3571] = 8'h00;
+ ram[3572] = 8'h00; ram[3573] = 8'h00; ram[3574] = 8'h00; ram[3575] = 8'h00;
+ ram[3576] = 8'h00; ram[3577] = 8'h00; ram[3578] = 8'h00; ram[3579] = 8'h00;
+ ram[3580] = 8'h00; ram[3581] = 8'h00; ram[3582] = 8'h00; ram[3583] = 8'h00;
+ ram[3584] = 8'h00; ram[3585] = 8'h00; ram[3586] = 8'h00; ram[3587] = 8'h00;
+ ram[3588] = 8'h00; ram[3589] = 8'h00; ram[3590] = 8'h00; ram[3591] = 8'h00;
+ ram[3592] = 8'h00; ram[3593] = 8'h00; ram[3594] = 8'h00; ram[3595] = 8'h00;
+ ram[3596] = 8'h00; ram[3597] = 8'h00; ram[3598] = 8'h00; ram[3599] = 8'h00;
+ ram[3600] = 8'h00; ram[3601] = 8'h00; ram[3602] = 8'h00; ram[3603] = 8'h00;
+ ram[3604] = 8'h00; ram[3605] = 8'h00; ram[3606] = 8'h00; ram[3607] = 8'h00;
+ ram[3608] = 8'h00; ram[3609] = 8'h00; ram[3610] = 8'h00; ram[3611] = 8'h00;
+ ram[3612] = 8'h00; ram[3613] = 8'h00; ram[3614] = 8'h00; ram[3615] = 8'h00;
+ ram[3616] = 8'h00; ram[3617] = 8'h00; ram[3618] = 8'h00; ram[3619] = 8'h00;
+ ram[3620] = 8'h00; ram[3621] = 8'h00; ram[3622] = 8'h00; ram[3623] = 8'h00;
+ ram[3624] = 8'h00; ram[3625] = 8'h00; ram[3626] = 8'h00; ram[3627] = 8'h00;
+ ram[3628] = 8'h00; ram[3629] = 8'h00; ram[3630] = 8'h00; ram[3631] = 8'h00;
+ ram[3632] = 8'h00; ram[3633] = 8'h00; ram[3634] = 8'h00; ram[3635] = 8'h00;
+ ram[3636] = 8'h00; ram[3637] = 8'h00; ram[3638] = 8'h00; ram[3639] = 8'h00;
+ ram[3640] = 8'h00; ram[3641] = 8'h00; ram[3642] = 8'h00; ram[3643] = 8'h00;
+ ram[3644] = 8'h00; ram[3645] = 8'h00; ram[3646] = 8'h00; ram[3647] = 8'h00;
+ ram[3648] = 8'h00; ram[3649] = 8'h00; ram[3650] = 8'h00; ram[3651] = 8'h00;
+ ram[3652] = 8'h00; ram[3653] = 8'h00; ram[3654] = 8'h00; ram[3655] = 8'h00;
+ ram[3656] = 8'h00; ram[3657] = 8'h00; ram[3658] = 8'h00; ram[3659] = 8'h00;
+ ram[3660] = 8'h00; ram[3661] = 8'h00; ram[3662] = 8'h00; ram[3663] = 8'h00;
+ ram[3664] = 8'h00; ram[3665] = 8'h00; ram[3666] = 8'h00; ram[3667] = 8'h00;
+ ram[3668] = 8'h00; ram[3669] = 8'h00; ram[3670] = 8'h00; ram[3671] = 8'h00;
+ ram[3672] = 8'h00; ram[3673] = 8'h00; ram[3674] = 8'h00; ram[3675] = 8'h00;
+ ram[3676] = 8'h00; ram[3677] = 8'h00; ram[3678] = 8'h00; ram[3679] = 8'h00;
+ ram[3680] = 8'h00; ram[3681] = 8'h00; ram[3682] = 8'h00; ram[3683] = 8'h00;
+ ram[3684] = 8'h00; ram[3685] = 8'h00; ram[3686] = 8'h00; ram[3687] = 8'h00;
+ ram[3688] = 8'h00; ram[3689] = 8'h00; ram[3690] = 8'h00; ram[3691] = 8'h00;
+ ram[3692] = 8'h00; ram[3693] = 8'h00; ram[3694] = 8'h00; ram[3695] = 8'h00;
+ ram[3696] = 8'h00; ram[3697] = 8'h00; ram[3698] = 8'h00; ram[3699] = 8'h00;
+ ram[3700] = 8'h00; ram[3701] = 8'h00; ram[3702] = 8'h00; ram[3703] = 8'h00;
+ ram[3704] = 8'h00; ram[3705] = 8'h00; ram[3706] = 8'h00; ram[3707] = 8'h00;
+ ram[3708] = 8'h00; ram[3709] = 8'h00; ram[3710] = 8'h00; ram[3711] = 8'h00;
+ ram[3712] = 8'h00; ram[3713] = 8'h00; ram[3714] = 8'h00; ram[3715] = 8'h00;
+ ram[3716] = 8'h00; ram[3717] = 8'h00; ram[3718] = 8'h00; ram[3719] = 8'h00;
+ ram[3720] = 8'h00; ram[3721] = 8'h00; ram[3722] = 8'h00; ram[3723] = 8'h00;
+ ram[3724] = 8'h00; ram[3725] = 8'h00; ram[3726] = 8'h00; ram[3727] = 8'h00;
+ ram[3728] = 8'h00; ram[3729] = 8'h00; ram[3730] = 8'h00; ram[3731] = 8'h00;
+ ram[3732] = 8'h00; ram[3733] = 8'h00; ram[3734] = 8'h00; ram[3735] = 8'h00;
+ ram[3736] = 8'h00; ram[3737] = 8'h00; ram[3738] = 8'h00; ram[3739] = 8'h00;
+ ram[3740] = 8'h00; ram[3741] = 8'h00; ram[3742] = 8'h00; ram[3743] = 8'h00;
+ ram[3744] = 8'h00; ram[3745] = 8'h00; ram[3746] = 8'h00; ram[3747] = 8'h00;
+ ram[3748] = 8'h00; ram[3749] = 8'h00; ram[3750] = 8'h00; ram[3751] = 8'h00;
+ ram[3752] = 8'h00; ram[3753] = 8'h00; ram[3754] = 8'h00; ram[3755] = 8'h00;
+ ram[3756] = 8'h00; ram[3757] = 8'h00; ram[3758] = 8'h00; ram[3759] = 8'h00;
+ ram[3760] = 8'h00; ram[3761] = 8'h00; ram[3762] = 8'h00; ram[3763] = 8'h00;
+ ram[3764] = 8'h00; ram[3765] = 8'h00; ram[3766] = 8'h00; ram[3767] = 8'h00;
+ ram[3768] = 8'h00; ram[3769] = 8'h00; ram[3770] = 8'h00; ram[3771] = 8'h00;
+ ram[3772] = 8'h00; ram[3773] = 8'h00; ram[3774] = 8'h00; ram[3775] = 8'h00;
+ ram[3776] = 8'h00; ram[3777] = 8'h00; ram[3778] = 8'h00; ram[3779] = 8'h00;
+ ram[3780] = 8'h00; ram[3781] = 8'h00; ram[3782] = 8'h00; ram[3783] = 8'h00;
+ ram[3784] = 8'h00; ram[3785] = 8'h00; ram[3786] = 8'h00; ram[3787] = 8'h00;
+ ram[3788] = 8'h00; ram[3789] = 8'h00; ram[3790] = 8'h00; ram[3791] = 8'h00;
+ ram[3792] = 8'h00; ram[3793] = 8'h00; ram[3794] = 8'h00; ram[3795] = 8'h00;
+ ram[3796] = 8'h00; ram[3797] = 8'h00; ram[3798] = 8'h00; ram[3799] = 8'h00;
+ ram[3800] = 8'h00; ram[3801] = 8'h00; ram[3802] = 8'h00; ram[3803] = 8'h00;
+ ram[3804] = 8'h00; ram[3805] = 8'h00; ram[3806] = 8'h00; ram[3807] = 8'h00;
+ ram[3808] = 8'h00; ram[3809] = 8'h00; ram[3810] = 8'h00; ram[3811] = 8'h00;
+ ram[3812] = 8'h00; ram[3813] = 8'h00; ram[3814] = 8'h00; ram[3815] = 8'h00;
+ ram[3816] = 8'h00; ram[3817] = 8'h00; ram[3818] = 8'h00; ram[3819] = 8'h00;
+ ram[3820] = 8'h00; ram[3821] = 8'h00; ram[3822] = 8'h00; ram[3823] = 8'h00;
+ ram[3824] = 8'h00; ram[3825] = 8'h00; ram[3826] = 8'h00; ram[3827] = 8'h00;
+ ram[3828] = 8'h00; ram[3829] = 8'h00; ram[3830] = 8'h00; ram[3831] = 8'h00;
+ ram[3832] = 8'h00; ram[3833] = 8'h00; ram[3834] = 8'h00; ram[3835] = 8'h00;
+ ram[3836] = 8'h00; ram[3837] = 8'h00; ram[3838] = 8'h00; ram[3839] = 8'h00;
+ ram[3840] = 8'h00; ram[3841] = 8'h00; ram[3842] = 8'h00; ram[3843] = 8'h00;
+ ram[3844] = 8'h00; ram[3845] = 8'h00; ram[3846] = 8'h00; ram[3847] = 8'h00;
+ ram[3848] = 8'h00; ram[3849] = 8'h00; ram[3850] = 8'h00; ram[3851] = 8'h00;
+ ram[3852] = 8'h00; ram[3853] = 8'h00; ram[3854] = 8'h00; ram[3855] = 8'h00;
+ ram[3856] = 8'h00; ram[3857] = 8'h00; ram[3858] = 8'h00; ram[3859] = 8'h00;
+ ram[3860] = 8'h00; ram[3861] = 8'h00; ram[3862] = 8'h00; ram[3863] = 8'h00;
+ ram[3864] = 8'h00; ram[3865] = 8'h00; ram[3866] = 8'h00; ram[3867] = 8'h00;
+ ram[3868] = 8'h00; ram[3869] = 8'h00; ram[3870] = 8'h00; ram[3871] = 8'h00;
+ ram[3872] = 8'h00; ram[3873] = 8'h00; ram[3874] = 8'h00; ram[3875] = 8'h00;
+ ram[3876] = 8'h00; ram[3877] = 8'h00; ram[3878] = 8'h00; ram[3879] = 8'h00;
+ ram[3880] = 8'h00; ram[3881] = 8'h00; ram[3882] = 8'h00; ram[3883] = 8'h00;
+ ram[3884] = 8'h00; ram[3885] = 8'h00; ram[3886] = 8'h00; ram[3887] = 8'h00;
+ ram[3888] = 8'h00; ram[3889] = 8'h00; ram[3890] = 8'h00; ram[3891] = 8'h00;
+ ram[3892] = 8'h00; ram[3893] = 8'h00; ram[3894] = 8'h00; ram[3895] = 8'h00;
+ ram[3896] = 8'h00; ram[3897] = 8'h00; ram[3898] = 8'h00; ram[3899] = 8'h00;
+ ram[3900] = 8'h00; ram[3901] = 8'h00; ram[3902] = 8'h00; ram[3903] = 8'h00;
+ ram[3904] = 8'h00; ram[3905] = 8'h00; ram[3906] = 8'h00; ram[3907] = 8'h00;
+ ram[3908] = 8'h00; ram[3909] = 8'h00; ram[3910] = 8'h00; ram[3911] = 8'h00;
+ ram[3912] = 8'h00; ram[3913] = 8'h00; ram[3914] = 8'h00; ram[3915] = 8'h00;
+ ram[3916] = 8'h00; ram[3917] = 8'h00; ram[3918] = 8'h00; ram[3919] = 8'h00;
+ ram[3920] = 8'h00; ram[3921] = 8'h00; ram[3922] = 8'h00; ram[3923] = 8'h00;
+ ram[3924] = 8'h00; ram[3925] = 8'h00; ram[3926] = 8'h00; ram[3927] = 8'h00;
+ ram[3928] = 8'h00; ram[3929] = 8'h00; ram[3930] = 8'h00; ram[3931] = 8'h00;
+ ram[3932] = 8'h00; ram[3933] = 8'h00; ram[3934] = 8'h00; ram[3935] = 8'h00;
+ ram[3936] = 8'h00; ram[3937] = 8'h00; ram[3938] = 8'h00; ram[3939] = 8'h00;
+ ram[3940] = 8'h00; ram[3941] = 8'h00; ram[3942] = 8'h00; ram[3943] = 8'h00;
+ ram[3944] = 8'h00; ram[3945] = 8'h00; ram[3946] = 8'h00; ram[3947] = 8'h00;
+ ram[3948] = 8'h00; ram[3949] = 8'h00; ram[3950] = 8'h00; ram[3951] = 8'h00;
+ ram[3952] = 8'h00; ram[3953] = 8'h00; ram[3954] = 8'h00; ram[3955] = 8'h00;
+ ram[3956] = 8'h00; ram[3957] = 8'h00; ram[3958] = 8'h00; ram[3959] = 8'h00;
+ ram[3960] = 8'h00; ram[3961] = 8'h00; ram[3962] = 8'h00; ram[3963] = 8'h00;
+ ram[3964] = 8'h00; ram[3965] = 8'h00; ram[3966] = 8'h00; ram[3967] = 8'h00;
+ ram[3968] = 8'h00; ram[3969] = 8'h00; ram[3970] = 8'h00; ram[3971] = 8'h00;
+ ram[3972] = 8'h00; ram[3973] = 8'h00; ram[3974] = 8'h00; ram[3975] = 8'h00;
+ ram[3976] = 8'h00; ram[3977] = 8'h00; ram[3978] = 8'h00; ram[3979] = 8'h00;
+ ram[3980] = 8'h00; ram[3981] = 8'h00; ram[3982] = 8'h00; ram[3983] = 8'h00;
+ ram[3984] = 8'h00; ram[3985] = 8'h00; ram[3986] = 8'h00; ram[3987] = 8'h00;
+ ram[3988] = 8'h00; ram[3989] = 8'h00; ram[3990] = 8'h00; ram[3991] = 8'h00;
+ ram[3992] = 8'h00; ram[3993] = 8'h00; ram[3994] = 8'h00; ram[3995] = 8'h00;
+ ram[3996] = 8'h00; ram[3997] = 8'h00; ram[3998] = 8'h00; ram[3999] = 8'h00;
+ ram[4000] = 8'h00; ram[4001] = 8'h00; ram[4002] = 8'h00; ram[4003] = 8'h00;
+ ram[4004] = 8'h00; ram[4005] = 8'h00; ram[4006] = 8'h00; ram[4007] = 8'h00;
+ ram[4008] = 8'h00; ram[4009] = 8'h00; ram[4010] = 8'h00; ram[4011] = 8'h00;
+ ram[4012] = 8'h00; ram[4013] = 8'h00; ram[4014] = 8'h00; ram[4015] = 8'h00;
+ ram[4016] = 8'h00; ram[4017] = 8'h00; ram[4018] = 8'h00; ram[4019] = 8'h00;
+ ram[4020] = 8'h00; ram[4021] = 8'h00; ram[4022] = 8'h00; ram[4023] = 8'h00;
+ ram[4024] = 8'h00; ram[4025] = 8'h00; ram[4026] = 8'h00; ram[4027] = 8'h00;
+ ram[4028] = 8'h00; ram[4029] = 8'h00; ram[4030] = 8'h00; ram[4031] = 8'h00;
+ ram[4032] = 8'h00; ram[4033] = 8'h00; ram[4034] = 8'h00; ram[4035] = 8'h00;
+ ram[4036] = 8'h00; ram[4037] = 8'h00; ram[4038] = 8'h00; ram[4039] = 8'h00;
+ ram[4040] = 8'h00; ram[4041] = 8'h00; ram[4042] = 8'h00; ram[4043] = 8'h00;
+ ram[4044] = 8'h00; ram[4045] = 8'h00; ram[4046] = 8'h00; ram[4047] = 8'h00;
+ ram[4048] = 8'h00; ram[4049] = 8'h00; ram[4050] = 8'h00; ram[4051] = 8'h00;
+ ram[4052] = 8'h00; ram[4053] = 8'h00; ram[4054] = 8'h00; ram[4055] = 8'h00;
+ ram[4056] = 8'h00; ram[4057] = 8'h00; ram[4058] = 8'h00; ram[4059] = 8'h00;
+ ram[4060] = 8'h00; ram[4061] = 8'h00; ram[4062] = 8'h00; ram[4063] = 8'h00;
+ ram[4064] = 8'h00; ram[4065] = 8'h00; ram[4066] = 8'h00; ram[4067] = 8'h00;
+ ram[4068] = 8'h00; ram[4069] = 8'h00; ram[4070] = 8'h00; ram[4071] = 8'h00;
+ ram[4072] = 8'h00; ram[4073] = 8'h00; ram[4074] = 8'h00; ram[4075] = 8'h00;
+ ram[4076] = 8'h00; ram[4077] = 8'h00; ram[4078] = 8'h00; ram[4079] = 8'h00;
+ ram[4080] = 8'h00; ram[4081] = 8'h00; ram[4082] = 8'h00; ram[4083] = 8'h00;
+ ram[4084] = 8'h00; ram[4085] = 8'h00; ram[4086] = 8'h00; ram[4087] = 8'h00;
+ ram[4088] = 8'h00; ram[4089] = 8'h00; ram[4090] = 8'h00; ram[4091] = 8'h00;
+ ram[4092] = 8'h00; ram[4093] = 8'h00; ram[4094] = 8'h00; ram[4095] = 8'h00;
+end
+
+//-----------------------------------------------------------------------------
+always @(posedge clk)
+begin
+ if (we)
+ ram[addr] <= din;
+ dout <= ram[addr];
+end
+
+endmodule
+//-----------------------------------------------------------------------------
Index: trunk/c/HELLO.HEX
===================================================================
--- trunk/c/HELLO.HEX (nonexistent)
+++ trunk/c/HELLO.HEX (revision 65)
@@ -0,0 +1,31 @@
+:2000000021000CF9CDE3027E6F079F67C97E23666FC97D12C97D12137C12C97DB36F7CB2E8
+:2000200067C97DAB6F7CAA67C97DA36F7CA267C9CD5600C82BC9CD5600C02BC9EBCD560002
+:20004000D82BC9CD5600C8D82BC9CD5600D02BC9CD5600D82BC97B955F7A9C210100FA6343
+:2000600000B3C9B337C9CD8000D02BC9CD8000D82BC9EBCD8000D82BC9CD8000C8D82BC942
+:200080007ABCC287007BBD210100C9EB7C177C1F677D1F6F1DC28C00C9EB291DC29A00C9A9
+:2000A0007B956F7A9C67C9CDAC0023C97C2F677D2F6FC9444D210000790FD2BE0019AF7816
+:2000C0001F47791F4FB0C8AF7B175F7A1757B3C8C3B800444D7AA8F57AB7FC140178B7FCC8
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+:200380003A203078004563686F696E672072656365697665642062797465733A200000D2C4
+:0303A000042E1612
+:00000001FF
Index: trunk/c/compile.bat
===================================================================
--- trunk/c/compile.bat (nonexistent)
+++ trunk/c/compile.bat (revision 65)
@@ -0,0 +1,17 @@
+@echo off
+@echo ----------------------------------------------------------------------------------------
+@echo Small-C Compiler
+@echo ----------------------------------------------------------------------------------------
+..\tools\c80\c80 -sc00 -ohello.asm hello.c
+@echo ----------------------------------------------------------------------------------------
+@echo AS80 Assembler
+@echo ----------------------------------------------------------------------------------------
+..\tools\c80\as80 -l -t -s2 hello.asm
+@echo ----------------------------------------------------------------------------------------
+@echo Convert HEX File to Xilinx Memory Init File
+@echo ----------------------------------------------------------------------------------------
+..\tools\ihex2vlog\ihex2vlog.exe -a12 -s4096 -mram_image hello.hex ram_image.v
+@echo ----------------------------------------------------------------------------------------
+@echo Copy file to RTL directory
+@echo ----------------------------------------------------------------------------------------
+copy ram_image.v ..\verilog\rtl
Index: trunk/c
===================================================================
--- trunk/c (nonexistent)
+++ trunk/c (revision 65)
trunk/c
Property changes :
Added: svn:ignore
## -0,0 +1 ##
+*.bak
Index: trunk/verilog/bench/tb_l80soc.v
===================================================================
--- trunk/verilog/bench/tb_l80soc.v (nonexistent)
+++ trunk/verilog/bench/tb_l80soc.v (revision 65)
@@ -0,0 +1,138 @@
+//---------------------------------------------------------------------------------------
+// Project: light8080 SOC WiCores Solutions
+//
+// Filename: tb_l80soc.v (February 04, 2012)
+//
+// Author(s): Moti Litochevski
+//
+// Description:
+// This file implements the light8080 SOC test bench.
+//
+//---------------------------------------------------------------------------------------
+//
+// To Do:
+// -
+//
+//---------------------------------------------------------------------------------------
+//
+// Copyright (C) 2012 Moti Litochevski
+//
+// This source file may be used and distributed without restriction provided that this
+// copyright statement is not removed from the file and that any derivative work
+// contains the original copyright notice and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
+// FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module test;
+//---------------------------------------------------------------------------------------
+// test bench global defines
+// the following define selects between CPU instruction trace and uart transmitted bytes
+//`define CPU_TRACE 1
+
+
+//---------------------------------------------------------------------------------------
+// internal signals
+reg clock; // global clock
+reg reset; // global reset
+
+// UUT interfaces
+wire rxd, txd;
+wire [7:0] p1dio, p2dio;
+
+//---------------------------------------------------------------------------------------
+// test bench implementation
+// global signals generation
+initial
+begin
+ clock = 0;
+ reset = 1;
+ #100 reset = 0;
+end
+
+// clock generator - 50MHz clock
+always
+begin
+ #10 clock = 0;
+ #10 clock = 1;
+end
+
+// test bench dump variables
+initial
+begin
+ $display("");
+ $display(" light8080 SOC simulation");
+ $display("--------------------------------------");
+ $dumpfile("test.vcd");
+ $dumpvars(0, test);
+ $display("");
+end
+
+// simulation end condition
+always @ (posedge clock)
+begin
+ if (dut.cpu_io && (dut.cpu_addr[7:0] == 8'hff))
+ begin
+ $display("");
+ $display("Simulation ended by software");
+ $finish;
+ end
+end
+
+//------------------------------------------------------------------
+// device under test
+l80soc dut
+(
+ .clock(clock),
+ .reset(reset),
+ .txd(txd),
+ .rxd(rxd),
+ .p1dio(p1dio),
+ .p2dio(p2dio)
+);
+
+//------------------------------------------------------------------
+// uart receive is not used in this test becnch
+assign rxd = 1'b1;
+
+`ifdef CPU_TRACE
+// display executed instructions
+reg [15:0] saddr;
+reg scpu_rd;
+always @ (posedge clock)
+begin
+ if (dut.cpu.uc_decode)
+ begin
+ $display("");
+ $write("%x : %x", saddr, dut.cpu.data_in);
+ end
+ else if (scpu_rd)
+ $write("%x", dut.cpu.data_in);
+
+ // sampled address bus and read pulse
+ saddr <= dut.cpu.addr_out;
+ scpu_rd <= dut.cpu.rd;
+end
+`else
+// display characters transmitted to the uart
+initial
+begin
+ $display("Characters sent to the UART:");
+end
+
+// check uart write pulse
+always @ (posedge clock)
+begin
+ if (dut.txValid)
+ $write("%c", dut.cpu_dout);
+end
+`endif
+endmodule
+//---------------------------------------------------------------------------------------
+// Th.. Th.. Th.. Thats all folks !!!
+//---------------------------------------------------------------------------------------
Index: trunk/verilog/rtl/uart.v
===================================================================
--- trunk/verilog/rtl/uart.v (nonexistent)
+++ trunk/verilog/rtl/uart.v (revision 65)
@@ -0,0 +1,194 @@
+//---------------------------------------------------------------------------------------
+// uart top level module
+//
+//---------------------------------------------------------------------------------------
+
+module uart
+(
+ clock, reset,
+ serIn, serOut,
+ txData, txValid,
+ txBusy, txDone,
+ rxData, rxValid,
+ baudDiv
+);
+//---------------------------------------------------------------------------------------
+// module interfaces
+// global signals
+input clock; // global clock input
+input reset; // global reset input
+// uart serial signals
+input serIn; // serial data input
+output serOut; // serial data output
+// transmit and receive internal interface signals
+input [7:0] txData; // data byte to transmit
+input txValid; // asserted to indicate that there is a new data byte for transmission
+output txBusy; // signs that transmitter is busy
+output txDone; // transmitter done pulse
+output [7:0] rxData; // data byte received
+output rxValid; // signs that a new byte was received
+// baud rate configuration register
+input [15:0] baudDiv; // baud rate setting register = round(clock_freq/baud_rate/16) - 1
+
+//---------------------------------------------------------------------------------------
+// internal declarations
+// registered output
+reg serOut, txBusy, txDone, rxValid;
+reg [7:0] rxData;
+
+// internals
+reg [8:0] txShiftReg;
+reg [7:0] rxShiftReg;
+reg [3:0] txBaudCnt, txBitCnt, rxBaudCnt, rxBitCnt;
+reg [15:0] baudCount;
+reg baudCE16, sserIn, rxBusy;
+
+//---------------------------------------------------------------------------------------
+// module implementation
+// transmitter control process
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ begin
+ txBusy <= 1'b0;
+ txDone <= 1'b0;
+ txShiftReg <= 9'b0;
+ serOut <= 1'b1;
+ txBaudCnt <= 4'b0;
+ txBitCnt <= 4'b0;
+ end
+ else if (!txBusy)
+ begin
+ // check if transmitter operation should start
+ if (txValid)
+ begin
+ // register the data shift register and assert the transmitter busy flag
+ txShiftReg <= {txData, 1'b0};
+ txBusy <= 1'b1;
+ end
+
+ // defaults
+ serOut <= 1'b1;
+ txDone <= 1'b0;
+ txBaudCnt <= 4'b0;
+ txBitCnt <= 4'b0;
+ end
+ else if (baudCE16)
+ begin
+ // check if next bit should be sent out
+ if (txBaudCnt == 4'b0)
+ begin
+ //check if this is the last bit
+ if (txBitCnt == 4'd10)
+ begin
+ // clear the busy flag and pulse done flag
+ txBusy <= 1'b0;
+ txDone <= 1'b1;
+ end
+
+ // update the bit counter
+ txBitCnt <= txBitCnt + 4'd1;
+
+ // update the serial output and shift register
+ serOut <= txShiftReg[0];
+ txShiftReg <= {1'b1, txShiftReg[8:1]};
+ end
+
+ // update the baud clock counter
+ txBaudCnt <= txBaudCnt + 4'd1;
+ end
+end
+
+// receiver control process
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ begin
+ rxBusy <= 1'b0;
+ rxShiftReg <= 8'b0;
+ rxBaudCnt <= 4'b0;
+ rxBitCnt <= 4'b0;
+ rxData <= 8'b0;
+ rxValid <= 1'b0;
+ end
+ else if (!rxBusy)
+ begin
+ // check start bit
+ if (!sserIn && baudCE16)
+ begin
+ // check if the serial input is zero for 8 baudCE16 cycles
+ if (rxBaudCnt == 4'd7)
+ begin
+ // sign that receiver is busy and clear the bit counter
+ rxBusy <= 1'b1;
+ rxBaudCnt <= 4'b0;
+ end
+ else
+ rxBaudCnt <= rxBaudCnt + 4'd1;
+ end
+
+ // defaults
+ rxBitCnt <= 4'b0;
+ rxValid <= 1'b0;
+ end
+ else if (baudCE16)
+ begin
+ // check if bit should be sampled
+ if (rxBaudCnt == 4'd15)
+ begin
+ // update the input shift register and bit counter
+ rxShiftReg <= {sserIn, rxShiftReg[7:1]};
+ rxBitCnt <= rxBitCnt + 4'd1;
+
+ // check if this is the last data bit
+ if (rxBitCnt == 4'd8)
+ begin
+ // sample the received data byte
+ rxData <= rxShiftReg;
+ rxValid <= 1'b1;
+
+ // clear receiver busy flag
+ rxBusy <= 1'b0;
+ end
+ end
+
+ // update the baud clock counter
+ rxBaudCnt <= rxBaudCnt + 4'd1;
+ end
+end
+
+// sample serial input
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ sserIn <= 1'b0;
+ else
+ sserIn <= serIn;
+end
+
+// baud rate clock generator
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ begin
+ baudCount <= 16'b0;
+ baudCE16 <= 1'b0;
+ end
+ else if (baudCount == baudDiv)
+ begin
+ // clear the divider counter and pulse the clock enable signal
+ baudCount <= 16'b0;
+ baudCE16 <= 1'b1;
+ end
+ else
+ begin
+ // update the clock divider counter and clear the
+ baudCount <= baudCount + 16'd1;
+ baudCE16 <= 1'b0;
+ end
+end
+
+endmodule
+//---------------------------------------------------------------------------------------
+// Th.. Th.. Th.. Thats all folks !!!
+//---------------------------------------------------------------------------------------
Index: trunk/verilog/rtl/ram_image.v
===================================================================
--- trunk/verilog/rtl/ram_image.v (nonexistent)
+++ trunk/verilog/rtl/ram_image.v (revision 65)
@@ -0,0 +1,1058 @@
+//-----------------------------------------------------------------------------
+//
+// RAM image for input code file: hello.hex
+//
+//-----------------------------------------------------------------------------
+module ram_image
+(
+ clk, addr,
+ we, din, dout
+);
+//-----------------------------------------------------------------------------
+input clk;
+input [11:0] addr;
+input we;
+input [7:0] din;
+output [7:0] dout;
+//-----------------------------------------------------------------------------
+reg [7:0] dout;
+reg [7:0] ram [4095:0];
+//-----------------------------------------------------------------------------
+initial
+begin
+ ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
+ ram[4] = 8'hcd; ram[5] = 8'he3; ram[6] = 8'h02; ram[7] = 8'h7e;
+ ram[8] = 8'h6f; ram[9] = 8'h07; ram[10] = 8'h9f; ram[11] = 8'h67;
+ ram[12] = 8'hc9; ram[13] = 8'h7e; ram[14] = 8'h23; ram[15] = 8'h66;
+ ram[16] = 8'h6f; ram[17] = 8'hc9; ram[18] = 8'h7d; ram[19] = 8'h12;
+ ram[20] = 8'hc9; ram[21] = 8'h7d; ram[22] = 8'h12; ram[23] = 8'h13;
+ ram[24] = 8'h7c; ram[25] = 8'h12; ram[26] = 8'hc9; ram[27] = 8'h7d;
+ ram[28] = 8'hb3; ram[29] = 8'h6f; ram[30] = 8'h7c; ram[31] = 8'hb2;
+ ram[32] = 8'h67; ram[33] = 8'hc9; ram[34] = 8'h7d; ram[35] = 8'hab;
+ ram[36] = 8'h6f; ram[37] = 8'h7c; ram[38] = 8'haa; ram[39] = 8'h67;
+ ram[40] = 8'hc9; ram[41] = 8'h7d; ram[42] = 8'ha3; ram[43] = 8'h6f;
+ ram[44] = 8'h7c; ram[45] = 8'ha2; ram[46] = 8'h67; ram[47] = 8'hc9;
+ ram[48] = 8'hcd; ram[49] = 8'h56; ram[50] = 8'h00; ram[51] = 8'hc8;
+ ram[52] = 8'h2b; ram[53] = 8'hc9; ram[54] = 8'hcd; ram[55] = 8'h56;
+ ram[56] = 8'h00; ram[57] = 8'hc0; ram[58] = 8'h2b; ram[59] = 8'hc9;
+ ram[60] = 8'heb; ram[61] = 8'hcd; ram[62] = 8'h56; ram[63] = 8'h00;
+ ram[64] = 8'hd8; ram[65] = 8'h2b; ram[66] = 8'hc9; ram[67] = 8'hcd;
+ ram[68] = 8'h56; ram[69] = 8'h00; ram[70] = 8'hc8; ram[71] = 8'hd8;
+ ram[72] = 8'h2b; ram[73] = 8'hc9; ram[74] = 8'hcd; ram[75] = 8'h56;
+ ram[76] = 8'h00; ram[77] = 8'hd0; ram[78] = 8'h2b; ram[79] = 8'hc9;
+ ram[80] = 8'hcd; ram[81] = 8'h56; ram[82] = 8'h00; ram[83] = 8'hd8;
+ ram[84] = 8'h2b; ram[85] = 8'hc9; ram[86] = 8'h7b; ram[87] = 8'h95;
+ ram[88] = 8'h5f; ram[89] = 8'h7a; ram[90] = 8'h9c; ram[91] = 8'h21;
+ ram[92] = 8'h01; ram[93] = 8'h00; ram[94] = 8'hfa; ram[95] = 8'h63;
+ ram[96] = 8'h00; ram[97] = 8'hb3; ram[98] = 8'hc9; ram[99] = 8'hb3;
+ ram[100] = 8'h37; ram[101] = 8'hc9; ram[102] = 8'hcd; ram[103] = 8'h80;
+ ram[104] = 8'h00; ram[105] = 8'hd0; ram[106] = 8'h2b; ram[107] = 8'hc9;
+ ram[108] = 8'hcd; ram[109] = 8'h80; ram[110] = 8'h00; ram[111] = 8'hd8;
+ ram[112] = 8'h2b; ram[113] = 8'hc9; ram[114] = 8'heb; ram[115] = 8'hcd;
+ ram[116] = 8'h80; ram[117] = 8'h00; ram[118] = 8'hd8; ram[119] = 8'h2b;
+ ram[120] = 8'hc9; ram[121] = 8'hcd; ram[122] = 8'h80; ram[123] = 8'h00;
+ ram[124] = 8'hc8; ram[125] = 8'hd8; ram[126] = 8'h2b; ram[127] = 8'hc9;
+ ram[128] = 8'h7a; ram[129] = 8'hbc; ram[130] = 8'hc2; ram[131] = 8'h87;
+ ram[132] = 8'h00; ram[133] = 8'h7b; ram[134] = 8'hbd; ram[135] = 8'h21;
+ ram[136] = 8'h01; ram[137] = 8'h00; ram[138] = 8'hc9; ram[139] = 8'heb;
+ ram[140] = 8'h7c; ram[141] = 8'h17; ram[142] = 8'h7c; ram[143] = 8'h1f;
+ ram[144] = 8'h67; ram[145] = 8'h7d; ram[146] = 8'h1f; ram[147] = 8'h6f;
+ ram[148] = 8'h1d; ram[149] = 8'hc2; ram[150] = 8'h8c; ram[151] = 8'h00;
+ ram[152] = 8'hc9; ram[153] = 8'heb; ram[154] = 8'h29; ram[155] = 8'h1d;
+ ram[156] = 8'hc2; ram[157] = 8'h9a; ram[158] = 8'h00; ram[159] = 8'hc9;
+ ram[160] = 8'h7b; ram[161] = 8'h95; ram[162] = 8'h6f; ram[163] = 8'h7a;
+ ram[164] = 8'h9c; ram[165] = 8'h67; ram[166] = 8'hc9; ram[167] = 8'hcd;
+ ram[168] = 8'hac; ram[169] = 8'h00; ram[170] = 8'h23; ram[171] = 8'hc9;
+ ram[172] = 8'h7c; ram[173] = 8'h2f; ram[174] = 8'h67; ram[175] = 8'h7d;
+ ram[176] = 8'h2f; ram[177] = 8'h6f; ram[178] = 8'hc9; ram[179] = 8'h44;
+ ram[180] = 8'h4d; ram[181] = 8'h21; ram[182] = 8'h00; ram[183] = 8'h00;
+ ram[184] = 8'h79; ram[185] = 8'h0f; ram[186] = 8'hd2; ram[187] = 8'hbe;
+ ram[188] = 8'h00; ram[189] = 8'h19; ram[190] = 8'haf; ram[191] = 8'h78;
+ ram[192] = 8'h1f; ram[193] = 8'h47; ram[194] = 8'h79; ram[195] = 8'h1f;
+ ram[196] = 8'h4f; ram[197] = 8'hb0; ram[198] = 8'hc8; ram[199] = 8'haf;
+ ram[200] = 8'h7b; ram[201] = 8'h17; ram[202] = 8'h5f; ram[203] = 8'h7a;
+ ram[204] = 8'h17; ram[205] = 8'h57; ram[206] = 8'hb3; ram[207] = 8'hc8;
+ ram[208] = 8'hc3; ram[209] = 8'hb8; ram[210] = 8'h00; ram[211] = 8'h44;
+ ram[212] = 8'h4d; ram[213] = 8'h7a; ram[214] = 8'ha8; ram[215] = 8'hf5;
+ ram[216] = 8'h7a; ram[217] = 8'hb7; ram[218] = 8'hfc; ram[219] = 8'h14;
+ ram[220] = 8'h01; ram[221] = 8'h78; ram[222] = 8'hb7; ram[223] = 8'hfc;
+ ram[224] = 8'h1c; ram[225] = 8'h01; ram[226] = 8'h3e; ram[227] = 8'h10;
+ ram[228] = 8'hf5; ram[229] = 8'heb; ram[230] = 8'h11; ram[231] = 8'h00;
+ ram[232] = 8'h00; ram[233] = 8'h29; ram[234] = 8'hcd; ram[235] = 8'h24;
+ ram[236] = 8'h01; ram[237] = 8'hca; ram[238] = 8'h00; ram[239] = 8'h01;
+ ram[240] = 8'hcd; ram[241] = 8'h2c; ram[242] = 8'h01; ram[243] = 8'hfa;
+ ram[244] = 8'h00; ram[245] = 8'h01; ram[246] = 8'h7d; ram[247] = 8'hf6;
+ ram[248] = 8'h01; ram[249] = 8'h6f; ram[250] = 8'h7b; ram[251] = 8'h91;
+ ram[252] = 8'h5f; ram[253] = 8'h7a; ram[254] = 8'h98; ram[255] = 8'h57;
+ ram[256] = 8'hf1; ram[257] = 8'h3d; ram[258] = 8'hca; ram[259] = 8'h09;
+ ram[260] = 8'h01; ram[261] = 8'hf5; ram[262] = 8'hc3; ram[263] = 8'he9;
+ ram[264] = 8'h00; ram[265] = 8'hf1; ram[266] = 8'hf0; ram[267] = 8'hcd;
+ ram[268] = 8'h14; ram[269] = 8'h01; ram[270] = 8'heb; ram[271] = 8'hcd;
+ ram[272] = 8'h14; ram[273] = 8'h01; ram[274] = 8'heb; ram[275] = 8'hc9;
+ ram[276] = 8'h7a; ram[277] = 8'h2f; ram[278] = 8'h57; ram[279] = 8'h7b;
+ ram[280] = 8'h2f; ram[281] = 8'h5f; ram[282] = 8'h13; ram[283] = 8'hc9;
+ ram[284] = 8'h78; ram[285] = 8'h2f; ram[286] = 8'h47; ram[287] = 8'h79;
+ ram[288] = 8'h2f; ram[289] = 8'h4f; ram[290] = 8'h03; ram[291] = 8'hc9;
+ ram[292] = 8'h7b; ram[293] = 8'h17; ram[294] = 8'h5f; ram[295] = 8'h7a;
+ ram[296] = 8'h17; ram[297] = 8'h57; ram[298] = 8'hb3; ram[299] = 8'hc9;
+ ram[300] = 8'h7b; ram[301] = 8'h91; ram[302] = 8'h7a; ram[303] = 8'h98;
+ ram[304] = 8'hc9; ram[305] = 8'hdb; ram[306] = 8'h83; ram[307] = 8'hcf;
+ ram[308] = 8'he5; ram[309] = 8'h21; ram[310] = 8'h01; ram[311] = 8'h00;
+ ram[312] = 8'hd1; ram[313] = 8'hcd; ram[314] = 8'h29; ram[315] = 8'h00;
+ ram[316] = 8'h7c; ram[317] = 8'hb5; ram[318] = 8'hca; ram[319] = 8'h44;
+ ram[320] = 8'h01; ram[321] = 8'hc3; ram[322] = 8'h31; ram[323] = 8'h01;
+ ram[324] = 8'h21; ram[325] = 8'h02; ram[326] = 8'h00; ram[327] = 8'h39;
+ ram[328] = 8'hcd; ram[329] = 8'h07; ram[330] = 8'h00; ram[331] = 8'h7d;
+ ram[332] = 8'hd3; ram[333] = 8'h80; ram[334] = 8'hc9; ram[335] = 8'hdb;
+ ram[336] = 8'h83; ram[337] = 8'hcf; ram[338] = 8'he5; ram[339] = 8'h21;
+ ram[340] = 8'h10; ram[341] = 8'h00; ram[342] = 8'hd1; ram[343] = 8'hcd;
+ ram[344] = 8'h29; ram[345] = 8'h00; ram[346] = 8'h7c; ram[347] = 8'hb5;
+ ram[348] = 8'hca; ram[349] = 8'h6d; ram[350] = 8'h01; ram[351] = 8'hdb;
+ ram[352] = 8'h80; ram[353] = 8'hcf; ram[354] = 8'h7d; ram[355] = 8'h32;
+ ram[356] = 8'h9e; ram[357] = 8'h03; ram[358] = 8'h21; ram[359] = 8'h01;
+ ram[360] = 8'h00; ram[361] = 8'hc9; ram[362] = 8'hc3; ram[363] = 8'h71;
+ ram[364] = 8'h01; ram[365] = 8'h21; ram[366] = 8'h00; ram[367] = 8'h00;
+ ram[368] = 8'hc9; ram[369] = 8'hc9; ram[370] = 8'h21; ram[371] = 8'h0d;
+ ram[372] = 8'h00; ram[373] = 8'he5; ram[374] = 8'hcd; ram[375] = 8'h31;
+ ram[376] = 8'h01; ram[377] = 8'hc1; ram[378] = 8'h21; ram[379] = 8'h0a;
+ ram[380] = 8'h00; ram[381] = 8'he5; ram[382] = 8'hcd; ram[383] = 8'h31;
+ ram[384] = 8'h01; ram[385] = 8'hc1; ram[386] = 8'hc9; ram[387] = 8'h21;
+ ram[388] = 8'h02; ram[389] = 8'h00; ram[390] = 8'h39; ram[391] = 8'hcd;
+ ram[392] = 8'h0d; ram[393] = 8'h00; ram[394] = 8'hcd; ram[395] = 8'h07;
+ ram[396] = 8'h00; ram[397] = 8'he5; ram[398] = 8'h21; ram[399] = 8'h00;
+ ram[400] = 8'h00; ram[401] = 8'hd1; ram[402] = 8'hcd; ram[403] = 8'h36;
+ ram[404] = 8'h00; ram[405] = 8'h7c; ram[406] = 8'hb5; ram[407] = 8'hca;
+ ram[408] = 8'hb3; ram[409] = 8'h01; ram[410] = 8'h21; ram[411] = 8'h02;
+ ram[412] = 8'h00; ram[413] = 8'h39; ram[414] = 8'he5; ram[415] = 8'hcd;
+ ram[416] = 8'h0d; ram[417] = 8'h00; ram[418] = 8'h23; ram[419] = 8'hd1;
+ ram[420] = 8'hcd; ram[421] = 8'h15; ram[422] = 8'h00; ram[423] = 8'h2b;
+ ram[424] = 8'hcd; ram[425] = 8'h07; ram[426] = 8'h00; ram[427] = 8'he5;
+ ram[428] = 8'hcd; ram[429] = 8'h31; ram[430] = 8'h01; ram[431] = 8'hc1;
+ ram[432] = 8'hc3; ram[433] = 8'h83; ram[434] = 8'h01; ram[435] = 8'hc9;
+ ram[436] = 8'h21; ram[437] = 8'h02; ram[438] = 8'h00; ram[439] = 8'h39;
+ ram[440] = 8'hcd; ram[441] = 8'h0d; ram[442] = 8'h00; ram[443] = 8'he5;
+ ram[444] = 8'h21; ram[445] = 8'h00; ram[446] = 8'h00; ram[447] = 8'hd1;
+ ram[448] = 8'hcd; ram[449] = 8'h50; ram[450] = 8'h00; ram[451] = 8'h7c;
+ ram[452] = 8'hb5; ram[453] = 8'hca; ram[454] = 8'he3; ram[455] = 8'h01;
+ ram[456] = 8'h21; ram[457] = 8'h2d; ram[458] = 8'h00; ram[459] = 8'he5;
+ ram[460] = 8'hcd; ram[461] = 8'h31; ram[462] = 8'h01; ram[463] = 8'hc1;
+ ram[464] = 8'h21; ram[465] = 8'h02; ram[466] = 8'h00; ram[467] = 8'h39;
+ ram[468] = 8'he5; ram[469] = 8'h21; ram[470] = 8'h04; ram[471] = 8'h00;
+ ram[472] = 8'h39; ram[473] = 8'hcd; ram[474] = 8'h0d; ram[475] = 8'h00;
+ ram[476] = 8'hcd; ram[477] = 8'ha7; ram[478] = 8'h00; ram[479] = 8'hd1;
+ ram[480] = 8'hcd; ram[481] = 8'h15; ram[482] = 8'h00; ram[483] = 8'h21;
+ ram[484] = 8'h02; ram[485] = 8'h00; ram[486] = 8'h39; ram[487] = 8'hcd;
+ ram[488] = 8'h0d; ram[489] = 8'h00; ram[490] = 8'he5; ram[491] = 8'hcd;
+ ram[492] = 8'hf0; ram[493] = 8'h01; ram[494] = 8'hc1; ram[495] = 8'hc9;
+ ram[496] = 8'hc5; ram[497] = 8'h21; ram[498] = 8'h00; ram[499] = 8'h00;
+ ram[500] = 8'h39; ram[501] = 8'he5; ram[502] = 8'h21; ram[503] = 8'h06;
+ ram[504] = 8'h00; ram[505] = 8'h39; ram[506] = 8'hcd; ram[507] = 8'h0d;
+ ram[508] = 8'h00; ram[509] = 8'he5; ram[510] = 8'h21; ram[511] = 8'h0a;
+ ram[512] = 8'h00; ram[513] = 8'hd1; ram[514] = 8'hcd; ram[515] = 8'hd3;
+ ram[516] = 8'h00; ram[517] = 8'hd1; ram[518] = 8'hcd; ram[519] = 8'h15;
+ ram[520] = 8'h00; ram[521] = 8'h21; ram[522] = 8'h00; ram[523] = 8'h00;
+ ram[524] = 8'h39; ram[525] = 8'hcd; ram[526] = 8'h0d; ram[527] = 8'h00;
+ ram[528] = 8'h7c; ram[529] = 8'hb5; ram[530] = 8'hca; ram[531] = 8'h21;
+ ram[532] = 8'h02; ram[533] = 8'h21; ram[534] = 8'h00; ram[535] = 8'h00;
+ ram[536] = 8'h39; ram[537] = 8'hcd; ram[538] = 8'h0d; ram[539] = 8'h00;
+ ram[540] = 8'he5; ram[541] = 8'hcd; ram[542] = 8'hf0; ram[543] = 8'h01;
+ ram[544] = 8'hc1; ram[545] = 8'h21; ram[546] = 8'h30; ram[547] = 8'h00;
+ ram[548] = 8'he5; ram[549] = 8'h21; ram[550] = 8'h06; ram[551] = 8'h00;
+ ram[552] = 8'h39; ram[553] = 8'hcd; ram[554] = 8'h0d; ram[555] = 8'h00;
+ ram[556] = 8'he5; ram[557] = 8'h21; ram[558] = 8'h04; ram[559] = 8'h00;
+ ram[560] = 8'h39; ram[561] = 8'hcd; ram[562] = 8'h0d; ram[563] = 8'h00;
+ ram[564] = 8'he5; ram[565] = 8'h21; ram[566] = 8'h0a; ram[567] = 8'h00;
+ ram[568] = 8'hd1; ram[569] = 8'hcd; ram[570] = 8'hb3; ram[571] = 8'h00;
+ ram[572] = 8'hd1; ram[573] = 8'hcd; ram[574] = 8'ha0; ram[575] = 8'h00;
+ ram[576] = 8'hd1; ram[577] = 8'h19; ram[578] = 8'he5; ram[579] = 8'hcd;
+ ram[580] = 8'h31; ram[581] = 8'h01; ram[582] = 8'hc1; ram[583] = 8'hc1;
+ ram[584] = 8'hc9; ram[585] = 8'hc5; ram[586] = 8'h21; ram[587] = 8'h00;
+ ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'he5; ram[591] = 8'h21;
+ ram[592] = 8'h06; ram[593] = 8'h00; ram[594] = 8'h39; ram[595] = 8'hcd;
+ ram[596] = 8'h0d; ram[597] = 8'h00; ram[598] = 8'he5; ram[599] = 8'h21;
+ ram[600] = 8'h10; ram[601] = 8'h00; ram[602] = 8'hd1; ram[603] = 8'hcd;
+ ram[604] = 8'hd3; ram[605] = 8'h00; ram[606] = 8'hd1; ram[607] = 8'hcd;
+ ram[608] = 8'h15; ram[609] = 8'h00; ram[610] = 8'h21; ram[611] = 8'h00;
+ ram[612] = 8'h00; ram[613] = 8'h39; ram[614] = 8'hcd; ram[615] = 8'h0d;
+ ram[616] = 8'h00; ram[617] = 8'h7c; ram[618] = 8'hb5; ram[619] = 8'hca;
+ ram[620] = 8'h7a; ram[621] = 8'h02; ram[622] = 8'h21; ram[623] = 8'h00;
+ ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h0d;
+ ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'hcd; ram[631] = 8'h49;
+ ram[632] = 8'h02; ram[633] = 8'hc1; ram[634] = 8'h21; ram[635] = 8'h00;
+ ram[636] = 8'h00; ram[637] = 8'h39; ram[638] = 8'he5; ram[639] = 8'h21;
+ ram[640] = 8'h06; ram[641] = 8'h00; ram[642] = 8'h39; ram[643] = 8'hcd;
+ ram[644] = 8'h0d; ram[645] = 8'h00; ram[646] = 8'he5; ram[647] = 8'h21;
+ ram[648] = 8'h04; ram[649] = 8'h00; ram[650] = 8'h39; ram[651] = 8'hcd;
+ ram[652] = 8'h0d; ram[653] = 8'h00; ram[654] = 8'he5; ram[655] = 8'h21;
+ ram[656] = 8'h10; ram[657] = 8'h00; ram[658] = 8'hd1; ram[659] = 8'hcd;
+ ram[660] = 8'hb3; ram[661] = 8'h00; ram[662] = 8'hd1; ram[663] = 8'hcd;
+ ram[664] = 8'ha0; ram[665] = 8'h00; ram[666] = 8'hd1; ram[667] = 8'hcd;
+ ram[668] = 8'h15; ram[669] = 8'h00; ram[670] = 8'h21; ram[671] = 8'h00;
+ ram[672] = 8'h00; ram[673] = 8'h39; ram[674] = 8'hcd; ram[675] = 8'h0d;
+ ram[676] = 8'h00; ram[677] = 8'he5; ram[678] = 8'h21; ram[679] = 8'h09;
+ ram[680] = 8'h00; ram[681] = 8'hd1; ram[682] = 8'hcd; ram[683] = 8'h3c;
+ ram[684] = 8'h00; ram[685] = 8'h7c; ram[686] = 8'hb5; ram[687] = 8'hca;
+ ram[688] = 8'hcf; ram[689] = 8'h02; ram[690] = 8'h21; ram[691] = 8'h41;
+ ram[692] = 8'h00; ram[693] = 8'he5; ram[694] = 8'h21; ram[695] = 8'h02;
+ ram[696] = 8'h00; ram[697] = 8'h39; ram[698] = 8'hcd; ram[699] = 8'h0d;
+ ram[700] = 8'h00; ram[701] = 8'hd1; ram[702] = 8'h19; ram[703] = 8'he5;
+ ram[704] = 8'h21; ram[705] = 8'h0a; ram[706] = 8'h00; ram[707] = 8'hd1;
+ ram[708] = 8'hcd; ram[709] = 8'ha0; ram[710] = 8'h00; ram[711] = 8'he5;
+ ram[712] = 8'hcd; ram[713] = 8'h31; ram[714] = 8'h01; ram[715] = 8'hc1;
+ ram[716] = 8'hc3; ram[717] = 8'he1; ram[718] = 8'h02; ram[719] = 8'h21;
+ ram[720] = 8'h30; ram[721] = 8'h00; ram[722] = 8'he5; ram[723] = 8'h21;
+ ram[724] = 8'h02; ram[725] = 8'h00; ram[726] = 8'h39; ram[727] = 8'hcd;
+ ram[728] = 8'h0d; ram[729] = 8'h00; ram[730] = 8'hd1; ram[731] = 8'h19;
+ ram[732] = 8'he5; ram[733] = 8'hcd; ram[734] = 8'h31; ram[735] = 8'h01;
+ ram[736] = 8'hc1; ram[737] = 8'hc1; ram[738] = 8'hc9; ram[739] = 8'h21;
+ ram[740] = 8'hc3; ram[741] = 8'h00; ram[742] = 8'h7d; ram[743] = 8'hd3;
+ ram[744] = 8'h81; ram[745] = 8'h21; ram[746] = 8'h00; ram[747] = 8'h00;
+ ram[748] = 8'h7d; ram[749] = 8'hd3; ram[750] = 8'h82; ram[751] = 8'h21;
+ ram[752] = 8'h5c; ram[753] = 8'h03; ram[754] = 8'he5; ram[755] = 8'hcd;
+ ram[756] = 8'h83; ram[757] = 8'h01; ram[758] = 8'hc1; ram[759] = 8'hcd;
+ ram[760] = 8'h72; ram[761] = 8'h01; ram[762] = 8'h21; ram[763] = 8'h6b;
+ ram[764] = 8'h03; ram[765] = 8'he5; ram[766] = 8'hcd; ram[767] = 8'h83;
+ ram[768] = 8'h01; ram[769] = 8'hc1; ram[770] = 8'h21; ram[771] = 8'h9f;
+ ram[772] = 8'h03; ram[773] = 8'he5; ram[774] = 8'h21; ram[775] = 8'h01;
+ ram[776] = 8'h00; ram[777] = 8'h29; ram[778] = 8'hd1; ram[779] = 8'h19;
+ ram[780] = 8'hcd; ram[781] = 8'h0d; ram[782] = 8'h00; ram[783] = 8'he5;
+ ram[784] = 8'hcd; ram[785] = 8'hb4; ram[786] = 8'h01; ram[787] = 8'hc1;
+ ram[788] = 8'hcd; ram[789] = 8'h72; ram[790] = 8'h01; ram[791] = 8'h21;
+ ram[792] = 8'h77; ram[793] = 8'h03; ram[794] = 8'he5; ram[795] = 8'hcd;
+ ram[796] = 8'h83; ram[797] = 8'h01; ram[798] = 8'hc1; ram[799] = 8'h21;
+ ram[800] = 8'h9f; ram[801] = 8'h03; ram[802] = 8'he5; ram[803] = 8'h21;
+ ram[804] = 8'h00; ram[805] = 8'h00; ram[806] = 8'h29; ram[807] = 8'hd1;
+ ram[808] = 8'h19; ram[809] = 8'hcd; ram[810] = 8'h0d; ram[811] = 8'h00;
+ ram[812] = 8'he5; ram[813] = 8'hcd; ram[814] = 8'h49; ram[815] = 8'h02;
+ ram[816] = 8'hc1; ram[817] = 8'hcd; ram[818] = 8'h72; ram[819] = 8'h01;
+ ram[820] = 8'h21; ram[821] = 8'h85; ram[822] = 8'h03; ram[823] = 8'he5;
+ ram[824] = 8'hcd; ram[825] = 8'h83; ram[826] = 8'h01; ram[827] = 8'hc1;
+ ram[828] = 8'hcd; ram[829] = 8'h72; ram[830] = 8'h01; ram[831] = 8'h21;
+ ram[832] = 8'h01; ram[833] = 8'h00; ram[834] = 8'h7c; ram[835] = 8'hb5;
+ ram[836] = 8'hca; ram[837] = 8'h5b; ram[838] = 8'h03; ram[839] = 8'hcd;
+ ram[840] = 8'h4f; ram[841] = 8'h01; ram[842] = 8'h7c; ram[843] = 8'hb5;
+ ram[844] = 8'hca; ram[845] = 8'h58; ram[846] = 8'h03; ram[847] = 8'h3a;
+ ram[848] = 8'h9e; ram[849] = 8'h03; ram[850] = 8'hcf; ram[851] = 8'he5;
+ ram[852] = 8'hcd; ram[853] = 8'h31; ram[854] = 8'h01; ram[855] = 8'hc1;
+ ram[856] = 8'hc3; ram[857] = 8'h3f; ram[858] = 8'h03; ram[859] = 8'hc9;
+ ram[860] = 8'h48; ram[861] = 8'h65; ram[862] = 8'h6c; ram[863] = 8'h6c;
+ ram[864] = 8'h6f; ram[865] = 8'h20; ram[866] = 8'h57; ram[867] = 8'h6f;
+ ram[868] = 8'h72; ram[869] = 8'h6c; ram[870] = 8'h64; ram[871] = 8'h21;
+ ram[872] = 8'h21; ram[873] = 8'h21; ram[874] = 8'h00; ram[875] = 8'h44;
+ ram[876] = 8'h65; ram[877] = 8'h63; ram[878] = 8'h20; ram[879] = 8'h76;
+ ram[880] = 8'h61; ram[881] = 8'h6c; ram[882] = 8'h75; ram[883] = 8'h65;
+ ram[884] = 8'h3a; ram[885] = 8'h20; ram[886] = 8'h00; ram[887] = 8'h48;
+ ram[888] = 8'h65; ram[889] = 8'h78; ram[890] = 8'h20; ram[891] = 8'h76;
+ ram[892] = 8'h61; ram[893] = 8'h6c; ram[894] = 8'h75; ram[895] = 8'h65;
+ ram[896] = 8'h3a; ram[897] = 8'h20; ram[898] = 8'h30; ram[899] = 8'h78;
+ ram[900] = 8'h00; ram[901] = 8'h45; ram[902] = 8'h63; ram[903] = 8'h68;
+ ram[904] = 8'h6f; ram[905] = 8'h69; ram[906] = 8'h6e; ram[907] = 8'h67;
+ ram[908] = 8'h20; ram[909] = 8'h72; ram[910] = 8'h65; ram[911] = 8'h63;
+ ram[912] = 8'h65; ram[913] = 8'h69; ram[914] = 8'h76; ram[915] = 8'h65;
+ ram[916] = 8'h64; ram[917] = 8'h20; ram[918] = 8'h62; ram[919] = 8'h79;
+ ram[920] = 8'h74; ram[921] = 8'h65; ram[922] = 8'h73; ram[923] = 8'h3a;
+ ram[924] = 8'h20; ram[925] = 8'h00; ram[926] = 8'h00; ram[927] = 8'hd2;
+ ram[928] = 8'h04; ram[929] = 8'h2e; ram[930] = 8'h16; ram[931] = 8'h00;
+ ram[932] = 8'h00; ram[933] = 8'h00; ram[934] = 8'h00; ram[935] = 8'h00;
+ ram[936] = 8'h00; ram[937] = 8'h00; ram[938] = 8'h00; ram[939] = 8'h00;
+ ram[940] = 8'h00; ram[941] = 8'h00; ram[942] = 8'h00; ram[943] = 8'h00;
+ ram[944] = 8'h00; ram[945] = 8'h00; ram[946] = 8'h00; ram[947] = 8'h00;
+ ram[948] = 8'h00; ram[949] = 8'h00; ram[950] = 8'h00; ram[951] = 8'h00;
+ ram[952] = 8'h00; ram[953] = 8'h00; ram[954] = 8'h00; ram[955] = 8'h00;
+ ram[956] = 8'h00; ram[957] = 8'h00; ram[958] = 8'h00; ram[959] = 8'h00;
+ ram[960] = 8'h00; ram[961] = 8'h00; ram[962] = 8'h00; ram[963] = 8'h00;
+ ram[964] = 8'h00; ram[965] = 8'h00; ram[966] = 8'h00; ram[967] = 8'h00;
+ ram[968] = 8'h00; ram[969] = 8'h00; ram[970] = 8'h00; ram[971] = 8'h00;
+ ram[972] = 8'h00; ram[973] = 8'h00; ram[974] = 8'h00; ram[975] = 8'h00;
+ ram[976] = 8'h00; ram[977] = 8'h00; ram[978] = 8'h00; ram[979] = 8'h00;
+ ram[980] = 8'h00; ram[981] = 8'h00; ram[982] = 8'h00; ram[983] = 8'h00;
+ ram[984] = 8'h00; ram[985] = 8'h00; ram[986] = 8'h00; ram[987] = 8'h00;
+ ram[988] = 8'h00; ram[989] = 8'h00; ram[990] = 8'h00; ram[991] = 8'h00;
+ ram[992] = 8'h00; ram[993] = 8'h00; ram[994] = 8'h00; ram[995] = 8'h00;
+ ram[996] = 8'h00; ram[997] = 8'h00; ram[998] = 8'h00; ram[999] = 8'h00;
+ ram[1000] = 8'h00; ram[1001] = 8'h00; ram[1002] = 8'h00; ram[1003] = 8'h00;
+ ram[1004] = 8'h00; ram[1005] = 8'h00; ram[1006] = 8'h00; ram[1007] = 8'h00;
+ ram[1008] = 8'h00; ram[1009] = 8'h00; ram[1010] = 8'h00; ram[1011] = 8'h00;
+ ram[1012] = 8'h00; ram[1013] = 8'h00; ram[1014] = 8'h00; ram[1015] = 8'h00;
+ ram[1016] = 8'h00; ram[1017] = 8'h00; ram[1018] = 8'h00; ram[1019] = 8'h00;
+ ram[1020] = 8'h00; ram[1021] = 8'h00; ram[1022] = 8'h00; ram[1023] = 8'h00;
+ ram[1024] = 8'h00; ram[1025] = 8'h00; ram[1026] = 8'h00; ram[1027] = 8'h00;
+ ram[1028] = 8'h00; ram[1029] = 8'h00; ram[1030] = 8'h00; ram[1031] = 8'h00;
+ ram[1032] = 8'h00; ram[1033] = 8'h00; ram[1034] = 8'h00; ram[1035] = 8'h00;
+ ram[1036] = 8'h00; ram[1037] = 8'h00; ram[1038] = 8'h00; ram[1039] = 8'h00;
+ ram[1040] = 8'h00; ram[1041] = 8'h00; ram[1042] = 8'h00; ram[1043] = 8'h00;
+ ram[1044] = 8'h00; ram[1045] = 8'h00; ram[1046] = 8'h00; ram[1047] = 8'h00;
+ ram[1048] = 8'h00; ram[1049] = 8'h00; ram[1050] = 8'h00; ram[1051] = 8'h00;
+ ram[1052] = 8'h00; ram[1053] = 8'h00; ram[1054] = 8'h00; ram[1055] = 8'h00;
+ ram[1056] = 8'h00; ram[1057] = 8'h00; ram[1058] = 8'h00; ram[1059] = 8'h00;
+ ram[1060] = 8'h00; ram[1061] = 8'h00; ram[1062] = 8'h00; ram[1063] = 8'h00;
+ ram[1064] = 8'h00; ram[1065] = 8'h00; ram[1066] = 8'h00; ram[1067] = 8'h00;
+ ram[1068] = 8'h00; ram[1069] = 8'h00; ram[1070] = 8'h00; ram[1071] = 8'h00;
+ ram[1072] = 8'h00; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
+ ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
+ ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
+ ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
+ ram[1088] = 8'h00; ram[1089] = 8'h00; ram[1090] = 8'h00; ram[1091] = 8'h00;
+ ram[1092] = 8'h00; ram[1093] = 8'h00; ram[1094] = 8'h00; ram[1095] = 8'h00;
+ ram[1096] = 8'h00; ram[1097] = 8'h00; ram[1098] = 8'h00; ram[1099] = 8'h00;
+ ram[1100] = 8'h00; ram[1101] = 8'h00; ram[1102] = 8'h00; ram[1103] = 8'h00;
+ ram[1104] = 8'h00; ram[1105] = 8'h00; ram[1106] = 8'h00; ram[1107] = 8'h00;
+ ram[1108] = 8'h00; ram[1109] = 8'h00; ram[1110] = 8'h00; ram[1111] = 8'h00;
+ ram[1112] = 8'h00; ram[1113] = 8'h00; ram[1114] = 8'h00; ram[1115] = 8'h00;
+ ram[1116] = 8'h00; ram[1117] = 8'h00; ram[1118] = 8'h00; ram[1119] = 8'h00;
+ ram[1120] = 8'h00; ram[1121] = 8'h00; ram[1122] = 8'h00; ram[1123] = 8'h00;
+ ram[1124] = 8'h00; ram[1125] = 8'h00; ram[1126] = 8'h00; ram[1127] = 8'h00;
+ ram[1128] = 8'h00; ram[1129] = 8'h00; ram[1130] = 8'h00; ram[1131] = 8'h00;
+ ram[1132] = 8'h00; ram[1133] = 8'h00; ram[1134] = 8'h00; ram[1135] = 8'h00;
+ ram[1136] = 8'h00; ram[1137] = 8'h00; ram[1138] = 8'h00; ram[1139] = 8'h00;
+ ram[1140] = 8'h00; ram[1141] = 8'h00; ram[1142] = 8'h00; ram[1143] = 8'h00;
+ ram[1144] = 8'h00; ram[1145] = 8'h00; ram[1146] = 8'h00; ram[1147] = 8'h00;
+ ram[1148] = 8'h00; ram[1149] = 8'h00; ram[1150] = 8'h00; ram[1151] = 8'h00;
+ ram[1152] = 8'h00; ram[1153] = 8'h00; ram[1154] = 8'h00; ram[1155] = 8'h00;
+ ram[1156] = 8'h00; ram[1157] = 8'h00; ram[1158] = 8'h00; ram[1159] = 8'h00;
+ ram[1160] = 8'h00; ram[1161] = 8'h00; ram[1162] = 8'h00; ram[1163] = 8'h00;
+ ram[1164] = 8'h00; ram[1165] = 8'h00; ram[1166] = 8'h00; ram[1167] = 8'h00;
+ ram[1168] = 8'h00; ram[1169] = 8'h00; ram[1170] = 8'h00; ram[1171] = 8'h00;
+ ram[1172] = 8'h00; ram[1173] = 8'h00; ram[1174] = 8'h00; ram[1175] = 8'h00;
+ ram[1176] = 8'h00; ram[1177] = 8'h00; ram[1178] = 8'h00; ram[1179] = 8'h00;
+ ram[1180] = 8'h00; ram[1181] = 8'h00; ram[1182] = 8'h00; ram[1183] = 8'h00;
+ ram[1184] = 8'h00; ram[1185] = 8'h00; ram[1186] = 8'h00; ram[1187] = 8'h00;
+ ram[1188] = 8'h00; ram[1189] = 8'h00; ram[1190] = 8'h00; ram[1191] = 8'h00;
+ ram[1192] = 8'h00; ram[1193] = 8'h00; ram[1194] = 8'h00; ram[1195] = 8'h00;
+ ram[1196] = 8'h00; ram[1197] = 8'h00; ram[1198] = 8'h00; ram[1199] = 8'h00;
+ ram[1200] = 8'h00; ram[1201] = 8'h00; ram[1202] = 8'h00; ram[1203] = 8'h00;
+ ram[1204] = 8'h00; ram[1205] = 8'h00; ram[1206] = 8'h00; ram[1207] = 8'h00;
+ ram[1208] = 8'h00; ram[1209] = 8'h00; ram[1210] = 8'h00; ram[1211] = 8'h00;
+ ram[1212] = 8'h00; ram[1213] = 8'h00; ram[1214] = 8'h00; ram[1215] = 8'h00;
+ ram[1216] = 8'h00; ram[1217] = 8'h00; ram[1218] = 8'h00; ram[1219] = 8'h00;
+ ram[1220] = 8'h00; ram[1221] = 8'h00; ram[1222] = 8'h00; ram[1223] = 8'h00;
+ ram[1224] = 8'h00; ram[1225] = 8'h00; ram[1226] = 8'h00; ram[1227] = 8'h00;
+ ram[1228] = 8'h00; ram[1229] = 8'h00; ram[1230] = 8'h00; ram[1231] = 8'h00;
+ ram[1232] = 8'h00; ram[1233] = 8'h00; ram[1234] = 8'h00; ram[1235] = 8'h00;
+ ram[1236] = 8'h00; ram[1237] = 8'h00; ram[1238] = 8'h00; ram[1239] = 8'h00;
+ ram[1240] = 8'h00; ram[1241] = 8'h00; ram[1242] = 8'h00; ram[1243] = 8'h00;
+ ram[1244] = 8'h00; ram[1245] = 8'h00; ram[1246] = 8'h00; ram[1247] = 8'h00;
+ ram[1248] = 8'h00; ram[1249] = 8'h00; ram[1250] = 8'h00; ram[1251] = 8'h00;
+ ram[1252] = 8'h00; ram[1253] = 8'h00; ram[1254] = 8'h00; ram[1255] = 8'h00;
+ ram[1256] = 8'h00; ram[1257] = 8'h00; ram[1258] = 8'h00; ram[1259] = 8'h00;
+ ram[1260] = 8'h00; ram[1261] = 8'h00; ram[1262] = 8'h00; ram[1263] = 8'h00;
+ ram[1264] = 8'h00; ram[1265] = 8'h00; ram[1266] = 8'h00; ram[1267] = 8'h00;
+ ram[1268] = 8'h00; ram[1269] = 8'h00; ram[1270] = 8'h00; ram[1271] = 8'h00;
+ ram[1272] = 8'h00; ram[1273] = 8'h00; ram[1274] = 8'h00; ram[1275] = 8'h00;
+ ram[1276] = 8'h00; ram[1277] = 8'h00; ram[1278] = 8'h00; ram[1279] = 8'h00;
+ ram[1280] = 8'h00; ram[1281] = 8'h00; ram[1282] = 8'h00; ram[1283] = 8'h00;
+ ram[1284] = 8'h00; ram[1285] = 8'h00; ram[1286] = 8'h00; ram[1287] = 8'h00;
+ ram[1288] = 8'h00; ram[1289] = 8'h00; ram[1290] = 8'h00; ram[1291] = 8'h00;
+ ram[1292] = 8'h00; ram[1293] = 8'h00; ram[1294] = 8'h00; ram[1295] = 8'h00;
+ ram[1296] = 8'h00; ram[1297] = 8'h00; ram[1298] = 8'h00; ram[1299] = 8'h00;
+ ram[1300] = 8'h00; ram[1301] = 8'h00; ram[1302] = 8'h00; ram[1303] = 8'h00;
+ ram[1304] = 8'h00; ram[1305] = 8'h00; ram[1306] = 8'h00; ram[1307] = 8'h00;
+ ram[1308] = 8'h00; ram[1309] = 8'h00; ram[1310] = 8'h00; ram[1311] = 8'h00;
+ ram[1312] = 8'h00; ram[1313] = 8'h00; ram[1314] = 8'h00; ram[1315] = 8'h00;
+ ram[1316] = 8'h00; ram[1317] = 8'h00; ram[1318] = 8'h00; ram[1319] = 8'h00;
+ ram[1320] = 8'h00; ram[1321] = 8'h00; ram[1322] = 8'h00; ram[1323] = 8'h00;
+ ram[1324] = 8'h00; ram[1325] = 8'h00; ram[1326] = 8'h00; ram[1327] = 8'h00;
+ ram[1328] = 8'h00; ram[1329] = 8'h00; ram[1330] = 8'h00; ram[1331] = 8'h00;
+ ram[1332] = 8'h00; ram[1333] = 8'h00; ram[1334] = 8'h00; ram[1335] = 8'h00;
+ ram[1336] = 8'h00; ram[1337] = 8'h00; ram[1338] = 8'h00; ram[1339] = 8'h00;
+ ram[1340] = 8'h00; ram[1341] = 8'h00; ram[1342] = 8'h00; ram[1343] = 8'h00;
+ ram[1344] = 8'h00; ram[1345] = 8'h00; ram[1346] = 8'h00; ram[1347] = 8'h00;
+ ram[1348] = 8'h00; ram[1349] = 8'h00; ram[1350] = 8'h00; ram[1351] = 8'h00;
+ ram[1352] = 8'h00; ram[1353] = 8'h00; ram[1354] = 8'h00; ram[1355] = 8'h00;
+ ram[1356] = 8'h00; ram[1357] = 8'h00; ram[1358] = 8'h00; ram[1359] = 8'h00;
+ ram[1360] = 8'h00; ram[1361] = 8'h00; ram[1362] = 8'h00; ram[1363] = 8'h00;
+ ram[1364] = 8'h00; ram[1365] = 8'h00; ram[1366] = 8'h00; ram[1367] = 8'h00;
+ ram[1368] = 8'h00; ram[1369] = 8'h00; ram[1370] = 8'h00; ram[1371] = 8'h00;
+ ram[1372] = 8'h00; ram[1373] = 8'h00; ram[1374] = 8'h00; ram[1375] = 8'h00;
+ ram[1376] = 8'h00; ram[1377] = 8'h00; ram[1378] = 8'h00; ram[1379] = 8'h00;
+ ram[1380] = 8'h00; ram[1381] = 8'h00; ram[1382] = 8'h00; ram[1383] = 8'h00;
+ ram[1384] = 8'h00; ram[1385] = 8'h00; ram[1386] = 8'h00; ram[1387] = 8'h00;
+ ram[1388] = 8'h00; ram[1389] = 8'h00; ram[1390] = 8'h00; ram[1391] = 8'h00;
+ ram[1392] = 8'h00; ram[1393] = 8'h00; ram[1394] = 8'h00; ram[1395] = 8'h00;
+ ram[1396] = 8'h00; ram[1397] = 8'h00; ram[1398] = 8'h00; ram[1399] = 8'h00;
+ ram[1400] = 8'h00; ram[1401] = 8'h00; ram[1402] = 8'h00; ram[1403] = 8'h00;
+ ram[1404] = 8'h00; ram[1405] = 8'h00; ram[1406] = 8'h00; ram[1407] = 8'h00;
+ ram[1408] = 8'h00; ram[1409] = 8'h00; ram[1410] = 8'h00; ram[1411] = 8'h00;
+ ram[1412] = 8'h00; ram[1413] = 8'h00; ram[1414] = 8'h00; ram[1415] = 8'h00;
+ ram[1416] = 8'h00; ram[1417] = 8'h00; ram[1418] = 8'h00; ram[1419] = 8'h00;
+ ram[1420] = 8'h00; ram[1421] = 8'h00; ram[1422] = 8'h00; ram[1423] = 8'h00;
+ ram[1424] = 8'h00; ram[1425] = 8'h00; ram[1426] = 8'h00; ram[1427] = 8'h00;
+ ram[1428] = 8'h00; ram[1429] = 8'h00; ram[1430] = 8'h00; ram[1431] = 8'h00;
+ ram[1432] = 8'h00; ram[1433] = 8'h00; ram[1434] = 8'h00; ram[1435] = 8'h00;
+ ram[1436] = 8'h00; ram[1437] = 8'h00; ram[1438] = 8'h00; ram[1439] = 8'h00;
+ ram[1440] = 8'h00; ram[1441] = 8'h00; ram[1442] = 8'h00; ram[1443] = 8'h00;
+ ram[1444] = 8'h00; ram[1445] = 8'h00; ram[1446] = 8'h00; ram[1447] = 8'h00;
+ ram[1448] = 8'h00; ram[1449] = 8'h00; ram[1450] = 8'h00; ram[1451] = 8'h00;
+ ram[1452] = 8'h00; ram[1453] = 8'h00; ram[1454] = 8'h00; ram[1455] = 8'h00;
+ ram[1456] = 8'h00; ram[1457] = 8'h00; ram[1458] = 8'h00; ram[1459] = 8'h00;
+ ram[1460] = 8'h00; ram[1461] = 8'h00; ram[1462] = 8'h00; ram[1463] = 8'h00;
+ ram[1464] = 8'h00; ram[1465] = 8'h00; ram[1466] = 8'h00; ram[1467] = 8'h00;
+ ram[1468] = 8'h00; ram[1469] = 8'h00; ram[1470] = 8'h00; ram[1471] = 8'h00;
+ ram[1472] = 8'h00; ram[1473] = 8'h00; ram[1474] = 8'h00; ram[1475] = 8'h00;
+ ram[1476] = 8'h00; ram[1477] = 8'h00; ram[1478] = 8'h00; ram[1479] = 8'h00;
+ ram[1480] = 8'h00; ram[1481] = 8'h00; ram[1482] = 8'h00; ram[1483] = 8'h00;
+ ram[1484] = 8'h00; ram[1485] = 8'h00; ram[1486] = 8'h00; ram[1487] = 8'h00;
+ ram[1488] = 8'h00; ram[1489] = 8'h00; ram[1490] = 8'h00; ram[1491] = 8'h00;
+ ram[1492] = 8'h00; ram[1493] = 8'h00; ram[1494] = 8'h00; ram[1495] = 8'h00;
+ ram[1496] = 8'h00; ram[1497] = 8'h00; ram[1498] = 8'h00; ram[1499] = 8'h00;
+ ram[1500] = 8'h00; ram[1501] = 8'h00; ram[1502] = 8'h00; ram[1503] = 8'h00;
+ ram[1504] = 8'h00; ram[1505] = 8'h00; ram[1506] = 8'h00; ram[1507] = 8'h00;
+ ram[1508] = 8'h00; ram[1509] = 8'h00; ram[1510] = 8'h00; ram[1511] = 8'h00;
+ ram[1512] = 8'h00; ram[1513] = 8'h00; ram[1514] = 8'h00; ram[1515] = 8'h00;
+ ram[1516] = 8'h00; ram[1517] = 8'h00; ram[1518] = 8'h00; ram[1519] = 8'h00;
+ ram[1520] = 8'h00; ram[1521] = 8'h00; ram[1522] = 8'h00; ram[1523] = 8'h00;
+ ram[1524] = 8'h00; ram[1525] = 8'h00; ram[1526] = 8'h00; ram[1527] = 8'h00;
+ ram[1528] = 8'h00; ram[1529] = 8'h00; ram[1530] = 8'h00; ram[1531] = 8'h00;
+ ram[1532] = 8'h00; ram[1533] = 8'h00; ram[1534] = 8'h00; ram[1535] = 8'h00;
+ ram[1536] = 8'h00; ram[1537] = 8'h00; ram[1538] = 8'h00; ram[1539] = 8'h00;
+ ram[1540] = 8'h00; ram[1541] = 8'h00; ram[1542] = 8'h00; ram[1543] = 8'h00;
+ ram[1544] = 8'h00; ram[1545] = 8'h00; ram[1546] = 8'h00; ram[1547] = 8'h00;
+ ram[1548] = 8'h00; ram[1549] = 8'h00; ram[1550] = 8'h00; ram[1551] = 8'h00;
+ ram[1552] = 8'h00; ram[1553] = 8'h00; ram[1554] = 8'h00; ram[1555] = 8'h00;
+ ram[1556] = 8'h00; ram[1557] = 8'h00; ram[1558] = 8'h00; ram[1559] = 8'h00;
+ ram[1560] = 8'h00; ram[1561] = 8'h00; ram[1562] = 8'h00; ram[1563] = 8'h00;
+ ram[1564] = 8'h00; ram[1565] = 8'h00; ram[1566] = 8'h00; ram[1567] = 8'h00;
+ ram[1568] = 8'h00; ram[1569] = 8'h00; ram[1570] = 8'h00; ram[1571] = 8'h00;
+ ram[1572] = 8'h00; ram[1573] = 8'h00; ram[1574] = 8'h00; ram[1575] = 8'h00;
+ ram[1576] = 8'h00; ram[1577] = 8'h00; ram[1578] = 8'h00; ram[1579] = 8'h00;
+ ram[1580] = 8'h00; ram[1581] = 8'h00; ram[1582] = 8'h00; ram[1583] = 8'h00;
+ ram[1584] = 8'h00; ram[1585] = 8'h00; ram[1586] = 8'h00; ram[1587] = 8'h00;
+ ram[1588] = 8'h00; ram[1589] = 8'h00; ram[1590] = 8'h00; ram[1591] = 8'h00;
+ ram[1592] = 8'h00; ram[1593] = 8'h00; ram[1594] = 8'h00; ram[1595] = 8'h00;
+ ram[1596] = 8'h00; ram[1597] = 8'h00; ram[1598] = 8'h00; ram[1599] = 8'h00;
+ ram[1600] = 8'h00; ram[1601] = 8'h00; ram[1602] = 8'h00; ram[1603] = 8'h00;
+ ram[1604] = 8'h00; ram[1605] = 8'h00; ram[1606] = 8'h00; ram[1607] = 8'h00;
+ ram[1608] = 8'h00; ram[1609] = 8'h00; ram[1610] = 8'h00; ram[1611] = 8'h00;
+ ram[1612] = 8'h00; ram[1613] = 8'h00; ram[1614] = 8'h00; ram[1615] = 8'h00;
+ ram[1616] = 8'h00; ram[1617] = 8'h00; ram[1618] = 8'h00; ram[1619] = 8'h00;
+ ram[1620] = 8'h00; ram[1621] = 8'h00; ram[1622] = 8'h00; ram[1623] = 8'h00;
+ ram[1624] = 8'h00; ram[1625] = 8'h00; ram[1626] = 8'h00; ram[1627] = 8'h00;
+ ram[1628] = 8'h00; ram[1629] = 8'h00; ram[1630] = 8'h00; ram[1631] = 8'h00;
+ ram[1632] = 8'h00; ram[1633] = 8'h00; ram[1634] = 8'h00; ram[1635] = 8'h00;
+ ram[1636] = 8'h00; ram[1637] = 8'h00; ram[1638] = 8'h00; ram[1639] = 8'h00;
+ ram[1640] = 8'h00; ram[1641] = 8'h00; ram[1642] = 8'h00; ram[1643] = 8'h00;
+ ram[1644] = 8'h00; ram[1645] = 8'h00; ram[1646] = 8'h00; ram[1647] = 8'h00;
+ ram[1648] = 8'h00; ram[1649] = 8'h00; ram[1650] = 8'h00; ram[1651] = 8'h00;
+ ram[1652] = 8'h00; ram[1653] = 8'h00; ram[1654] = 8'h00; ram[1655] = 8'h00;
+ ram[1656] = 8'h00; ram[1657] = 8'h00; ram[1658] = 8'h00; ram[1659] = 8'h00;
+ ram[1660] = 8'h00; ram[1661] = 8'h00; ram[1662] = 8'h00; ram[1663] = 8'h00;
+ ram[1664] = 8'h00; ram[1665] = 8'h00; ram[1666] = 8'h00; ram[1667] = 8'h00;
+ ram[1668] = 8'h00; ram[1669] = 8'h00; ram[1670] = 8'h00; ram[1671] = 8'h00;
+ ram[1672] = 8'h00; ram[1673] = 8'h00; ram[1674] = 8'h00; ram[1675] = 8'h00;
+ ram[1676] = 8'h00; ram[1677] = 8'h00; ram[1678] = 8'h00; ram[1679] = 8'h00;
+ ram[1680] = 8'h00; ram[1681] = 8'h00; ram[1682] = 8'h00; ram[1683] = 8'h00;
+ ram[1684] = 8'h00; ram[1685] = 8'h00; ram[1686] = 8'h00; ram[1687] = 8'h00;
+ ram[1688] = 8'h00; ram[1689] = 8'h00; ram[1690] = 8'h00; ram[1691] = 8'h00;
+ ram[1692] = 8'h00; ram[1693] = 8'h00; ram[1694] = 8'h00; ram[1695] = 8'h00;
+ ram[1696] = 8'h00; ram[1697] = 8'h00; ram[1698] = 8'h00; ram[1699] = 8'h00;
+ ram[1700] = 8'h00; ram[1701] = 8'h00; ram[1702] = 8'h00; ram[1703] = 8'h00;
+ ram[1704] = 8'h00; ram[1705] = 8'h00; ram[1706] = 8'h00; ram[1707] = 8'h00;
+ ram[1708] = 8'h00; ram[1709] = 8'h00; ram[1710] = 8'h00; ram[1711] = 8'h00;
+ ram[1712] = 8'h00; ram[1713] = 8'h00; ram[1714] = 8'h00; ram[1715] = 8'h00;
+ ram[1716] = 8'h00; ram[1717] = 8'h00; ram[1718] = 8'h00; ram[1719] = 8'h00;
+ ram[1720] = 8'h00; ram[1721] = 8'h00; ram[1722] = 8'h00; ram[1723] = 8'h00;
+ ram[1724] = 8'h00; ram[1725] = 8'h00; ram[1726] = 8'h00; ram[1727] = 8'h00;
+ ram[1728] = 8'h00; ram[1729] = 8'h00; ram[1730] = 8'h00; ram[1731] = 8'h00;
+ ram[1732] = 8'h00; ram[1733] = 8'h00; ram[1734] = 8'h00; ram[1735] = 8'h00;
+ ram[1736] = 8'h00; ram[1737] = 8'h00; ram[1738] = 8'h00; ram[1739] = 8'h00;
+ ram[1740] = 8'h00; ram[1741] = 8'h00; ram[1742] = 8'h00; ram[1743] = 8'h00;
+ ram[1744] = 8'h00; ram[1745] = 8'h00; ram[1746] = 8'h00; ram[1747] = 8'h00;
+ ram[1748] = 8'h00; ram[1749] = 8'h00; ram[1750] = 8'h00; ram[1751] = 8'h00;
+ ram[1752] = 8'h00; ram[1753] = 8'h00; ram[1754] = 8'h00; ram[1755] = 8'h00;
+ ram[1756] = 8'h00; ram[1757] = 8'h00; ram[1758] = 8'h00; ram[1759] = 8'h00;
+ ram[1760] = 8'h00; ram[1761] = 8'h00; ram[1762] = 8'h00; ram[1763] = 8'h00;
+ ram[1764] = 8'h00; ram[1765] = 8'h00; ram[1766] = 8'h00; ram[1767] = 8'h00;
+ ram[1768] = 8'h00; ram[1769] = 8'h00; ram[1770] = 8'h00; ram[1771] = 8'h00;
+ ram[1772] = 8'h00; ram[1773] = 8'h00; ram[1774] = 8'h00; ram[1775] = 8'h00;
+ ram[1776] = 8'h00; ram[1777] = 8'h00; ram[1778] = 8'h00; ram[1779] = 8'h00;
+ ram[1780] = 8'h00; ram[1781] = 8'h00; ram[1782] = 8'h00; ram[1783] = 8'h00;
+ ram[1784] = 8'h00; ram[1785] = 8'h00; ram[1786] = 8'h00; ram[1787] = 8'h00;
+ ram[1788] = 8'h00; ram[1789] = 8'h00; ram[1790] = 8'h00; ram[1791] = 8'h00;
+ ram[1792] = 8'h00; ram[1793] = 8'h00; ram[1794] = 8'h00; ram[1795] = 8'h00;
+ ram[1796] = 8'h00; ram[1797] = 8'h00; ram[1798] = 8'h00; ram[1799] = 8'h00;
+ ram[1800] = 8'h00; ram[1801] = 8'h00; ram[1802] = 8'h00; ram[1803] = 8'h00;
+ ram[1804] = 8'h00; ram[1805] = 8'h00; ram[1806] = 8'h00; ram[1807] = 8'h00;
+ ram[1808] = 8'h00; ram[1809] = 8'h00; ram[1810] = 8'h00; ram[1811] = 8'h00;
+ ram[1812] = 8'h00; ram[1813] = 8'h00; ram[1814] = 8'h00; ram[1815] = 8'h00;
+ ram[1816] = 8'h00; ram[1817] = 8'h00; ram[1818] = 8'h00; ram[1819] = 8'h00;
+ ram[1820] = 8'h00; ram[1821] = 8'h00; ram[1822] = 8'h00; ram[1823] = 8'h00;
+ ram[1824] = 8'h00; ram[1825] = 8'h00; ram[1826] = 8'h00; ram[1827] = 8'h00;
+ ram[1828] = 8'h00; ram[1829] = 8'h00; ram[1830] = 8'h00; ram[1831] = 8'h00;
+ ram[1832] = 8'h00; ram[1833] = 8'h00; ram[1834] = 8'h00; ram[1835] = 8'h00;
+ ram[1836] = 8'h00; ram[1837] = 8'h00; ram[1838] = 8'h00; ram[1839] = 8'h00;
+ ram[1840] = 8'h00; ram[1841] = 8'h00; ram[1842] = 8'h00; ram[1843] = 8'h00;
+ ram[1844] = 8'h00; ram[1845] = 8'h00; ram[1846] = 8'h00; ram[1847] = 8'h00;
+ ram[1848] = 8'h00; ram[1849] = 8'h00; ram[1850] = 8'h00; ram[1851] = 8'h00;
+ ram[1852] = 8'h00; ram[1853] = 8'h00; ram[1854] = 8'h00; ram[1855] = 8'h00;
+ ram[1856] = 8'h00; ram[1857] = 8'h00; ram[1858] = 8'h00; ram[1859] = 8'h00;
+ ram[1860] = 8'h00; ram[1861] = 8'h00; ram[1862] = 8'h00; ram[1863] = 8'h00;
+ ram[1864] = 8'h00; ram[1865] = 8'h00; ram[1866] = 8'h00; ram[1867] = 8'h00;
+ ram[1868] = 8'h00; ram[1869] = 8'h00; ram[1870] = 8'h00; ram[1871] = 8'h00;
+ ram[1872] = 8'h00; ram[1873] = 8'h00; ram[1874] = 8'h00; ram[1875] = 8'h00;
+ ram[1876] = 8'h00; ram[1877] = 8'h00; ram[1878] = 8'h00; ram[1879] = 8'h00;
+ ram[1880] = 8'h00; ram[1881] = 8'h00; ram[1882] = 8'h00; ram[1883] = 8'h00;
+ ram[1884] = 8'h00; ram[1885] = 8'h00; ram[1886] = 8'h00; ram[1887] = 8'h00;
+ ram[1888] = 8'h00; ram[1889] = 8'h00; ram[1890] = 8'h00; ram[1891] = 8'h00;
+ ram[1892] = 8'h00; ram[1893] = 8'h00; ram[1894] = 8'h00; ram[1895] = 8'h00;
+ ram[1896] = 8'h00; ram[1897] = 8'h00; ram[1898] = 8'h00; ram[1899] = 8'h00;
+ ram[1900] = 8'h00; ram[1901] = 8'h00; ram[1902] = 8'h00; ram[1903] = 8'h00;
+ ram[1904] = 8'h00; ram[1905] = 8'h00; ram[1906] = 8'h00; ram[1907] = 8'h00;
+ ram[1908] = 8'h00; ram[1909] = 8'h00; ram[1910] = 8'h00; ram[1911] = 8'h00;
+ ram[1912] = 8'h00; ram[1913] = 8'h00; ram[1914] = 8'h00; ram[1915] = 8'h00;
+ ram[1916] = 8'h00; ram[1917] = 8'h00; ram[1918] = 8'h00; ram[1919] = 8'h00;
+ ram[1920] = 8'h00; ram[1921] = 8'h00; ram[1922] = 8'h00; ram[1923] = 8'h00;
+ ram[1924] = 8'h00; ram[1925] = 8'h00; ram[1926] = 8'h00; ram[1927] = 8'h00;
+ ram[1928] = 8'h00; ram[1929] = 8'h00; ram[1930] = 8'h00; ram[1931] = 8'h00;
+ ram[1932] = 8'h00; ram[1933] = 8'h00; ram[1934] = 8'h00; ram[1935] = 8'h00;
+ ram[1936] = 8'h00; ram[1937] = 8'h00; ram[1938] = 8'h00; ram[1939] = 8'h00;
+ ram[1940] = 8'h00; ram[1941] = 8'h00; ram[1942] = 8'h00; ram[1943] = 8'h00;
+ ram[1944] = 8'h00; ram[1945] = 8'h00; ram[1946] = 8'h00; ram[1947] = 8'h00;
+ ram[1948] = 8'h00; ram[1949] = 8'h00; ram[1950] = 8'h00; ram[1951] = 8'h00;
+ ram[1952] = 8'h00; ram[1953] = 8'h00; ram[1954] = 8'h00; ram[1955] = 8'h00;
+ ram[1956] = 8'h00; ram[1957] = 8'h00; ram[1958] = 8'h00; ram[1959] = 8'h00;
+ ram[1960] = 8'h00; ram[1961] = 8'h00; ram[1962] = 8'h00; ram[1963] = 8'h00;
+ ram[1964] = 8'h00; ram[1965] = 8'h00; ram[1966] = 8'h00; ram[1967] = 8'h00;
+ ram[1968] = 8'h00; ram[1969] = 8'h00; ram[1970] = 8'h00; ram[1971] = 8'h00;
+ ram[1972] = 8'h00; ram[1973] = 8'h00; ram[1974] = 8'h00; ram[1975] = 8'h00;
+ ram[1976] = 8'h00; ram[1977] = 8'h00; ram[1978] = 8'h00; ram[1979] = 8'h00;
+ ram[1980] = 8'h00; ram[1981] = 8'h00; ram[1982] = 8'h00; ram[1983] = 8'h00;
+ ram[1984] = 8'h00; ram[1985] = 8'h00; ram[1986] = 8'h00; ram[1987] = 8'h00;
+ ram[1988] = 8'h00; ram[1989] = 8'h00; ram[1990] = 8'h00; ram[1991] = 8'h00;
+ ram[1992] = 8'h00; ram[1993] = 8'h00; ram[1994] = 8'h00; ram[1995] = 8'h00;
+ ram[1996] = 8'h00; ram[1997] = 8'h00; ram[1998] = 8'h00; ram[1999] = 8'h00;
+ ram[2000] = 8'h00; ram[2001] = 8'h00; ram[2002] = 8'h00; ram[2003] = 8'h00;
+ ram[2004] = 8'h00; ram[2005] = 8'h00; ram[2006] = 8'h00; ram[2007] = 8'h00;
+ ram[2008] = 8'h00; ram[2009] = 8'h00; ram[2010] = 8'h00; ram[2011] = 8'h00;
+ ram[2012] = 8'h00; ram[2013] = 8'h00; ram[2014] = 8'h00; ram[2015] = 8'h00;
+ ram[2016] = 8'h00; ram[2017] = 8'h00; ram[2018] = 8'h00; ram[2019] = 8'h00;
+ ram[2020] = 8'h00; ram[2021] = 8'h00; ram[2022] = 8'h00; ram[2023] = 8'h00;
+ ram[2024] = 8'h00; ram[2025] = 8'h00; ram[2026] = 8'h00; ram[2027] = 8'h00;
+ ram[2028] = 8'h00; ram[2029] = 8'h00; ram[2030] = 8'h00; ram[2031] = 8'h00;
+ ram[2032] = 8'h00; ram[2033] = 8'h00; ram[2034] = 8'h00; ram[2035] = 8'h00;
+ ram[2036] = 8'h00; ram[2037] = 8'h00; ram[2038] = 8'h00; ram[2039] = 8'h00;
+ ram[2040] = 8'h00; ram[2041] = 8'h00; ram[2042] = 8'h00; ram[2043] = 8'h00;
+ ram[2044] = 8'h00; ram[2045] = 8'h00; ram[2046] = 8'h00; ram[2047] = 8'h00;
+ ram[2048] = 8'h00; ram[2049] = 8'h00; ram[2050] = 8'h00; ram[2051] = 8'h00;
+ ram[2052] = 8'h00; ram[2053] = 8'h00; ram[2054] = 8'h00; ram[2055] = 8'h00;
+ ram[2056] = 8'h00; ram[2057] = 8'h00; ram[2058] = 8'h00; ram[2059] = 8'h00;
+ ram[2060] = 8'h00; ram[2061] = 8'h00; ram[2062] = 8'h00; ram[2063] = 8'h00;
+ ram[2064] = 8'h00; ram[2065] = 8'h00; ram[2066] = 8'h00; ram[2067] = 8'h00;
+ ram[2068] = 8'h00; ram[2069] = 8'h00; ram[2070] = 8'h00; ram[2071] = 8'h00;
+ ram[2072] = 8'h00; ram[2073] = 8'h00; ram[2074] = 8'h00; ram[2075] = 8'h00;
+ ram[2076] = 8'h00; ram[2077] = 8'h00; ram[2078] = 8'h00; ram[2079] = 8'h00;
+ ram[2080] = 8'h00; ram[2081] = 8'h00; ram[2082] = 8'h00; ram[2083] = 8'h00;
+ ram[2084] = 8'h00; ram[2085] = 8'h00; ram[2086] = 8'h00; ram[2087] = 8'h00;
+ ram[2088] = 8'h00; ram[2089] = 8'h00; ram[2090] = 8'h00; ram[2091] = 8'h00;
+ ram[2092] = 8'h00; ram[2093] = 8'h00; ram[2094] = 8'h00; ram[2095] = 8'h00;
+ ram[2096] = 8'h00; ram[2097] = 8'h00; ram[2098] = 8'h00; ram[2099] = 8'h00;
+ ram[2100] = 8'h00; ram[2101] = 8'h00; ram[2102] = 8'h00; ram[2103] = 8'h00;
+ ram[2104] = 8'h00; ram[2105] = 8'h00; ram[2106] = 8'h00; ram[2107] = 8'h00;
+ ram[2108] = 8'h00; ram[2109] = 8'h00; ram[2110] = 8'h00; ram[2111] = 8'h00;
+ ram[2112] = 8'h00; ram[2113] = 8'h00; ram[2114] = 8'h00; ram[2115] = 8'h00;
+ ram[2116] = 8'h00; ram[2117] = 8'h00; ram[2118] = 8'h00; ram[2119] = 8'h00;
+ ram[2120] = 8'h00; ram[2121] = 8'h00; ram[2122] = 8'h00; ram[2123] = 8'h00;
+ ram[2124] = 8'h00; ram[2125] = 8'h00; ram[2126] = 8'h00; ram[2127] = 8'h00;
+ ram[2128] = 8'h00; ram[2129] = 8'h00; ram[2130] = 8'h00; ram[2131] = 8'h00;
+ ram[2132] = 8'h00; ram[2133] = 8'h00; ram[2134] = 8'h00; ram[2135] = 8'h00;
+ ram[2136] = 8'h00; ram[2137] = 8'h00; ram[2138] = 8'h00; ram[2139] = 8'h00;
+ ram[2140] = 8'h00; ram[2141] = 8'h00; ram[2142] = 8'h00; ram[2143] = 8'h00;
+ ram[2144] = 8'h00; ram[2145] = 8'h00; ram[2146] = 8'h00; ram[2147] = 8'h00;
+ ram[2148] = 8'h00; ram[2149] = 8'h00; ram[2150] = 8'h00; ram[2151] = 8'h00;
+ ram[2152] = 8'h00; ram[2153] = 8'h00; ram[2154] = 8'h00; ram[2155] = 8'h00;
+ ram[2156] = 8'h00; ram[2157] = 8'h00; ram[2158] = 8'h00; ram[2159] = 8'h00;
+ ram[2160] = 8'h00; ram[2161] = 8'h00; ram[2162] = 8'h00; ram[2163] = 8'h00;
+ ram[2164] = 8'h00; ram[2165] = 8'h00; ram[2166] = 8'h00; ram[2167] = 8'h00;
+ ram[2168] = 8'h00; ram[2169] = 8'h00; ram[2170] = 8'h00; ram[2171] = 8'h00;
+ ram[2172] = 8'h00; ram[2173] = 8'h00; ram[2174] = 8'h00; ram[2175] = 8'h00;
+ ram[2176] = 8'h00; ram[2177] = 8'h00; ram[2178] = 8'h00; ram[2179] = 8'h00;
+ ram[2180] = 8'h00; ram[2181] = 8'h00; ram[2182] = 8'h00; ram[2183] = 8'h00;
+ ram[2184] = 8'h00; ram[2185] = 8'h00; ram[2186] = 8'h00; ram[2187] = 8'h00;
+ ram[2188] = 8'h00; ram[2189] = 8'h00; ram[2190] = 8'h00; ram[2191] = 8'h00;
+ ram[2192] = 8'h00; ram[2193] = 8'h00; ram[2194] = 8'h00; ram[2195] = 8'h00;
+ ram[2196] = 8'h00; ram[2197] = 8'h00; ram[2198] = 8'h00; ram[2199] = 8'h00;
+ ram[2200] = 8'h00; ram[2201] = 8'h00; ram[2202] = 8'h00; ram[2203] = 8'h00;
+ ram[2204] = 8'h00; ram[2205] = 8'h00; ram[2206] = 8'h00; ram[2207] = 8'h00;
+ ram[2208] = 8'h00; ram[2209] = 8'h00; ram[2210] = 8'h00; ram[2211] = 8'h00;
+ ram[2212] = 8'h00; ram[2213] = 8'h00; ram[2214] = 8'h00; ram[2215] = 8'h00;
+ ram[2216] = 8'h00; ram[2217] = 8'h00; ram[2218] = 8'h00; ram[2219] = 8'h00;
+ ram[2220] = 8'h00; ram[2221] = 8'h00; ram[2222] = 8'h00; ram[2223] = 8'h00;
+ ram[2224] = 8'h00; ram[2225] = 8'h00; ram[2226] = 8'h00; ram[2227] = 8'h00;
+ ram[2228] = 8'h00; ram[2229] = 8'h00; ram[2230] = 8'h00; ram[2231] = 8'h00;
+ ram[2232] = 8'h00; ram[2233] = 8'h00; ram[2234] = 8'h00; ram[2235] = 8'h00;
+ ram[2236] = 8'h00; ram[2237] = 8'h00; ram[2238] = 8'h00; ram[2239] = 8'h00;
+ ram[2240] = 8'h00; ram[2241] = 8'h00; ram[2242] = 8'h00; ram[2243] = 8'h00;
+ ram[2244] = 8'h00; ram[2245] = 8'h00; ram[2246] = 8'h00; ram[2247] = 8'h00;
+ ram[2248] = 8'h00; ram[2249] = 8'h00; ram[2250] = 8'h00; ram[2251] = 8'h00;
+ ram[2252] = 8'h00; ram[2253] = 8'h00; ram[2254] = 8'h00; ram[2255] = 8'h00;
+ ram[2256] = 8'h00; ram[2257] = 8'h00; ram[2258] = 8'h00; ram[2259] = 8'h00;
+ ram[2260] = 8'h00; ram[2261] = 8'h00; ram[2262] = 8'h00; ram[2263] = 8'h00;
+ ram[2264] = 8'h00; ram[2265] = 8'h00; ram[2266] = 8'h00; ram[2267] = 8'h00;
+ ram[2268] = 8'h00; ram[2269] = 8'h00; ram[2270] = 8'h00; ram[2271] = 8'h00;
+ ram[2272] = 8'h00; ram[2273] = 8'h00; ram[2274] = 8'h00; ram[2275] = 8'h00;
+ ram[2276] = 8'h00; ram[2277] = 8'h00; ram[2278] = 8'h00; ram[2279] = 8'h00;
+ ram[2280] = 8'h00; ram[2281] = 8'h00; ram[2282] = 8'h00; ram[2283] = 8'h00;
+ ram[2284] = 8'h00; ram[2285] = 8'h00; ram[2286] = 8'h00; ram[2287] = 8'h00;
+ ram[2288] = 8'h00; ram[2289] = 8'h00; ram[2290] = 8'h00; ram[2291] = 8'h00;
+ ram[2292] = 8'h00; ram[2293] = 8'h00; ram[2294] = 8'h00; ram[2295] = 8'h00;
+ ram[2296] = 8'h00; ram[2297] = 8'h00; ram[2298] = 8'h00; ram[2299] = 8'h00;
+ ram[2300] = 8'h00; ram[2301] = 8'h00; ram[2302] = 8'h00; ram[2303] = 8'h00;
+ ram[2304] = 8'h00; ram[2305] = 8'h00; ram[2306] = 8'h00; ram[2307] = 8'h00;
+ ram[2308] = 8'h00; ram[2309] = 8'h00; ram[2310] = 8'h00; ram[2311] = 8'h00;
+ ram[2312] = 8'h00; ram[2313] = 8'h00; ram[2314] = 8'h00; ram[2315] = 8'h00;
+ ram[2316] = 8'h00; ram[2317] = 8'h00; ram[2318] = 8'h00; ram[2319] = 8'h00;
+ ram[2320] = 8'h00; ram[2321] = 8'h00; ram[2322] = 8'h00; ram[2323] = 8'h00;
+ ram[2324] = 8'h00; ram[2325] = 8'h00; ram[2326] = 8'h00; ram[2327] = 8'h00;
+ ram[2328] = 8'h00; ram[2329] = 8'h00; ram[2330] = 8'h00; ram[2331] = 8'h00;
+ ram[2332] = 8'h00; ram[2333] = 8'h00; ram[2334] = 8'h00; ram[2335] = 8'h00;
+ ram[2336] = 8'h00; ram[2337] = 8'h00; ram[2338] = 8'h00; ram[2339] = 8'h00;
+ ram[2340] = 8'h00; ram[2341] = 8'h00; ram[2342] = 8'h00; ram[2343] = 8'h00;
+ ram[2344] = 8'h00; ram[2345] = 8'h00; ram[2346] = 8'h00; ram[2347] = 8'h00;
+ ram[2348] = 8'h00; ram[2349] = 8'h00; ram[2350] = 8'h00; ram[2351] = 8'h00;
+ ram[2352] = 8'h00; ram[2353] = 8'h00; ram[2354] = 8'h00; ram[2355] = 8'h00;
+ ram[2356] = 8'h00; ram[2357] = 8'h00; ram[2358] = 8'h00; ram[2359] = 8'h00;
+ ram[2360] = 8'h00; ram[2361] = 8'h00; ram[2362] = 8'h00; ram[2363] = 8'h00;
+ ram[2364] = 8'h00; ram[2365] = 8'h00; ram[2366] = 8'h00; ram[2367] = 8'h00;
+ ram[2368] = 8'h00; ram[2369] = 8'h00; ram[2370] = 8'h00; ram[2371] = 8'h00;
+ ram[2372] = 8'h00; ram[2373] = 8'h00; ram[2374] = 8'h00; ram[2375] = 8'h00;
+ ram[2376] = 8'h00; ram[2377] = 8'h00; ram[2378] = 8'h00; ram[2379] = 8'h00;
+ ram[2380] = 8'h00; ram[2381] = 8'h00; ram[2382] = 8'h00; ram[2383] = 8'h00;
+ ram[2384] = 8'h00; ram[2385] = 8'h00; ram[2386] = 8'h00; ram[2387] = 8'h00;
+ ram[2388] = 8'h00; ram[2389] = 8'h00; ram[2390] = 8'h00; ram[2391] = 8'h00;
+ ram[2392] = 8'h00; ram[2393] = 8'h00; ram[2394] = 8'h00; ram[2395] = 8'h00;
+ ram[2396] = 8'h00; ram[2397] = 8'h00; ram[2398] = 8'h00; ram[2399] = 8'h00;
+ ram[2400] = 8'h00; ram[2401] = 8'h00; ram[2402] = 8'h00; ram[2403] = 8'h00;
+ ram[2404] = 8'h00; ram[2405] = 8'h00; ram[2406] = 8'h00; ram[2407] = 8'h00;
+ ram[2408] = 8'h00; ram[2409] = 8'h00; ram[2410] = 8'h00; ram[2411] = 8'h00;
+ ram[2412] = 8'h00; ram[2413] = 8'h00; ram[2414] = 8'h00; ram[2415] = 8'h00;
+ ram[2416] = 8'h00; ram[2417] = 8'h00; ram[2418] = 8'h00; ram[2419] = 8'h00;
+ ram[2420] = 8'h00; ram[2421] = 8'h00; ram[2422] = 8'h00; ram[2423] = 8'h00;
+ ram[2424] = 8'h00; ram[2425] = 8'h00; ram[2426] = 8'h00; ram[2427] = 8'h00;
+ ram[2428] = 8'h00; ram[2429] = 8'h00; ram[2430] = 8'h00; ram[2431] = 8'h00;
+ ram[2432] = 8'h00; ram[2433] = 8'h00; ram[2434] = 8'h00; ram[2435] = 8'h00;
+ ram[2436] = 8'h00; ram[2437] = 8'h00; ram[2438] = 8'h00; ram[2439] = 8'h00;
+ ram[2440] = 8'h00; ram[2441] = 8'h00; ram[2442] = 8'h00; ram[2443] = 8'h00;
+ ram[2444] = 8'h00; ram[2445] = 8'h00; ram[2446] = 8'h00; ram[2447] = 8'h00;
+ ram[2448] = 8'h00; ram[2449] = 8'h00; ram[2450] = 8'h00; ram[2451] = 8'h00;
+ ram[2452] = 8'h00; ram[2453] = 8'h00; ram[2454] = 8'h00; ram[2455] = 8'h00;
+ ram[2456] = 8'h00; ram[2457] = 8'h00; ram[2458] = 8'h00; ram[2459] = 8'h00;
+ ram[2460] = 8'h00; ram[2461] = 8'h00; ram[2462] = 8'h00; ram[2463] = 8'h00;
+ ram[2464] = 8'h00; ram[2465] = 8'h00; ram[2466] = 8'h00; ram[2467] = 8'h00;
+ ram[2468] = 8'h00; ram[2469] = 8'h00; ram[2470] = 8'h00; ram[2471] = 8'h00;
+ ram[2472] = 8'h00; ram[2473] = 8'h00; ram[2474] = 8'h00; ram[2475] = 8'h00;
+ ram[2476] = 8'h00; ram[2477] = 8'h00; ram[2478] = 8'h00; ram[2479] = 8'h00;
+ ram[2480] = 8'h00; ram[2481] = 8'h00; ram[2482] = 8'h00; ram[2483] = 8'h00;
+ ram[2484] = 8'h00; ram[2485] = 8'h00; ram[2486] = 8'h00; ram[2487] = 8'h00;
+ ram[2488] = 8'h00; ram[2489] = 8'h00; ram[2490] = 8'h00; ram[2491] = 8'h00;
+ ram[2492] = 8'h00; ram[2493] = 8'h00; ram[2494] = 8'h00; ram[2495] = 8'h00;
+ ram[2496] = 8'h00; ram[2497] = 8'h00; ram[2498] = 8'h00; ram[2499] = 8'h00;
+ ram[2500] = 8'h00; ram[2501] = 8'h00; ram[2502] = 8'h00; ram[2503] = 8'h00;
+ ram[2504] = 8'h00; ram[2505] = 8'h00; ram[2506] = 8'h00; ram[2507] = 8'h00;
+ ram[2508] = 8'h00; ram[2509] = 8'h00; ram[2510] = 8'h00; ram[2511] = 8'h00;
+ ram[2512] = 8'h00; ram[2513] = 8'h00; ram[2514] = 8'h00; ram[2515] = 8'h00;
+ ram[2516] = 8'h00; ram[2517] = 8'h00; ram[2518] = 8'h00; ram[2519] = 8'h00;
+ ram[2520] = 8'h00; ram[2521] = 8'h00; ram[2522] = 8'h00; ram[2523] = 8'h00;
+ ram[2524] = 8'h00; ram[2525] = 8'h00; ram[2526] = 8'h00; ram[2527] = 8'h00;
+ ram[2528] = 8'h00; ram[2529] = 8'h00; ram[2530] = 8'h00; ram[2531] = 8'h00;
+ ram[2532] = 8'h00; ram[2533] = 8'h00; ram[2534] = 8'h00; ram[2535] = 8'h00;
+ ram[2536] = 8'h00; ram[2537] = 8'h00; ram[2538] = 8'h00; ram[2539] = 8'h00;
+ ram[2540] = 8'h00; ram[2541] = 8'h00; ram[2542] = 8'h00; ram[2543] = 8'h00;
+ ram[2544] = 8'h00; ram[2545] = 8'h00; ram[2546] = 8'h00; ram[2547] = 8'h00;
+ ram[2548] = 8'h00; ram[2549] = 8'h00; ram[2550] = 8'h00; ram[2551] = 8'h00;
+ ram[2552] = 8'h00; ram[2553] = 8'h00; ram[2554] = 8'h00; ram[2555] = 8'h00;
+ ram[2556] = 8'h00; ram[2557] = 8'h00; ram[2558] = 8'h00; ram[2559] = 8'h00;
+ ram[2560] = 8'h00; ram[2561] = 8'h00; ram[2562] = 8'h00; ram[2563] = 8'h00;
+ ram[2564] = 8'h00; ram[2565] = 8'h00; ram[2566] = 8'h00; ram[2567] = 8'h00;
+ ram[2568] = 8'h00; ram[2569] = 8'h00; ram[2570] = 8'h00; ram[2571] = 8'h00;
+ ram[2572] = 8'h00; ram[2573] = 8'h00; ram[2574] = 8'h00; ram[2575] = 8'h00;
+ ram[2576] = 8'h00; ram[2577] = 8'h00; ram[2578] = 8'h00; ram[2579] = 8'h00;
+ ram[2580] = 8'h00; ram[2581] = 8'h00; ram[2582] = 8'h00; ram[2583] = 8'h00;
+ ram[2584] = 8'h00; ram[2585] = 8'h00; ram[2586] = 8'h00; ram[2587] = 8'h00;
+ ram[2588] = 8'h00; ram[2589] = 8'h00; ram[2590] = 8'h00; ram[2591] = 8'h00;
+ ram[2592] = 8'h00; ram[2593] = 8'h00; ram[2594] = 8'h00; ram[2595] = 8'h00;
+ ram[2596] = 8'h00; ram[2597] = 8'h00; ram[2598] = 8'h00; ram[2599] = 8'h00;
+ ram[2600] = 8'h00; ram[2601] = 8'h00; ram[2602] = 8'h00; ram[2603] = 8'h00;
+ ram[2604] = 8'h00; ram[2605] = 8'h00; ram[2606] = 8'h00; ram[2607] = 8'h00;
+ ram[2608] = 8'h00; ram[2609] = 8'h00; ram[2610] = 8'h00; ram[2611] = 8'h00;
+ ram[2612] = 8'h00; ram[2613] = 8'h00; ram[2614] = 8'h00; ram[2615] = 8'h00;
+ ram[2616] = 8'h00; ram[2617] = 8'h00; ram[2618] = 8'h00; ram[2619] = 8'h00;
+ ram[2620] = 8'h00; ram[2621] = 8'h00; ram[2622] = 8'h00; ram[2623] = 8'h00;
+ ram[2624] = 8'h00; ram[2625] = 8'h00; ram[2626] = 8'h00; ram[2627] = 8'h00;
+ ram[2628] = 8'h00; ram[2629] = 8'h00; ram[2630] = 8'h00; ram[2631] = 8'h00;
+ ram[2632] = 8'h00; ram[2633] = 8'h00; ram[2634] = 8'h00; ram[2635] = 8'h00;
+ ram[2636] = 8'h00; ram[2637] = 8'h00; ram[2638] = 8'h00; ram[2639] = 8'h00;
+ ram[2640] = 8'h00; ram[2641] = 8'h00; ram[2642] = 8'h00; ram[2643] = 8'h00;
+ ram[2644] = 8'h00; ram[2645] = 8'h00; ram[2646] = 8'h00; ram[2647] = 8'h00;
+ ram[2648] = 8'h00; ram[2649] = 8'h00; ram[2650] = 8'h00; ram[2651] = 8'h00;
+ ram[2652] = 8'h00; ram[2653] = 8'h00; ram[2654] = 8'h00; ram[2655] = 8'h00;
+ ram[2656] = 8'h00; ram[2657] = 8'h00; ram[2658] = 8'h00; ram[2659] = 8'h00;
+ ram[2660] = 8'h00; ram[2661] = 8'h00; ram[2662] = 8'h00; ram[2663] = 8'h00;
+ ram[2664] = 8'h00; ram[2665] = 8'h00; ram[2666] = 8'h00; ram[2667] = 8'h00;
+ ram[2668] = 8'h00; ram[2669] = 8'h00; ram[2670] = 8'h00; ram[2671] = 8'h00;
+ ram[2672] = 8'h00; ram[2673] = 8'h00; ram[2674] = 8'h00; ram[2675] = 8'h00;
+ ram[2676] = 8'h00; ram[2677] = 8'h00; ram[2678] = 8'h00; ram[2679] = 8'h00;
+ ram[2680] = 8'h00; ram[2681] = 8'h00; ram[2682] = 8'h00; ram[2683] = 8'h00;
+ ram[2684] = 8'h00; ram[2685] = 8'h00; ram[2686] = 8'h00; ram[2687] = 8'h00;
+ ram[2688] = 8'h00; ram[2689] = 8'h00; ram[2690] = 8'h00; ram[2691] = 8'h00;
+ ram[2692] = 8'h00; ram[2693] = 8'h00; ram[2694] = 8'h00; ram[2695] = 8'h00;
+ ram[2696] = 8'h00; ram[2697] = 8'h00; ram[2698] = 8'h00; ram[2699] = 8'h00;
+ ram[2700] = 8'h00; ram[2701] = 8'h00; ram[2702] = 8'h00; ram[2703] = 8'h00;
+ ram[2704] = 8'h00; ram[2705] = 8'h00; ram[2706] = 8'h00; ram[2707] = 8'h00;
+ ram[2708] = 8'h00; ram[2709] = 8'h00; ram[2710] = 8'h00; ram[2711] = 8'h00;
+ ram[2712] = 8'h00; ram[2713] = 8'h00; ram[2714] = 8'h00; ram[2715] = 8'h00;
+ ram[2716] = 8'h00; ram[2717] = 8'h00; ram[2718] = 8'h00; ram[2719] = 8'h00;
+ ram[2720] = 8'h00; ram[2721] = 8'h00; ram[2722] = 8'h00; ram[2723] = 8'h00;
+ ram[2724] = 8'h00; ram[2725] = 8'h00; ram[2726] = 8'h00; ram[2727] = 8'h00;
+ ram[2728] = 8'h00; ram[2729] = 8'h00; ram[2730] = 8'h00; ram[2731] = 8'h00;
+ ram[2732] = 8'h00; ram[2733] = 8'h00; ram[2734] = 8'h00; ram[2735] = 8'h00;
+ ram[2736] = 8'h00; ram[2737] = 8'h00; ram[2738] = 8'h00; ram[2739] = 8'h00;
+ ram[2740] = 8'h00; ram[2741] = 8'h00; ram[2742] = 8'h00; ram[2743] = 8'h00;
+ ram[2744] = 8'h00; ram[2745] = 8'h00; ram[2746] = 8'h00; ram[2747] = 8'h00;
+ ram[2748] = 8'h00; ram[2749] = 8'h00; ram[2750] = 8'h00; ram[2751] = 8'h00;
+ ram[2752] = 8'h00; ram[2753] = 8'h00; ram[2754] = 8'h00; ram[2755] = 8'h00;
+ ram[2756] = 8'h00; ram[2757] = 8'h00; ram[2758] = 8'h00; ram[2759] = 8'h00;
+ ram[2760] = 8'h00; ram[2761] = 8'h00; ram[2762] = 8'h00; ram[2763] = 8'h00;
+ ram[2764] = 8'h00; ram[2765] = 8'h00; ram[2766] = 8'h00; ram[2767] = 8'h00;
+ ram[2768] = 8'h00; ram[2769] = 8'h00; ram[2770] = 8'h00; ram[2771] = 8'h00;
+ ram[2772] = 8'h00; ram[2773] = 8'h00; ram[2774] = 8'h00; ram[2775] = 8'h00;
+ ram[2776] = 8'h00; ram[2777] = 8'h00; ram[2778] = 8'h00; ram[2779] = 8'h00;
+ ram[2780] = 8'h00; ram[2781] = 8'h00; ram[2782] = 8'h00; ram[2783] = 8'h00;
+ ram[2784] = 8'h00; ram[2785] = 8'h00; ram[2786] = 8'h00; ram[2787] = 8'h00;
+ ram[2788] = 8'h00; ram[2789] = 8'h00; ram[2790] = 8'h00; ram[2791] = 8'h00;
+ ram[2792] = 8'h00; ram[2793] = 8'h00; ram[2794] = 8'h00; ram[2795] = 8'h00;
+ ram[2796] = 8'h00; ram[2797] = 8'h00; ram[2798] = 8'h00; ram[2799] = 8'h00;
+ ram[2800] = 8'h00; ram[2801] = 8'h00; ram[2802] = 8'h00; ram[2803] = 8'h00;
+ ram[2804] = 8'h00; ram[2805] = 8'h00; ram[2806] = 8'h00; ram[2807] = 8'h00;
+ ram[2808] = 8'h00; ram[2809] = 8'h00; ram[2810] = 8'h00; ram[2811] = 8'h00;
+ ram[2812] = 8'h00; ram[2813] = 8'h00; ram[2814] = 8'h00; ram[2815] = 8'h00;
+ ram[2816] = 8'h00; ram[2817] = 8'h00; ram[2818] = 8'h00; ram[2819] = 8'h00;
+ ram[2820] = 8'h00; ram[2821] = 8'h00; ram[2822] = 8'h00; ram[2823] = 8'h00;
+ ram[2824] = 8'h00; ram[2825] = 8'h00; ram[2826] = 8'h00; ram[2827] = 8'h00;
+ ram[2828] = 8'h00; ram[2829] = 8'h00; ram[2830] = 8'h00; ram[2831] = 8'h00;
+ ram[2832] = 8'h00; ram[2833] = 8'h00; ram[2834] = 8'h00; ram[2835] = 8'h00;
+ ram[2836] = 8'h00; ram[2837] = 8'h00; ram[2838] = 8'h00; ram[2839] = 8'h00;
+ ram[2840] = 8'h00; ram[2841] = 8'h00; ram[2842] = 8'h00; ram[2843] = 8'h00;
+ ram[2844] = 8'h00; ram[2845] = 8'h00; ram[2846] = 8'h00; ram[2847] = 8'h00;
+ ram[2848] = 8'h00; ram[2849] = 8'h00; ram[2850] = 8'h00; ram[2851] = 8'h00;
+ ram[2852] = 8'h00; ram[2853] = 8'h00; ram[2854] = 8'h00; ram[2855] = 8'h00;
+ ram[2856] = 8'h00; ram[2857] = 8'h00; ram[2858] = 8'h00; ram[2859] = 8'h00;
+ ram[2860] = 8'h00; ram[2861] = 8'h00; ram[2862] = 8'h00; ram[2863] = 8'h00;
+ ram[2864] = 8'h00; ram[2865] = 8'h00; ram[2866] = 8'h00; ram[2867] = 8'h00;
+ ram[2868] = 8'h00; ram[2869] = 8'h00; ram[2870] = 8'h00; ram[2871] = 8'h00;
+ ram[2872] = 8'h00; ram[2873] = 8'h00; ram[2874] = 8'h00; ram[2875] = 8'h00;
+ ram[2876] = 8'h00; ram[2877] = 8'h00; ram[2878] = 8'h00; ram[2879] = 8'h00;
+ ram[2880] = 8'h00; ram[2881] = 8'h00; ram[2882] = 8'h00; ram[2883] = 8'h00;
+ ram[2884] = 8'h00; ram[2885] = 8'h00; ram[2886] = 8'h00; ram[2887] = 8'h00;
+ ram[2888] = 8'h00; ram[2889] = 8'h00; ram[2890] = 8'h00; ram[2891] = 8'h00;
+ ram[2892] = 8'h00; ram[2893] = 8'h00; ram[2894] = 8'h00; ram[2895] = 8'h00;
+ ram[2896] = 8'h00; ram[2897] = 8'h00; ram[2898] = 8'h00; ram[2899] = 8'h00;
+ ram[2900] = 8'h00; ram[2901] = 8'h00; ram[2902] = 8'h00; ram[2903] = 8'h00;
+ ram[2904] = 8'h00; ram[2905] = 8'h00; ram[2906] = 8'h00; ram[2907] = 8'h00;
+ ram[2908] = 8'h00; ram[2909] = 8'h00; ram[2910] = 8'h00; ram[2911] = 8'h00;
+ ram[2912] = 8'h00; ram[2913] = 8'h00; ram[2914] = 8'h00; ram[2915] = 8'h00;
+ ram[2916] = 8'h00; ram[2917] = 8'h00; ram[2918] = 8'h00; ram[2919] = 8'h00;
+ ram[2920] = 8'h00; ram[2921] = 8'h00; ram[2922] = 8'h00; ram[2923] = 8'h00;
+ ram[2924] = 8'h00; ram[2925] = 8'h00; ram[2926] = 8'h00; ram[2927] = 8'h00;
+ ram[2928] = 8'h00; ram[2929] = 8'h00; ram[2930] = 8'h00; ram[2931] = 8'h00;
+ ram[2932] = 8'h00; ram[2933] = 8'h00; ram[2934] = 8'h00; ram[2935] = 8'h00;
+ ram[2936] = 8'h00; ram[2937] = 8'h00; ram[2938] = 8'h00; ram[2939] = 8'h00;
+ ram[2940] = 8'h00; ram[2941] = 8'h00; ram[2942] = 8'h00; ram[2943] = 8'h00;
+ ram[2944] = 8'h00; ram[2945] = 8'h00; ram[2946] = 8'h00; ram[2947] = 8'h00;
+ ram[2948] = 8'h00; ram[2949] = 8'h00; ram[2950] = 8'h00; ram[2951] = 8'h00;
+ ram[2952] = 8'h00; ram[2953] = 8'h00; ram[2954] = 8'h00; ram[2955] = 8'h00;
+ ram[2956] = 8'h00; ram[2957] = 8'h00; ram[2958] = 8'h00; ram[2959] = 8'h00;
+ ram[2960] = 8'h00; ram[2961] = 8'h00; ram[2962] = 8'h00; ram[2963] = 8'h00;
+ ram[2964] = 8'h00; ram[2965] = 8'h00; ram[2966] = 8'h00; ram[2967] = 8'h00;
+ ram[2968] = 8'h00; ram[2969] = 8'h00; ram[2970] = 8'h00; ram[2971] = 8'h00;
+ ram[2972] = 8'h00; ram[2973] = 8'h00; ram[2974] = 8'h00; ram[2975] = 8'h00;
+ ram[2976] = 8'h00; ram[2977] = 8'h00; ram[2978] = 8'h00; ram[2979] = 8'h00;
+ ram[2980] = 8'h00; ram[2981] = 8'h00; ram[2982] = 8'h00; ram[2983] = 8'h00;
+ ram[2984] = 8'h00; ram[2985] = 8'h00; ram[2986] = 8'h00; ram[2987] = 8'h00;
+ ram[2988] = 8'h00; ram[2989] = 8'h00; ram[2990] = 8'h00; ram[2991] = 8'h00;
+ ram[2992] = 8'h00; ram[2993] = 8'h00; ram[2994] = 8'h00; ram[2995] = 8'h00;
+ ram[2996] = 8'h00; ram[2997] = 8'h00; ram[2998] = 8'h00; ram[2999] = 8'h00;
+ ram[3000] = 8'h00; ram[3001] = 8'h00; ram[3002] = 8'h00; ram[3003] = 8'h00;
+ ram[3004] = 8'h00; ram[3005] = 8'h00; ram[3006] = 8'h00; ram[3007] = 8'h00;
+ ram[3008] = 8'h00; ram[3009] = 8'h00; ram[3010] = 8'h00; ram[3011] = 8'h00;
+ ram[3012] = 8'h00; ram[3013] = 8'h00; ram[3014] = 8'h00; ram[3015] = 8'h00;
+ ram[3016] = 8'h00; ram[3017] = 8'h00; ram[3018] = 8'h00; ram[3019] = 8'h00;
+ ram[3020] = 8'h00; ram[3021] = 8'h00; ram[3022] = 8'h00; ram[3023] = 8'h00;
+ ram[3024] = 8'h00; ram[3025] = 8'h00; ram[3026] = 8'h00; ram[3027] = 8'h00;
+ ram[3028] = 8'h00; ram[3029] = 8'h00; ram[3030] = 8'h00; ram[3031] = 8'h00;
+ ram[3032] = 8'h00; ram[3033] = 8'h00; ram[3034] = 8'h00; ram[3035] = 8'h00;
+ ram[3036] = 8'h00; ram[3037] = 8'h00; ram[3038] = 8'h00; ram[3039] = 8'h00;
+ ram[3040] = 8'h00; ram[3041] = 8'h00; ram[3042] = 8'h00; ram[3043] = 8'h00;
+ ram[3044] = 8'h00; ram[3045] = 8'h00; ram[3046] = 8'h00; ram[3047] = 8'h00;
+ ram[3048] = 8'h00; ram[3049] = 8'h00; ram[3050] = 8'h00; ram[3051] = 8'h00;
+ ram[3052] = 8'h00; ram[3053] = 8'h00; ram[3054] = 8'h00; ram[3055] = 8'h00;
+ ram[3056] = 8'h00; ram[3057] = 8'h00; ram[3058] = 8'h00; ram[3059] = 8'h00;
+ ram[3060] = 8'h00; ram[3061] = 8'h00; ram[3062] = 8'h00; ram[3063] = 8'h00;
+ ram[3064] = 8'h00; ram[3065] = 8'h00; ram[3066] = 8'h00; ram[3067] = 8'h00;
+ ram[3068] = 8'h00; ram[3069] = 8'h00; ram[3070] = 8'h00; ram[3071] = 8'h00;
+ ram[3072] = 8'h00; ram[3073] = 8'h00; ram[3074] = 8'h00; ram[3075] = 8'h00;
+ ram[3076] = 8'h00; ram[3077] = 8'h00; ram[3078] = 8'h00; ram[3079] = 8'h00;
+ ram[3080] = 8'h00; ram[3081] = 8'h00; ram[3082] = 8'h00; ram[3083] = 8'h00;
+ ram[3084] = 8'h00; ram[3085] = 8'h00; ram[3086] = 8'h00; ram[3087] = 8'h00;
+ ram[3088] = 8'h00; ram[3089] = 8'h00; ram[3090] = 8'h00; ram[3091] = 8'h00;
+ ram[3092] = 8'h00; ram[3093] = 8'h00; ram[3094] = 8'h00; ram[3095] = 8'h00;
+ ram[3096] = 8'h00; ram[3097] = 8'h00; ram[3098] = 8'h00; ram[3099] = 8'h00;
+ ram[3100] = 8'h00; ram[3101] = 8'h00; ram[3102] = 8'h00; ram[3103] = 8'h00;
+ ram[3104] = 8'h00; ram[3105] = 8'h00; ram[3106] = 8'h00; ram[3107] = 8'h00;
+ ram[3108] = 8'h00; ram[3109] = 8'h00; ram[3110] = 8'h00; ram[3111] = 8'h00;
+ ram[3112] = 8'h00; ram[3113] = 8'h00; ram[3114] = 8'h00; ram[3115] = 8'h00;
+ ram[3116] = 8'h00; ram[3117] = 8'h00; ram[3118] = 8'h00; ram[3119] = 8'h00;
+ ram[3120] = 8'h00; ram[3121] = 8'h00; ram[3122] = 8'h00; ram[3123] = 8'h00;
+ ram[3124] = 8'h00; ram[3125] = 8'h00; ram[3126] = 8'h00; ram[3127] = 8'h00;
+ ram[3128] = 8'h00; ram[3129] = 8'h00; ram[3130] = 8'h00; ram[3131] = 8'h00;
+ ram[3132] = 8'h00; ram[3133] = 8'h00; ram[3134] = 8'h00; ram[3135] = 8'h00;
+ ram[3136] = 8'h00; ram[3137] = 8'h00; ram[3138] = 8'h00; ram[3139] = 8'h00;
+ ram[3140] = 8'h00; ram[3141] = 8'h00; ram[3142] = 8'h00; ram[3143] = 8'h00;
+ ram[3144] = 8'h00; ram[3145] = 8'h00; ram[3146] = 8'h00; ram[3147] = 8'h00;
+ ram[3148] = 8'h00; ram[3149] = 8'h00; ram[3150] = 8'h00; ram[3151] = 8'h00;
+ ram[3152] = 8'h00; ram[3153] = 8'h00; ram[3154] = 8'h00; ram[3155] = 8'h00;
+ ram[3156] = 8'h00; ram[3157] = 8'h00; ram[3158] = 8'h00; ram[3159] = 8'h00;
+ ram[3160] = 8'h00; ram[3161] = 8'h00; ram[3162] = 8'h00; ram[3163] = 8'h00;
+ ram[3164] = 8'h00; ram[3165] = 8'h00; ram[3166] = 8'h00; ram[3167] = 8'h00;
+ ram[3168] = 8'h00; ram[3169] = 8'h00; ram[3170] = 8'h00; ram[3171] = 8'h00;
+ ram[3172] = 8'h00; ram[3173] = 8'h00; ram[3174] = 8'h00; ram[3175] = 8'h00;
+ ram[3176] = 8'h00; ram[3177] = 8'h00; ram[3178] = 8'h00; ram[3179] = 8'h00;
+ ram[3180] = 8'h00; ram[3181] = 8'h00; ram[3182] = 8'h00; ram[3183] = 8'h00;
+ ram[3184] = 8'h00; ram[3185] = 8'h00; ram[3186] = 8'h00; ram[3187] = 8'h00;
+ ram[3188] = 8'h00; ram[3189] = 8'h00; ram[3190] = 8'h00; ram[3191] = 8'h00;
+ ram[3192] = 8'h00; ram[3193] = 8'h00; ram[3194] = 8'h00; ram[3195] = 8'h00;
+ ram[3196] = 8'h00; ram[3197] = 8'h00; ram[3198] = 8'h00; ram[3199] = 8'h00;
+ ram[3200] = 8'h00; ram[3201] = 8'h00; ram[3202] = 8'h00; ram[3203] = 8'h00;
+ ram[3204] = 8'h00; ram[3205] = 8'h00; ram[3206] = 8'h00; ram[3207] = 8'h00;
+ ram[3208] = 8'h00; ram[3209] = 8'h00; ram[3210] = 8'h00; ram[3211] = 8'h00;
+ ram[3212] = 8'h00; ram[3213] = 8'h00; ram[3214] = 8'h00; ram[3215] = 8'h00;
+ ram[3216] = 8'h00; ram[3217] = 8'h00; ram[3218] = 8'h00; ram[3219] = 8'h00;
+ ram[3220] = 8'h00; ram[3221] = 8'h00; ram[3222] = 8'h00; ram[3223] = 8'h00;
+ ram[3224] = 8'h00; ram[3225] = 8'h00; ram[3226] = 8'h00; ram[3227] = 8'h00;
+ ram[3228] = 8'h00; ram[3229] = 8'h00; ram[3230] = 8'h00; ram[3231] = 8'h00;
+ ram[3232] = 8'h00; ram[3233] = 8'h00; ram[3234] = 8'h00; ram[3235] = 8'h00;
+ ram[3236] = 8'h00; ram[3237] = 8'h00; ram[3238] = 8'h00; ram[3239] = 8'h00;
+ ram[3240] = 8'h00; ram[3241] = 8'h00; ram[3242] = 8'h00; ram[3243] = 8'h00;
+ ram[3244] = 8'h00; ram[3245] = 8'h00; ram[3246] = 8'h00; ram[3247] = 8'h00;
+ ram[3248] = 8'h00; ram[3249] = 8'h00; ram[3250] = 8'h00; ram[3251] = 8'h00;
+ ram[3252] = 8'h00; ram[3253] = 8'h00; ram[3254] = 8'h00; ram[3255] = 8'h00;
+ ram[3256] = 8'h00; ram[3257] = 8'h00; ram[3258] = 8'h00; ram[3259] = 8'h00;
+ ram[3260] = 8'h00; ram[3261] = 8'h00; ram[3262] = 8'h00; ram[3263] = 8'h00;
+ ram[3264] = 8'h00; ram[3265] = 8'h00; ram[3266] = 8'h00; ram[3267] = 8'h00;
+ ram[3268] = 8'h00; ram[3269] = 8'h00; ram[3270] = 8'h00; ram[3271] = 8'h00;
+ ram[3272] = 8'h00; ram[3273] = 8'h00; ram[3274] = 8'h00; ram[3275] = 8'h00;
+ ram[3276] = 8'h00; ram[3277] = 8'h00; ram[3278] = 8'h00; ram[3279] = 8'h00;
+ ram[3280] = 8'h00; ram[3281] = 8'h00; ram[3282] = 8'h00; ram[3283] = 8'h00;
+ ram[3284] = 8'h00; ram[3285] = 8'h00; ram[3286] = 8'h00; ram[3287] = 8'h00;
+ ram[3288] = 8'h00; ram[3289] = 8'h00; ram[3290] = 8'h00; ram[3291] = 8'h00;
+ ram[3292] = 8'h00; ram[3293] = 8'h00; ram[3294] = 8'h00; ram[3295] = 8'h00;
+ ram[3296] = 8'h00; ram[3297] = 8'h00; ram[3298] = 8'h00; ram[3299] = 8'h00;
+ ram[3300] = 8'h00; ram[3301] = 8'h00; ram[3302] = 8'h00; ram[3303] = 8'h00;
+ ram[3304] = 8'h00; ram[3305] = 8'h00; ram[3306] = 8'h00; ram[3307] = 8'h00;
+ ram[3308] = 8'h00; ram[3309] = 8'h00; ram[3310] = 8'h00; ram[3311] = 8'h00;
+ ram[3312] = 8'h00; ram[3313] = 8'h00; ram[3314] = 8'h00; ram[3315] = 8'h00;
+ ram[3316] = 8'h00; ram[3317] = 8'h00; ram[3318] = 8'h00; ram[3319] = 8'h00;
+ ram[3320] = 8'h00; ram[3321] = 8'h00; ram[3322] = 8'h00; ram[3323] = 8'h00;
+ ram[3324] = 8'h00; ram[3325] = 8'h00; ram[3326] = 8'h00; ram[3327] = 8'h00;
+ ram[3328] = 8'h00; ram[3329] = 8'h00; ram[3330] = 8'h00; ram[3331] = 8'h00;
+ ram[3332] = 8'h00; ram[3333] = 8'h00; ram[3334] = 8'h00; ram[3335] = 8'h00;
+ ram[3336] = 8'h00; ram[3337] = 8'h00; ram[3338] = 8'h00; ram[3339] = 8'h00;
+ ram[3340] = 8'h00; ram[3341] = 8'h00; ram[3342] = 8'h00; ram[3343] = 8'h00;
+ ram[3344] = 8'h00; ram[3345] = 8'h00; ram[3346] = 8'h00; ram[3347] = 8'h00;
+ ram[3348] = 8'h00; ram[3349] = 8'h00; ram[3350] = 8'h00; ram[3351] = 8'h00;
+ ram[3352] = 8'h00; ram[3353] = 8'h00; ram[3354] = 8'h00; ram[3355] = 8'h00;
+ ram[3356] = 8'h00; ram[3357] = 8'h00; ram[3358] = 8'h00; ram[3359] = 8'h00;
+ ram[3360] = 8'h00; ram[3361] = 8'h00; ram[3362] = 8'h00; ram[3363] = 8'h00;
+ ram[3364] = 8'h00; ram[3365] = 8'h00; ram[3366] = 8'h00; ram[3367] = 8'h00;
+ ram[3368] = 8'h00; ram[3369] = 8'h00; ram[3370] = 8'h00; ram[3371] = 8'h00;
+ ram[3372] = 8'h00; ram[3373] = 8'h00; ram[3374] = 8'h00; ram[3375] = 8'h00;
+ ram[3376] = 8'h00; ram[3377] = 8'h00; ram[3378] = 8'h00; ram[3379] = 8'h00;
+ ram[3380] = 8'h00; ram[3381] = 8'h00; ram[3382] = 8'h00; ram[3383] = 8'h00;
+ ram[3384] = 8'h00; ram[3385] = 8'h00; ram[3386] = 8'h00; ram[3387] = 8'h00;
+ ram[3388] = 8'h00; ram[3389] = 8'h00; ram[3390] = 8'h00; ram[3391] = 8'h00;
+ ram[3392] = 8'h00; ram[3393] = 8'h00; ram[3394] = 8'h00; ram[3395] = 8'h00;
+ ram[3396] = 8'h00; ram[3397] = 8'h00; ram[3398] = 8'h00; ram[3399] = 8'h00;
+ ram[3400] = 8'h00; ram[3401] = 8'h00; ram[3402] = 8'h00; ram[3403] = 8'h00;
+ ram[3404] = 8'h00; ram[3405] = 8'h00; ram[3406] = 8'h00; ram[3407] = 8'h00;
+ ram[3408] = 8'h00; ram[3409] = 8'h00; ram[3410] = 8'h00; ram[3411] = 8'h00;
+ ram[3412] = 8'h00; ram[3413] = 8'h00; ram[3414] = 8'h00; ram[3415] = 8'h00;
+ ram[3416] = 8'h00; ram[3417] = 8'h00; ram[3418] = 8'h00; ram[3419] = 8'h00;
+ ram[3420] = 8'h00; ram[3421] = 8'h00; ram[3422] = 8'h00; ram[3423] = 8'h00;
+ ram[3424] = 8'h00; ram[3425] = 8'h00; ram[3426] = 8'h00; ram[3427] = 8'h00;
+ ram[3428] = 8'h00; ram[3429] = 8'h00; ram[3430] = 8'h00; ram[3431] = 8'h00;
+ ram[3432] = 8'h00; ram[3433] = 8'h00; ram[3434] = 8'h00; ram[3435] = 8'h00;
+ ram[3436] = 8'h00; ram[3437] = 8'h00; ram[3438] = 8'h00; ram[3439] = 8'h00;
+ ram[3440] = 8'h00; ram[3441] = 8'h00; ram[3442] = 8'h00; ram[3443] = 8'h00;
+ ram[3444] = 8'h00; ram[3445] = 8'h00; ram[3446] = 8'h00; ram[3447] = 8'h00;
+ ram[3448] = 8'h00; ram[3449] = 8'h00; ram[3450] = 8'h00; ram[3451] = 8'h00;
+ ram[3452] = 8'h00; ram[3453] = 8'h00; ram[3454] = 8'h00; ram[3455] = 8'h00;
+ ram[3456] = 8'h00; ram[3457] = 8'h00; ram[3458] = 8'h00; ram[3459] = 8'h00;
+ ram[3460] = 8'h00; ram[3461] = 8'h00; ram[3462] = 8'h00; ram[3463] = 8'h00;
+ ram[3464] = 8'h00; ram[3465] = 8'h00; ram[3466] = 8'h00; ram[3467] = 8'h00;
+ ram[3468] = 8'h00; ram[3469] = 8'h00; ram[3470] = 8'h00; ram[3471] = 8'h00;
+ ram[3472] = 8'h00; ram[3473] = 8'h00; ram[3474] = 8'h00; ram[3475] = 8'h00;
+ ram[3476] = 8'h00; ram[3477] = 8'h00; ram[3478] = 8'h00; ram[3479] = 8'h00;
+ ram[3480] = 8'h00; ram[3481] = 8'h00; ram[3482] = 8'h00; ram[3483] = 8'h00;
+ ram[3484] = 8'h00; ram[3485] = 8'h00; ram[3486] = 8'h00; ram[3487] = 8'h00;
+ ram[3488] = 8'h00; ram[3489] = 8'h00; ram[3490] = 8'h00; ram[3491] = 8'h00;
+ ram[3492] = 8'h00; ram[3493] = 8'h00; ram[3494] = 8'h00; ram[3495] = 8'h00;
+ ram[3496] = 8'h00; ram[3497] = 8'h00; ram[3498] = 8'h00; ram[3499] = 8'h00;
+ ram[3500] = 8'h00; ram[3501] = 8'h00; ram[3502] = 8'h00; ram[3503] = 8'h00;
+ ram[3504] = 8'h00; ram[3505] = 8'h00; ram[3506] = 8'h00; ram[3507] = 8'h00;
+ ram[3508] = 8'h00; ram[3509] = 8'h00; ram[3510] = 8'h00; ram[3511] = 8'h00;
+ ram[3512] = 8'h00; ram[3513] = 8'h00; ram[3514] = 8'h00; ram[3515] = 8'h00;
+ ram[3516] = 8'h00; ram[3517] = 8'h00; ram[3518] = 8'h00; ram[3519] = 8'h00;
+ ram[3520] = 8'h00; ram[3521] = 8'h00; ram[3522] = 8'h00; ram[3523] = 8'h00;
+ ram[3524] = 8'h00; ram[3525] = 8'h00; ram[3526] = 8'h00; ram[3527] = 8'h00;
+ ram[3528] = 8'h00; ram[3529] = 8'h00; ram[3530] = 8'h00; ram[3531] = 8'h00;
+ ram[3532] = 8'h00; ram[3533] = 8'h00; ram[3534] = 8'h00; ram[3535] = 8'h00;
+ ram[3536] = 8'h00; ram[3537] = 8'h00; ram[3538] = 8'h00; ram[3539] = 8'h00;
+ ram[3540] = 8'h00; ram[3541] = 8'h00; ram[3542] = 8'h00; ram[3543] = 8'h00;
+ ram[3544] = 8'h00; ram[3545] = 8'h00; ram[3546] = 8'h00; ram[3547] = 8'h00;
+ ram[3548] = 8'h00; ram[3549] = 8'h00; ram[3550] = 8'h00; ram[3551] = 8'h00;
+ ram[3552] = 8'h00; ram[3553] = 8'h00; ram[3554] = 8'h00; ram[3555] = 8'h00;
+ ram[3556] = 8'h00; ram[3557] = 8'h00; ram[3558] = 8'h00; ram[3559] = 8'h00;
+ ram[3560] = 8'h00; ram[3561] = 8'h00; ram[3562] = 8'h00; ram[3563] = 8'h00;
+ ram[3564] = 8'h00; ram[3565] = 8'h00; ram[3566] = 8'h00; ram[3567] = 8'h00;
+ ram[3568] = 8'h00; ram[3569] = 8'h00; ram[3570] = 8'h00; ram[3571] = 8'h00;
+ ram[3572] = 8'h00; ram[3573] = 8'h00; ram[3574] = 8'h00; ram[3575] = 8'h00;
+ ram[3576] = 8'h00; ram[3577] = 8'h00; ram[3578] = 8'h00; ram[3579] = 8'h00;
+ ram[3580] = 8'h00; ram[3581] = 8'h00; ram[3582] = 8'h00; ram[3583] = 8'h00;
+ ram[3584] = 8'h00; ram[3585] = 8'h00; ram[3586] = 8'h00; ram[3587] = 8'h00;
+ ram[3588] = 8'h00; ram[3589] = 8'h00; ram[3590] = 8'h00; ram[3591] = 8'h00;
+ ram[3592] = 8'h00; ram[3593] = 8'h00; ram[3594] = 8'h00; ram[3595] = 8'h00;
+ ram[3596] = 8'h00; ram[3597] = 8'h00; ram[3598] = 8'h00; ram[3599] = 8'h00;
+ ram[3600] = 8'h00; ram[3601] = 8'h00; ram[3602] = 8'h00; ram[3603] = 8'h00;
+ ram[3604] = 8'h00; ram[3605] = 8'h00; ram[3606] = 8'h00; ram[3607] = 8'h00;
+ ram[3608] = 8'h00; ram[3609] = 8'h00; ram[3610] = 8'h00; ram[3611] = 8'h00;
+ ram[3612] = 8'h00; ram[3613] = 8'h00; ram[3614] = 8'h00; ram[3615] = 8'h00;
+ ram[3616] = 8'h00; ram[3617] = 8'h00; ram[3618] = 8'h00; ram[3619] = 8'h00;
+ ram[3620] = 8'h00; ram[3621] = 8'h00; ram[3622] = 8'h00; ram[3623] = 8'h00;
+ ram[3624] = 8'h00; ram[3625] = 8'h00; ram[3626] = 8'h00; ram[3627] = 8'h00;
+ ram[3628] = 8'h00; ram[3629] = 8'h00; ram[3630] = 8'h00; ram[3631] = 8'h00;
+ ram[3632] = 8'h00; ram[3633] = 8'h00; ram[3634] = 8'h00; ram[3635] = 8'h00;
+ ram[3636] = 8'h00; ram[3637] = 8'h00; ram[3638] = 8'h00; ram[3639] = 8'h00;
+ ram[3640] = 8'h00; ram[3641] = 8'h00; ram[3642] = 8'h00; ram[3643] = 8'h00;
+ ram[3644] = 8'h00; ram[3645] = 8'h00; ram[3646] = 8'h00; ram[3647] = 8'h00;
+ ram[3648] = 8'h00; ram[3649] = 8'h00; ram[3650] = 8'h00; ram[3651] = 8'h00;
+ ram[3652] = 8'h00; ram[3653] = 8'h00; ram[3654] = 8'h00; ram[3655] = 8'h00;
+ ram[3656] = 8'h00; ram[3657] = 8'h00; ram[3658] = 8'h00; ram[3659] = 8'h00;
+ ram[3660] = 8'h00; ram[3661] = 8'h00; ram[3662] = 8'h00; ram[3663] = 8'h00;
+ ram[3664] = 8'h00; ram[3665] = 8'h00; ram[3666] = 8'h00; ram[3667] = 8'h00;
+ ram[3668] = 8'h00; ram[3669] = 8'h00; ram[3670] = 8'h00; ram[3671] = 8'h00;
+ ram[3672] = 8'h00; ram[3673] = 8'h00; ram[3674] = 8'h00; ram[3675] = 8'h00;
+ ram[3676] = 8'h00; ram[3677] = 8'h00; ram[3678] = 8'h00; ram[3679] = 8'h00;
+ ram[3680] = 8'h00; ram[3681] = 8'h00; ram[3682] = 8'h00; ram[3683] = 8'h00;
+ ram[3684] = 8'h00; ram[3685] = 8'h00; ram[3686] = 8'h00; ram[3687] = 8'h00;
+ ram[3688] = 8'h00; ram[3689] = 8'h00; ram[3690] = 8'h00; ram[3691] = 8'h00;
+ ram[3692] = 8'h00; ram[3693] = 8'h00; ram[3694] = 8'h00; ram[3695] = 8'h00;
+ ram[3696] = 8'h00; ram[3697] = 8'h00; ram[3698] = 8'h00; ram[3699] = 8'h00;
+ ram[3700] = 8'h00; ram[3701] = 8'h00; ram[3702] = 8'h00; ram[3703] = 8'h00;
+ ram[3704] = 8'h00; ram[3705] = 8'h00; ram[3706] = 8'h00; ram[3707] = 8'h00;
+ ram[3708] = 8'h00; ram[3709] = 8'h00; ram[3710] = 8'h00; ram[3711] = 8'h00;
+ ram[3712] = 8'h00; ram[3713] = 8'h00; ram[3714] = 8'h00; ram[3715] = 8'h00;
+ ram[3716] = 8'h00; ram[3717] = 8'h00; ram[3718] = 8'h00; ram[3719] = 8'h00;
+ ram[3720] = 8'h00; ram[3721] = 8'h00; ram[3722] = 8'h00; ram[3723] = 8'h00;
+ ram[3724] = 8'h00; ram[3725] = 8'h00; ram[3726] = 8'h00; ram[3727] = 8'h00;
+ ram[3728] = 8'h00; ram[3729] = 8'h00; ram[3730] = 8'h00; ram[3731] = 8'h00;
+ ram[3732] = 8'h00; ram[3733] = 8'h00; ram[3734] = 8'h00; ram[3735] = 8'h00;
+ ram[3736] = 8'h00; ram[3737] = 8'h00; ram[3738] = 8'h00; ram[3739] = 8'h00;
+ ram[3740] = 8'h00; ram[3741] = 8'h00; ram[3742] = 8'h00; ram[3743] = 8'h00;
+ ram[3744] = 8'h00; ram[3745] = 8'h00; ram[3746] = 8'h00; ram[3747] = 8'h00;
+ ram[3748] = 8'h00; ram[3749] = 8'h00; ram[3750] = 8'h00; ram[3751] = 8'h00;
+ ram[3752] = 8'h00; ram[3753] = 8'h00; ram[3754] = 8'h00; ram[3755] = 8'h00;
+ ram[3756] = 8'h00; ram[3757] = 8'h00; ram[3758] = 8'h00; ram[3759] = 8'h00;
+ ram[3760] = 8'h00; ram[3761] = 8'h00; ram[3762] = 8'h00; ram[3763] = 8'h00;
+ ram[3764] = 8'h00; ram[3765] = 8'h00; ram[3766] = 8'h00; ram[3767] = 8'h00;
+ ram[3768] = 8'h00; ram[3769] = 8'h00; ram[3770] = 8'h00; ram[3771] = 8'h00;
+ ram[3772] = 8'h00; ram[3773] = 8'h00; ram[3774] = 8'h00; ram[3775] = 8'h00;
+ ram[3776] = 8'h00; ram[3777] = 8'h00; ram[3778] = 8'h00; ram[3779] = 8'h00;
+ ram[3780] = 8'h00; ram[3781] = 8'h00; ram[3782] = 8'h00; ram[3783] = 8'h00;
+ ram[3784] = 8'h00; ram[3785] = 8'h00; ram[3786] = 8'h00; ram[3787] = 8'h00;
+ ram[3788] = 8'h00; ram[3789] = 8'h00; ram[3790] = 8'h00; ram[3791] = 8'h00;
+ ram[3792] = 8'h00; ram[3793] = 8'h00; ram[3794] = 8'h00; ram[3795] = 8'h00;
+ ram[3796] = 8'h00; ram[3797] = 8'h00; ram[3798] = 8'h00; ram[3799] = 8'h00;
+ ram[3800] = 8'h00; ram[3801] = 8'h00; ram[3802] = 8'h00; ram[3803] = 8'h00;
+ ram[3804] = 8'h00; ram[3805] = 8'h00; ram[3806] = 8'h00; ram[3807] = 8'h00;
+ ram[3808] = 8'h00; ram[3809] = 8'h00; ram[3810] = 8'h00; ram[3811] = 8'h00;
+ ram[3812] = 8'h00; ram[3813] = 8'h00; ram[3814] = 8'h00; ram[3815] = 8'h00;
+ ram[3816] = 8'h00; ram[3817] = 8'h00; ram[3818] = 8'h00; ram[3819] = 8'h00;
+ ram[3820] = 8'h00; ram[3821] = 8'h00; ram[3822] = 8'h00; ram[3823] = 8'h00;
+ ram[3824] = 8'h00; ram[3825] = 8'h00; ram[3826] = 8'h00; ram[3827] = 8'h00;
+ ram[3828] = 8'h00; ram[3829] = 8'h00; ram[3830] = 8'h00; ram[3831] = 8'h00;
+ ram[3832] = 8'h00; ram[3833] = 8'h00; ram[3834] = 8'h00; ram[3835] = 8'h00;
+ ram[3836] = 8'h00; ram[3837] = 8'h00; ram[3838] = 8'h00; ram[3839] = 8'h00;
+ ram[3840] = 8'h00; ram[3841] = 8'h00; ram[3842] = 8'h00; ram[3843] = 8'h00;
+ ram[3844] = 8'h00; ram[3845] = 8'h00; ram[3846] = 8'h00; ram[3847] = 8'h00;
+ ram[3848] = 8'h00; ram[3849] = 8'h00; ram[3850] = 8'h00; ram[3851] = 8'h00;
+ ram[3852] = 8'h00; ram[3853] = 8'h00; ram[3854] = 8'h00; ram[3855] = 8'h00;
+ ram[3856] = 8'h00; ram[3857] = 8'h00; ram[3858] = 8'h00; ram[3859] = 8'h00;
+ ram[3860] = 8'h00; ram[3861] = 8'h00; ram[3862] = 8'h00; ram[3863] = 8'h00;
+ ram[3864] = 8'h00; ram[3865] = 8'h00; ram[3866] = 8'h00; ram[3867] = 8'h00;
+ ram[3868] = 8'h00; ram[3869] = 8'h00; ram[3870] = 8'h00; ram[3871] = 8'h00;
+ ram[3872] = 8'h00; ram[3873] = 8'h00; ram[3874] = 8'h00; ram[3875] = 8'h00;
+ ram[3876] = 8'h00; ram[3877] = 8'h00; ram[3878] = 8'h00; ram[3879] = 8'h00;
+ ram[3880] = 8'h00; ram[3881] = 8'h00; ram[3882] = 8'h00; ram[3883] = 8'h00;
+ ram[3884] = 8'h00; ram[3885] = 8'h00; ram[3886] = 8'h00; ram[3887] = 8'h00;
+ ram[3888] = 8'h00; ram[3889] = 8'h00; ram[3890] = 8'h00; ram[3891] = 8'h00;
+ ram[3892] = 8'h00; ram[3893] = 8'h00; ram[3894] = 8'h00; ram[3895] = 8'h00;
+ ram[3896] = 8'h00; ram[3897] = 8'h00; ram[3898] = 8'h00; ram[3899] = 8'h00;
+ ram[3900] = 8'h00; ram[3901] = 8'h00; ram[3902] = 8'h00; ram[3903] = 8'h00;
+ ram[3904] = 8'h00; ram[3905] = 8'h00; ram[3906] = 8'h00; ram[3907] = 8'h00;
+ ram[3908] = 8'h00; ram[3909] = 8'h00; ram[3910] = 8'h00; ram[3911] = 8'h00;
+ ram[3912] = 8'h00; ram[3913] = 8'h00; ram[3914] = 8'h00; ram[3915] = 8'h00;
+ ram[3916] = 8'h00; ram[3917] = 8'h00; ram[3918] = 8'h00; ram[3919] = 8'h00;
+ ram[3920] = 8'h00; ram[3921] = 8'h00; ram[3922] = 8'h00; ram[3923] = 8'h00;
+ ram[3924] = 8'h00; ram[3925] = 8'h00; ram[3926] = 8'h00; ram[3927] = 8'h00;
+ ram[3928] = 8'h00; ram[3929] = 8'h00; ram[3930] = 8'h00; ram[3931] = 8'h00;
+ ram[3932] = 8'h00; ram[3933] = 8'h00; ram[3934] = 8'h00; ram[3935] = 8'h00;
+ ram[3936] = 8'h00; ram[3937] = 8'h00; ram[3938] = 8'h00; ram[3939] = 8'h00;
+ ram[3940] = 8'h00; ram[3941] = 8'h00; ram[3942] = 8'h00; ram[3943] = 8'h00;
+ ram[3944] = 8'h00; ram[3945] = 8'h00; ram[3946] = 8'h00; ram[3947] = 8'h00;
+ ram[3948] = 8'h00; ram[3949] = 8'h00; ram[3950] = 8'h00; ram[3951] = 8'h00;
+ ram[3952] = 8'h00; ram[3953] = 8'h00; ram[3954] = 8'h00; ram[3955] = 8'h00;
+ ram[3956] = 8'h00; ram[3957] = 8'h00; ram[3958] = 8'h00; ram[3959] = 8'h00;
+ ram[3960] = 8'h00; ram[3961] = 8'h00; ram[3962] = 8'h00; ram[3963] = 8'h00;
+ ram[3964] = 8'h00; ram[3965] = 8'h00; ram[3966] = 8'h00; ram[3967] = 8'h00;
+ ram[3968] = 8'h00; ram[3969] = 8'h00; ram[3970] = 8'h00; ram[3971] = 8'h00;
+ ram[3972] = 8'h00; ram[3973] = 8'h00; ram[3974] = 8'h00; ram[3975] = 8'h00;
+ ram[3976] = 8'h00; ram[3977] = 8'h00; ram[3978] = 8'h00; ram[3979] = 8'h00;
+ ram[3980] = 8'h00; ram[3981] = 8'h00; ram[3982] = 8'h00; ram[3983] = 8'h00;
+ ram[3984] = 8'h00; ram[3985] = 8'h00; ram[3986] = 8'h00; ram[3987] = 8'h00;
+ ram[3988] = 8'h00; ram[3989] = 8'h00; ram[3990] = 8'h00; ram[3991] = 8'h00;
+ ram[3992] = 8'h00; ram[3993] = 8'h00; ram[3994] = 8'h00; ram[3995] = 8'h00;
+ ram[3996] = 8'h00; ram[3997] = 8'h00; ram[3998] = 8'h00; ram[3999] = 8'h00;
+ ram[4000] = 8'h00; ram[4001] = 8'h00; ram[4002] = 8'h00; ram[4003] = 8'h00;
+ ram[4004] = 8'h00; ram[4005] = 8'h00; ram[4006] = 8'h00; ram[4007] = 8'h00;
+ ram[4008] = 8'h00; ram[4009] = 8'h00; ram[4010] = 8'h00; ram[4011] = 8'h00;
+ ram[4012] = 8'h00; ram[4013] = 8'h00; ram[4014] = 8'h00; ram[4015] = 8'h00;
+ ram[4016] = 8'h00; ram[4017] = 8'h00; ram[4018] = 8'h00; ram[4019] = 8'h00;
+ ram[4020] = 8'h00; ram[4021] = 8'h00; ram[4022] = 8'h00; ram[4023] = 8'h00;
+ ram[4024] = 8'h00; ram[4025] = 8'h00; ram[4026] = 8'h00; ram[4027] = 8'h00;
+ ram[4028] = 8'h00; ram[4029] = 8'h00; ram[4030] = 8'h00; ram[4031] = 8'h00;
+ ram[4032] = 8'h00; ram[4033] = 8'h00; ram[4034] = 8'h00; ram[4035] = 8'h00;
+ ram[4036] = 8'h00; ram[4037] = 8'h00; ram[4038] = 8'h00; ram[4039] = 8'h00;
+ ram[4040] = 8'h00; ram[4041] = 8'h00; ram[4042] = 8'h00; ram[4043] = 8'h00;
+ ram[4044] = 8'h00; ram[4045] = 8'h00; ram[4046] = 8'h00; ram[4047] = 8'h00;
+ ram[4048] = 8'h00; ram[4049] = 8'h00; ram[4050] = 8'h00; ram[4051] = 8'h00;
+ ram[4052] = 8'h00; ram[4053] = 8'h00; ram[4054] = 8'h00; ram[4055] = 8'h00;
+ ram[4056] = 8'h00; ram[4057] = 8'h00; ram[4058] = 8'h00; ram[4059] = 8'h00;
+ ram[4060] = 8'h00; ram[4061] = 8'h00; ram[4062] = 8'h00; ram[4063] = 8'h00;
+ ram[4064] = 8'h00; ram[4065] = 8'h00; ram[4066] = 8'h00; ram[4067] = 8'h00;
+ ram[4068] = 8'h00; ram[4069] = 8'h00; ram[4070] = 8'h00; ram[4071] = 8'h00;
+ ram[4072] = 8'h00; ram[4073] = 8'h00; ram[4074] = 8'h00; ram[4075] = 8'h00;
+ ram[4076] = 8'h00; ram[4077] = 8'h00; ram[4078] = 8'h00; ram[4079] = 8'h00;
+ ram[4080] = 8'h00; ram[4081] = 8'h00; ram[4082] = 8'h00; ram[4083] = 8'h00;
+ ram[4084] = 8'h00; ram[4085] = 8'h00; ram[4086] = 8'h00; ram[4087] = 8'h00;
+ ram[4088] = 8'h00; ram[4089] = 8'h00; ram[4090] = 8'h00; ram[4091] = 8'h00;
+ ram[4092] = 8'h00; ram[4093] = 8'h00; ram[4094] = 8'h00; ram[4095] = 8'h00;
+end
+
+//-----------------------------------------------------------------------------
+always @(posedge clk)
+begin
+ if (we)
+ ram[addr] <= din;
+ dout <= ram[addr];
+end
+
+endmodule
+//-----------------------------------------------------------------------------
Index: trunk/verilog/rtl/micro_rom.v
===================================================================
--- trunk/verilog/rtl/micro_rom.v (nonexistent)
+++ trunk/verilog/rtl/micro_rom.v (revision 65)
@@ -0,0 +1,552 @@
+//---------------------------------------------------------------------------------------
+//
+// Project: light8080
+//
+// Filename: micro_rom.v (November 25, 2011)
+//
+//---------------------------------------------------------------------------------------
+
+module micro_rom
+(
+ clock,
+ uc_addr,
+ uc_dout
+);
+//---------------------------------------------------------------------------------------
+input clock; // global clock
+input [8:0] uc_addr; // micro code ROM address
+output [31:0] uc_dout; // micro code ROM data
+
+//---------------------------------------------------------------------------------------
+reg [31:0] uc_dat, uc_dout;
+
+//---------------------------------------------------------------------------------------
+// module implementation
+// microcode ROM : see design notes and microcode source file
+always @ (uc_addr)
+begin
+ case (uc_addr)
+ 9'h000: uc_dat <= 32'b00000000000000000000000000000000;
+ 9'h001: uc_dat <= 32'b00000000000001001000000001000100;
+ 9'h002: uc_dat <= 32'b00000000000001000000000001000100;
+ 9'h003: uc_dat <= 32'b10111101101001001000000001001101;
+ 9'h004: uc_dat <= 32'b10110110101001000000000001001101;
+ 9'h005: uc_dat <= 32'b00100000000000000000000000000000;
+ 9'h006: uc_dat <= 32'b00000000000000000000000000000000;
+ 9'h007: uc_dat <= 32'b11100100000000000000000000000000;
+ 9'h008: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h009: uc_dat <= 32'b00000100000100000000000001010111;
+ 9'h00a: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h00b: uc_dat <= 32'b00000100000100000000000001010111;
+ 9'h00c: uc_dat <= 32'b00000000101010000000000010010111;
+ 9'h00d: uc_dat <= 32'b00001000000000000000110000011100;
+ 9'h00e: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h00f: uc_dat <= 32'b00000100000100000000000001010111;
+ 9'h010: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h011: uc_dat <= 32'b00001000000000000000110000011100;
+ 9'h012: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h013: uc_dat <= 32'b00000000000110001000000001010111;
+ 9'h014: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h015: uc_dat <= 32'b00000100000110000000000001010111;
+ 9'h016: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h017: uc_dat <= 32'b00001000000000000000110000100010;
+ 9'h018: uc_dat <= 32'b00000100000000111000000001010111;
+ 9'h019: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h01a: uc_dat <= 32'b00000000101000111000000010010111;
+ 9'h01b: uc_dat <= 32'b00001000000000000000110000100101;
+ 9'h01c: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h01d: uc_dat <= 32'b10111101101001100000000001001101;
+ 9'h01e: uc_dat <= 32'b10110110101001101000000001001101;
+ 9'h01f: uc_dat <= 32'b00000000100000101000000001010111;
+ 9'h020: uc_dat <= 32'b00001000000000000000110000100010;
+ 9'h021: uc_dat <= 32'b00000100000000100000000001010111;
+ 9'h022: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h023: uc_dat <= 32'b00000000101000101000000010010111;
+ 9'h024: uc_dat <= 32'b10111101101001100000000001001101;
+ 9'h025: uc_dat <= 32'b10111010101001101000000001001101;
+ 9'h026: uc_dat <= 32'b00000000101000100000000010010111;
+ 9'h027: uc_dat <= 32'b00001000000000000000110000100101;
+ 9'h028: uc_dat <= 32'b00001000000000000000110000101000;
+ 9'h029: uc_dat <= 32'b00000100000000111000000001010111;
+ 9'h02a: uc_dat <= 32'b00000000101000111000000010010111;
+ 9'h02b: uc_dat <= 32'b00001000000000000000110000101011;
+ 9'h02c: uc_dat <= 32'b00000000101000010000000000000000;
+ 9'h02d: uc_dat <= 32'b00000000000001010000000001010111;
+ 9'h02e: uc_dat <= 32'b00000000101000011000000000000000;
+ 9'h02f: uc_dat <= 32'b00000000000001011000000001010111;
+ 9'h030: uc_dat <= 32'b00000000101000100000000000000000;
+ 9'h031: uc_dat <= 32'b00000000000000010000000001010111;
+ 9'h032: uc_dat <= 32'b00000000101000101000000000000000;
+ 9'h033: uc_dat <= 32'b00000000000000011000000001010111;
+ 9'h034: uc_dat <= 32'b00000000101001010000000000000000;
+ 9'h035: uc_dat <= 32'b00000000000000100000000001010111;
+ 9'h036: uc_dat <= 32'b00000000101001011000000000000000;
+ 9'h037: uc_dat <= 32'b00000100000000101000000001010111;
+ 9'h038: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h039: uc_dat <= 32'b00000100011000111000001101001100;
+ 9'h03a: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h03b: uc_dat <= 32'b00000100011000111000001101001101;
+ 9'h03c: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h03d: uc_dat <= 32'b00000100011000111000001101001110;
+ 9'h03e: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h03f: uc_dat <= 32'b00000100011000111000001101001111;
+ 9'h040: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h041: uc_dat <= 32'b00000100011000111100001101000100;
+ 9'h042: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h043: uc_dat <= 32'b00000100011000111100001101000101;
+ 9'h044: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h045: uc_dat <= 32'b00000100011000111100001101000110;
+ 9'h046: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h047: uc_dat <= 32'b00000100011000111000001110001110;
+ 9'h048: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h049: uc_dat <= 32'b00000100011000111000001101001100;
+ 9'h04a: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h04b: uc_dat <= 32'b00000100011000111000001101001101;
+ 9'h04c: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h04d: uc_dat <= 32'b00000100011000111000001101001110;
+ 9'h04e: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h04f: uc_dat <= 32'b00000100011000111000001101001111;
+ 9'h050: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h051: uc_dat <= 32'b00000100011000111100001101000100;
+ 9'h052: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h053: uc_dat <= 32'b00000100011000111100001101000101;
+ 9'h054: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h055: uc_dat <= 32'b00000100011000111100001101000110;
+ 9'h056: uc_dat <= 32'b00000000101010000000000000000000;
+ 9'h057: uc_dat <= 32'b00000100011000111000001110001110;
+ 9'h058: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h059: uc_dat <= 32'b00000100011000111000001101001100;
+ 9'h05a: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h05b: uc_dat <= 32'b00000100011000111000001101001101;
+ 9'h05c: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h05d: uc_dat <= 32'b00000100011000111000001101001110;
+ 9'h05e: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h05f: uc_dat <= 32'b00000100011000111000001101001111;
+ 9'h060: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h061: uc_dat <= 32'b00000100011000111100001101000100;
+ 9'h062: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h063: uc_dat <= 32'b00000100011000111100001101000101;
+ 9'h064: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h065: uc_dat <= 32'b00000100011000111100001101000110;
+ 9'h066: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h067: uc_dat <= 32'b00000100011000111000001110001110;
+ 9'h068: uc_dat <= 32'b10111100101100000000001001001101;
+ 9'h069: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h06a: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h06b: uc_dat <= 32'b10111100000000000000001010001101;
+ 9'h06c: uc_dat <= 32'b00001000000000000000110000011100;
+ 9'h06d: uc_dat <= 32'b10111100011100000000001001001111;
+ 9'h06e: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h06f: uc_dat <= 32'b00001000000000000000110000011001;
+ 9'h070: uc_dat <= 32'b11000000000000000000000000000000;
+ 9'h071: uc_dat <= 32'b10111100011001010000001010001111;
+ 9'h072: uc_dat <= 32'b00001000000000000000110000011100;
+ 9'h073: uc_dat <= 32'b10111100101110001000000001001101;
+ 9'h074: uc_dat <= 32'b10100100101110000000000001001101;
+ 9'h075: uc_dat <= 32'b10111100011110001000000001001111;
+ 9'h076: uc_dat <= 32'b10100100011110000000000001001111;
+ 9'h077: uc_dat <= 32'b00000000011110001000000000000000;
+ 9'h078: uc_dat <= 32'b00000000101000101000000101001100;
+ 9'h079: uc_dat <= 32'b00000000011110000000000000000000;
+ 9'h07a: uc_dat <= 32'b00000100101000100000000101001101;
+ 9'h07b: uc_dat <= 32'b00000000101000111000000010101000;
+ 9'h07c: uc_dat <= 32'b00000100101000111000001101101000;
+ 9'h07d: uc_dat <= 32'b00000100101000111000000101000000;
+ 9'h07e: uc_dat <= 32'b00000100101000111000000101000001;
+ 9'h07f: uc_dat <= 32'b00000100101000111000000101000010;
+ 9'h080: uc_dat <= 32'b00000100101000111000000101000011;
+ 9'h081: uc_dat <= 32'b00000100101000111000000001000111;
+ 9'h082: uc_dat <= 32'b00000100000000000000000100101100;
+ 9'h083: uc_dat <= 32'b00000100000000000000000100101101;
+ 9'h084: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h085: uc_dat <= 32'b00000000101001100000000000000000;
+ 9'h086: uc_dat <= 32'b00000000000001001000000001010111;
+ 9'h087: uc_dat <= 32'b00000000101001101000000000000000;
+ 9'h088: uc_dat <= 32'b00000100000001000000000001010111;
+ 9'h089: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h08a: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h08b: uc_dat <= 32'b00010000000000000000100000000101;
+ 9'h08c: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h08d: uc_dat <= 32'b11000000101001000000000010010111;
+ 9'h08e: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h08f: uc_dat <= 32'b11000000101001001000000010010111;
+ 9'h090: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h091: uc_dat <= 32'b00000000101001100000000000000000;
+ 9'h092: uc_dat <= 32'b00000000000001001000000001010111;
+ 9'h093: uc_dat <= 32'b00000000101001101000000000000000;
+ 9'h094: uc_dat <= 32'b00000100000001000000000001010111;
+ 9'h095: uc_dat <= 32'b00001000000000000000110000101110;
+ 9'h096: uc_dat <= 32'b00010000000000000000100000001101;
+ 9'h097: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h098: uc_dat <= 32'b00000000000001001000000001010111;
+ 9'h099: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h09a: uc_dat <= 32'b00000100000001000000000001010111;
+ 9'h09b: uc_dat <= 32'b00010000000000000000100000010111;
+ 9'h09c: uc_dat <= 32'b11000000101001000000000010010111;
+ 9'h09d: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h09e: uc_dat <= 32'b11000000101001001000000010010111;
+ 9'h09f: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0a0: uc_dat <= 32'b11000000000001001000000001011111;
+ 9'h0a1: uc_dat <= 32'b00000100000001000000000001000100;
+ 9'h0a2: uc_dat <= 32'b00000000101000101000000000000000;
+ 9'h0a3: uc_dat <= 32'b00000000000001001000000001010111;
+ 9'h0a4: uc_dat <= 32'b00000000101000100000000000000000;
+ 9'h0a5: uc_dat <= 32'b00000100000001000000000001010111;
+ 9'h0a6: uc_dat <= 32'b11000000101110000000000010010111;
+ 9'h0a7: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0a8: uc_dat <= 32'b11000000101110001000000010010111;
+ 9'h0a9: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0aa: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0ab: uc_dat <= 32'b11000000101000111000000010010111;
+ 9'h0ac: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0ad: uc_dat <= 32'b11000000000000000000000010110000;
+ 9'h0ae: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0af: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0b0: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0b1: uc_dat <= 32'b00000000000110001000000001010111;
+ 9'h0b2: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0b3: uc_dat <= 32'b00000100000110000000000001010111;
+ 9'h0b4: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0b5: uc_dat <= 32'b00000000000000110000001101010111;
+ 9'h0b6: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0b7: uc_dat <= 32'b00000100000000111000000001010111;
+ 9'h0b8: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0b9: uc_dat <= 32'b00000000000001100000000001010111;
+ 9'h0ba: uc_dat <= 32'b00001000000000000000110000111001;
+ 9'h0bb: uc_dat <= 32'b00000000000001101000000001010111;
+ 9'h0bc: uc_dat <= 32'b11000000101000100000000010010111;
+ 9'h0bd: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0be: uc_dat <= 32'b11000000101000101000000010010111;
+ 9'h0bf: uc_dat <= 32'b00001000000000000000110000110100;
+ 9'h0c0: uc_dat <= 32'b00000000101001100000000000000000;
+ 9'h0c1: uc_dat <= 32'b00000000000000101000000001010111;
+ 9'h0c2: uc_dat <= 32'b00000000101001101000000000000000;
+ 9'h0c3: uc_dat <= 32'b00000100000000100000000001010111;
+ 9'h0c4: uc_dat <= 32'b00000000101000101000000000000000;
+ 9'h0c5: uc_dat <= 32'b00000000000001111000000001010111;
+ 9'h0c6: uc_dat <= 32'b00000000101000100000000000000000;
+ 9'h0c7: uc_dat <= 32'b00000100000001110000000001010111;
+ 9'h0c8: uc_dat <= 32'b01100100000000000000000000000000;
+ 9'h0c9: uc_dat <= 32'b01000100000000000000000000000000;
+ 9'h0ca: uc_dat <= 32'b00000000000001101000000001010111;
+ 9'h0cb: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h0cc: uc_dat <= 32'b00000000000001100000000001010111;
+ 9'h0cd: uc_dat <= 32'b00000000000000000000000000000000;
+ 9'h0ce: uc_dat <= 32'b00000001101001100000000000000000;
+ 9'h0cf: uc_dat <= 32'b10010110101001101000000000000000;
+ 9'h0d0: uc_dat <= 32'b00000100100000111000000001010111;
+ 9'h0d1: uc_dat <= 32'b00000000000001101000000001010111;
+ 9'h0d2: uc_dat <= 32'b00001000000000000000110000011111;
+ 9'h0d3: uc_dat <= 32'b00000000000001100000000001010111;
+ 9'h0d4: uc_dat <= 32'b00000000101000111000000010010111;
+ 9'h0d5: uc_dat <= 32'b00000001101001100000000000000000;
+ 9'h0d6: uc_dat <= 32'b10011010101001101000000000000000;
+ 9'h0d7: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0d8: uc_dat <= 32'b11100100000000000000000000000000;
+ 9'h0d9: uc_dat <= 32'b00000001101000101000000000000000;
+ 9'h0da: uc_dat <= 32'b00010110101000100000000000000000;
+ 9'h0db: uc_dat <= 32'b00001100100001010000000001010111;
+ 9'h0dc: uc_dat <= 32'b00000001101000101000000000000000;
+ 9'h0dd: uc_dat <= 32'b00011010101000100000000000000000;
+ 9'h0de: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0df: uc_dat <= 32'b10111101101001001000000001001101;
+ 9'h0e0: uc_dat <= 32'b10110110101001000000000001001101;
+ 9'h0e1: uc_dat <= 32'b00001100100000000000000010010111;
+ 9'h0e2: uc_dat <= 32'b00000001101001100000000000000000;
+ 9'h0e3: uc_dat <= 32'b00010110101001101000000000000000;
+ 9'h0e4: uc_dat <= 32'b00001100100000000000000000000000;
+ 9'h0e5: uc_dat <= 32'b00000001101001100000000000000000;
+ 9'h0e6: uc_dat <= 32'b00011010101001101000000000000000;
+ 9'h0e7: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0e8: uc_dat <= 32'b00000001101110001000000000000000;
+ 9'h0e9: uc_dat <= 32'b00010110101110000000000000000000;
+ 9'h0ea: uc_dat <= 32'b00001100100000000000000000000000;
+ 9'h0eb: uc_dat <= 32'b00000001101110001000000000000000;
+ 9'h0ec: uc_dat <= 32'b00011010101110000000000000000000;
+ 9'h0ed: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0ee: uc_dat <= 32'b10111101101001001000000001001101;
+ 9'h0ef: uc_dat <= 32'b10110110101001000000000001001101;
+ 9'h0f0: uc_dat <= 32'b00000000100001100000000001010111;
+ 9'h0f1: uc_dat <= 32'b10111101101001001000000001001101;
+ 9'h0f2: uc_dat <= 32'b10110110101001000000000001001101;
+ 9'h0f3: uc_dat <= 32'b00001100100001101000000001010111;
+ 9'h0f4: uc_dat <= 32'b10111100011001111000000001001111;
+ 9'h0f5: uc_dat <= 32'b10100000011001110000000001001111;
+ 9'h0f6: uc_dat <= 32'b00000001101001111000000000000000;
+ 9'h0f7: uc_dat <= 32'b00011010101001110000000000000000;
+ 9'h0f8: uc_dat <= 32'b00001100000000000000000000000000;
+ 9'h0f9: uc_dat <= 32'b10111101101001111000000001001101;
+ 9'h0fa: uc_dat <= 32'b10110110101001110000000001001101;
+ 9'h0fb: uc_dat <= 32'b00001100100000000000000000000000;
+ 9'h0fc: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0fd: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0fe: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h0ff: uc_dat <= 32'b00000100000000000000000000000000;
+ 9'h100: uc_dat <= 32'b00001000000000000000100000001001;
+ 9'h101: uc_dat <= 32'b00001000000000000000000000010010;
+ 9'h102: uc_dat <= 32'b00001000000000000000000000101010;
+ 9'h103: uc_dat <= 32'b00001000000000000000010000110011;
+ 9'h104: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h105: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h106: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h107: uc_dat <= 32'b00001000000000000000010000111101;
+ 9'h108: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h109: uc_dat <= 32'b00001000000000000000010000110111;
+ 9'h10a: uc_dat <= 32'b00001000000000000000000000101000;
+ 9'h10b: uc_dat <= 32'b00001000000000000000010000110101;
+ 9'h10c: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h10d: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h10e: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h10f: uc_dat <= 32'b00001000000000000000010000111110;
+ 9'h110: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h111: uc_dat <= 32'b00001000000000000000000000010010;
+ 9'h112: uc_dat <= 32'b00001000000000000000000000101010;
+ 9'h113: uc_dat <= 32'b00001000000000000000010000110011;
+ 9'h114: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h115: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h116: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h117: uc_dat <= 32'b00001000000000000000010000111111;
+ 9'h118: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h119: uc_dat <= 32'b00001000000000000000010000110111;
+ 9'h11a: uc_dat <= 32'b00001000000000000000000000101000;
+ 9'h11b: uc_dat <= 32'b00001000000000000000010000110101;
+ 9'h11c: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h11d: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h11e: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h11f: uc_dat <= 32'b00001000000000000000100000000000;
+ 9'h120: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h121: uc_dat <= 32'b00001000000000000000000000010010;
+ 9'h122: uc_dat <= 32'b00001000000000000000000000100010;
+ 9'h123: uc_dat <= 32'b00001000000000000000010000110011;
+ 9'h124: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h125: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h126: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h127: uc_dat <= 32'b00001000000000000000010000111011;
+ 9'h128: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h129: uc_dat <= 32'b00001000000000000000010000110111;
+ 9'h12a: uc_dat <= 32'b00001000000000000000000000011100;
+ 9'h12b: uc_dat <= 32'b00001000000000000000010000110101;
+ 9'h12c: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h12d: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h12e: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h12f: uc_dat <= 32'b00001000000000000000100000000001;
+ 9'h130: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h131: uc_dat <= 32'b00001000000000000000000000010010;
+ 9'h132: uc_dat <= 32'b00001000000000000000000000011001;
+ 9'h133: uc_dat <= 32'b00001000000000000000010000110011;
+ 9'h134: uc_dat <= 32'b00001000000000000000010000101010;
+ 9'h135: uc_dat <= 32'b00001000000000000000010000101111;
+ 9'h136: uc_dat <= 32'b00001000000000000000000000010000;
+ 9'h137: uc_dat <= 32'b00001000000000000000100000000011;
+ 9'h138: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h139: uc_dat <= 32'b00001000000000000000010000110111;
+ 9'h13a: uc_dat <= 32'b00001000000000000000000000010110;
+ 9'h13b: uc_dat <= 32'b00001000000000000000010000110101;
+ 9'h13c: uc_dat <= 32'b00001000000000000000010000101000;
+ 9'h13d: uc_dat <= 32'b00001000000000000000010000101101;
+ 9'h13e: uc_dat <= 32'b00001000000000000000000000001110;
+ 9'h13f: uc_dat <= 32'b00001000000000000000100000000010;
+ 9'h140: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h141: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h142: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h143: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h144: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h145: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h146: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h147: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h148: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h149: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h14a: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h14b: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h14c: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h14d: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h14e: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h14f: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h150: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h151: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h152: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h153: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h154: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h155: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h156: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h157: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h158: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h159: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h15a: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h15b: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h15c: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h15d: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h15e: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h15f: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h160: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h161: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h162: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h163: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h164: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h165: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h166: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h167: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h168: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h169: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h16a: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h16b: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h16c: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h16d: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h16e: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h16f: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h170: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h171: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h172: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h173: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h174: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h175: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h176: uc_dat <= 32'b00001000000000000000110000011000;
+ 9'h177: uc_dat <= 32'b00001000000000000000000000001100;
+ 9'h178: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h179: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h17a: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h17b: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h17c: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h17d: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h17e: uc_dat <= 32'b00001000000000000000000000001010;
+ 9'h17f: uc_dat <= 32'b00001000000000000000000000001000;
+ 9'h180: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h181: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h182: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h183: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h184: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h185: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h186: uc_dat <= 32'b00001000000000000000010000011000;
+ 9'h187: uc_dat <= 32'b00001000000000000000010000001000;
+ 9'h188: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h189: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h18a: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h18b: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h18c: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h18d: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h18e: uc_dat <= 32'b00001000000000000000010000011010;
+ 9'h18f: uc_dat <= 32'b00001000000000000000010000001010;
+ 9'h190: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h191: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h192: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h193: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h194: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h195: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h196: uc_dat <= 32'b00001000000000000000010000011100;
+ 9'h197: uc_dat <= 32'b00001000000000000000010000001100;
+ 9'h198: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h199: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h19a: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h19b: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h19c: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h19d: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h19e: uc_dat <= 32'b00001000000000000000010000011110;
+ 9'h19f: uc_dat <= 32'b00001000000000000000010000001110;
+ 9'h1a0: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a1: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a2: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a3: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a4: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a5: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a6: uc_dat <= 32'b00001000000000000000010000100000;
+ 9'h1a7: uc_dat <= 32'b00001000000000000000010000010000;
+ 9'h1a8: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1a9: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1aa: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1ab: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1ac: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1ad: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1ae: uc_dat <= 32'b00001000000000000000010000100010;
+ 9'h1af: uc_dat <= 32'b00001000000000000000010000010010;
+ 9'h1b0: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b1: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b2: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b3: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b4: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b5: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b6: uc_dat <= 32'b00001000000000000000010000100100;
+ 9'h1b7: uc_dat <= 32'b00001000000000000000010000010100;
+ 9'h1b8: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1b9: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1ba: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1bb: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1bc: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1bd: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1be: uc_dat <= 32'b00001000000000000000010000100110;
+ 9'h1bf: uc_dat <= 32'b00001000000000000000010000010110;
+ 9'h1c0: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1c1: uc_dat <= 32'b00001000000000000000100000110000;
+ 9'h1c2: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1c3: uc_dat <= 32'b00001000000000000000100000000100;
+ 9'h1c4: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1c5: uc_dat <= 32'b00001000000000000000100000100110;
+ 9'h1c6: uc_dat <= 32'b00001000000000000000000000111000;
+ 9'h1c7: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1c8: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1c9: uc_dat <= 32'b00001000000000000000100000010111;
+ 9'h1ca: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1cb: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h1cc: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1cd: uc_dat <= 32'b00001000000000000000100000001100;
+ 9'h1ce: uc_dat <= 32'b00001000000000000000000000111010;
+ 9'h1cf: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1d0: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1d1: uc_dat <= 32'b00001000000000000000100000110000;
+ 9'h1d2: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1d3: uc_dat <= 32'b00001000000000000000110000010001;
+ 9'h1d4: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1d5: uc_dat <= 32'b00001000000000000000100000100110;
+ 9'h1d6: uc_dat <= 32'b00001000000000000000000000111100;
+ 9'h1d7: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1d8: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1d9: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h1da: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1db: uc_dat <= 32'b00001000000000000000110000001010;
+ 9'h1dc: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1dd: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h1de: uc_dat <= 32'b00001000000000000000000000111110;
+ 9'h1df: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1e0: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1e1: uc_dat <= 32'b00001000000000000000100000110000;
+ 9'h1e2: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1e3: uc_dat <= 32'b00001000000000000000100000111000;
+ 9'h1e4: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1e5: uc_dat <= 32'b00001000000000000000100000100110;
+ 9'h1e6: uc_dat <= 32'b00001000000000000000010000000000;
+ 9'h1e7: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1e8: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1e9: uc_dat <= 32'b00001000000000000000100000100010;
+ 9'h1ea: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1eb: uc_dat <= 32'b00001000000000000000000000101100;
+ 9'h1ec: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1ed: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h1ee: uc_dat <= 32'b00001000000000000000010000000010;
+ 9'h1ef: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1f0: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1f1: uc_dat <= 32'b00001000000000000000100000110100;
+ 9'h1f2: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1f3: uc_dat <= 32'b00001000000000000000110000001001;
+ 9'h1f4: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1f5: uc_dat <= 32'b00001000000000000000100000101011;
+ 9'h1f6: uc_dat <= 32'b00001000000000000000010000000100;
+ 9'h1f7: uc_dat <= 32'b00001000000000000000100000011100;
+ 9'h1f8: uc_dat <= 32'b00001000000000000000100000011011;
+ 9'h1f9: uc_dat <= 32'b00001000000000000000110000000100;
+ 9'h1fa: uc_dat <= 32'b00001000000000000000100000001010;
+ 9'h1fb: uc_dat <= 32'b00001000000000000000110000001000;
+ 9'h1fc: uc_dat <= 32'b00001000000000000000100000010101;
+ 9'h1fd: uc_dat <= 32'b00001000000000000000000000000000;
+ 9'h1fe: uc_dat <= 32'b00001000000000000000010000000110;
+ 9'h1ff: uc_dat <= 32'b00001000000000000000100000011100;
+ endcase
+end
+// end of microcode ROM
+
+always @ (posedge clock)
+begin
+ uc_dout <= uc_dat;
+end
+
+endmodule
+//---------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------
Index: trunk/verilog/rtl/light8080.v
===================================================================
--- trunk/verilog/rtl/light8080.v (nonexistent)
+++ trunk/verilog/rtl/light8080.v (revision 65)
@@ -0,0 +1,828 @@
+//---------------------------------------------------------------------------------------
+// light8080 : Intel 8080 binary compatible core
+//---------------------------------------------------------------------------------------
+// v1.3 (12 FEB 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
+// v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
+// v1.1 (20 sep 2008) Microcode bug in INR fixed.
+// v1.0 (05 nov 2007) First release. Jose A. Ruiz.
+//
+// This file and all the light8080 project files are freeware (See COPYING.TXT)
+//---------------------------------------------------------------------------------------
+//
+// vma : enable a memory or io r/w access.
+// io : access in progress is io (and not memory)
+// rd : read memory or io
+// wr : write memory or io
+// data_out : data output
+// addr_out : memory and io address
+// data_in : data input
+// halt : halt status (1 when in halt state)
+// inte : interrupt status (1 when enabled)
+// intr : interrupt request
+// inta : interrupt acknowledge
+// reset : synchronous reset
+// clk : clock
+//
+// (see timing diagrams at bottom of file)
+//---------------------------------------------------------------------------------------
+//
+// Timing diagram 1: RD and WR cycles
+//
+// 1 2 3 4 5 6 7 8
+// __ __ __ __ __ __ __ __
+// clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
+//
+// ==|=====|=====|=====|=====|=====|=====|=====|=====|
+//
+// addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
+//
+// data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
+//
+// data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
+// _____ _____
+// vma_o ______________/ \___________/ \___________
+// _____
+// rd_o ______________/ \_____________________________
+// _____
+// wr_o ________________________________/ \___________
+//
+// (functional diagram, actual time delays not shown)
+////////////////////////////////////////////////////////////////////////////////
+// This diagram shows a read cycle and a write cycle back to back.
+// In clock edges (4) and (7), the address is loaded into the external
+// synchronous RAM address register.
+// In clock edge (5), read data is loaded into the CPU.
+// In clock edge (7), write data is loaded into the external synchronous RAM.
+// In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock
+// cycles, which is a waste of RAM bandwidth.
+//
+//---------------------------------------------------------------------------------------
+
+module light8080
+(
+ clk, reset,
+ addr_out, vma,
+ io, rd,
+ wr, fetch,
+ data_in, data_out,
+ inta, inte,
+ halt, intr
+);
+
+//---------------------------------------------------------------------------------------
+//
+// All memory and io accesses are synchronous (rising clock edge). Signal vma
+// works as the master memory and io synchronous enable. More specifically:
+//
+// * All memory/io control signals (io,rd,wr) are valid only when vma is
+// high. They never activate when vma is inactive.
+// * Signals data_out and address are only valid when vma=1'b1. The high
+// address byte is 0x00 for all io accesses.
+// * Signal data_in should be valid by the end of the cycle after vma=1'b1,
+// data is clocked in by the rising clock edge.
+//
+// All signals are assumed to be synchronous to the master clock. Prevention of
+// metastability, if necessary, is up to you.
+//
+// Signal reset needs to be active for just 1 clock cycle (it is sampled on a
+// positive clock edge and is subject to setup and hold times).
+// Once reset is deasserted, the first fetch at address 0x0000 will happen 4
+// cycles later.
+//
+// Signal intr is sampled on all positive clock edges. If asserted when inte is
+// high, interrupts will be disabled, inta will be asserted high and a fetch
+// cycle will occur immediately after the current instruction ends execution,
+// except if intr was asserted at the last cycle of an instruction. In that case
+// it will be honored after the next instruction ends.
+// The fetched instruction will be executed normally, except that PC will not
+// be valid in any subsequent fetch cycles of the same instruction,
+// and will not be incremented (In practice, the same as the original 8080).
+// inta will remain high for the duration of the fetched instruction, including
+// fetch and execution time (in the original 8080 it was high only for the
+// opcode fetch cycle).
+// PC will not be autoincremented while inta is high, but it can be explicitly
+// modified (e.g. RST, CALL, etc.). Again, the same as the original.
+// Interrupts will be disabled upon assertion of inta, and remain disabled
+// until explicitly enabled by the program (as in the original).
+// If intr is asserted when inte is low, the interrupt will not be attended but
+// it will be registered in an int_pending flag, so it will be honored when
+// interrupts are enabled.
+//
+//
+// The above means that any instruction can be supplied in an inta cycle,
+// either single byte or multibyte. See the design notes.
+//---------------------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------------------
+// module interfaces
+input clk;
+input reset;
+
+output [15:0] addr_out;
+output vma;
+output io;
+output rd;
+output wr;
+output fetch;
+
+input [7:0] data_in;
+output [7:0] data_out;
+
+output inta;
+output inte;
+output halt;
+input intr;
+
+//---------------------------------------------------------------------------------------
+// internal signals
+// addr_low: low byte of address
+reg [7:0] addr_low;
+// IR: instruction register. some bits left unused.
+reg [7:0] IR;
+// s_field: IR field, sss source reg code
+wire [2:0] s_field;
+// d_field: IR field, ddd destination reg code
+wire [2:0] d_field;
+// p_field: IR field, pp 16-bit reg pair code
+wire [1:0] p_field;
+// rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs
+wire rbh; // 1 when P=11 (special case)
+// alu_op: uinst field, ALU operation code
+wire [3:0] alu_op;
+// uc_addr: microcode (ucode) address
+reg [7:0] uc_addr;
+// next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch)
+reg [8:0] next_uc_addr;
+// uc_jmp_addr: uinst field, absolute ucode jump address
+wire [7:0] uc_jmp_addr;
+// uc_ret_address: ucode return address saved in previous jump
+reg [7:0] uc_ret_addr;
+// addr_plus_1: uaddr + 1
+wire [7:0] addr_plus_1;
+// do_reset: reset, delayed 1 cycle // used to reset the microcode sequencer
+reg do_reset;
+
+// uc_flags1: uinst field, encoded flag of group 1 (see ucode file)
+wire [2:0] uc_flags1;
+// uc_flags2: uinst field, encoded flag of group 2 (see ucode file)
+wire [2:0] uc_flags2;
+// uc_addr_sel: selection of next uc_addr, composition of 4 flags
+wire [3:0] uc_addr_sel;
+// NOTE: see microcode file for information on flags
+wire uc_jsr; // uinst field, decoded 'jsr' flag
+wire uc_tjsr; // uinst field, decoded 'tjsr' flag
+wire uc_decode; // uinst field, decoded 'decode' flag
+wire uc_end; // uinst field, decoded 'end' flag
+reg condition_reg; // registered tjst condition
+// condition: tjsr condition (computed ccc condition from '80 instructions)
+reg condition;
+// condition_sel: IR field, ccc condition code
+wire uc_do_jmp; // uinst jump (jsr/tjsr) flag, pipelined
+wire uc_do_ret; // ret flag, pipelined
+wire uc_halt_flag; // uinst field, decoded 'halt' flag
+wire uc_halt; // halt command
+reg halt_reg; // halt status reg, output as 'halt' signal
+wire uc_ei; // uinst field, decoded 'ei' flag
+wire uc_di; // uinst field, decoded 'di' flag
+reg inte_reg; // inte status reg, output as 'inte' signal
+reg int_pending; // intr requested, inta not active yet
+reg inta_reg; // inta status reg, output as 'inta'
+wire clr_t1; // uinst field, explicitly erase T1
+wire do_clr_t1; // clr_t1 pipelined
+wire clr_t2; // uinst field, explicitly erase T2
+wire do_clr_t2; // clr_t2 pipelined
+wire [31:0] ucode; // microcode word
+reg [24:0] ucode_field2; // pipelined microcode
+// used to delay interrup enable for one entire instruction after EI
+reg delayed_ei;
+
+wire load_al; // uinst field, load AL reg from rbank
+wire load_addr; // uinst field, enable external addr reg load
+wire load_t1; // uinst field, load reg T1
+wire load_t2; // uinst field, load reg T2
+wire mux_in; // uinst field, T1/T2 input data selection
+wire load_do; // uinst field, pipelined, load DO reg
+// rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field)
+wire [1:0] rb_addr_sel;
+// ra_field: uinst field, explicit reg bank address
+wire [3:0] ra_field;
+wire [7:0] rbank_data; // rbank output
+reg [7:0] alu_output; // ALU output
+// data_output: datapath output: ALU output vs. F reg
+wire [7:0] data_output;
+reg [7:0] T1; // T1 reg (ALU operand)
+reg [7:0] T2; // T2 reg (ALU operand)
+// alu_input: data loaded into T1, T2: rbank data vs. DI
+wire [7:0] alu_input;
+wire we_rb; // uinst field, commands a write to the rbank
+wire inhibit_pc_increment; // avoid PC changes (during INTA)
+reg [3:0] rbank_rd_addr; // rbank rd addr
+wire [3:0] rbank_wr_addr; // rbank wr addr
+reg [7:0] DO; // data output reg
+
+// Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
+// This will be implemented as asynchronous LUT RAM in those devices where this
+// feature is available (Xilinx) and as multiplexed registers where it isn't
+// (Altera).
+reg [7:0] rbank[0:15];
+
+reg [7:0] flag_reg; // F register
+// flag_pattern: uinst field, F update pattern: which flags are updated
+wire [1:0] flag_pattern;
+wire flag_s; // new computed S flag
+wire flag_z; // new computed Z flag
+wire flag_p; // new computed P flag
+wire flag_cy; // new computed C flag
+wire flag_cy_1; // C flag computed from arith/logic operation
+wire flag_cy_2; // C flag computed from CPC circuit
+wire do_cy_op; // ALU explicit CY operation (CPC, etc.)
+wire do_cy_op_d; // do_cy_op, pipelined
+wire do_cpc; // ALU operation is CPC
+wire do_cpc_d; // do_cpc, pipelined
+wire do_daa; // ALU operation is DAA
+wire clear_cy; // Instruction unconditionally clears CY
+wire clear_ac; // Instruction unconditionally clears AC
+wire set_ac; // Instruction unconditionally sets AC
+wire flag_ac; // new computed half carry flag
+// flag_aux_cy: new computed half carry flag (used in 16-bit ops)
+wire flag_aux_cy;
+wire load_psw; // load F register
+
+// aux carry computation and control signals
+wire use_aux; // decoded from flags in 1st phase
+wire use_aux_cy; // 2nd phase signal
+reg reg_aux_cy;
+wire aux_cy_in;
+wire set_aux_cy;
+wire set_aux;
+
+// ALU control signals, together they select ALU operation
+wire [1:0] alu_fn;
+wire use_logic; // logic/arith mux control
+wire [1:0] mux_fn;
+wire use_psw; // ALU/F mux control
+
+// ALU arithmetic operands and result
+wire [8:0] arith_op1;
+wire [8:0] arith_op2;
+wire [8:0] arith_op2_sgn;
+wire [8:0] arith_res;
+wire [7:0] arith_res8;
+
+// ALU DAA intermediate signals (DAA has fully dedicated logic)
+wire [8:0] daa_res;
+reg [8:0] daa_res9;
+wire daa_test1;
+wire daa_test1a;
+wire daa_test2;
+wire [7:0] arith_daa_res;
+wire cy_daa;
+
+// ALU CY flag intermediate signals
+wire cy_in_sgn;
+wire cy_in;
+wire cy_in_gated;
+wire cy_adder;
+wire cy_arith;
+wire cy_shifter;
+
+// ALU intermediate results
+reg [7:0] logic_res;
+wire [7:0] shift_res;
+wire [7:0] alu_mux1;
+
+//---------------------------------------------------------------------------------------
+// module implementation
+// IR register, load when uc_decode flag activates
+always @ (posedge clk)
+begin
+ if (uc_decode)
+ IR <= data_in;
+end
+
+assign s_field = IR[2:0]; // IR field extraction : sss reg code
+assign d_field = IR[5:3]; // ddd reg code
+assign p_field = IR[5:4]; // pp 16-bit reg pair code
+
+//---------------------------------------------------------------------------------------
+// Microcode sequencer
+// do_reset is reset delayed 1 cycle
+always @ (posedge clk)
+ do_reset <= reset;
+
+assign uc_flags1 = ucode[31:29];
+assign uc_flags2 = ucode[28:26];
+
+// microcode address control flags are gated by do_reset (reset has priority)
+assign uc_do_ret = ((uc_flags2 == 3'b011) && !do_reset) ? 1'b1 : 1'b0;
+assign uc_jsr = ((uc_flags2 == 3'b010) && !do_reset) ? 1'b1 : 1'b0;
+assign uc_tjsr = ((uc_flags2 == 3'b100) && !do_reset) ? 1'b1 : 1'b0;
+assign uc_decode = ((uc_flags1 == 3'b001) && !do_reset) ? 1'b1 : 1'b0;
+assign uc_end = (((uc_flags2 == 3'b001) || (uc_tjsr && !condition_reg)) && !do_reset) ? 1'b1 : 1'b0;
+
+// other microinstruction flags are decoded
+assign uc_halt_flag = (uc_flags1 == 3'b111) ? 1'b1 : 1'b0;
+assign uc_halt = (uc_halt_flag && !inta_reg) ? 1'b1 : 1'b0;
+assign uc_ei = (uc_flags1 == 3'b011) ? 1'b1 : 1'b0;
+assign uc_di = ((uc_flags1 == 3'b010) || inta_reg) ? 1'b1 : 1'b0;
+// clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly
+// at the end of each instruction (by uc_decode)
+assign clr_t2 = (uc_flags2 == 3'b001) ? 1'b1 : 1'b0;
+assign clr_t1 = (uc_flags1 == 3'b110) ? 1'b1 : 1'b0;
+assign use_aux = (uc_flags1 == 3'b101) ? 1'b1 : 1'b0;
+assign set_aux = (uc_flags2 == 3'b111) ? 1'b1 : 1'b0;
+
+assign load_al = ucode[24];
+assign load_addr = ucode[25];
+
+assign do_cy_op_d = (ucode[5:2] == 4'b1011) ? 1'b1 : 1'b0; // decode CY ALU op
+assign do_cpc_d = ucode[0]; // decode CPC ALU op
+
+// uinst jump command, either unconditional or on a given condition
+assign uc_do_jmp = uc_jsr | (uc_tjsr & condition_reg);
+
+assign vma = load_addr; // addr is valid, either for memory or io
+
+// assume the only uinst that does memory access in the range 0..f is 'fetch'
+assign fetch = ((uc_addr[7:4] == 4'b0) && load_addr) ? 1'b1 : 1'b0;
+
+// external bus interface control signals
+assign io = (uc_flags1 == 3'b100) ? 1'b1 : 1'b0; // IO access (vs. memory)
+assign rd = (uc_flags2 == 3'b101) ? 1'b1 : 1'b0; // RD access
+assign wr = (uc_flags2 == 3'b110) ? 1'b1 : 1'b0; // WR access
+
+assign uc_jmp_addr = {ucode[11:10], ucode[5:0]};
+assign uc_addr_sel = {uc_do_ret, uc_do_jmp, uc_decode, uc_end};
+assign addr_plus_1 = uc_addr + 8'd1;
+
+// TODO simplify this!!
+
+// NOTE: when end==1'b1 we jump either to the FETCH ucode or to the HALT ucode
+// depending on the value of the halt signal.
+// We use the unregistered uc_halt instead of halt_reg because otherwise #end
+// should be on the cycle following #halt, wasting a cycle.
+// This means that the flag #halt has to be used with #end or will be ignored.
+// Note how we used DI (containing instruction opcode) as a microcode address
+always @ (*)
+begin
+ case (uc_addr_sel)
+ 4'b1000: next_uc_addr <= {1'b0, uc_ret_addr}; // ret
+ 4'b0100: next_uc_addr <= {1'b0, uc_jmp_addr}; // jsr/tjsr
+ 4'b0000: next_uc_addr <= {1'b0, addr_plus_1}; // uaddr++
+ 4'b0001: next_uc_addr <= {6'b0, uc_halt, 2'b11}; // end: go to fetch/halt uaddr
+ default: next_uc_addr <= {1'b1, data_in}; // decode fetched address
+ endcase
+end
+
+// read microcode rom is implemented here in a different module
+micro_rom rom
+(
+ .clock(clk),
+ .uc_addr(next_uc_addr),
+ .uc_dout(ucode)
+);
+
+// microcode address register
+always @ (posedge clk)
+begin
+ if (reset)
+ uc_addr <= 8'h0;
+ else
+ uc_addr <= next_uc_addr[7:0];
+end
+
+// ucode address 1-level 'return stack'
+always @ (posedge clk)
+begin
+ if (reset)
+ uc_ret_addr <= 8'h0;
+ else if (uc_do_jmp)
+ uc_ret_addr <= addr_plus_1;
+end
+
+assign alu_op = ucode[3:0];
+
+// pipeline uinst field2 for 1-cycle delayed execution.
+// note the same rbank addr field is used in cycles 1 and 2; this enforces
+// some constraints on uinst programming but simplifies the system.
+always @ (posedge clk)
+begin
+ ucode_field2 <= {do_cy_op_d, do_cpc_d, clr_t2, clr_t1,
+ set_aux, use_aux, rbank_rd_addr, ucode[14:4], alu_op};
+end
+
+//---------------------------------------------------------------------------------------
+// HALT logic
+always @ (posedge clk)
+begin
+ if (reset || int_pending) //inta_reg
+ halt_reg <= 1'b0;
+ else if (uc_halt)
+ halt_reg <= 1'b1;
+end
+
+assign halt = halt_reg;
+
+//---------------------------------------------------------------------------------------
+// INTE logic // inte_reg = 1'b1 means interrupts ENABLED
+always @ (posedge clk)
+begin
+ if (reset)
+ begin
+ inte_reg <= 1'b0;
+ delayed_ei <= 1'b0;
+ end
+ else
+ begin
+ if ((uc_di || uc_ei) && uc_end)
+ begin
+ //inte_reg <= uc_ei;
+ delayed_ei <= uc_ei; // FIXME DI must not be delayed
+ end
+
+ // at the last cycle of every instruction...
+ if (uc_end)
+ begin
+ // ...disable interrupts if the instruction is DI...
+ if (uc_di)
+ inte_reg <= 1'b0;
+ else
+ // ...of enable interrupts after the instruction following EI
+ inte_reg <= delayed_ei;
+ end
+ end
+end
+
+assign inte = inte_reg;
+
+// interrupts are ignored when inte=1'b0 but they are registered and will be
+// honored when interrupts are enabled
+always @ (posedge clk)
+begin
+ if (reset)
+ int_pending <= 1'b0;
+ else
+ begin
+ // intr will raise int_pending only if inta has not been asserted.
+ // Otherwise, if intr overlapped inta, we'd enter a microcode endless
+ // loop, executing the interrupt vector again and again.
+ if (intr && inte_reg && !int_pending && !inta_reg)
+ int_pending <= 1'b1;
+ else if (inte_reg && uc_end)
+ // int_pending is cleared when we're about to service the interrupt,
+ // that is when interrupts are enabled and the current instruction ends.
+ int_pending <= 1'b0;
+ end
+end
+
+//---------------------------------------------------------------------------------------
+// INTA logic
+// INTA goes high from END to END, that is for the entire time the instruction
+// takes to fetch and execute; in the original 8080 it was asserted only for
+// the M1 cycle.
+// All instructions can be used in an inta cycle, including XTHL which was
+// forbidden in the original 8080.
+// It's up to you figuring out which cycle is which in multibyte instructions.
+always @ (posedge clk)
+begin
+ if (reset)
+ inta_reg <= 1'b0;
+ else if (int_pending && uc_end)
+ // enter INTA state
+ inta_reg <= 1'b1;
+ else if (uc_end && !uc_halt_flag)
+ // exit INTA state
+ // NOTE: don't reset inta when exiting halt state (uc_halt_flag=1'b1).
+ // If we omit this condition, when intr happens on halt state, inta
+ // will only last for 1 cycle, because in halt state uc_end is
+ // always asserted.
+ inta_reg <= 1'b0;
+end
+
+assign inta = inta_reg;
+
+//---------------------------------------------------------------------------------------
+// Datapath
+
+// extract pipelined microcode fields
+assign ra_field = ucode[18:15];
+assign load_t1 = ucode[23];
+assign load_t2 = ucode[22];
+assign mux_in = ucode[21];
+assign rb_addr_sel = ucode[20:19];
+assign load_do = ucode_field2[7];
+assign set_aux_cy = ucode_field2[20];
+assign do_clr_t1 = ucode_field2[21];
+assign do_clr_t2 = ucode_field2[22];
+
+// T1 register
+always @ (posedge clk)
+begin
+ if (reset || uc_decode || do_clr_t1)
+ T1 <= 8'h0;
+ else if (load_t1)
+ T1 <= alu_input;
+end
+
+// T2 register
+always @ (posedge clk)
+begin
+ if (reset || uc_decode || do_clr_t2)
+ T2 <= 8'h0;
+ else if (load_t2)
+ T2 <= alu_input;
+end
+
+// T1/T2 input data mux
+assign alu_input = mux_in ? rbank_data : data_in;
+
+// register bank address mux logic
+assign rbh = (p_field == 2'b11) ? 1'b1 : 1'b0;
+
+always @ (*)
+begin
+ case (rb_addr_sel)
+ 2'b00: rbank_rd_addr <= ra_field;
+ 2'b01: rbank_rd_addr <= {1'b0, s_field};
+ 2'b10: rbank_rd_addr <= {1'b0, d_field};
+ 2'b11: rbank_rd_addr <= {rbh, p_field, ra_field[0]};
+ endcase
+end
+
+// RBank writes are inhibited in INTA state, but only for PC increments.
+assign inhibit_pc_increment = (inta_reg && use_aux_cy && (rbank_wr_addr[3:1] == 3'b100)) ? 1'b1 : 1'b0;
+assign we_rb = ucode_field2[6] & ~inhibit_pc_increment;
+
+// Register bank logic
+// NOTE: read is asynchronous, while write is synchronous; but note also
+// that write phase for a given uinst happens the cycle after the read phase.
+// This way we give the ALU time to do its job.
+assign rbank_wr_addr = ucode_field2[18:15];
+always @ (posedge clk)
+begin
+ if (we_rb)
+ rbank[rbank_wr_addr] <= alu_output;
+end
+assign rbank_data = rbank[rbank_rd_addr];
+
+// should we read F register or ALU output?
+assign use_psw = (ucode_field2[5:4] == 2'b11) ? 1'b1 : 1'b0;
+assign data_output = use_psw ? flag_reg : alu_output;
+
+always @ (posedge clk)
+begin
+ if (load_do)
+ DO <= data_output;
+end
+
+//---------------------------------------------------------------------------------------
+// ALU
+assign alu_fn = ucode_field2[1:0];
+assign use_logic = ucode_field2[2];
+assign mux_fn = ucode_field2[4:3];
+//#### make sure this is "00" in the microcode when no F updates should happen!
+assign flag_pattern = ucode_field2[9:8];
+assign use_aux_cy = ucode_field2[19];
+assign do_cpc = ucode_field2[23];
+assign do_cy_op = ucode_field2[24];
+assign do_daa = (ucode_field2[5:2] == 4'b1010) ? 1'b1 : 1'b0;
+
+// ucode_field2(14) will be set for those instructions that modify CY and AC
+// without following the standard rules -- AND, OR and XOR instructions.
+// Some instructions will unconditionally clear CY (AND, OR, XOR)
+assign clear_cy = ucode_field2[14];
+// Some instructions will unconditionally clear AC (OR, XOR)...
+assign clear_ac = (ucode_field2[14] && (ucode_field2[5:0] != 6'b000100)) ? 1'b1 : 1'b0;
+// ...and some others unconditionally SET AC (AND)
+assign set_ac = (ucode_field2[14] && (ucode_field2[5:0] == 6'b000100)) ? 1'b1 : 1'b0;
+
+assign aux_cy_in = (!set_aux_cy) ? reg_aux_cy : 1'b1;
+
+// carry input selection: normal or aux (for 16 bit increments)?
+assign cy_in = (!use_aux_cy) ? flag_reg[0] : aux_cy_in;
+
+// carry is not used (0) in add/sub operations
+assign cy_in_gated = cy_in & alu_fn[0];
+
+//---------------------------------------------------------------------------------------
+// Adder/substractor
+
+// zero extend adder operands to 9 bits to ease CY output synthesis
+// use zero extension because we're only interested in cy from 7 to 8
+assign arith_op1 = {1'b0, T2};
+assign arith_op2 = {1'b0, T1};
+
+// The adder/substractor is done in 2 stages to help XSL synth it properly
+// Other codings result in 1 adder + a substractor + 1 mux
+
+// do 2nd op 2's complement if substracting...
+assign arith_op2_sgn = (!alu_fn[1]) ? arith_op2 : ~arith_op2;
+// ...and complement cy input too
+assign cy_in_sgn = (!alu_fn[1]) ? cy_in_gated : ~cy_in_gated;
+
+// once 2nd operand has been negated (or not) add operands normally
+assign arith_res = arith_op1 + arith_op2_sgn + cy_in_sgn;
+
+// take only 8 bits; 9th bit of adder is cy output
+assign arith_res8 = arith_res[7:0];
+assign cy_adder = arith_res[8];
+
+//---------------------------------------------------------------------------------------
+// DAA dedicated logic
+// Note a DAA takes 2 cycles to complete!
+
+//daa_test1a=1'b1 when daa_res9(7:4) > 0x06
+assign daa_test1a = arith_op2[3] & (arith_op2[2] | arith_op2[1] | arith_op2[0]);
+assign daa_test1 = (flag_reg[4] || daa_test1a) ? 1'b1 : 1'b0;
+
+always @ (posedge clk)
+begin
+ if (reset)
+ daa_res9 <= 9'b0;
+ else if (daa_test1)
+ daa_res9 <= arith_op2 + 9'd6;
+ else
+ daa_res9 <= arith_op2;
+end
+
+assign daa_test2 = (flag_reg[0] || daa_test1a) ? 1'b1 : 1'b0;
+
+assign daa_res = daa_test2 ? ({1'b0, daa_res9[7:0]} + 9'h60) : daa_res9;
+
+assign cy_daa = daa_res[8];
+
+// DAA vs. adder mux
+assign arith_daa_res = do_daa ? daa_res[7:0] : arith_res8;
+
+// DAA vs. adder CY mux
+assign cy_arith = do_daa ? cy_daa : cy_adder;
+
+//---------------------------------------------------------------------------------------
+// Logic operations block
+always @ (*)
+begin
+ case (alu_fn)
+ 2'b00: logic_res <= T1 & T2;
+ 2'b01: logic_res <= T1 ^ T2;
+ 2'b10: logic_res <= T1 | T2;
+ 2'b11: logic_res <= ~T1;
+ endcase
+end
+
+//---------------------------------------------------------------------------------------
+// Shifter
+assign shift_res[6:1] = (!alu_fn[0]) ? T1[5:0] : T1[7:2];
+
+assign shift_res[0] = (alu_fn == 2'b00) ? T1[7] : // rot left
+ (alu_fn == 2'b10) ? cy_in : // rot left through carry
+ T1[1]; // rot right
+assign shift_res[7] = (alu_fn == 2'b01) ? T1[0] : // rot right
+ (alu_fn == 2'b11) ? cy_in : // rot right through carry
+ T1[6]; // rot left
+
+assign cy_shifter = (!alu_fn[0]) ? T1[7] : // left
+ T1[0]; // right
+
+assign alu_mux1 = use_logic ? logic_res : shift_res;
+
+always @ (*)
+begin
+ case (mux_fn)
+ 2'b00: alu_output <= alu_mux1;
+ 2'b01: alu_output <= arith_daa_res;
+ 2'b10: alu_output <= ~alu_mux1;
+ 2'b11: alu_output <= {2'b0, d_field, 3'b0}; // RST
+ endcase
+end
+
+//---------------------------------------------------------------------------------------
+// flag computation
+assign flag_s = alu_output[7];
+assign flag_p = ~(^alu_output);
+assign flag_z = (alu_output == 8'h0) ? 1'b1 : 1'b0;
+
+// AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
+assign flag_ac = set_ac ? 1'b1 :
+ clear_ac ? 1'b0 :
+ (arith_op1[4] ^ arith_op2_sgn[4] ^ alu_output[4]);
+
+// CY comes from the adder or the shifter, or is 0 if the instruction
+// implicitly clears it.
+assign flag_cy_1 = clear_cy ? 1'b0 :
+ use_logic ? cy_arith :
+ cy_shifter;
+
+assign flag_cy_2 = (!do_cpc) ? ~flag_reg[0] : 1'b1; // cmc, stc
+assign flag_cy = (!do_cy_op) ? flag_cy_1 : flag_cy_2;
+
+assign flag_aux_cy = cy_adder;
+
+// auxiliary carry reg
+always @ (posedge clk)
+begin
+ if (reset || uc_decode)
+ reg_aux_cy <= 1'b1; // inits to 0 every instruction
+ else
+ reg_aux_cy <= flag_aux_cy;
+end
+
+// load PSW from ALU (i.e. POP AF) or from flag signals
+assign load_psw = (we_rb && (rbank_wr_addr == 4'b0110)) ? 1'b1 : 1'b0;
+
+// The F register has been split in two separate groups that always update
+// together (C and all others).
+
+// F register, flags S,Z,AC,P and C
+always @ (posedge clk)
+begin
+ if (reset)
+ begin
+ flag_reg[7] <= 1'b0;
+ flag_reg[6] <= 1'b0;
+ flag_reg[5] <= 1'b0; // constant flag
+ flag_reg[4] <= 1'b0;
+ flag_reg[3] <= 1'b0; // constant flag
+ flag_reg[2] <= 1'b0;
+ flag_reg[1] <= 1'b1; // constant flag
+ flag_reg[0] <= 1'b0;
+ end
+ else
+ begin
+ if (flag_pattern[1])
+ begin
+ if (load_psw)
+ begin
+ flag_reg[7] <= alu_output[7];
+ flag_reg[6] <= alu_output[6];
+ flag_reg[4] <= alu_output[4];
+ flag_reg[2] <= alu_output[2];
+ end
+ else
+ begin
+ flag_reg[7] <= flag_s;
+ flag_reg[6] <= flag_z;
+ flag_reg[4] <= flag_ac;
+ flag_reg[2] <= flag_p;
+ end
+ end
+
+ // C flag
+ if (flag_pattern[0])
+ begin
+ if (load_psw)
+ flag_reg[0] <= alu_output[0];
+ else
+ flag_reg[0] <= flag_cy;
+ end
+
+ // constant flags
+ flag_reg[5] <= 1'b0; // constant flag
+ flag_reg[3] <= 1'b0; // constant flag
+ flag_reg[1] <= 1'b1; // constant flag
+ end
+end
+
+//---------------------------------------------------------------------------------------
+// Condition computation
+always @ (*)
+begin
+ case (d_field[2:0])
+ 3'b000: condition <= ~flag_reg[6]; // NZ
+ 3'b001: condition <= flag_reg[6]; // Z
+ 3'b010: condition <= ~flag_reg[0]; // NC
+ 3'b011: condition <= flag_reg[0]; // C
+ 3'b100: condition <= ~flag_reg[2]; // PO
+ 3'b101: condition <= flag_reg[2]; // PE
+ 3'b110: condition <= ~flag_reg[7]; // P
+ 3'b111: condition <= flag_reg[7]; // M
+ endcase
+end
+
+// condition is registered to shorten the delay path; the extra 1-cycle
+// delay is not relevant because conditions are tested in the next instruction
+// at the earliest, and there's at least the fetch uinsts intervening.
+always @ (posedge clk)
+begin
+ if (reset)
+ condition_reg <= 1'b0;
+ else
+ condition_reg <= condition;
+end
+
+// low byte address register
+always @ (posedge clk)
+begin
+ if (reset)
+ addr_low <= 8'h0;
+ else if (load_al)
+ addr_low <= rbank_data;
+end
+
+// note external address registers (high byte) are loaded directly from rbank
+assign addr_out = {rbank_data, addr_low};
+
+assign data_out = DO;
+
+endmodule
+//---------------------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------
Index: trunk/verilog/rtl/l80soc.v
===================================================================
--- trunk/verilog/rtl/l80soc.v (nonexistent)
+++ trunk/verilog/rtl/l80soc.v (revision 65)
@@ -0,0 +1,208 @@
+//---------------------------------------------------------------------------------------
+// Project: light8080 SOC WiCores Solutions
+//
+// File name: l80soc.v (February 04, 2012)
+//
+// Writer: Moti Litochevski
+//
+// Description:
+// This file contains the light8080 System On a Chip (SOC). the system includes the
+// CPU, program and data RAM and a UART interface and a general purpose digital IO.
+//
+// Revision History:
+//
+// Rev
+//
+//
+//---------------------------------------------------------------------------------------
+//
+// Copyright (C) 2012 Moti Litochevski
+//
+// This source file may be used and distributed without restriction provided that this
+// copyright statement is not removed from the file and that any derivative work
+// contains the original copyright notice and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
+// FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------------------
+
+module l80soc
+(
+ clock, reset,
+ txd, rxd,
+ p1dio, p2dio
+);
+//---------------------------------------------------------------------------------------
+// module interfaces
+// global signals
+input clock; // global clock input
+input reset; // global reset input
+// uart serial signals
+output txd; // serial data output
+input rxd; // serial data input
+// digital IO ports
+inout [7:0] p1dio; // port 1 digital IO
+inout [7:0] p2dio; // port 2 digital IO
+
+//---------------------------------------------------------------------------------------
+// io space registers addresses
+// uart registers
+`define UDATA_REG 8'h80 // used for both transmit and receive
+`define UBAUDL_REG 8'h81 // low byte of baud rate register
+`define UBAUDH_REG 8'h82 // low byte of baud rate register
+`define USTAT_REG 8'h83 // uart status register
+// dio port registers
+`define P1_DATA_REG 8'h84 // port 1 data register
+`define P1_DIR_REG 8'h85 // port 1 direction register
+`define P2_DATA_REG 8'h86 // port 2 data register
+`define P2_DIR_REG 8'h87 // port 2 direction register
+
+//---------------------------------------------------------------------------------------
+// internal declarations
+// registered output
+
+// internals
+wire [15:0] cpu_addr;
+wire [7:0] cpu_din, cpu_dout, ram_dout;
+wire cpu_io, cpu_rd, cpu_wr;
+wire [7:0] txData;
+wire txValid, txBusy, rxValid, lcd_clk;
+wire [7:0] rxData;
+reg [15:0] uartbaud;
+reg rxfull, scpu_io;
+reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
+
+//---------------------------------------------------------------------------------------
+// module implementation
+// light8080 CPU instance
+light8080 cpu
+(
+ .clk(clock),
+ .reset(reset),
+ .addr_out(cpu_addr),
+ .vma(/* nu */),
+ .io(cpu_io),
+ .rd(cpu_rd),
+ .wr(cpu_wr),
+ .fetch(/* nu */),
+ .data_in(cpu_din),
+ .data_out(cpu_dout),
+ .inta(/* nu */),
+ .inte(/* nu */),
+ .halt(/* nu */),
+ .intr(1'b0)
+);
+// cpu data input selection
+assign cpu_din = scpu_io ? io_dout : ram_dout;
+
+// program and data Xilinx RAM memory
+ram_image ram
+(
+ .clk(clock),
+ .addr(cpu_addr[11:0]),
+ .we(cpu_wr & ~cpu_io),
+ .din(cpu_dout),
+ .dout(ram_dout)
+);
+
+// io space write registers
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ begin
+ uartbaud <= 16'b0;
+ rxfull <= 1'b0;
+ p1reg <= 8'b0;
+ p1dir <= 8'b0;
+ p2reg <= 8'b0;
+ p2dir <= 8'b0;
+ end
+ else
+ begin
+ // io space registers
+ if (cpu_wr && cpu_io)
+ begin
+ if (cpu_addr[7:0] == `UBAUDL_REG) uartbaud[7:0] <= cpu_dout;
+ if (cpu_addr[7:0] == `UBAUDH_REG) uartbaud[15:8] <= cpu_dout;
+ if (cpu_addr[7:0] == `P1_DATA_REG) p1reg <= cpu_dout;
+ if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
+ if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
+ if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
+ end
+
+ // receiver full flag
+ if (rxValid && !rxfull)
+ rxfull <= 1'b1;
+ else if (cpu_rd && cpu_io && (cpu_addr[7:0] == `UDATA_REG) && rxfull)
+ rxfull <= 1'b0;
+ end
+end
+// uart transmit write pulse
+assign txValid = cpu_wr & cpu_io & (cpu_addr[7:0] == `UDATA_REG);
+
+// io space read registers
+always @ (posedge reset or posedge clock)
+begin
+ if (reset)
+ begin
+ io_dout <= 8'b0;
+ end
+ else
+ begin
+ // io space read registers
+ if (cpu_io && (cpu_addr[7:0] == `UDATA_REG))
+ io_dout <= rxData;
+ else if (cpu_io && (cpu_addr[7:0] == `USTAT_REG))
+ io_dout <= {3'b0, rxfull, 3'b0, txBusy};
+ else if (cpu_io && (cpu_addr[7:0] == `P1_DATA_REG))
+ io_dout <= p1dio;
+ else if (cpu_io && (cpu_addr[7:0] == `P2_DATA_REG))
+ io_dout <= p2dio;
+
+ // sampled io control to select cpu data input
+ scpu_io <= cpu_io;
+ end
+end
+
+// uart module mapped to the io space
+uart uart
+(
+ .clock(clock),
+ .reset(reset),
+ .serIn(rxd),
+ .serOut(txd),
+ .txData(cpu_dout),
+ .txValid(txValid),
+ .txBusy(txBusy),
+ .txDone(/* nu */),
+ .rxData(rxData),
+ .rxValid(rxValid),
+ .baudDiv(uartbaud)
+);
+
+// digital IO ports
+// port 1
+assign p1dio[0] = p1dir[0] ? p1reg[0] : 1'bz;
+assign p1dio[1] = p1dir[1] ? p1reg[1] : 1'bz;
+assign p1dio[2] = p1dir[2] ? p1reg[2] : 1'bz;
+assign p1dio[3] = p1dir[3] ? p1reg[3] : 1'bz;
+assign p1dio[4] = p1dir[4] ? p1reg[4] : 1'bz;
+assign p1dio[5] = p1dir[5] ? p1reg[5] : 1'bz;
+assign p1dio[6] = p1dir[6] ? p1reg[6] : 1'bz;
+assign p1dio[7] = p1dir[7] ? p1reg[7] : 1'bz;
+// port 2
+assign p2dio[0] = p2dir[0] ? p2reg[0] : 1'bz;
+assign p2dio[1] = p2dir[1] ? p2reg[1] : 1'bz;
+assign p2dio[2] = p2dir[2] ? p2reg[2] : 1'bz;
+assign p2dio[3] = p2dir[3] ? p2reg[3] : 1'bz;
+assign p2dio[4] = p2dir[4] ? p2reg[4] : 1'bz;
+assign p2dio[5] = p2dir[5] ? p2reg[5] : 1'bz;
+assign p2dio[6] = p2dir[6] ? p2reg[6] : 1'bz;
+assign p2dio[7] = p2dir[7] ? p2reg[7] : 1'bz;
+
+endmodule
+//---------------------------------------------------------------------------------------
+// Th.. Th.. Th.. Thats all folks !!!
+//---------------------------------------------------------------------------------------
Index: trunk/verilog/sim/icarus/block.cfg
===================================================================
--- trunk/verilog/sim/icarus/block.cfg (nonexistent)
+++ trunk/verilog/sim/icarus/block.cfg (revision 65)
@@ -0,0 +1,6 @@
+../../rtl/uart.v
+../../rtl/ram_image.v
+../../rtl/micro_rom.v
+../../rtl/light8080.v
+../../rtl/l80soc.v
+../../bench/tb_l80soc.v
Index: trunk/verilog/sim/icarus/run.bat
===================================================================
--- trunk/verilog/sim/icarus/run.bat (nonexistent)
+++ trunk/verilog/sim/icarus/run.bat (revision 65)
@@ -0,0 +1 @@
+vvp -l test.log test.vvp
Index: trunk/verilog/sim/icarus/gtk.bat
===================================================================
--- trunk/verilog/sim/icarus/gtk.bat (nonexistent)
+++ trunk/verilog/sim/icarus/gtk.bat (revision 65)
@@ -0,0 +1 @@
+gtkwave test.vcd -a test.sav
Index: trunk/verilog/sim/icarus/compile.bat
===================================================================
--- trunk/verilog/sim/icarus/compile.bat (nonexistent)
+++ trunk/verilog/sim/icarus/compile.bat (revision 65)
@@ -0,0 +1 @@
+iverilog -o test.vvp -cblock.cfg
Index: trunk/verilog/syn/xilinx_s3/l80soc.ucf
===================================================================
--- trunk/verilog/syn/xilinx_s3/l80soc.ucf (nonexistent)
+++ trunk/verilog/syn/xilinx_s3/l80soc.ucf (revision 65)
@@ -0,0 +1,2 @@
+NET "clock" TNM_NET = clock;
+TIMESPEC TS_clock = PERIOD "clock" 20 ns HIGH 50%;
Index: trunk/verilog/syn/xilinx_s3/xilinx_s3.xise
===================================================================
--- trunk/verilog/syn/xilinx_s3/xilinx_s3.xise (nonexistent)
+++ trunk/verilog/syn/xilinx_s3/xilinx_s3.xise (revision 65)
@@ -0,0 +1,299 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: trunk/verilog/syn/xilinx_s3/l80soc_summary.html
===================================================================
--- trunk/verilog/syn/xilinx_s3/l80soc_summary.html (nonexistent)
+++ trunk/verilog/syn/xilinx_s3/l80soc_summary.html (revision 65)
@@ -0,0 +1,178 @@
+Xilinx Design Summary
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Date Generated: 02/21/2012 - 11:58:43
+
\ No newline at end of file
Index: trunk/verilog/syn/altera_c2/l80soc.qsf
===================================================================
--- trunk/verilog/syn/altera_c2/l80soc.qsf (nonexistent)
+++ trunk/verilog/syn/altera_c2/l80soc.qsf (revision 65)
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 15:57:36 February 17, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# l80soc_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY l80soc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:36 FEBRUARY 17, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
+set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
+set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
+set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
+set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
+set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
+set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
+set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name FMAX_REQUIREMENT "15 ns"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: trunk/verilog/syn/altera_c2/l80soc.fit.rpt
===================================================================
--- trunk/verilog/syn/altera_c2/l80soc.fit.rpt (nonexistent)
+++ trunk/verilog/syn/altera_c2/l80soc.fit.rpt (revision 65)
@@ -0,0 +1,1115 @@
+Fitter report for l80soc
+Tue Feb 21 12:01:11 2012
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. Bidir Pins
+ 13. I/O Bank Usage
+ 14. All Package Pins
+ 15. Output Pin Default Load For Reported TCO
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Control Signals
+ 20. Global & Other Fast Signals
+ 21. Non-Global High Fan-Out Signals
+ 22. Fitter RAM Summary
+ 23. Interconnect Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Estimated Delay Added for Hold Timing
+ 32. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Tue Feb 21 12:01:11 2012 ;
+; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name ; l80soc ;
+; Top-level Entity Name ; l80soc ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Total logic elements ; 596 / 8,256 ( 7 % ) ;
+; Total combinational functions ; 452 / 8,256 ( 5 % ) ;
+; Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
+; Total registers ; 339 ;
+; Total pins ; 20 / 138 ( 14 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 47,616 / 165,888 ( 29 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Use Best Effort Settings for Compilation ; Off ; Off ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 2 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 854 ( 0.00 % ) ;
+; -- Achieved ; 0 / 854 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 854 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/altera_c2/l80soc.pin.
+
+
++-------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+---------------------------+
+; Resource ; Usage ;
++---------------------------------------------+---------------------------+
+; Total logic elements ; 596 / 8,256 ( 7 % ) ;
+; -- Combinational with no register ; 257 ;
+; -- Register only ; 144 ;
+; -- Combinational with a register ; 195 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 275 ;
+; -- 3 input functions ; 68 ;
+; -- <=2 input functions ; 109 ;
+; -- Register only ; 144 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 406 ;
+; -- arithmetic mode ; 46 ;
+; ; ;
+; Total registers* ; 339 / 8,646 ( 4 % ) ;
+; -- Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
+; -- I/O registers ; 0 / 390 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 47 / 516 ( 9 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 20 / 138 ( 14 % ) ;
+; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 12 / 36 ( 33 % ) ;
+; Total block memory bits ; 47,616 / 165,888 ( 29 % ) ;
+; Total block memory implementation bits ; 55,296 / 165,888 ( 33 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 2% / 2% / 3% ;
+; Peak interconnect usage (total/H/V) ; 6% / 6% / 7% ;
+; Maximum fan-out node ; clock~clkctrl ;
+; Maximum fan-out ; 351 ;
+; Highest non-global fan-out signal ; reset ;
+; Highest non-global fan-out ; 50 ;
+; Total fan-out ; 2865 ;
+; Average fan-out ; 3.16 ;
++---------------------------------------------+---------------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 51 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; rxd ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; txd ; 61 ; 4 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; p1dio[0] ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;
+; p1dio[1] ; 189 ; 2 ; 12 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;
+; p1dio[2] ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;
+; p1dio[3] ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;
+; p1dio[4] ; 35 ; 1 ; 0 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;
+; p1dio[5] ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;
+; p1dio[6] ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;
+; p1dio[7] ; 187 ; 2 ; 14 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;
+; p2dio[0] ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;
+; p2dio[1] ; 60 ; 4 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;
+; p2dio[2] ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;
+; p2dio[3] ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;
+; p2dio[4] ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;
+; p2dio[5] ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;
+; p2dio[6] ; 64 ; 4 ; 5 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;
+; p2dio[7] ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 8 / 32 ( 25 % ) ; 3.3V ; -- ;
+; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
+; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 4 ; 12 / 36 ( 33 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; 23 ; 27 ; 1 ; clock ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 24 ; 28 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; 27 ; 30 ; 1 ; rxd ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 35 ; 37 ; 1 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 37 ; 39 ; 1 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 61 ; 59 ; 4 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 67 ; 69 ; 4 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 68 ; 70 ; 4 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 69 ; 71 ; 4 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 70 ; 74 ; 4 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 72 ; 75 ; 4 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 74 ; 76 ; 4 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 75 ; 77 ; 4 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 76 ; 78 ; 4 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 77 ; 79 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 187 ; 181 ; 2 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
+; |l80soc ; 596 (90) ; 339 (58) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 20 ; 0 ; 257 (32) ; 144 (37) ; 195 (15) ; |l80soc ; work ;
+; |light8080:cpu| ; 422 (422) ; 218 (218) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 204 (204) ; 89 (89) ; 129 (129) ; |l80soc|light8080:cpu ; ;
+; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; ;
+; |altsyncram:Ram0_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0 ; ;
+; |altsyncram_ts61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated ; ;
+; |ram_image:ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram ; work ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_9il1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated ; ;
+; |uart:uart| ; 91 (91) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 18 (18) ; 52 (52) ; |l80soc|uart:uart ; ;
++----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[2] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[4] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
+; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[0] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
+; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
+; p2dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+; txd ; Output ; -- ; -- ; -- ; -- ;
+; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
+; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
+; rxd ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
++----------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; p1dio[0] ; ; ;
+; - io_dout~3 ; 0 ; 6 ;
+; p1dio[1] ; ; ;
+; - io_dout~7 ; 0 ; 6 ;
+; p1dio[2] ; ; ;
+; - io_dout~9 ; 0 ; 6 ;
+; p1dio[3] ; ; ;
+; - io_dout~11 ; 0 ; 6 ;
+; p1dio[4] ; ; ;
+; - io_dout~14 ; 1 ; 6 ;
+; p1dio[5] ; ; ;
+; - io_dout~15 ; 0 ; 6 ;
+; p1dio[6] ; ; ;
+; - io_dout~17 ; 0 ; 6 ;
+; p1dio[7] ; ; ;
+; - io_dout~19 ; 0 ; 6 ;
+; p2dio[0] ; ; ;
+; - io_dout~2 ; 0 ; 6 ;
+; p2dio[1] ; ; ;
+; - io_dout~7 ; 1 ; 6 ;
+; p2dio[2] ; ; ;
+; - io_dout~9 ; 0 ; 6 ;
+; p2dio[3] ; ; ;
+; - io_dout~11 ; 0 ; 6 ;
+; p2dio[4] ; ; ;
+; - io_dout~13 ; 0 ; 6 ;
+; p2dio[5] ; ; ;
+; - io_dout~15 ; 0 ; 6 ;
+; p2dio[6] ; ; ;
+; - io_dout~17 ; 1 ; 6 ;
+; p2dio[7] ; ; ;
+; - io_dout~19 ; 0 ; 6 ;
+; clock ; ; ;
+; reset ; ; ;
+; rxd ; ; ;
++---------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
+; clock ; PIN_23 ; 351 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
+; comb~0 ; LCCOMB_X12_Y8_N22 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
+; io_dout[0]~5 ; LCCOMB_X13_Y6_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|Equal18~0 ; LCCOMB_X14_Y12_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;
+; light8080:cpu|T1[2]~3 ; LCCOMB_X15_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|T2[0]~3 ; LCCOMB_X15_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|addr_low[1]~1 ; LCCOMB_X12_Y8_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|flag_reg[2]~8 ; LCCOMB_X15_Y8_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~209 ; LCCOMB_X14_Y9_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~211 ; LCCOMB_X14_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~213 ; LCCOMB_X12_Y13_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~215 ; LCCOMB_X16_Y11_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~217 ; LCCOMB_X13_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~219 ; LCCOMB_X16_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~221 ; LCCOMB_X14_Y9_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~223 ; LCCOMB_X13_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~225 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~227 ; LCCOMB_X14_Y9_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~229 ; LCCOMB_X14_Y9_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~231 ; LCCOMB_X16_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~233 ; LCCOMB_X13_Y11_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~235 ; LCCOMB_X13_Y11_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~237 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|rbank~239 ; LCCOMB_X16_Y11_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|uc_decode~0 ; LCCOMB_X16_Y9_N26 ; 21 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|uc_ret_addr[4]~1 ; LCCOMB_X16_Y7_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; light8080:cpu|ucode_field2[7] ; LCFF_X17_Y9_N17 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; p1dir[0] ; LCFF_X14_Y7_N31 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[0]~1 ; LCCOMB_X14_Y7_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; p1dir[1] ; LCFF_X14_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[2] ; LCFF_X14_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[3] ; LCFF_X14_Y7_N15 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[4] ; LCFF_X14_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[5] ; LCFF_X14_Y7_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[6] ; LCFF_X14_Y7_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1dir[7] ; LCFF_X14_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p1reg[0]~0 ; LCCOMB_X14_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; p2dir[0] ; LCFF_X13_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[0]~0 ; LCCOMB_X13_Y7_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; p2dir[1] ; LCFF_X13_Y7_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[2] ; LCFF_X13_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[3] ; LCFF_X13_Y7_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[4] ; LCFF_X13_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[5] ; LCFF_X13_Y7_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[6] ; LCFF_X13_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2dir[7] ; LCFF_X13_Y7_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
+; p2reg[0]~0 ; LCCOMB_X12_Y7_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; reset ; PIN_24 ; 51 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
+; reset ; PIN_24 ; 120 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
+; uart:uart|Equal5~10 ; LCCOMB_X9_Y6_N2 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
+; uart:uart|rxBaudCnt[3]~1 ; LCCOMB_X8_Y6_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|rxBitCnt[0]~12 ; LCCOMB_X9_Y6_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|rxBusy ; LCFF_X8_Y6_N29 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
+; uart:uart|rxData[0]~0 ; LCCOMB_X9_Y6_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X9_Y6_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|txBitCnt[0]~6 ; LCCOMB_X8_Y8_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|txBusy ; LCFF_X9_Y8_N15 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
+; uart:uart|txShiftReg[3]~6 ; LCCOMB_X10_Y8_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
+; uart:uart|txShiftReg~14 ; LCCOMB_X10_Y8_N10 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
+; uartbaud[15]~1 ; LCCOMB_X10_Y7_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; uartbaud[7]~0 ; LCCOMB_X10_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
++--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+; clock ; PIN_23 ; 351 ; Global Clock ; GCLK2 ; -- ;
+; reset ; PIN_24 ; 120 ; Global Clock ; GCLK1 ; -- ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++------------------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++------------------------------------------------------------------------------------------------+---------+
+; reset ; 50 ;
+; light8080:cpu|Mux10~1 ; 31 ;
+; light8080:cpu|Mux11~1 ; 31 ;
+; light8080:cpu|Mux8~1 ; 31 ;
+; light8080:cpu|Mux9~1 ; 31 ;
+; light8080:cpu|addr_low[0] ; 26 ;
+; light8080:cpu|ucode_field2[4] ; 25 ;
+; uart:uart|txBusy ; 24 ;
+; light8080:cpu|addr_low[1] ; 23 ;
+; light8080:cpu|ucode_field2[0] ; 21 ;
+; light8080:cpu|ucode_field2[1] ; 21 ;
+; light8080:cpu|uc_decode~0 ; 21 ;
+; light8080:cpu|addr_low[2] ; 21 ;
+; light8080:cpu|DO[4]~1 ; 21 ;
+; light8080:cpu|Mux20~3 ; 20 ;
+; light8080:cpu|Mux27~1 ; 20 ;
+; light8080:cpu|ucode_field2[2] ; 20 ;
+; light8080:cpu|addr_low[3] ; 20 ;
+; light8080:cpu|Mux22~5 ; 19 ;
+; light8080:cpu|Mux21~3 ; 19 ;
+; light8080:cpu|rbank~207 ; 19 ;
+; light8080:cpu|rbank~197 ; 19 ;
+; light8080:cpu|rbank~187 ; 19 ;
+; light8080:cpu|rbank~177 ; 19 ;
+; light8080:cpu|DO[2]~0 ; 19 ;
+; light8080:cpu|Mux24~7 ; 18 ;
+; light8080:cpu|Mux26~8 ; 18 ;
+; light8080:cpu|ucode_field2[18] ; 17 ;
+; light8080:cpu|ucode_field2[17] ; 17 ;
+; light8080:cpu|ucode_field2[16] ; 17 ;
+; light8080:cpu|ucode_field2[15] ; 17 ;
+; light8080:cpu|ucode_field2[6] ; 17 ;
+; uart:uart|Equal5~10 ; 17 ;
+; light8080:cpu|addr_low[4] ; 17 ;
+; light8080:cpu|addr_low[5] ; 17 ;
+; light8080:cpu|addr_low[6] ; 17 ;
+; light8080:cpu|addr_low[7] ; 17 ;
+; uart:uart|rxBusy ; 13 ;
+; light8080:cpu|Equal13~0 ; 13 ;
+; light8080:cpu|ucode_field2[3] ; 12 ;
+; uart:uart|baudCE16 ; 12 ;
+; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 11 ;
+; io_dout[0]~0 ; 9 ;
+; light8080:cpu|T1[2] ; 9 ;
+; light8080:cpu|Equal19~1 ; 9 ;
+; light8080:cpu|ucode_field2[5] ; 9 ;
+; light8080:cpu|T1[0] ; 9 ;
+; uart:uart|rxShiftReg[0]~0 ; 8 ;
+; uart:uart|rxData[0]~0 ; 8 ;
+; light8080:cpu|T2[0]~3 ; 8 ;
++------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary ;
++---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
++---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
+; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X11_Y9, M4K_X11_Y5, M4K_X27_Y9, M4K_X27_Y7 ;
+; ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X11_Y11, M4K_X11_Y14, M4K_X11_Y13, M4K_X11_Y6, M4K_X11_Y7, M4K_X11_Y12, M4K_X11_Y8, M4K_X11_Y10 ;
++---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+------------------------+
+; Block interconnects ; 1,076 / 26,052 ( 4 % ) ;
+; C16 interconnects ; 8 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 558 / 17,952 ( 3 % ) ;
+; Direct links ; 135 / 26,052 ( < 1 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; Local interconnects ; 275 / 8,256 ( 3 % ) ;
+; R24 interconnects ; 12 / 1,020 ( 1 % ) ;
+; R4 interconnects ; 533 / 22,440 ( 2 % ) ;
++----------------------------+------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Logic Elements ;
++---------------------------------------------+------------------------------+
+; Number of Logic Elements (Average = 12.68) ; Number of LABs (Total = 47) ;
++---------------------------------------------+------------------------------+
+; 1 ; 2 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 1 ;
+; 7 ; 2 ;
+; 8 ; 2 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
+; 11 ; 3 ;
+; 12 ; 1 ;
+; 13 ; 2 ;
+; 14 ; 1 ;
+; 15 ; 4 ;
+; 16 ; 24 ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+------------------------------+
+; LAB-wide Signals (Average = 1.98) ; Number of LABs (Total = 47) ;
++------------------------------------+------------------------------+
+; 1 Async. clear ; 13 ;
+; 1 Clock ; 47 ;
+; 1 Clock enable ; 13 ;
+; 1 Sync. clear ; 4 ;
+; 2 Clock enables ; 16 ;
++------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced (Average = 18.47) ; Number of LABs (Total = 47) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 2 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
+; 11 ; 3 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 2 ;
+; 15 ; 1 ;
+; 16 ; 1 ;
+; 17 ; 2 ;
+; 18 ; 4 ;
+; 19 ; 3 ;
+; 20 ; 3 ;
+; 21 ; 2 ;
+; 22 ; 4 ;
+; 23 ; 3 ;
+; 24 ; 3 ;
+; 25 ; 3 ;
+; 26 ; 1 ;
+; 27 ; 1 ;
+; 28 ; 2 ;
+; 29 ; 1 ;
+; 30 ; 0 ;
+; 31 ; 0 ;
+; 32 ; 1 ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out (Average = 9.00) ; Number of LABs (Total = 47) ;
++-------------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 4 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 4 ;
+; 5 ; 0 ;
+; 6 ; 2 ;
+; 7 ; 5 ;
+; 8 ; 1 ;
+; 9 ; 5 ;
+; 10 ; 2 ;
+; 11 ; 7 ;
+; 12 ; 5 ;
+; 13 ; 6 ;
+; 14 ; 1 ;
+; 15 ; 0 ;
+; 16 ; 3 ;
++-------------------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 18.77) ; Number of LABs (Total = 47) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 1 ;
+; 3 ; 2 ;
+; 4 ; 0 ;
+; 5 ; 3 ;
+; 6 ; 1 ;
+; 7 ; 1 ;
+; 8 ; 1 ;
+; 9 ; 2 ;
+; 10 ; 0 ;
+; 11 ; 1 ;
+; 12 ; 1 ;
+; 13 ; 0 ;
+; 14 ; 2 ;
+; 15 ; 1 ;
+; 16 ; 0 ;
+; 17 ; 4 ;
+; 18 ; 2 ;
+; 19 ; 0 ;
+; 20 ; 1 ;
+; 21 ; 2 ;
+; 22 ; 1 ;
+; 23 ; 3 ;
+; 24 ; 2 ;
+; 25 ; 1 ;
+; 26 ; 4 ;
+; 27 ; 1 ;
+; 28 ; 5 ;
+; 29 ; 0 ;
+; 30 ; 2 ;
+; 31 ; 3 ;
++----------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+ Info: Processing started: Tue Feb 21 12:01:04 2012
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off l80soc -c l80soc
+Info: Selected device EP2C8Q208C8 for design "l80soc"
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C5Q208C8 is compatible
+ Info: Device EP2C5Q208I8 is compatible
+ Info: Device EP2C8Q208I8 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location 1
+ Info: Pin ~nCSO~ is reserved at location 2
+ Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning: No exact pin location assignment(s) for 20 pins of 20 total pins
+ Info: Pin p1dio[0] not assigned to an exact location on the device
+ Info: Pin p1dio[1] not assigned to an exact location on the device
+ Info: Pin p1dio[2] not assigned to an exact location on the device
+ Info: Pin p1dio[3] not assigned to an exact location on the device
+ Info: Pin p1dio[4] not assigned to an exact location on the device
+ Info: Pin p1dio[5] not assigned to an exact location on the device
+ Info: Pin p1dio[6] not assigned to an exact location on the device
+ Info: Pin p1dio[7] not assigned to an exact location on the device
+ Info: Pin p2dio[0] not assigned to an exact location on the device
+ Info: Pin p2dio[1] not assigned to an exact location on the device
+ Info: Pin p2dio[2] not assigned to an exact location on the device
+ Info: Pin p2dio[3] not assigned to an exact location on the device
+ Info: Pin p2dio[4] not assigned to an exact location on the device
+ Info: Pin p2dio[5] not assigned to an exact location on the device
+ Info: Pin p2dio[6] not assigned to an exact location on the device
+ Info: Pin p2dio[7] not assigned to an exact location on the device
+ Info: Pin txd not assigned to an exact location on the device
+ Info: Pin clock not assigned to an exact location on the device
+ Info: Pin reset not assigned to an exact location on the device
+ Info: Pin rxd not assigned to an exact location on the device
+Info: Timing-driven compilation is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: Automatically promoted node clock (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
+Info: Automatically promoted node reset (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
+ Info: Following destination nodes may be non-global or may not use global or regional clocks
+ Info: Destination node light8080:cpu|condition_reg
+ Info: Destination node light8080:cpu|flag_reg[0]
+ Info: Destination node light8080:cpu|flag_reg[6]
+ Info: Destination node light8080:cpu|flag_reg[2]
+ Info: Destination node light8080:cpu|daa_res9[1]
+ Info: Destination node light8080:cpu|daa_res9[2]
+ Info: Destination node light8080:cpu|daa_res9[3]
+ Info: Destination node light8080:cpu|daa_res9[4]
+ Info: Destination node light8080:cpu|flag_reg[4]
+ Info: Destination node light8080:cpu|daa_res9[5]
+ Info: Non-global destination nodes limited to 10 nodes
+Info: Starting register packing
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 18 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 16 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:02
+Info: Estimated most critical path is memory to register delay of 13.149 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16~porta_address_reg8'
+ Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16'
+ Info: 3: + IC(0.892 ns) + CELL(0.624 ns) = 5.277 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'light8080:cpu|Mux10~0'
+ Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 6.088 ns; Loc. = LAB_X12_Y9; Fanout = 31; COMB Node = 'light8080:cpu|Mux10~1'
+ Info: 5: + IC(1.157 ns) + CELL(0.370 ns) = 7.615 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~172'
+ Info: 6: + IC(1.173 ns) + CELL(0.366 ns) = 9.154 ns; Loc. = LAB_X13_Y13; Fanout = 1; COMB Node = 'light8080:cpu|rbank~173'
+ Info: 7: + IC(1.337 ns) + CELL(0.206 ns) = 10.697 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~174'
+ Info: 8: + IC(0.441 ns) + CELL(0.366 ns) = 11.504 ns; Loc. = LAB_X12_Y10; Fanout = 19; COMB Node = 'light8080:cpu|rbank~177'
+ Info: 9: + IC(0.887 ns) + CELL(0.650 ns) = 13.041 ns; Loc. = LAB_X13_Y12; Fanout = 1; COMB Node = 'light8080:cpu|T2~9'
+ Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 13.149 ns; Loc. = LAB_X13_Y12; Fanout = 3; REG Node = 'light8080:cpu|T2[2]'
+ Info: Total cell delay = 7.102 ns ( 54.01 % )
+ Info: Total interconnect delay = 6.047 ns ( 45.99 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 2% of the available device resources
+ Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9
+Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 17 output pins without output pin load capacitance assignment
+ Info: Pin "p1dio[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p1dio[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "p2dio[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "txd" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Quartus II Fitter was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 208 megabytes
+ Info: Processing ended: Tue Feb 21 12:01:11 2012
+ Info: Elapsed time: 00:00:07
+ Info: Total CPU time (on all processors): 00:00:06
+
+
Index: trunk/verilog/syn/altera_c2/l80soc.qpf
===================================================================
--- trunk/verilog/syn/altera_c2/l80soc.qpf (nonexistent)
+++ trunk/verilog/syn/altera_c2/l80soc.qpf (revision 65)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 15:57:36 February 17, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.1"
+DATE = "15:57:36 February 17, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "l80soc"
Index: trunk/readme.txt
===================================================================
--- trunk/readme.txt (revision 64)
+++ trunk/readme.txt (revision 65)
@@ -46,3 +46,20 @@
asm\hexconv.pl Intel HEX to VHDL converter
asm\tasmtb.bat BATCH script to build the test benches
asm\readme.txt How to assemble the sources
+
+verilog\rtl\ contains the Verilog files of the light8080 CPU and SOC
+verilog\bench\ Verilog light8080 SOC testbench
+verilog\sim\icarus files used for Verilog simulation using Icaru Verilog
+verilog\syn\altera_c2 Altera Quartus project file ucing Cyclone II FPGA
+verilog\syn\xilinx_s3 Xilinx ISE project file ucing Spartan 3 FPGA
+
+c\ Hello World Small-C light8080 SOC sample
+
+tools\c80\ C80 compiler and AS80 assembler tools used to compile
+ the C example program. The c80.exe executable was compiled
+ using tcc (Tiny C Compiler).
+
+tools\ihex2vlog\ Intel HEX to Verilog tool used to generate the Verilog
+ program & RAM memory file used by the verilog SOC.
+ The ihex2vlog.exe executable was compiled using tcc
+ (Tiny C Compiler).
| xilinx_s3 Project Status (02/21/2012 - 11:58:43) | |||
| Project File: | +xilinx_s3.ise | +Implementation State: | +Placed and Routed | +
| Module Name: | +l80soc | +
|
++No Errors | +
| Target Device: | +xc3s200-4ft256 | +
|
+33 Warnings | +
| Product Version: | ISE 11.4 | +
|
++All Signals Completely Routed | +
| Design Goal: | +Balanced | +
|
++All Constraints Met | +
| Design Strategy: | +Xilinx Default (unlocked) | +
|
+0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report) | +
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | +|
| Number of Slice Flip Flops | +211 | +3,840 | +5% | ++ | |
| Number of 4 input LUTs | +327 | +3,840 | +8% | ++ | |
| Number of occupied Slices | +223 | +1,920 | +11% | ++ | |
| Number of Slices containing only related logic | +223 | +223 | +100% | ++ | |
| Number of Slices containing unrelated logic | +0 | +223 | +0% | ++ | |
| Total Number of 4 input LUTs | +328 | +3,840 | +8% | ++ | |
| Number used as logic | +311 | ++ | + | + | |
| Number used as a route-thru | +1 | ++ | + | + | |
| Number used for Dual Port RAMs | +16 | ++ | + | + | |
| Number of bonded IOBs | +20 | +173 | +11% | ++ | |
| Number of RAMB16s | +3 | +12 | +25% | ++ | |
| Number of BUFGMUXs | +1 | +8 | +12% | ++ | |
| Average Fanout of Non-Clock Nets | +3.29 | ++ | + | + | |
| Performance Summary | [-] | |||
| Final Timing Score: | +0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | +Pinout Data: | +Pinout Report | +|
| Routing Results: | +All Signals Completely Routed | +Clock Data: | +Clock Report | +|
| Timing Constraints: | ++All Constraints Met | ++ | + | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | +Errors | Warnings | Infos | |
| Synthesis Report | Current | Tue Feb 21 11:54:55 2012 | 0 | 31 Warnings | 6 Infos | |
| Translation Report | Current | Tue Feb 21 11:58:21 2012 | 0 | 0 | 0 | |
| Map Report | Current | Tue Feb 21 11:58:29 2012 | 0 | 2 Warnings | 2 Infos | |
| Place and Route Report | Current | Tue Feb 21 11:58:40 2012 | 0 | 0 | 0 | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Tue Feb 21 11:58:43 2012 | 0 | 0 | 2 Infos | |
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |