OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /light8080
    from Rev 65 to Rev 66
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  •

Rev 65 → Rev 66

/trunk/tools/c80/c80.lib
308,5 → 308,4
ld a,d
sbc b
ret
 
#endasm
/trunk/tools/c80/c80.c
2445,7 → 2445,7
 
/* Return from subroutine */
zret()
{ ol("RET");
{ ol("ret");
}
/* Perform subroutine call to value on top of stack */
callstk()
/trunk/c/intr_vec.h
0,0 → 1,91
//---------------------------------------------------------------------------------------
// Project: light8080 SOC WiCores Solutions
//
// File name: intr_vec.h (March 03, 2012)
//
// Writer: Moti Litochevski
//
// Description:
// This file contains a simple example of calling interrupt service routine. this
// file defines the interrupt vector for external interrupt 0 located at address
// 0x0008. the interrupts vectors addresses are set in the verilog interrupt
// controller "intr_ctrl.v" file.
// Code is generated for all 4 supported external interrupts but non used interrupt
// are not called.
// On execution of an interrupt the CPU will automatically clear the interrupt
// enable flag set by the EI instruction. the interrupt vectors in this example
// enable the interrupts again after interrupt service routine execution. to enable
// nested interrupts just move the EI instruction to the code executed before the
// call instruction to the service routine (see comments below).
// Note that this code is not optimized in any way. this is just an example to
// verify the interrupt mechanism of the light8080 CPU and show a simple example.
//
// Revision History:
//
// Rev <revnumber> <Date> <owner>
// <comment>
//---------------------------------------------------------------------------------------
 
// to support interrupt enable the respective interrupt vector is defined here at the
// beginning of the output assembly file. only the interrupt vector for used interrupts
// should call a valid interrupt service routine name defined in the C source file. the
// C function name should be prefixed by "__".
#asm
;Preserve space for interrupt routines
;interrupt 0 vector
org #0008
push af
push bc
push de
push hl
; ei ; to enable nested interrupts uncomment this instruction
call __int0_isr
pop hl
pop de
pop bc
pop af
ei ; interrupt are not enabled during the execution os the isr
ret
;interrupt 1 vector
org #0018
push af
push bc
push de
push hl
; call __int1_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
;interrupt 2 vector
org #0028
push af
push bc
push de
push hl
; call __int2_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
;interrupt 3 vector
org #0038
push af
push bc
push de
push hl
; call __int3_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
#endasm
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
/trunk/c/hello.asm
17,6 → 17,8
;// Description:
;// This file contains a simple program written in Small-C that sends a string to
;// the UART and then switches to echo received bytes.
;// This example also include a simple interrupt example which will work with the
;// verilog testbench. the testbench
;//
;// Revision History:
;//
23,6 → 25,99
;// Rev <revnumber> <Date> <owner>
;// <comment>
;//---------------------------------------------------------------------------------------
;// define interrupt vectors
;// note that this file must be edited to enable interrupt used
;#include intr_vec.h
;//---------------------------------------------------------------------------------------
;// Project: light8080 SOC WiCores Solutions
;//
;// File name: intr_vec.h (March 03, 2012)
;//
;// Writer: Moti Litochevski
;//
;// Description:
;// This file contains a simple example of calling interrupt service routine. this
;// file defines the interrupt vector for external interrupt 0 located at address
;// 0x0008. the interrupts vectors addresses are set in the verilog interrupt
;// controller "intr_ctrl.v" file.
;// Code is generated for all 4 supported external interrupts but non used interrupt
;// are not called.
;// On execution of an interrupt the CPU will automatically clear the interrupt
;// enable flag set by the EI instruction. the interrupt vectors in this example
;// enable the interrupts again after interrupt service routine execution. to enable
;// nested interrupts just move the EI instruction to the code executed before the
;// call instruction to the service routine (see comments below).
;// Note that this code is not optimized in any way. this is just an example to
;// verify the interrupt mechanism of the light8080 CPU and show a simple example.
;//
;// Revision History:
;//
;// Rev <revnumber> <Date> <owner>
;// <comment>
;//---------------------------------------------------------------------------------------
;// to support interrupt enable the respective interrupt vector is defined here at the
;// beginning of the output assembly file. only the interrupt vector for used interrupts
;// should call a valid interrupt service routine name defined in the C source file. the
;// C function name should be prefixed by "__".
;#asm
;Preserve space for interrupt routines
;interrupt 0 vector
org #0008
push af
push bc
push de
push hl
; ei ; to enable nested interrupts uncomment this instruction
call __int0_isr
pop hl
pop de
pop bc
pop af
ei ; interrupt are not enabled during the execution os the isr
ret
;interrupt 1 vector
org #0018
push af
push bc
push de
push hl
; call __int1_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
;interrupt 2 vector
org #0028
push af
push bc
push de
push hl
; call __int2_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
;interrupt 3 vector
org #0038
push af
push bc
push de
push hl
; call __int3_isr ; interrupt not used
pop hl
pop de
pop bc
pop af
ei
ret
;//---------------------------------------------------------------------------------------
;// Th.. Th.. Th.. Thats all folks !!!
;//---------------------------------------------------------------------------------------
;// insert c80 assmbly library to the output file
;#include ..\tools\c80\c80.lib
;#asm
;
340,10 → 435,12
;port (130) UBAUDH; // low byte of baud rate register
;port (131) USTAT; // uart status register
;// digital IO ports registers
;port (132) P1REG; // output port1 - used as first attenuator control
;port (133) P2REG; // output port2 - used as low digit LCD
;port (134) P3REG; // output port3 - used as high digit LCD
;port (135) P4REG; // output port4
;port (132) P1DATA; // port 1 data register
;port (133) P1DIR; // port 1 direction register control
;port (134) P2DATA; // port 2 data register
;port (135) P2DIR; // port 2 direction register control
;// interrupt controller register
;port (136) INTRENA; // interrupts enable register
;// simulation end register
;// writing any value to this port will end the verilog simulation when using tb_l80soc
;// test bench.
663,6 → 760,18
;}
pop bc
ret
;// external interrupt 0 service routine
;int0_isr()
__int0_isr:
;{
; printstr("Interrupt 0 was asserted."); nl();
ld hl,cc1+0
push hl
call __printstr
pop bc
call __nl
;}
ret
;// program main routine
;main()
__main:
669,25 → 778,61
;{
; // configure UART baud rate - set to 9600 for 30MHz clock
; // BAUD = round(<clock>/<baud rate>/16) = round(30e6/9600/16) = 195
; UBAUDL = 195;
ld hl,195
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
;// UBAUDL = 195;
; UBAUDL = 1;
ld hl,1
ld a,l
out (129),a
 
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
; UBAUDH = 0;
ld hl,0
ld a,l
out (130),a
 
; // configure both ports to output and digital outputs as zeros
; P1DATA = 0x00;
ld hl,0
ld a,l
out (132),a
 
; P1DIR = 0xff;
ld hl,255
ld a,l
out (133),a
 
; P2DATA = 0x00;
ld hl,0
ld a,l
out (134),a
 
; P2DIR = 0xff;
ld hl,255
ld a,l
out (135),a
 
; // enable interrupt 0 only
; INTRENA = 0x01;
ld hl,1
ld a,l
out (136),a
 
; // enable CPU interrupt
;#asm
ei
;
; // print message
; printstr("Hello World!!!"); nl();
ld hl,cc1+0
ld hl,cc1+26
push hl
call __printstr
pop bc
call __nl
; printstr("Dec value: "); printdec(tstary[1]); nl();
ld hl,cc1+15
ld hl,cc1+41
push hl
call __printstr
pop bc
703,7 → 848,7
pop bc
call __nl
; printstr("Hex value: 0x"); printhex(tstary[0]); nl();
ld hl,cc1+27
ld hl,cc1+53
push hl
call __printstr
pop bc
718,13 → 863,19
call __printhex
pop bc
call __nl
; // assert bit 0 of port 1 to test external interrupt 0
; P1DATA = 0x01;
ld hl,1
ld a,l
out (132),a
 
;
; printstr("Echoing received bytes: "); nl();
ld hl,cc1+41
ld hl,cc1+67
push hl
call __printstr
pop bc
call __nl
;
; // loop forever
; while (1) {
cc13:
755,13 → 906,16
;// Th.. Th.. Th.. Thats all folks !!!
;//---------------------------------------------------------------------------------------
cc1:
db 72,101,108,108,111,32,87,111,114,108
db 100,33,33,33,0,68,101,99,32,118
db 97,108,117,101,58,32,0,72,101,120
db 32,118,97,108,117,101,58,32,48,120
db 0,69,99,104,111,105,110,103,32,114
db 101,99,101,105,118,101,100,32,98,121
db 116,101,115,58,32,0
db 73,110,116,101,114,114,117,112,116,32
db 48,32,119,97,115,32,97,115,115,101
db 114,116,101,100,46,0,72,101,108,108
db 111,32,87,111,114,108,100,33,33,33
db 0,68,101,99,32,118,97,108,117,101
db 58,32,0,72,101,120,32,118,97,108
db 117,101,58,32,48,120,0,69,99,104
db 111,105,110,103,32,114,101,99,101,105
db 118,101,100,32,98,121,116,101,115,58
db 32,0
__rxbyte:
ds 1
__tstary:
/trunk/c/HELLO.LST
5,75 → 5,76
 
Symbol Value Decimal
 
ccand : $0029 41
ccasl : $0099 153
ccasr : $008b 139
ccbcneg : $011c 284
cccmp : $0056 86
cccmpbcde : $012c 300
cccmp1 : $0063 99
cccom : $00ac 172
ccdeneg : $0114 276
ccdiv : $00d3 211
ccdiv1 : $00e9 233
ccdiv2 : $0100 256
ccdiv3 : $0109 265
cceq : $0030 48
ccgchar : $0007 7
ccge : $004a 74
ccgint : $000d 13
ccgt : $003c 60
ccle : $0043 67
cclt : $0050 80
ccmult : $00b3 179
ccmult1 : $00b8 184
ccne : $0036 54
ccneg : $00a7 167
ccor : $001b 27
ccpchar : $0012 18
ccpint : $0015 21
ccrdel : $0124 292
ccsub : $00a0 160
ccsxt : $0008 8
ccucmp : $0080 128
ccuge : $0066 102
ccugt : $0072 114
ccule : $0079 121
ccult : $006c 108
ccxor : $0022 34
cc1 : $035c 860
cc10 : $027a 634
cc11 : $02cf 719
cc12 : $02e1 737
cc13 : $033f 831
cc14 : $035b 859
cc15 : $0358 856
cc2 : $0131 305
cc3 : $0144 324
cc4 : $016d 365
cc5 : $0171 369
cc6 : $0183 387
cc7 : $01b3 435
cc8 : $01e3 483
cc9 : $0221 545
__getbyte : $014f 335
__main : $02e3 739
__nl : $0172 370
__outint : $01f0 496
__printdec : $01b4 436
__printhex : $0249 585
__printstr : $0183 387
ccand : $0064 100
ccasl : $00d4 212
ccasr : $00c6 198
ccbcneg : $0157 343
cccmp : $0091 145
cccmpbcde : $0167 359
cccmp1 : $009e 158
cccom : $00e7 231
ccdeneg : $014f 335
ccdiv : $010e 270
ccdiv1 : $0124 292
ccdiv2 : $013b 315
ccdiv3 : $0144 324
cceq : $006b 107
ccgchar : $0042 66
ccge : $0085 133
ccgint : $0048 72
ccgt : $0077 119
ccle : $007e 126
cclt : $008b 139
ccmult : $00ee 238
ccmult1 : $00f3 243
ccne : $0071 113
ccneg : $00e2 226
ccor : $0056 86
ccpchar : $004d 77
ccpint : $0050 80
ccrdel : $015f 351
ccsub : $00db 219
ccsxt : $0043 67
ccucmp : $00bb 187
ccuge : $00a1 161
ccugt : $00ad 173
ccule : $00b4 180
ccult : $00a7 167
ccxor : $005d 93
cc1 : $03d0 976
cc10 : $02bb 699
cc11 : $0310 784
cc12 : $0322 802
cc13 : $03b1 945
cc14 : $03cf 975
cc15 : $03cc 972
cc2 : $016c 364
cc3 : $0181 385
cc4 : $01ae 430
cc5 : $01b2 434
cc6 : $01c4 452
cc7 : $01f4 500
cc8 : $0224 548
cc9 : $0262 610
__getbyte : $018c 396
__int0_isr : $0324 804
__main : $0330 816
__nl : $01b3 435
__outint : $0231 561
__printdec : $01f5 501
__printhex : $028a 650
AS80 Assembler for i8080-Z180 [1.11]. Page 2
--------------------------------- HELLO.ASM ----------------------------------
 
__rxbyte : $039e 926
__sendbyte : $0131 305
__tstary : $039f 927
__printstr : $01c4 452
__rxbyte : $042c 1068
__sendbyte : $016c 364
__tstary : $042d 1069
__8080__ : $0001 1
 
62 labels used
63 labels used
 
770 lines read, no errors in pass 1.
924 lines read, no errors in pass 1.
AS80 Assembler for i8080-Z180 [1.11]. Page 3
--------------------------------- HELLO.ASM ----------------------------------
 
85,7 → 86,7
0000 = org #0000
0000 : 21000c ld hl,3072
0003 : f9 ld sp,hl
0004 : cde302 call __main
0004 : cd3003 call __main
;//---------------------------------------------------
;// Project: light8080 SOC WiCores Solutions
;//
96,6 → 97,8
;// Description:
;// This file contains a simple program written in Sm
;// the UART and then switches to echo received bytes
;// This example also include a simple interrupt exam
;// verilog testbench. the testbench
;//
;// Revision History:
;//
102,10 → 105,109
;// Rev <revnumber> <Date> <owner>
;// <comment>
;//---------------------------------------------------
;// define interrupt vectors
;// note that this file must be edited to enable inter
;#include intr_vec.h
;//---------------------------------------------------
;// Project: light8080 SOC WiCores Solutions
;//
;// File name: intr_vec.h (March 03, 2012)
;//
;// Writer: Moti Litochevski
;//
;// Description:
;// This file contains a simple example of calling in
;// file defines the interrupt vector for external in
;// 0x0008. the interrupts vectors addresses are set
;// controller "intr_ctrl.v" file.
;// Code is generated for all 4 supported external in
;// are not called.
;// On execution of an interrupt the CPU will automat
;// enable flag set by the EI instruction. the interr
;// enable the interrupts again after interrupt servi
;// nested interrupts just move the EI instruction to
;// call instruction to the service routine (see comm
;// Note that this code is not optimized in any way.
;// verify the interrupt mechanism of the light8080 C
;//
;// Revision History:
;//
;// Rev <revnumber> <Date> <owner>
;// <comment>
;//---------------------------------------------------
;// to support interrupt enable the respective interru
;// beginning of the output assembly file. only the in
;// should call a valid interrupt service routine name
;// C function name should be prefixed by "__".
;#asm
AS80 Assembler for i8080-Z180 [1.11]. Page 4
--------------------------------- HELLO.ASM ----------------------------------
 
;Preserve space for interrupt routines
;interrupt 0 vector
0008 = org #0008
0008 : f5 push af
0009 : c5 push bc
000a : d5 push de
000b : e5 push hl
; ei ; to enable nested interrupts uncomment this
000c : cd2403 call __int0_isr
000f : e1 pop hl
0010 : d1 pop de
0011 : c1 pop bc
0012 : f1 pop af
0013 : fb ei ; interrupt are not enabled during the execut
0014 : c9 ret
;interrupt 1 vector
0018 = org #0018
0018 : f5 push af
0019 : c5 push bc
001a : d5 push de
001b : e5 push hl
; call __int1_isr ; interrupt not used
001c : e1 pop hl
001d : d1 pop de
001e : c1 pop bc
001f : f1 pop af
0020 : fb ei
0021 : c9 ret
;interrupt 2 vector
0028 = org #0028
0028 : f5 push af
0029 : c5 push bc
002a : d5 push de
002b : e5 push hl
; call __int2_isr ; interrupt not used
002c : e1 pop hl
002d : d1 pop de
002e : c1 pop bc
002f : f1 pop af
0030 : fb ei
0031 : c9 ret
;interrupt 3 vector
0038 = org #0038
0038 : f5 push af
0039 : c5 push bc
003a : d5 push de
003b : e5 push hl
; call __int3_isr ; interrupt not used
003c : e1 pop hl
003d : d1 pop de
003e : c1 pop bc
003f : f1 pop af
0040 : fb ei
0041 : c9 ret
;//---------------------------------------------------
;// Th.. Th.. Th.. Thats all folks !!!
;//---------------------------------------------------
;// insert c80 assmbly library to the output file
;#include ..\tools\c80\c80.lib
;#asm
;
;-----------------------------------------------------
AS80 Assembler for i8080-Z180 [1.11]. Page 5
--------------------------------- HELLO.ASM ----------------------------------
 
; Small-C Run-time Librray
;
; V4d As of July 16, 1980 (gtf)
113,331 → 215,333
;-----------------------------------------------------
;
;Fetch a single byte from the address in HL and sign e
0007 : ccgchar:
0007 : 7e ld a,(hl)
0008 : ccsxt:
0008 : 6f ld l,a
0009 : 07 rlca
000a : 9f sbc a
000b : 67 ld h,a
000c : c9 ret
0042 : ccgchar:
0042 : 7e ld a,(hl)
0043 : ccsxt:
0043 : 6f ld l,a
0044 : 07 rlca
0045 : 9f sbc a
0046 : 67 ld h,a
0047 : c9 ret
;Fetch a full 16-bit integer from the address in HL
000d : ccgint:
000d : 7e ld a,(hl)
000e : 23 inc hl
000f : 66 ld h,(hl)
0010 : 6f ld l,a
0011 : c9 ret
0048 : ccgint:
0048 : 7e ld a,(hl)
0049 : 23 inc hl
004a : 66 ld h,(hl)
004b : 6f ld l,a
004c : c9 ret
;Store a single byte from HL at the address in DE
0012 : ccpchar:
0012 : 7d ld a,l
0013 : 12 ld (de),a
0014 : c9 ret
004d : ccpchar:
004d : 7d ld a,l
004e : 12 ld (de),a
004f : c9 ret
;Store a 16-bit integer in HL at the address in DE
0015 : ccpint:
0015 : 7d ld a,l
0016 : 12 ld (de),a
0017 : 13 inc de
0018 : 7c ld a,h
AS80 Assembler for i8080-Z180 [1.11]. Page 4
--------------------------------- HELLO.ASM ----------------------------------
 
0019 : 12 ld (de),a
001a : c9 ret
0050 : ccpint:
0050 : 7d ld a,l
0051 : 12 ld (de),a
0052 : 13 inc de
0053 : 7c ld a,h
0054 : 12 ld (de),a
0055 : c9 ret
;Inclusive "or" HL and DE into HL
001b : ccor:
001b : 7d ld a,l
001c : b3 or e
001d : 6f ld l,a
001e : 7c ld a,h
001f : b2 or d
0020 : 67 ld h,a
0021 : c9 ret
0056 : ccor:
0056 : 7d ld a,l
0057 : b3 or e
0058 : 6f ld l,a
0059 : 7c ld a,h
005a : b2 or d
005b : 67 ld h,a
005c : c9 ret
;Exclusive "or" HL and DE into HL
0022 : ccxor:
0022 : 7d ld a,l
0023 : ab xor e
0024 : 6f ld l,a
0025 : 7c ld a,h
0026 : aa xor d
0027 : 67 ld h,a
0028 : c9 ret
005d : ccxor:
005d : 7d ld a,l
005e : ab xor e
005f : 6f ld l,a
0060 : 7c ld a,h
0061 : aa xor d
0062 : 67 ld h,a
0063 : c9 ret
;"And" HL and DE into HL
0029 : ccand:
0029 : 7d ld a,l
002a : a3 and e
002b : 6f ld l,a
002c : 7c ld a,h
002d : a2 and d
002e : 67 ld h,a
002f : c9 ret
0064 : ccand:
0064 : 7d ld a,l
0065 : a3 and e
0066 : 6f ld l,a
0067 : 7c ld a,h
0068 : a2 and d
0069 : 67 ld h,a
006a : c9 ret
AS80 Assembler for i8080-Z180 [1.11]. Page 6
--------------------------------- HELLO.ASM ----------------------------------
 
;Test if HL = DE and set HL = 1 if true else 0
0030 : cceq:
0030 : cd5600 call cccmp
0033 : c8 ret z
0034 : 2b dec hl
0035 : c9 ret
006b : cceq:
006b : cd9100 call cccmp
006e : c8 ret z
006f : 2b dec hl
0070 : c9 ret
;Test if DE ~= HL
0036 : ccne:
0036 : cd5600 call cccmp
0039 : c0 ret nz
003a : 2b dec hl
003b : c9 ret
0071 : ccne:
0071 : cd9100 call cccmp
0074 : c0 ret nz
0075 : 2b dec hl
0076 : c9 ret
;Test if DE > HL (signed)
003c : ccgt:
003c : eb ex de,hl
003d : cd5600 call cccmp
0040 : d8 ret c
0041 : 2b dec hl
0042 : c9 ret
0077 : ccgt:
0077 : eb ex de,hl
0078 : cd9100 call cccmp
007b : d8 ret c
007c : 2b dec hl
007d : c9 ret
;Test if DE <= HL (signed)
0043 : ccle:
0043 : cd5600 call cccmp
0046 : c8 ret z
0047 : d8 ret c
0048 : 2b dec hl
0049 : c9 ret
007e : ccle:
007e : cd9100 call cccmp
0081 : c8 ret z
0082 : d8 ret c
0083 : 2b dec hl
0084 : c9 ret
;Test if DE >= HL (signed)
004a : ccge:
004a : cd5600 call cccmp
004d : d0 ret nc
004e : 2b dec hl
004f : c9 ret
0085 : ccge:
0085 : cd9100 call cccmp
0088 : d0 ret nc
0089 : 2b dec hl
008a : c9 ret
;Test if DE < HL (signed)
AS80 Assembler for i8080-Z180 [1.11]. Page 5
--------------------------------- HELLO.ASM ----------------------------------
 
0050 : cclt:
0050 : cd5600 call cccmp
0053 : d8 ret c
0054 : 2b dec hl
0055 : c9 ret
008b : cclt:
008b : cd9100 call cccmp
008e : d8 ret c
008f : 2b dec hl
0090 : c9 ret
; Signed compare of DE and HL
; Performs DE - HL and sets the conditions:
; Carry reflects sign of difference (set means DE < HL
; Zero/non-zero set according to equality.
0056 : cccmp:
0056 : 7b ld a,e
0057 : 95 sub l
0058 : 5f ld e,a
0059 : 7a ld a,d
005a : 9c sbc h
005b : 210100 ld hl,1
005e : fa6300 jp m,cccmp1
0061 : b3 or e ;"OR" resets carry
0062 : c9 ret
0063 : cccmp1:
0063 : b3 or e
0064 : 37 scf ;set carry to signal minus
0065 : c9 ret
0091 : cccmp:
0091 : 7b ld a,e
0092 : 95 sub l
0093 : 5f ld e,a
0094 : 7a ld a,d
0095 : 9c sbc h
0096 : 210100 ld hl,1
0099 : fa9e00 jp m,cccmp1
009c : b3 or e ;"OR" resets carry
009d : c9 ret
009e : cccmp1:
009e : b3 or e
009f : 37 scf ;set carry to signal minus
00a0 : c9 ret
;Test if DE >= HL (unsigned)
0066 : ccuge:
0066 : cd8000 call ccucmp
0069 : d0 ret nc
006a : 2b dec hl
006b : c9 ret
00a1 : ccuge:
00a1 : cdbb00 call ccucmp
00a4 : d0 ret nc
00a5 : 2b dec hl
00a6 : c9 ret
AS80 Assembler for i8080-Z180 [1.11]. Page 7
--------------------------------- HELLO.ASM ----------------------------------
 
;Test if DE < HL (unsigned)
006c : ccult:
006c : cd8000 call ccucmp
006f : d8 ret c
0070 : 2b dec hl
0071 : c9 ret
00a7 : ccult:
00a7 : cdbb00 call ccucmp
00aa : d8 ret c
00ab : 2b dec hl
00ac : c9 ret
;Test if DE > HL (unsigned)
0072 : ccugt:
0072 : eb ex de,hl
0073 : cd8000 call ccucmp
0076 : d8 ret c
0077 : 2b dec hl
0078 : c9 ret
00ad : ccugt:
00ad : eb ex de,hl
00ae : cdbb00 call ccucmp
00b1 : d8 ret c
00b2 : 2b dec hl
00b3 : c9 ret
;Test if DE <= HL (unsigned)
0079 : ccule:
0079 : cd8000 call ccucmp
007c : c8 ret z
007d : d8 ret c
007e : 2b dec hl
007f : c9 ret
00b4 : ccule:
00b4 : cdbb00 call ccucmp
00b7 : c8 ret z
00b8 : d8 ret c
00b9 : 2b dec hl
00ba : c9 ret
;Routine to perform unsigned compare
;carry set if DE < HL
;zero/nonzero set accordingly
0080 : ccucmp:
0080 : 7a ld a,d
0081 : bc cp h
0082 : c28700 jp nz,$+5
0085 : 7b ld a,e
0086 : bd cp l
0087 : 210100 ld hl,1
008a : c9 ret
00bb : ccucmp:
00bb : 7a ld a,d
00bc : bc cp h
00bd : c2c200 jp nz,$+5
00c0 : 7b ld a,e
00c1 : bd cp l
00c2 : 210100 ld hl,1
00c5 : c9 ret
;Shift DE arithmetically right by HL and return in HL
008b : ccasr:
AS80 Assembler for i8080-Z180 [1.11]. Page 6
--------------------------------- HELLO.ASM ----------------------------------
 
008b : eb ex de,hl
008c : 7c ld a,h
008d : 17 rla
008e : 7c ld a,h
008f : 1f rra
0090 : 67 ld h,a
0091 : 7d ld a,l
0092 : 1f rra
0093 : 6f ld l,a
0094 : 1d dec e
0095 : c28c00 jp nz,ccasr+1
0098 : c9 ret
00c6 : ccasr:
00c6 : eb ex de,hl
00c7 : 7c ld a,h
00c8 : 17 rla
00c9 : 7c ld a,h
00ca : 1f rra
00cb : 67 ld h,a
00cc : 7d ld a,l
00cd : 1f rra
00ce : 6f ld l,a
00cf : 1d dec e
00d0 : c2c700 jp nz,ccasr+1
00d3 : c9 ret
;Shift DE arithmetically left by HL and return in HL
0099 : ccasl:
0099 : eb ex de,hl
009a : 29 add hl,hl
009b : 1d dec e
009c : c29a00 jp nz,ccasl+1
009f : c9 ret
00d4 : ccasl:
00d4 : eb ex de,hl
00d5 : 29 add hl,hl
00d6 : 1d dec e
00d7 : c2d500 jp nz,ccasl+1
00da : c9 ret
;Subtract HL from DE and return in HL
00a0 : ccsub:
00a0 : 7b ld a,e
00a1 : 95 sub l
00a2 : 6f ld l,a
00a3 : 7a ld a,d
00a4 : 9c sbc h
00a5 : 67 ld h,a
00a6 : c9 ret
00db : ccsub:
00db : 7b ld a,e
00dc : 95 sub l
00dd : 6f ld l,a
00de : 7a ld a,d
00df : 9c sbc h
00e0 : 67 ld h,a
00e1 : c9 ret
;Form the two's complement of HL
00a7 : ccneg:
00a7 : cdac00 call cccom
00aa : 23 inc hl
00ab : c9 ret
AS80 Assembler for i8080-Z180 [1.11]. Page 8
--------------------------------- HELLO.ASM ----------------------------------
 
00e2 : ccneg:
00e2 : cde700 call cccom
00e5 : 23 inc hl
00e6 : c9 ret
;Form the one's complement of HL
00ac : cccom:
00ac : 7c ld a,h
00ad : 2f cpl
00ae : 67 ld h,a
00af : 7d ld a,l
00b0 : 2f cpl
00b1 : 6f ld l,a
00b2 : c9 ret
00e7 : cccom:
00e7 : 7c ld a,h
00e8 : 2f cpl
00e9 : 67 ld h,a
00ea : 7d ld a,l
00eb : 2f cpl
00ec : 6f ld l,a
00ed : c9 ret
;Multiply DE by HL and return in HL
00b3 : ccmult:
00b3 : 44 ld b,h
00b4 : 4d ld c,l
00b5 : 210000 ld hl,0
00b8 : ccmult1:
00b8 : 79 ld a,c
00b9 : 0f rrca
00ba : d2be00 jp nc,$+4
00bd : 19 add hl,de
00be : af xor a
00bf : 78 ld a,b
00c0 : 1f rra
00c1 : 47 ld b,a
00c2 : 79 ld a,c
00c3 : 1f rra
00c4 : 4f ld c,a
00c5 : b0 or b
00c6 : c8 ret z
00c7 : af xor a
AS80 Assembler for i8080-Z180 [1.11]. Page 7
--------------------------------- HELLO.ASM ----------------------------------
 
00c8 : 7b ld a,e
00c9 : 17 rla
00ca : 5f ld e,a
00cb : 7a ld a,d
00cc : 17 rla
00cd : 57 ld d,a
00ce : b3 or e
00cf : c8 ret z
00d0 : c3b800 jp ccmult1
00ee : ccmult:
00ee : 44 ld b,h
00ef : 4d ld c,l
00f0 : 210000 ld hl,0
00f3 : ccmult1:
00f3 : 79 ld a,c
00f4 : 0f rrca
00f5 : d2f900 jp nc,$+4
00f8 : 19 add hl,de
00f9 : af xor a
00fa : 78 ld a,b
00fb : 1f rra
00fc : 47 ld b,a
00fd : 79 ld a,c
00fe : 1f rra
00ff : 4f ld c,a
0100 : b0 or b
0101 : c8 ret z
0102 : af xor a
0103 : 7b ld a,e
0104 : 17 rla
0105 : 5f ld e,a
0106 : 7a ld a,d
0107 : 17 rla
0108 : 57 ld d,a
0109 : b3 or e
010a : c8 ret z
010b : c3f300 jp ccmult1
;Divide DE by HL and return quotient in HL, remainder
00d3 : ccdiv:
00d3 : 44 ld b,h
00d4 : 4d ld c,l
00d5 : 7a ld a,d
00d6 : a8 xor b
00d7 : f5 push af
00d8 : 7a ld a,d
00d9 : b7 or a
00da : fc1401 call m,ccdeneg
00dd : 78 ld a,b
00de : b7 or a
00df : fc1c01 call m,ccbcneg
00e2 : 3e10 ld a,16
00e4 : f5 push af
00e5 : eb ex de,hl
00e6 : 110000 ld de,0
00e9 : ccdiv1:
00e9 : 29 add hl,hl
00ea : cd2401 call ccrdel
00ed : ca0001 jp z,ccdiv2
00f0 : cd2c01 call cccmpbcde
00f3 : fa0001 jp m,ccdiv2
00f6 : 7d ld a,l
00f7 : f601 or 1
00f9 : 6f ld l,a
00fa : 7b ld a,e
00fb : 91 sub c
00fc : 5f ld e,a
00fd : 7a ld a,d
00fe : 98 sbc b
00ff : 57 ld d,a
0100 : ccdiv2:
0100 : f1 pop af
0101 : 3d dec a
0102 : ca0901 jp z,ccdiv3
0105 : f5 push af
0106 : c3e900 jp ccdiv1
0109 : ccdiv3:
0109 : f1 pop af
010a : f0 ret p
010b : cd1401 call ccdeneg
010e : eb ex de,hl
010f : cd1401 call ccdeneg
0112 : eb ex de,hl
0113 : c9 ret
0114 : ccdeneg:
0114 : 7a ld a,d
0115 : 2f cpl
0116 : 57 ld d,a
0117 : 7b ld a,e
0118 : 2f cpl
0119 : 5f ld e,a
AS80 Assembler for i8080-Z180 [1.11]. Page 8
010e : ccdiv:
010e : 44 ld b,h
010f : 4d ld c,l
0110 : 7a ld a,d
0111 : a8 xor b
0112 : f5 push af
0113 : 7a ld a,d
0114 : b7 or a
0115 : fc4f01 call m,ccdeneg
0118 : 78 ld a,b
0119 : b7 or a
011a : fc5701 call m,ccbcneg
011d : 3e10 ld a,16
011f : f5 push af
0120 : eb ex de,hl
0121 : 110000 ld de,0
0124 : ccdiv1:
0124 : 29 add hl,hl
0125 : cd5f01 call ccrdel
AS80 Assembler for i8080-Z180 [1.11]. Page 9
--------------------------------- HELLO.ASM ----------------------------------
 
011a : 13 inc de
011b : c9 ret
011c : ccbcneg:
011c : 78 ld a,b
011d : 2f cpl
011e : 47 ld b,a
011f : 79 ld a,c
0120 : 2f cpl
0121 : 4f ld c,a
0122 : 03 inc bc
0123 : c9 ret
0124 : ccrdel:
0124 : 7b ld a,e
0125 : 17 rla
0126 : 5f ld e,a
0127 : 7a ld a,d
0128 : 17 rla
0129 : 57 ld d,a
012a : b3 or e
012b : c9 ret
012c : cccmpbcde:
012c : 7b ld a,e
012d : 91 sub c
012e : 7a ld a,d
012f : 98 sbc b
0130 : c9 ret
0128 : ca3b01 jp z,ccdiv2
012b : cd6701 call cccmpbcde
012e : fa3b01 jp m,ccdiv2
0131 : 7d ld a,l
0132 : f601 or 1
0134 : 6f ld l,a
0135 : 7b ld a,e
0136 : 91 sub c
0137 : 5f ld e,a
0138 : 7a ld a,d
0139 : 98 sbc b
013a : 57 ld d,a
013b : ccdiv2:
013b : f1 pop af
013c : 3d dec a
013d : ca4401 jp z,ccdiv3
0140 : f5 push af
0141 : c32401 jp ccdiv1
0144 : ccdiv3:
0144 : f1 pop af
0145 : f0 ret p
0146 : cd4f01 call ccdeneg
0149 : eb ex de,hl
014a : cd4f01 call ccdeneg
014d : eb ex de,hl
014e : c9 ret
014f : ccdeneg:
014f : 7a ld a,d
0150 : 2f cpl
0151 : 57 ld d,a
0152 : 7b ld a,e
0153 : 2f cpl
0154 : 5f ld e,a
0155 : 13 inc de
0156 : c9 ret
0157 : ccbcneg:
0157 : 78 ld a,b
0158 : 2f cpl
0159 : 47 ld b,a
015a : 79 ld a,c
015b : 2f cpl
015c : 4f ld c,a
015d : 03 inc bc
015e : c9 ret
015f : ccrdel:
015f : 7b ld a,e
0160 : 17 rla
0161 : 5f ld e,a
0162 : 7a ld a,d
0163 : 17 rla
0164 : 57 ld d,a
0165 : b3 or e
0166 : c9 ret
0167 : cccmpbcde:
0167 : 7b ld a,e
0168 : 91 sub c
0169 : 7a ld a,d
016a : 98 sbc b
016b : c9 ret
;// UART IO registers
;port (128) UDATA; // uart data register used for bot
;port (129) UBAUDL; // low byte of baud rate register
AS80 Assembler for i8080-Z180 [1.11]. Page 10
--------------------------------- HELLO.ASM ----------------------------------
 
;port (130) UBAUDH; // low byte of baud rate register
;port (131) USTAT; // uart status register
;// digital IO ports registers
;port (132) P1REG; // output port1 - used as firs
;port (133) P2REG; // output port2 - used as low digi
;port (134) P3REG; // output port3 - used as high dig
;port (135) P4REG; // output port4
;port (132) P1DATA; // port 1 data register
;port (133) P1DIR; // port 1 direction register contr
;port (134) P2DATA; // port 2 data register
;port (135) P2DIR; // port 2 direction register contr
;// interrupt controller register
;port (136) INTRENA; // interrupts enable register
;// simulation end register
;// writing any value to this port will end the verilo
;// test bench.
452,435 → 556,492
;//---------------------------------------------------
;// send a single byte to the UART
;sendbyte(by)
0131 : __sendbyte:
016c : __sendbyte:
;char by;
;{
; while (USTAT & UTXBUSY);
0131 : cc2:
0131 : db83 in a,(131)
0133 : cf call ccsxt
0134 : e5 push hl
0135 : 210100 ld hl,1
0138 : d1 pop de
0139 : cd2900 call ccand
013c : 7c ld a,h
AS80 Assembler for i8080-Z180 [1.11]. Page 9
--------------------------------- HELLO.ASM ----------------------------------
 
013d : b5 or l
013e : ca4401 jp z,cc3
0141 : c33101 jp cc2
0144 : cc3:
016c : cc2:
016c : db83 in a,(131)
016e : cd4300 call ccsxt
0171 : e5 push hl
0172 : 210100 ld hl,1
0175 : d1 pop de
0176 : cd6400 call ccand
0179 : 7c ld a,h
017a : b5 or l
017b : ca8101 jp z,cc3
017e : c36c01 jp cc2
0181 : cc3:
; UDATA = by;
0144 : 210200 ld hl,2
0147 : 39 add hl,sp
0148 : cd0700 call ccgchar
014b : 7d ld a,l
014c : d380 out (128),a
0181 : 210200 ld hl,2
0184 : 39 add hl,sp
0185 : cd4200 call ccgchar
0188 : 7d ld a,l
0189 : d380 out (128),a
;}
014e : c9 ret
018b : c9 ret
;// check if a byte was received by the uart
;getbyte()
014f : __getbyte:
018c : __getbyte:
;{
; if (USTAT & URXFULL) {
014f : db83 in a,(131)
0151 : cf call ccsxt
0152 : e5 push hl
0153 : 211000 ld hl,16
0156 : d1 pop de
0157 : cd2900 call ccand
015a : 7c ld a,h
015b : b5 or l
015c : ca6d01 jp z,cc4
018c : db83 in a,(131)
018e : cd4300 call ccsxt
0191 : e5 push hl
0192 : 211000 ld hl,16
0195 : d1 pop de
0196 : cd6400 call ccand
0199 : 7c ld a,h
019a : b5 or l
019b : caae01 jp z,cc4
AS80 Assembler for i8080-Z180 [1.11]. Page 11
--------------------------------- HELLO.ASM ----------------------------------
 
; rxbyte = UDATA;
015f : db80 in a,(128)
0161 : cf call ccsxt
0162 : 7d ld a,l
0163 : 329e03 ld (__rxbyte),a
019e : db80 in a,(128)
01a0 : cd4300 call ccsxt
01a3 : 7d ld a,l
01a4 : 322c04 ld (__rxbyte),a
; return 1;
0166 : 210100 ld hl,1
0169 : c9 ret
01a7 : 210100 ld hl,1
01aa : c9 ret
; }
; else
016a : c37101 jp cc5
016d : cc4:
01ab : c3b201 jp cc5
01ae : cc4:
; return 0;
016d : 210000 ld hl,0
0170 : c9 ret
0171 : cc5:
01ae : 210000 ld hl,0
01b1 : c9 ret
01b2 : cc5:
;}
0171 : c9 ret
01b2 : c9 ret
;// send new line to the UART
;nl()
0172 : __nl:
01b3 : __nl:
;{
; sendbyte(13);
0172 : 210d00 ld hl,13
0175 : e5 push hl
0176 : cd3101 call __sendbyte
0179 : c1 pop bc
01b3 : 210d00 ld hl,13
01b6 : e5 push hl
01b7 : cd6c01 call __sendbyte
01ba : c1 pop bc
; sendbyte(10);
017a : 210a00 ld hl,10
017d : e5 push hl
017e : cd3101 call __sendbyte
0181 : c1 pop bc
01bb : 210a00 ld hl,10
01be : e5 push hl
01bf : cd6c01 call __sendbyte
01c2 : c1 pop bc
;}
0182 : c9 ret
01c3 : c9 ret
;// sends a string to the UART
AS80 Assembler for i8080-Z180 [1.11]. Page 10
--------------------------------- HELLO.ASM ----------------------------------
 
;printstr(sptr)
0183 : __printstr:
01c4 : __printstr:
;char *sptr;
;{
; while (*sptr != 0)
0183 : cc6:
0183 : 210200 ld hl,2
0186 : 39 add hl,sp
0187 : cd0d00 call ccgint
018a : cd0700 call ccgchar
018d : e5 push hl
018e : 210000 ld hl,0
0191 : d1 pop de
0192 : cd3600 call ccne
0195 : 7c ld a,h
0196 : b5 or l
0197 : cab301 jp z,cc7
01c4 : cc6:
01c4 : 210200 ld hl,2
01c7 : 39 add hl,sp
01c8 : cd4800 call ccgint
01cb : cd4200 call ccgchar
01ce : e5 push hl
01cf : 210000 ld hl,0
01d2 : d1 pop de
01d3 : cd7100 call ccne
01d6 : 7c ld a,h
01d7 : b5 or l
01d8 : caf401 jp z,cc7
; sendbyte(*sptr++);
019a : 210200 ld hl,2
019d : 39 add hl,sp
019e : e5 push hl
019f : cd0d00 call ccgint
01a2 : 23 inc hl
01a3 : d1 pop de
01a4 : cd1500 call ccpint
01a7 : 2b dec hl
01a8 : cd0700 call ccgchar
01ab : e5 push hl
01ac : cd3101 call __sendbyte
01af : c1 pop bc
01b0 : c38301 jp cc6
01b3 : cc7:
01db : 210200 ld hl,2
01de : 39 add hl,sp
01df : e5 push hl
01e0 : cd4800 call ccgint
01e3 : 23 inc hl
01e4 : d1 pop de
01e5 : cd5000 call ccpint
01e8 : 2b dec hl
01e9 : cd4200 call ccgchar
AS80 Assembler for i8080-Z180 [1.11]. Page 12
--------------------------------- HELLO.ASM ----------------------------------
 
01ec : e5 push hl
01ed : cd6c01 call __sendbyte
01f0 : c1 pop bc
01f1 : c3c401 jp cc6
01f4 : cc7:
;}
01b3 : c9 ret
01f4 : c9 ret
;// sends a decimal value to the UART
;printdec(dval)
01b4 : __printdec:
01f5 : __printdec:
;int dval;
;{
; if (dval<0) {
01b4 : 210200 ld hl,2
01b7 : 39 add hl,sp
01b8 : cd0d00 call ccgint
01bb : e5 push hl
01bc : 210000 ld hl,0
01bf : d1 pop de
01c0 : cd5000 call cclt
01c3 : 7c ld a,h
01c4 : b5 or l
01c5 : cae301 jp z,cc8
01f5 : 210200 ld hl,2
01f8 : 39 add hl,sp
01f9 : cd4800 call ccgint
01fc : e5 push hl
01fd : 210000 ld hl,0
0200 : d1 pop de
0201 : cd8b00 call cclt
0204 : 7c ld a,h
0205 : b5 or l
0206 : ca2402 jp z,cc8
; sendbyte('-');
01c8 : 212d00 ld hl,45
01cb : e5 push hl
01cc : cd3101 call __sendbyte
01cf : c1 pop bc
0209 : 212d00 ld hl,45
020c : e5 push hl
020d : cd6c01 call __sendbyte
0210 : c1 pop bc
; dval = -dval;
01d0 : 210200 ld hl,2
01d3 : 39 add hl,sp
01d4 : e5 push hl
01d5 : 210400 ld hl,4
01d8 : 39 add hl,sp
01d9 : cd0d00 call ccgint
AS80 Assembler for i8080-Z180 [1.11]. Page 11
--------------------------------- HELLO.ASM ----------------------------------
 
01dc : cda700 call ccneg
01df : d1 pop de
01e0 : cd1500 call ccpint
0211 : 210200 ld hl,2
0214 : 39 add hl,sp
0215 : e5 push hl
0216 : 210400 ld hl,4
0219 : 39 add hl,sp
021a : cd4800 call ccgint
021d : cde200 call ccneg
0220 : d1 pop de
0221 : cd5000 call ccpint
; }
; outint(dval);
01e3 : cc8:
01e3 : 210200 ld hl,2
01e6 : 39 add hl,sp
01e7 : cd0d00 call ccgint
01ea : e5 push hl
01eb : cdf001 call __outint
01ee : c1 pop bc
0224 : cc8:
0224 : 210200 ld hl,2
0227 : 39 add hl,sp
0228 : cd4800 call ccgint
022b : e5 push hl
022c : cd3102 call __outint
022f : c1 pop bc
;}
01ef : c9 ret
0230 : c9 ret
;// function copied from c80dos.c
;outint(n)
01f0 : __outint:
0231 : __outint:
;int n;
;{
;int q;
01f0 : c5 push bc
0231 : c5 push bc
; q = n/10;
01f1 : 210000 ld hl,0
01f4 : 39 add hl,sp
01f5 : e5 push hl
01f6 : 210600 ld hl,6
01f9 : 39 add hl,sp
01fa : cd0d00 call ccgint
01fd : e5 push hl
01fe : 210a00 ld hl,10
0201 : d1 pop de
0202 : cdd300 call ccdiv
0205 : d1 pop de
0206 : cd1500 call ccpint
0232 : 210000 ld hl,0
0235 : 39 add hl,sp
0236 : e5 push hl
0237 : 210600 ld hl,6
023a : 39 add hl,sp
AS80 Assembler for i8080-Z180 [1.11]. Page 13
--------------------------------- HELLO.ASM ----------------------------------
 
023b : cd4800 call ccgint
023e : e5 push hl
023f : 210a00 ld hl,10
0242 : d1 pop de
0243 : cd0e01 call ccdiv
0246 : d1 pop de
0247 : cd5000 call ccpint
; if (q) outint(q);
0209 : 210000 ld hl,0
020c : 39 add hl,sp
020d : cd0d00 call ccgint
0210 : 7c ld a,h
0211 : b5 or l
0212 : ca2102 jp z,cc9
0215 : 210000 ld hl,0
0218 : 39 add hl,sp
0219 : cd0d00 call ccgint
021c : e5 push hl
021d : cdf001 call __outint
0220 : c1 pop bc
024a : 210000 ld hl,0
024d : 39 add hl,sp
024e : cd4800 call ccgint
0251 : 7c ld a,h
0252 : b5 or l
0253 : ca6202 jp z,cc9
0256 : 210000 ld hl,0
0259 : 39 add hl,sp
025a : cd4800 call ccgint
025d : e5 push hl
025e : cd3102 call __outint
0261 : c1 pop bc
; sendbyte('0'+(n-q*10));
0221 : cc9:
0221 : 213000 ld hl,48
0224 : e5 push hl
0225 : 210600 ld hl,6
0228 : 39 add hl,sp
0229 : cd0d00 call ccgint
022c : e5 push hl
022d : 210400 ld hl,4
0230 : 39 add hl,sp
0231 : cd0d00 call ccgint
0234 : e5 push hl
0235 : 210a00 ld hl,10
0238 : d1 pop de
0239 : cdb300 call ccmult
AS80 Assembler for i8080-Z180 [1.11]. Page 12
--------------------------------- HELLO.ASM ----------------------------------
 
023c : d1 pop de
023d : cda000 call ccsub
0240 : d1 pop de
0241 : 19 add hl,de
0242 : e5 push hl
0243 : cd3101 call __sendbyte
0246 : c1 pop bc
0262 : cc9:
0262 : 213000 ld hl,48
0265 : e5 push hl
0266 : 210600 ld hl,6
0269 : 39 add hl,sp
026a : cd4800 call ccgint
026d : e5 push hl
026e : 210400 ld hl,4
0271 : 39 add hl,sp
0272 : cd4800 call ccgint
0275 : e5 push hl
0276 : 210a00 ld hl,10
0279 : d1 pop de
027a : cdee00 call ccmult
027d : d1 pop de
027e : cddb00 call ccsub
0281 : d1 pop de
0282 : 19 add hl,de
0283 : e5 push hl
0284 : cd6c01 call __sendbyte
0287 : c1 pop bc
;}
0247 : c1 pop bc
0248 : c9 ret
0288 : c1 pop bc
0289 : c9 ret
;// sends a hexadecimal value to the UART
;printhex(hval)
0249 : __printhex:
028a : __printhex:
;int hval;
;{
;int q;
0249 : c5 push bc
028a : c5 push bc
; q = hval/16;
024a : 210000 ld hl,0
024d : 39 add hl,sp
024e : e5 push hl
024f : 210600 ld hl,6
0252 : 39 add hl,sp
0253 : cd0d00 call ccgint
0256 : e5 push hl
0257 : 211000 ld hl,16
025a : d1 pop de
025b : cdd300 call ccdiv
025e : d1 pop de
025f : cd1500 call ccpint
028b : 210000 ld hl,0
028e : 39 add hl,sp
028f : e5 push hl
0290 : 210600 ld hl,6
0293 : 39 add hl,sp
0294 : cd4800 call ccgint
0297 : e5 push hl
0298 : 211000 ld hl,16
029b : d1 pop de
AS80 Assembler for i8080-Z180 [1.11]. Page 14
--------------------------------- HELLO.ASM ----------------------------------
 
029c : cd0e01 call ccdiv
029f : d1 pop de
02a0 : cd5000 call ccpint
; if (q) printhex(q);
0262 : 210000 ld hl,0
0265 : 39 add hl,sp
0266 : cd0d00 call ccgint
0269 : 7c ld a,h
026a : b5 or l
026b : ca7a02 jp z,cc10
026e : 210000 ld hl,0
0271 : 39 add hl,sp
0272 : cd0d00 call ccgint
0275 : e5 push hl
0276 : cd4902 call __printhex
0279 : c1 pop bc
02a3 : 210000 ld hl,0
02a6 : 39 add hl,sp
02a7 : cd4800 call ccgint
02aa : 7c ld a,h
02ab : b5 or l
02ac : cabb02 jp z,cc10
02af : 210000 ld hl,0
02b2 : 39 add hl,sp
02b3 : cd4800 call ccgint
02b6 : e5 push hl
02b7 : cd8a02 call __printhex
02ba : c1 pop bc
; q = hval-q*16;
027a : cc10:
027a : 210000 ld hl,0
027d : 39 add hl,sp
027e : e5 push hl
027f : 210600 ld hl,6
0282 : 39 add hl,sp
0283 : cd0d00 call ccgint
0286 : e5 push hl
0287 : 210400 ld hl,4
028a : 39 add hl,sp
028b : cd0d00 call ccgint
028e : e5 push hl
028f : 211000 ld hl,16
0292 : d1 pop de
0293 : cdb300 call ccmult
0296 : d1 pop de
0297 : cda000 call ccsub
029a : d1 pop de
AS80 Assembler for i8080-Z180 [1.11]. Page 13
02bb : cc10:
02bb : 210000 ld hl,0
02be : 39 add hl,sp
02bf : e5 push hl
02c0 : 210600 ld hl,6
02c3 : 39 add hl,sp
02c4 : cd4800 call ccgint
02c7 : e5 push hl
02c8 : 210400 ld hl,4
02cb : 39 add hl,sp
02cc : cd4800 call ccgint
02cf : e5 push hl
02d0 : 211000 ld hl,16
02d3 : d1 pop de
02d4 : cdee00 call ccmult
02d7 : d1 pop de
02d8 : cddb00 call ccsub
02db : d1 pop de
02dc : cd5000 call ccpint
; if (q > 9)
02df : 210000 ld hl,0
02e2 : 39 add hl,sp
02e3 : cd4800 call ccgint
02e6 : e5 push hl
02e7 : 210900 ld hl,9
02ea : d1 pop de
02eb : cd7700 call ccgt
02ee : 7c ld a,h
02ef : b5 or l
02f0 : ca1003 jp z,cc11
; sendbyte('A'+q-10);
02f3 : 214100 ld hl,65
02f6 : e5 push hl
02f7 : 210200 ld hl,2
02fa : 39 add hl,sp
02fb : cd4800 call ccgint
02fe : d1 pop de
02ff : 19 add hl,de
0300 : e5 push hl
0301 : 210a00 ld hl,10
0304 : d1 pop de
0305 : cddb00 call ccsub
0308 : e5 push hl
0309 : cd6c01 call __sendbyte
030c : c1 pop bc
AS80 Assembler for i8080-Z180 [1.11]. Page 15
--------------------------------- HELLO.ASM ----------------------------------
 
029b : cd1500 call ccpint
; if (q > 9)
029e : 210000 ld hl,0
02a1 : 39 add hl,sp
02a2 : cd0d00 call ccgint
02a5 : e5 push hl
02a6 : 210900 ld hl,9
02a9 : d1 pop de
02aa : cd3c00 call ccgt
02ad : 7c ld a,h
02ae : b5 or l
02af : cacf02 jp z,cc11
; sendbyte('A'+q-10);
02b2 : 214100 ld hl,65
02b5 : e5 push hl
02b6 : 210200 ld hl,2
02b9 : 39 add hl,sp
02ba : cd0d00 call ccgint
02bd : d1 pop de
02be : 19 add hl,de
02bf : e5 push hl
02c0 : 210a00 ld hl,10
02c3 : d1 pop de
02c4 : cda000 call ccsub
02c7 : e5 push hl
02c8 : cd3101 call __sendbyte
02cb : c1 pop bc
; else
02cc : c3e102 jp cc12
02cf : cc11:
030d : c32203 jp cc12
0310 : cc11:
; sendbyte('0'+q);
02cf : 213000 ld hl,48
02d2 : e5 push hl
02d3 : 210200 ld hl,2
02d6 : 39 add hl,sp
02d7 : cd0d00 call ccgint
02da : d1 pop de
02db : 19 add hl,de
02dc : e5 push hl
02dd : cd3101 call __sendbyte
02e0 : c1 pop bc
02e1 : cc12:
0310 : 213000 ld hl,48
0313 : e5 push hl
0314 : 210200 ld hl,2
0317 : 39 add hl,sp
0318 : cd4800 call ccgint
031b : d1 pop de
031c : 19 add hl,de
031d : e5 push hl
031e : cd6c01 call __sendbyte
0321 : c1 pop bc
0322 : cc12:
;}
02e1 : c1 pop bc
02e2 : c9 ret
0322 : c1 pop bc
0323 : c9 ret
;// external interrupt 0 service routine
;int0_isr()
0324 : __int0_isr:
;{
; printstr("Interrupt 0 was asserted."); nl();
0324 : 21d003 ld hl,cc1+0
0327 : e5 push hl
0328 : cdc401 call __printstr
032b : c1 pop bc
032c : cdb301 call __nl
;}
032f : c9 ret
;// program main routine
;main()
02e3 : __main:
0330 : __main:
;{
; // configure UART baud rate - set to 9600 for 30MHz
; // BAUD = round(<clock>/<baud rate>/16) = round(30e6
; UBAUDL = 195;
02e3 : 21c300 ld hl,195
02e6 : 7d ld a,l
02e7 : d381 out (129),a
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT
;// UBAUDL = 195;
; UBAUDL = 1;
0330 : 210100 ld hl,1
0333 : 7d ld a,l
0334 : d381 out (129),a
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT
;//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOT
; UBAUDH = 0;
02e9 : 210000 ld hl,0
02ec : 7d ld a,l
02ed : d382 out (130),a
0336 : 210000 ld hl,0
0339 : 7d ld a,l
033a : d382 out (130),a
; // print message
AS80 Assembler for i8080-Z180 [1.11]. Page 14
; // configure both ports to output and digital output
; P1DATA = 0x00;
033c : 210000 ld hl,0
033f : 7d ld a,l
0340 : d384 out (132),a
; P1DIR = 0xff;
0342 : 21ff00 ld hl,255
0345 : 7d ld a,l
0346 : d385 out (133),a
AS80 Assembler for i8080-Z180 [1.11]. Page 16
--------------------------------- HELLO.ASM ----------------------------------
 
; P2DATA = 0x00;
0348 : 210000 ld hl,0
034b : 7d ld a,l
034c : d386 out (134),a
; P2DIR = 0xff;
034e : 21ff00 ld hl,255
0351 : 7d ld a,l
0352 : d387 out (135),a
; // enable interrupt 0 only
; INTRENA = 0x01;
0354 : 210100 ld hl,1
0357 : 7d ld a,l
0358 : d388 out (136),a
; // enable CPU interrupt
;#asm
035a : fb ei
;
; // print message
; printstr("Hello World!!!"); nl();
02ef : 215c03 ld hl,cc1+0
02f2 : e5 push hl
02f3 : cd8301 call __printstr
02f6 : c1 pop bc
02f7 : cd7201 call __nl
035b : 21ea03 ld hl,cc1+26
035e : e5 push hl
035f : cdc401 call __printstr
0362 : c1 pop bc
0363 : cdb301 call __nl
; printstr("Dec value: "); printdec(tstary[1]); nl();
02fa : 216b03 ld hl,cc1+15
02fd : e5 push hl
02fe : cd8301 call __printstr
0301 : c1 pop bc
0302 : 219f03 ld hl,__tstary
0305 : e5 push hl
0306 : 210100 ld hl,1
0309 : 29 add hl,hl
030a : d1 pop de
030b : 19 add hl,de
030c : cd0d00 call ccgint
030f : e5 push hl
0310 : cdb401 call __printdec
0313 : c1 pop bc
0314 : cd7201 call __nl
0366 : 21f903 ld hl,cc1+41
0369 : e5 push hl
036a : cdc401 call __printstr
036d : c1 pop bc
036e : 212d04 ld hl,__tstary
0371 : e5 push hl
0372 : 210100 ld hl,1
0375 : 29 add hl,hl
0376 : d1 pop de
0377 : 19 add hl,de
0378 : cd4800 call ccgint
037b : e5 push hl
037c : cdf501 call __printdec
037f : c1 pop bc
0380 : cdb301 call __nl
; printstr("Hex value: 0x"); printhex(tstary[0]); nl()
0317 : 217703 ld hl,cc1+27
031a : e5 push hl
031b : cd8301 call __printstr
031e : c1 pop bc
031f : 219f03 ld hl,__tstary
0322 : e5 push hl
0323 : 210000 ld hl,0
0326 : 29 add hl,hl
0327 : d1 pop de
0328 : 19 add hl,de
0329 : cd0d00 call ccgint
032c : e5 push hl
032d : cd4902 call __printhex
0330 : c1 pop bc
0331 : cd7201 call __nl
0383 : 210504 ld hl,cc1+53
0386 : e5 push hl
0387 : cdc401 call __printstr
038a : c1 pop bc
038b : 212d04 ld hl,__tstary
038e : e5 push hl
038f : 210000 ld hl,0
0392 : 29 add hl,hl
0393 : d1 pop de
0394 : 19 add hl,de
0395 : cd4800 call ccgint
0398 : e5 push hl
0399 : cd8a02 call __printhex
039c : c1 pop bc
039d : cdb301 call __nl
; // assert bit 0 of port 1 to test external interrupt
; P1DATA = 0x01;
03a0 : 210100 ld hl,1
AS80 Assembler for i8080-Z180 [1.11]. Page 17
--------------------------------- HELLO.ASM ----------------------------------
 
03a3 : 7d ld a,l
03a4 : d384 out (132),a
;
; printstr("Echoing received bytes: "); nl();
0334 : 218503 ld hl,cc1+41
0337 : e5 push hl
0338 : cd8301 call __printstr
033b : c1 pop bc
033c : cd7201 call __nl
;
03a6 : 211304 ld hl,cc1+67
03a9 : e5 push hl
03aa : cdc401 call __printstr
03ad : c1 pop bc
03ae : cdb301 call __nl
; // loop forever
; while (1) {
033f : cc13:
033f : 210100 ld hl,1
0342 : 7c ld a,h
0343 : b5 or l
0344 : ca5b03 jp z,cc14
03b1 : cc13:
03b1 : 210100 ld hl,1
03b4 : 7c ld a,h
03b5 : b5 or l
03b6 : cacf03 jp z,cc14
; // check if a new byte was received
; if (getbyte())
0347 : cd4f01 call __getbyte
034a : 7c ld a,h
034b : b5 or l
034c : ca5803 jp z,cc15
03b9 : cd8c01 call __getbyte
03bc : 7c ld a,h
03bd : b5 or l
03be : cacc03 jp z,cc15
; // echo the received byte to the UART
; sendbyte(rxbyte);
034f : 3a9e03 ld a,(__rxbyte)
0352 : cf call ccsxt
AS80 Assembler for i8080-Z180 [1.11]. Page 15
--------------------------------- HELLO.ASM ----------------------------------
 
0353 : e5 push hl
0354 : cd3101 call __sendbyte
0357 : c1 pop bc
03c1 : 3a2c04 ld a,(__rxbyte)
03c4 : cd4300 call ccsxt
03c7 : e5 push hl
03c8 : cd6c01 call __sendbyte
03cb : c1 pop bc
; }
0358 : cc15:
0358 : c33f03 jp cc13
035b : cc14:
03cc : cc15:
03cc : c3b103 jp cc13
03cf : cc14:
;}
035b : c9 ret
03cf : c9 ret
;//---------------------------------------------------
;// Th.. Th.. Th.. Thats all folks !!!
;//---------------------------------------------------
035c : cc1:
035c : 48656c6c6f2057.. db 72,101,108,108,111,32,87,111,114,108
0366 : 64212121004465.. db 100,33,33,33,0,68,101,99,32,118
0370 : 616c75653a2000.. db 97,108,117,101,58,32,0,72,101,120
037a : 2076616c75653a.. db 32,118,97,108,117,101,58,32,48,120
0384 : 004563686f696e.. db 0,69,99,104,111,105,110,103,32,114
038e : 65636569766564.. db 101,99,101,105,118,101,100,32,98,121
0398 : 7465733a2000 db 116,101,115,58,32,0
039e : __rxbyte:
039e : 00 ds 1
039f : __tstary:
039f : d2042e16 db -46,4,46,22
03d0 : cc1:
03d0 : 496e7465727275.. db 73,110,116,101,114,114,117,112,116,32
03da : 30207761732061.. db 48,32,119,97,115,32,97,115,115,101
03e4 : 727465642e0048.. db 114,116,101,100,46,0,72,101,108,108
03ee : 6f20576f726c64.. db 111,32,87,111,114,108,100,33,33,33
03f8 : 00446563207661.. db 0,68,101,99,32,118,97,108,117,101
0402 : 3a200048657820.. db 58,32,0,72,101,120,32,118,97,108
040c : 75653a20307800.. db 117,101,58,32,48,120,0,69,99,104
0416 : 6f696e67207265.. db 111,105,110,103,32,114,101,99,101,105
0420 : 76656420627974.. db 118,101,100,32,98,121,116,101,115,58
042a : 2000 db 32,0
042c : __rxbyte:
042c : 00 ds 1
042d : __tstary:
042d : d2042e16 db -46,4,46,22
; --- End of Compilation ---
No errors in pass 2.
/trunk/c/hello.c
8,6 → 8,8
// Description:
// This file contains a simple program written in Small-C that sends a string to
// the UART and then switches to echo received bytes.
// This example also include a simple interrupt example which will work with the
// verilog testbench. the testbench
//
// Revision History:
//
15,6 → 17,10
// <comment>
//---------------------------------------------------------------------------------------
 
// define interrupt vectors
// note that this file must be edited to enable interrupt used
#include intr_vec.h
// insert c80 assmbly library to the output file
#include ..\tools\c80\c80.lib
 
// UART IO registers
23,10 → 29,12
port (130) UBAUDH; // low byte of baud rate register
port (131) USTAT; // uart status register
// digital IO ports registers
port (132) P1REG; // output port1 - used as first attenuator control
port (133) P2REG; // output port2 - used as low digit LCD
port (134) P3REG; // output port3 - used as high digit LCD
port (135) P4REG; // output port4
port (132) P1DATA; // port 1 data register
port (133) P1DIR; // port 1 direction register control
port (134) P2DATA; // port 2 data register
port (135) P2DIR; // port 2 direction register control
// interrupt controller register
port (136) INTRENA; // interrupts enable register
// simulation end register
// writing any value to this port will end the verilog simulation when using tb_l80soc
// test bench.
113,20 → 121,46
sendbyte('0'+q);
}
 
// external interrupt 0 service routine
int0_isr()
{
printstr("Interrupt 0 was asserted."); nl();
}
 
// program main routine
main()
{
// configure UART baud rate - set to 9600 for 30MHz clock
// BAUD = round(<clock>/<baud rate>/16) = round(30e6/9600/16) = 195
UBAUDL = 195;
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
// UBAUDL = 195;
UBAUDL = 1;
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
//MOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTIMOTI
UBAUDH = 0;
 
// configure both ports to output and digital outputs as zeros
P1DATA = 0x00;
P1DIR = 0xff;
P2DATA = 0x00;
P2DIR = 0xff;
// enable interrupt 0 only
INTRENA = 0x01;
// enable CPU interrupt
#asm
ei
#endasm
// print message
printstr("Hello World!!!"); nl();
printstr("Dec value: "); printdec(tstary[1]); nl();
printstr("Hex value: 0x"); printhex(tstary[0]); nl();
 
// assert bit 0 of port 1 to test external interrupt 0
P1DATA = 0x01;
printstr("Echoing received bytes: "); nl();
// loop forever
while (1) {
// check if a new byte was received
135,7 → 169,6
sendbyte(rxbyte);
}
}
 
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
/trunk/c/ram_image.v
21,274 → 21,274
initial
begin
ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
ram[4] = 8'hcd; ram[5] = 8'he3; ram[6] = 8'h02; ram[7] = 8'h7e;
ram[8] = 8'h6f; ram[9] = 8'h07; ram[10] = 8'h9f; ram[11] = 8'h67;
ram[12] = 8'hc9; ram[13] = 8'h7e; ram[14] = 8'h23; ram[15] = 8'h66;
ram[16] = 8'h6f; ram[17] = 8'hc9; ram[18] = 8'h7d; ram[19] = 8'h12;
ram[20] = 8'hc9; ram[21] = 8'h7d; ram[22] = 8'h12; ram[23] = 8'h13;
ram[24] = 8'h7c; ram[25] = 8'h12; ram[26] = 8'hc9; ram[27] = 8'h7d;
ram[28] = 8'hb3; ram[29] = 8'h6f; ram[30] = 8'h7c; ram[31] = 8'hb2;
ram[32] = 8'h67; ram[33] = 8'hc9; ram[34] = 8'h7d; ram[35] = 8'hab;
ram[36] = 8'h6f; ram[37] = 8'h7c; ram[38] = 8'haa; ram[39] = 8'h67;
ram[40] = 8'hc9; ram[41] = 8'h7d; ram[42] = 8'ha3; ram[43] = 8'h6f;
ram[44] = 8'h7c; ram[45] = 8'ha2; ram[46] = 8'h67; ram[47] = 8'hc9;
ram[48] = 8'hcd; ram[49] = 8'h56; ram[50] = 8'h00; ram[51] = 8'hc8;
ram[52] = 8'h2b; ram[53] = 8'hc9; ram[54] = 8'hcd; ram[55] = 8'h56;
ram[56] = 8'h00; ram[57] = 8'hc0; ram[58] = 8'h2b; ram[59] = 8'hc9;
ram[60] = 8'heb; ram[61] = 8'hcd; ram[62] = 8'h56; ram[63] = 8'h00;
ram[64] = 8'hd8; ram[65] = 8'h2b; ram[66] = 8'hc9; ram[67] = 8'hcd;
ram[68] = 8'h56; ram[69] = 8'h00; ram[70] = 8'hc8; ram[71] = 8'hd8;
ram[72] = 8'h2b; ram[73] = 8'hc9; ram[74] = 8'hcd; ram[75] = 8'h56;
ram[76] = 8'h00; ram[77] = 8'hd0; ram[78] = 8'h2b; ram[79] = 8'hc9;
ram[80] = 8'hcd; ram[81] = 8'h56; ram[82] = 8'h00; ram[83] = 8'hd8;
ram[84] = 8'h2b; ram[85] = 8'hc9; ram[86] = 8'h7b; ram[87] = 8'h95;
ram[88] = 8'h5f; ram[89] = 8'h7a; ram[90] = 8'h9c; ram[91] = 8'h21;
ram[92] = 8'h01; ram[93] = 8'h00; ram[94] = 8'hfa; ram[95] = 8'h63;
ram[96] = 8'h00; ram[97] = 8'hb3; ram[98] = 8'hc9; ram[99] = 8'hb3;
ram[100] = 8'h37; ram[101] = 8'hc9; ram[102] = 8'hcd; ram[103] = 8'h80;
ram[104] = 8'h00; ram[105] = 8'hd0; ram[106] = 8'h2b; ram[107] = 8'hc9;
ram[108] = 8'hcd; ram[109] = 8'h80; ram[110] = 8'h00; ram[111] = 8'hd8;
ram[112] = 8'h2b; ram[113] = 8'hc9; ram[114] = 8'heb; ram[115] = 8'hcd;
ram[116] = 8'h80; ram[117] = 8'h00; ram[118] = 8'hd8; ram[119] = 8'h2b;
ram[120] = 8'hc9; ram[121] = 8'hcd; ram[122] = 8'h80; ram[123] = 8'h00;
ram[124] = 8'hc8; ram[125] = 8'hd8; ram[126] = 8'h2b; ram[127] = 8'hc9;
ram[128] = 8'h7a; ram[129] = 8'hbc; ram[130] = 8'hc2; ram[131] = 8'h87;
ram[132] = 8'h00; ram[133] = 8'h7b; ram[134] = 8'hbd; ram[135] = 8'h21;
ram[136] = 8'h01; ram[137] = 8'h00; ram[138] = 8'hc9; ram[139] = 8'heb;
ram[140] = 8'h7c; ram[141] = 8'h17; ram[142] = 8'h7c; ram[143] = 8'h1f;
ram[144] = 8'h67; ram[145] = 8'h7d; ram[146] = 8'h1f; ram[147] = 8'h6f;
ram[148] = 8'h1d; ram[149] = 8'hc2; ram[150] = 8'h8c; ram[151] = 8'h00;
ram[152] = 8'hc9; ram[153] = 8'heb; ram[154] = 8'h29; ram[155] = 8'h1d;
ram[156] = 8'hc2; ram[157] = 8'h9a; ram[158] = 8'h00; ram[159] = 8'hc9;
ram[160] = 8'h7b; ram[161] = 8'h95; ram[162] = 8'h6f; ram[163] = 8'h7a;
ram[164] = 8'h9c; ram[165] = 8'h67; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hac; ram[169] = 8'h00; ram[170] = 8'h23; ram[171] = 8'hc9;
ram[172] = 8'h7c; ram[173] = 8'h2f; ram[174] = 8'h67; ram[175] = 8'h7d;
ram[176] = 8'h2f; ram[177] = 8'h6f; ram[178] = 8'hc9; ram[179] = 8'h44;
ram[180] = 8'h4d; ram[181] = 8'h21; ram[182] = 8'h00; ram[183] = 8'h00;
ram[184] = 8'h79; ram[185] = 8'h0f; ram[186] = 8'hd2; ram[187] = 8'hbe;
ram[188] = 8'h00; ram[189] = 8'h19; ram[190] = 8'haf; ram[191] = 8'h78;
ram[192] = 8'h1f; ram[193] = 8'h47; ram[194] = 8'h79; ram[195] = 8'h1f;
ram[196] = 8'h4f; ram[197] = 8'hb0; ram[198] = 8'hc8; ram[199] = 8'haf;
ram[200] = 8'h7b; ram[201] = 8'h17; ram[202] = 8'h5f; ram[203] = 8'h7a;
ram[204] = 8'h17; ram[205] = 8'h57; ram[206] = 8'hb3; ram[207] = 8'hc8;
ram[208] = 8'hc3; ram[209] = 8'hb8; ram[210] = 8'h00; ram[211] = 8'h44;
ram[212] = 8'h4d; ram[213] = 8'h7a; ram[214] = 8'ha8; ram[215] = 8'hf5;
ram[216] = 8'h7a; ram[217] = 8'hb7; ram[218] = 8'hfc; ram[219] = 8'h14;
ram[220] = 8'h01; ram[221] = 8'h78; ram[222] = 8'hb7; ram[223] = 8'hfc;
ram[224] = 8'h1c; ram[225] = 8'h01; ram[226] = 8'h3e; ram[227] = 8'h10;
ram[228] = 8'hf5; ram[229] = 8'heb; ram[230] = 8'h11; ram[231] = 8'h00;
ram[232] = 8'h00; ram[233] = 8'h29; ram[234] = 8'hcd; ram[235] = 8'h24;
ram[236] = 8'h01; ram[237] = 8'hca; ram[238] = 8'h00; ram[239] = 8'h01;
ram[240] = 8'hcd; ram[241] = 8'h2c; ram[242] = 8'h01; ram[243] = 8'hfa;
ram[244] = 8'h00; ram[245] = 8'h01; ram[246] = 8'h7d; ram[247] = 8'hf6;
ram[248] = 8'h01; ram[249] = 8'h6f; ram[250] = 8'h7b; ram[251] = 8'h91;
ram[252] = 8'h5f; ram[253] = 8'h7a; ram[254] = 8'h98; ram[255] = 8'h57;
ram[256] = 8'hf1; ram[257] = 8'h3d; ram[258] = 8'hca; ram[259] = 8'h09;
ram[260] = 8'h01; ram[261] = 8'hf5; ram[262] = 8'hc3; ram[263] = 8'he9;
ram[264] = 8'h00; ram[265] = 8'hf1; ram[266] = 8'hf0; ram[267] = 8'hcd;
ram[268] = 8'h14; ram[269] = 8'h01; ram[270] = 8'heb; ram[271] = 8'hcd;
ram[272] = 8'h14; ram[273] = 8'h01; ram[274] = 8'heb; ram[275] = 8'hc9;
ram[276] = 8'h7a; ram[277] = 8'h2f; ram[278] = 8'h57; ram[279] = 8'h7b;
ram[280] = 8'h2f; ram[281] = 8'h5f; ram[282] = 8'h13; ram[283] = 8'hc9;
ram[284] = 8'h78; ram[285] = 8'h2f; ram[286] = 8'h47; ram[287] = 8'h79;
ram[288] = 8'h2f; ram[289] = 8'h4f; ram[290] = 8'h03; ram[291] = 8'hc9;
ram[292] = 8'h7b; ram[293] = 8'h17; ram[294] = 8'h5f; ram[295] = 8'h7a;
ram[296] = 8'h17; ram[297] = 8'h57; ram[298] = 8'hb3; ram[299] = 8'hc9;
ram[300] = 8'h7b; ram[301] = 8'h91; ram[302] = 8'h7a; ram[303] = 8'h98;
ram[304] = 8'hc9; ram[305] = 8'hdb; ram[306] = 8'h83; ram[307] = 8'hcf;
ram[308] = 8'he5; ram[309] = 8'h21; ram[310] = 8'h01; ram[311] = 8'h00;
ram[312] = 8'hd1; ram[313] = 8'hcd; ram[314] = 8'h29; ram[315] = 8'h00;
ram[316] = 8'h7c; ram[317] = 8'hb5; ram[318] = 8'hca; ram[319] = 8'h44;
ram[320] = 8'h01; ram[321] = 8'hc3; ram[322] = 8'h31; ram[323] = 8'h01;
ram[324] = 8'h21; ram[325] = 8'h02; ram[326] = 8'h00; ram[327] = 8'h39;
ram[328] = 8'hcd; ram[329] = 8'h07; ram[330] = 8'h00; ram[331] = 8'h7d;
ram[332] = 8'hd3; ram[333] = 8'h80; ram[334] = 8'hc9; ram[335] = 8'hdb;
ram[336] = 8'h83; ram[337] = 8'hcf; ram[338] = 8'he5; ram[339] = 8'h21;
ram[340] = 8'h10; ram[341] = 8'h00; ram[342] = 8'hd1; ram[343] = 8'hcd;
ram[344] = 8'h29; ram[345] = 8'h00; ram[346] = 8'h7c; ram[347] = 8'hb5;
ram[348] = 8'hca; ram[349] = 8'h6d; ram[350] = 8'h01; ram[351] = 8'hdb;
ram[352] = 8'h80; ram[353] = 8'hcf; ram[354] = 8'h7d; ram[355] = 8'h32;
ram[356] = 8'h9e; ram[357] = 8'h03; ram[358] = 8'h21; ram[359] = 8'h01;
ram[360] = 8'h00; ram[361] = 8'hc9; ram[362] = 8'hc3; ram[363] = 8'h71;
ram[364] = 8'h01; ram[365] = 8'h21; ram[366] = 8'h00; ram[367] = 8'h00;
ram[368] = 8'hc9; ram[369] = 8'hc9; ram[370] = 8'h21; ram[371] = 8'h0d;
ram[372] = 8'h00; ram[373] = 8'he5; ram[374] = 8'hcd; ram[375] = 8'h31;
ram[376] = 8'h01; ram[377] = 8'hc1; ram[378] = 8'h21; ram[379] = 8'h0a;
ram[380] = 8'h00; ram[381] = 8'he5; ram[382] = 8'hcd; ram[383] = 8'h31;
ram[384] = 8'h01; ram[385] = 8'hc1; ram[386] = 8'hc9; ram[387] = 8'h21;
ram[388] = 8'h02; ram[389] = 8'h00; ram[390] = 8'h39; ram[391] = 8'hcd;
ram[392] = 8'h0d; ram[393] = 8'h00; ram[394] = 8'hcd; ram[395] = 8'h07;
ram[396] = 8'h00; ram[397] = 8'he5; ram[398] = 8'h21; ram[399] = 8'h00;
ram[400] = 8'h00; ram[401] = 8'hd1; ram[402] = 8'hcd; ram[403] = 8'h36;
ram[404] = 8'h00; ram[405] = 8'h7c; ram[406] = 8'hb5; ram[407] = 8'hca;
ram[408] = 8'hb3; ram[409] = 8'h01; ram[410] = 8'h21; ram[411] = 8'h02;
ram[412] = 8'h00; ram[413] = 8'h39; ram[414] = 8'he5; ram[415] = 8'hcd;
ram[416] = 8'h0d; ram[417] = 8'h00; ram[418] = 8'h23; ram[419] = 8'hd1;
ram[420] = 8'hcd; ram[421] = 8'h15; ram[422] = 8'h00; ram[423] = 8'h2b;
ram[424] = 8'hcd; ram[425] = 8'h07; ram[426] = 8'h00; ram[427] = 8'he5;
ram[428] = 8'hcd; ram[429] = 8'h31; ram[430] = 8'h01; ram[431] = 8'hc1;
ram[432] = 8'hc3; ram[433] = 8'h83; ram[434] = 8'h01; ram[435] = 8'hc9;
ram[436] = 8'h21; ram[437] = 8'h02; ram[438] = 8'h00; ram[439] = 8'h39;
ram[440] = 8'hcd; ram[441] = 8'h0d; ram[442] = 8'h00; ram[443] = 8'he5;
ram[444] = 8'h21; ram[445] = 8'h00; ram[446] = 8'h00; ram[447] = 8'hd1;
ram[448] = 8'hcd; ram[449] = 8'h50; ram[450] = 8'h00; ram[451] = 8'h7c;
ram[452] = 8'hb5; ram[453] = 8'hca; ram[454] = 8'he3; ram[455] = 8'h01;
ram[456] = 8'h21; ram[457] = 8'h2d; ram[458] = 8'h00; ram[459] = 8'he5;
ram[460] = 8'hcd; ram[461] = 8'h31; ram[462] = 8'h01; ram[463] = 8'hc1;
ram[464] = 8'h21; ram[465] = 8'h02; ram[466] = 8'h00; ram[467] = 8'h39;
ram[468] = 8'he5; ram[469] = 8'h21; ram[470] = 8'h04; ram[471] = 8'h00;
ram[472] = 8'h39; ram[473] = 8'hcd; ram[474] = 8'h0d; ram[475] = 8'h00;
ram[476] = 8'hcd; ram[477] = 8'ha7; ram[478] = 8'h00; ram[479] = 8'hd1;
ram[480] = 8'hcd; ram[481] = 8'h15; ram[482] = 8'h00; ram[483] = 8'h21;
ram[484] = 8'h02; ram[485] = 8'h00; ram[486] = 8'h39; ram[487] = 8'hcd;
ram[488] = 8'h0d; ram[489] = 8'h00; ram[490] = 8'he5; ram[491] = 8'hcd;
ram[492] = 8'hf0; ram[493] = 8'h01; ram[494] = 8'hc1; ram[495] = 8'hc9;
ram[496] = 8'hc5; ram[497] = 8'h21; ram[498] = 8'h00; ram[499] = 8'h00;
ram[500] = 8'h39; ram[501] = 8'he5; ram[502] = 8'h21; ram[503] = 8'h06;
ram[504] = 8'h00; ram[505] = 8'h39; ram[506] = 8'hcd; ram[507] = 8'h0d;
ram[508] = 8'h00; ram[509] = 8'he5; ram[510] = 8'h21; ram[511] = 8'h0a;
ram[512] = 8'h00; ram[513] = 8'hd1; ram[514] = 8'hcd; ram[515] = 8'hd3;
ram[516] = 8'h00; ram[517] = 8'hd1; ram[518] = 8'hcd; ram[519] = 8'h15;
ram[520] = 8'h00; ram[521] = 8'h21; ram[522] = 8'h00; ram[523] = 8'h00;
ram[524] = 8'h39; ram[525] = 8'hcd; ram[526] = 8'h0d; ram[527] = 8'h00;
ram[528] = 8'h7c; ram[529] = 8'hb5; ram[530] = 8'hca; ram[531] = 8'h21;
ram[532] = 8'h02; ram[533] = 8'h21; ram[534] = 8'h00; ram[535] = 8'h00;
ram[536] = 8'h39; ram[537] = 8'hcd; ram[538] = 8'h0d; ram[539] = 8'h00;
ram[540] = 8'he5; ram[541] = 8'hcd; ram[542] = 8'hf0; ram[543] = 8'h01;
ram[544] = 8'hc1; ram[545] = 8'h21; ram[546] = 8'h30; ram[547] = 8'h00;
ram[548] = 8'he5; ram[549] = 8'h21; ram[550] = 8'h06; ram[551] = 8'h00;
ram[552] = 8'h39; ram[553] = 8'hcd; ram[554] = 8'h0d; ram[555] = 8'h00;
ram[556] = 8'he5; ram[557] = 8'h21; ram[558] = 8'h04; ram[559] = 8'h00;
ram[560] = 8'h39; ram[561] = 8'hcd; ram[562] = 8'h0d; ram[563] = 8'h00;
ram[564] = 8'he5; ram[565] = 8'h21; ram[566] = 8'h0a; ram[567] = 8'h00;
ram[568] = 8'hd1; ram[569] = 8'hcd; ram[570] = 8'hb3; ram[571] = 8'h00;
ram[572] = 8'hd1; ram[573] = 8'hcd; ram[574] = 8'ha0; ram[575] = 8'h00;
ram[576] = 8'hd1; ram[577] = 8'h19; ram[578] = 8'he5; ram[579] = 8'hcd;
ram[580] = 8'h31; ram[581] = 8'h01; ram[582] = 8'hc1; ram[583] = 8'hc1;
ram[584] = 8'hc9; ram[585] = 8'hc5; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'he5; ram[591] = 8'h21;
ram[592] = 8'h06; ram[593] = 8'h00; ram[594] = 8'h39; ram[595] = 8'hcd;
ram[596] = 8'h0d; ram[597] = 8'h00; ram[598] = 8'he5; ram[599] = 8'h21;
ram[600] = 8'h10; ram[601] = 8'h00; ram[602] = 8'hd1; ram[603] = 8'hcd;
ram[604] = 8'hd3; ram[605] = 8'h00; ram[606] = 8'hd1; ram[607] = 8'hcd;
ram[608] = 8'h15; ram[609] = 8'h00; ram[610] = 8'h21; ram[611] = 8'h00;
ram[612] = 8'h00; ram[613] = 8'h39; ram[614] = 8'hcd; ram[615] = 8'h0d;
ram[616] = 8'h00; ram[617] = 8'h7c; ram[618] = 8'hb5; ram[619] = 8'hca;
ram[620] = 8'h7a; ram[621] = 8'h02; ram[622] = 8'h21; ram[623] = 8'h00;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h0d;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'hcd; ram[631] = 8'h49;
ram[632] = 8'h02; ram[633] = 8'hc1; ram[634] = 8'h21; ram[635] = 8'h00;
ram[636] = 8'h00; ram[637] = 8'h39; ram[638] = 8'he5; ram[639] = 8'h21;
ram[640] = 8'h06; ram[641] = 8'h00; ram[642] = 8'h39; ram[643] = 8'hcd;
ram[644] = 8'h0d; ram[645] = 8'h00; ram[646] = 8'he5; ram[647] = 8'h21;
ram[648] = 8'h04; ram[649] = 8'h00; ram[650] = 8'h39; ram[651] = 8'hcd;
ram[652] = 8'h0d; ram[653] = 8'h00; ram[654] = 8'he5; ram[655] = 8'h21;
ram[656] = 8'h10; ram[657] = 8'h00; ram[658] = 8'hd1; ram[659] = 8'hcd;
ram[660] = 8'hb3; ram[661] = 8'h00; ram[662] = 8'hd1; ram[663] = 8'hcd;
ram[664] = 8'ha0; ram[665] = 8'h00; ram[666] = 8'hd1; ram[667] = 8'hcd;
ram[668] = 8'h15; ram[669] = 8'h00; ram[670] = 8'h21; ram[671] = 8'h00;
ram[672] = 8'h00; ram[673] = 8'h39; ram[674] = 8'hcd; ram[675] = 8'h0d;
ram[676] = 8'h00; ram[677] = 8'he5; ram[678] = 8'h21; ram[679] = 8'h09;
ram[680] = 8'h00; ram[681] = 8'hd1; ram[682] = 8'hcd; ram[683] = 8'h3c;
ram[684] = 8'h00; ram[685] = 8'h7c; ram[686] = 8'hb5; ram[687] = 8'hca;
ram[688] = 8'hcf; ram[689] = 8'h02; ram[690] = 8'h21; ram[691] = 8'h41;
ram[692] = 8'h00; ram[693] = 8'he5; ram[694] = 8'h21; ram[695] = 8'h02;
ram[696] = 8'h00; ram[697] = 8'h39; ram[698] = 8'hcd; ram[699] = 8'h0d;
ram[700] = 8'h00; ram[701] = 8'hd1; ram[702] = 8'h19; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h0a; ram[706] = 8'h00; ram[707] = 8'hd1;
ram[708] = 8'hcd; ram[709] = 8'ha0; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'hcd; ram[713] = 8'h31; ram[714] = 8'h01; ram[715] = 8'hc1;
ram[716] = 8'hc3; ram[717] = 8'he1; ram[718] = 8'h02; ram[719] = 8'h21;
ram[720] = 8'h30; ram[721] = 8'h00; ram[722] = 8'he5; ram[723] = 8'h21;
ram[724] = 8'h02; ram[725] = 8'h00; ram[726] = 8'h39; ram[727] = 8'hcd;
ram[728] = 8'h0d; ram[729] = 8'h00; ram[730] = 8'hd1; ram[731] = 8'h19;
ram[732] = 8'he5; ram[733] = 8'hcd; ram[734] = 8'h31; ram[735] = 8'h01;
ram[736] = 8'hc1; ram[737] = 8'hc1; ram[738] = 8'hc9; ram[739] = 8'h21;
ram[740] = 8'hc3; ram[741] = 8'h00; ram[742] = 8'h7d; ram[743] = 8'hd3;
ram[744] = 8'h81; ram[745] = 8'h21; ram[746] = 8'h00; ram[747] = 8'h00;
ram[748] = 8'h7d; ram[749] = 8'hd3; ram[750] = 8'h82; ram[751] = 8'h21;
ram[752] = 8'h5c; ram[753] = 8'h03; ram[754] = 8'he5; ram[755] = 8'hcd;
ram[756] = 8'h83; ram[757] = 8'h01; ram[758] = 8'hc1; ram[759] = 8'hcd;
ram[760] = 8'h72; ram[761] = 8'h01; ram[762] = 8'h21; ram[763] = 8'h6b;
ram[764] = 8'h03; ram[765] = 8'he5; ram[766] = 8'hcd; ram[767] = 8'h83;
ram[768] = 8'h01; ram[769] = 8'hc1; ram[770] = 8'h21; ram[771] = 8'h9f;
ram[772] = 8'h03; ram[773] = 8'he5; ram[774] = 8'h21; ram[775] = 8'h01;
ram[776] = 8'h00; ram[777] = 8'h29; ram[778] = 8'hd1; ram[779] = 8'h19;
ram[780] = 8'hcd; ram[781] = 8'h0d; ram[782] = 8'h00; ram[783] = 8'he5;
ram[784] = 8'hcd; ram[785] = 8'hb4; ram[786] = 8'h01; ram[787] = 8'hc1;
ram[788] = 8'hcd; ram[789] = 8'h72; ram[790] = 8'h01; ram[791] = 8'h21;
ram[792] = 8'h77; ram[793] = 8'h03; ram[794] = 8'he5; ram[795] = 8'hcd;
ram[796] = 8'h83; ram[797] = 8'h01; ram[798] = 8'hc1; ram[799] = 8'h21;
ram[800] = 8'h9f; ram[801] = 8'h03; ram[802] = 8'he5; ram[803] = 8'h21;
ram[804] = 8'h00; ram[805] = 8'h00; ram[806] = 8'h29; ram[807] = 8'hd1;
ram[808] = 8'h19; ram[809] = 8'hcd; ram[810] = 8'h0d; ram[811] = 8'h00;
ram[812] = 8'he5; ram[813] = 8'hcd; ram[814] = 8'h49; ram[815] = 8'h02;
ram[816] = 8'hc1; ram[817] = 8'hcd; ram[818] = 8'h72; ram[819] = 8'h01;
ram[820] = 8'h21; ram[821] = 8'h85; ram[822] = 8'h03; ram[823] = 8'he5;
ram[824] = 8'hcd; ram[825] = 8'h83; ram[826] = 8'h01; ram[827] = 8'hc1;
ram[828] = 8'hcd; ram[829] = 8'h72; ram[830] = 8'h01; ram[831] = 8'h21;
ram[832] = 8'h01; ram[833] = 8'h00; ram[834] = 8'h7c; ram[835] = 8'hb5;
ram[836] = 8'hca; ram[837] = 8'h5b; ram[838] = 8'h03; ram[839] = 8'hcd;
ram[840] = 8'h4f; ram[841] = 8'h01; ram[842] = 8'h7c; ram[843] = 8'hb5;
ram[844] = 8'hca; ram[845] = 8'h58; ram[846] = 8'h03; ram[847] = 8'h3a;
ram[848] = 8'h9e; ram[849] = 8'h03; ram[850] = 8'hcf; ram[851] = 8'he5;
ram[852] = 8'hcd; ram[853] = 8'h31; ram[854] = 8'h01; ram[855] = 8'hc1;
ram[856] = 8'hc3; ram[857] = 8'h3f; ram[858] = 8'h03; ram[859] = 8'hc9;
ram[860] = 8'h48; ram[861] = 8'h65; ram[862] = 8'h6c; ram[863] = 8'h6c;
ram[864] = 8'h6f; ram[865] = 8'h20; ram[866] = 8'h57; ram[867] = 8'h6f;
ram[868] = 8'h72; ram[869] = 8'h6c; ram[870] = 8'h64; ram[871] = 8'h21;
ram[872] = 8'h21; ram[873] = 8'h21; ram[874] = 8'h00; ram[875] = 8'h44;
ram[876] = 8'h65; ram[877] = 8'h63; ram[878] = 8'h20; ram[879] = 8'h76;
ram[880] = 8'h61; ram[881] = 8'h6c; ram[882] = 8'h75; ram[883] = 8'h65;
ram[884] = 8'h3a; ram[885] = 8'h20; ram[886] = 8'h00; ram[887] = 8'h48;
ram[888] = 8'h65; ram[889] = 8'h78; ram[890] = 8'h20; ram[891] = 8'h76;
ram[892] = 8'h61; ram[893] = 8'h6c; ram[894] = 8'h75; ram[895] = 8'h65;
ram[896] = 8'h3a; ram[897] = 8'h20; ram[898] = 8'h30; ram[899] = 8'h78;
ram[900] = 8'h00; ram[901] = 8'h45; ram[902] = 8'h63; ram[903] = 8'h68;
ram[904] = 8'h6f; ram[905] = 8'h69; ram[906] = 8'h6e; ram[907] = 8'h67;
ram[908] = 8'h20; ram[909] = 8'h72; ram[910] = 8'h65; ram[911] = 8'h63;
ram[912] = 8'h65; ram[913] = 8'h69; ram[914] = 8'h76; ram[915] = 8'h65;
ram[916] = 8'h64; ram[917] = 8'h20; ram[918] = 8'h62; ram[919] = 8'h79;
ram[920] = 8'h74; ram[921] = 8'h65; ram[922] = 8'h73; ram[923] = 8'h3a;
ram[924] = 8'h20; ram[925] = 8'h00; ram[926] = 8'h00; ram[927] = 8'hd2;
ram[928] = 8'h04; ram[929] = 8'h2e; ram[930] = 8'h16; ram[931] = 8'h00;
ram[932] = 8'h00; ram[933] = 8'h00; ram[934] = 8'h00; ram[935] = 8'h00;
ram[936] = 8'h00; ram[937] = 8'h00; ram[938] = 8'h00; ram[939] = 8'h00;
ram[940] = 8'h00; ram[941] = 8'h00; ram[942] = 8'h00; ram[943] = 8'h00;
ram[944] = 8'h00; ram[945] = 8'h00; ram[946] = 8'h00; ram[947] = 8'h00;
ram[948] = 8'h00; ram[949] = 8'h00; ram[950] = 8'h00; ram[951] = 8'h00;
ram[952] = 8'h00; ram[953] = 8'h00; ram[954] = 8'h00; ram[955] = 8'h00;
ram[956] = 8'h00; ram[957] = 8'h00; ram[958] = 8'h00; ram[959] = 8'h00;
ram[960] = 8'h00; ram[961] = 8'h00; ram[962] = 8'h00; ram[963] = 8'h00;
ram[964] = 8'h00; ram[965] = 8'h00; ram[966] = 8'h00; ram[967] = 8'h00;
ram[968] = 8'h00; ram[969] = 8'h00; ram[970] = 8'h00; ram[971] = 8'h00;
ram[972] = 8'h00; ram[973] = 8'h00; ram[974] = 8'h00; ram[975] = 8'h00;
ram[976] = 8'h00; ram[977] = 8'h00; ram[978] = 8'h00; ram[979] = 8'h00;
ram[980] = 8'h00; ram[981] = 8'h00; ram[982] = 8'h00; ram[983] = 8'h00;
ram[984] = 8'h00; ram[985] = 8'h00; ram[986] = 8'h00; ram[987] = 8'h00;
ram[988] = 8'h00; ram[989] = 8'h00; ram[990] = 8'h00; ram[991] = 8'h00;
ram[992] = 8'h00; ram[993] = 8'h00; ram[994] = 8'h00; ram[995] = 8'h00;
ram[996] = 8'h00; ram[997] = 8'h00; ram[998] = 8'h00; ram[999] = 8'h00;
ram[1000] = 8'h00; ram[1001] = 8'h00; ram[1002] = 8'h00; ram[1003] = 8'h00;
ram[1004] = 8'h00; ram[1005] = 8'h00; ram[1006] = 8'h00; ram[1007] = 8'h00;
ram[1008] = 8'h00; ram[1009] = 8'h00; ram[1010] = 8'h00; ram[1011] = 8'h00;
ram[1012] = 8'h00; ram[1013] = 8'h00; ram[1014] = 8'h00; ram[1015] = 8'h00;
ram[1016] = 8'h00; ram[1017] = 8'h00; ram[1018] = 8'h00; ram[1019] = 8'h00;
ram[1020] = 8'h00; ram[1021] = 8'h00; ram[1022] = 8'h00; ram[1023] = 8'h00;
ram[1024] = 8'h00; ram[1025] = 8'h00; ram[1026] = 8'h00; ram[1027] = 8'h00;
ram[1028] = 8'h00; ram[1029] = 8'h00; ram[1030] = 8'h00; ram[1031] = 8'h00;
ram[1032] = 8'h00; ram[1033] = 8'h00; ram[1034] = 8'h00; ram[1035] = 8'h00;
ram[1036] = 8'h00; ram[1037] = 8'h00; ram[1038] = 8'h00; ram[1039] = 8'h00;
ram[1040] = 8'h00; ram[1041] = 8'h00; ram[1042] = 8'h00; ram[1043] = 8'h00;
ram[1044] = 8'h00; ram[1045] = 8'h00; ram[1046] = 8'h00; ram[1047] = 8'h00;
ram[1048] = 8'h00; ram[1049] = 8'h00; ram[1050] = 8'h00; ram[1051] = 8'h00;
ram[1052] = 8'h00; ram[1053] = 8'h00; ram[1054] = 8'h00; ram[1055] = 8'h00;
ram[1056] = 8'h00; ram[1057] = 8'h00; ram[1058] = 8'h00; ram[1059] = 8'h00;
ram[1060] = 8'h00; ram[1061] = 8'h00; ram[1062] = 8'h00; ram[1063] = 8'h00;
ram[1064] = 8'h00; ram[1065] = 8'h00; ram[1066] = 8'h00; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'h00; ram[1070] = 8'h00; ram[1071] = 8'h00;
ram[1072] = 8'h00; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[4] = 8'hcd; ram[5] = 8'h30; ram[6] = 8'h03; ram[7] = 8'h00;
ram[8] = 8'hf5; ram[9] = 8'hc5; ram[10] = 8'hd5; ram[11] = 8'he5;
ram[12] = 8'hcd; ram[13] = 8'h24; ram[14] = 8'h03; ram[15] = 8'he1;
ram[16] = 8'hd1; ram[17] = 8'hc1; ram[18] = 8'hf1; ram[19] = 8'hfb;
ram[20] = 8'hc9; ram[21] = 8'h00; ram[22] = 8'h00; ram[23] = 8'h00;
ram[24] = 8'hf5; ram[25] = 8'hc5; ram[26] = 8'hd5; ram[27] = 8'he5;
ram[28] = 8'he1; ram[29] = 8'hd1; ram[30] = 8'hc1; ram[31] = 8'hf1;
ram[32] = 8'hfb; ram[33] = 8'hc9; ram[34] = 8'h00; ram[35] = 8'h00;
ram[36] = 8'h00; ram[37] = 8'h00; ram[38] = 8'h00; ram[39] = 8'h00;
ram[40] = 8'hf5; ram[41] = 8'hc5; ram[42] = 8'hd5; ram[43] = 8'he5;
ram[44] = 8'he1; ram[45] = 8'hd1; ram[46] = 8'hc1; ram[47] = 8'hf1;
ram[48] = 8'hfb; ram[49] = 8'hc9; ram[50] = 8'h00; ram[51] = 8'h00;
ram[52] = 8'h00; ram[53] = 8'h00; ram[54] = 8'h00; ram[55] = 8'h00;
ram[56] = 8'hf5; ram[57] = 8'hc5; ram[58] = 8'hd5; ram[59] = 8'he5;
ram[60] = 8'he1; ram[61] = 8'hd1; ram[62] = 8'hc1; ram[63] = 8'hf1;
ram[64] = 8'hfb; ram[65] = 8'hc9; ram[66] = 8'h7e; ram[67] = 8'h6f;
ram[68] = 8'h07; ram[69] = 8'h9f; ram[70] = 8'h67; ram[71] = 8'hc9;
ram[72] = 8'h7e; ram[73] = 8'h23; ram[74] = 8'h66; ram[75] = 8'h6f;
ram[76] = 8'hc9; ram[77] = 8'h7d; ram[78] = 8'h12; ram[79] = 8'hc9;
ram[80] = 8'h7d; ram[81] = 8'h12; ram[82] = 8'h13; ram[83] = 8'h7c;
ram[84] = 8'h12; ram[85] = 8'hc9; ram[86] = 8'h7d; ram[87] = 8'hb3;
ram[88] = 8'h6f; ram[89] = 8'h7c; ram[90] = 8'hb2; ram[91] = 8'h67;
ram[92] = 8'hc9; ram[93] = 8'h7d; ram[94] = 8'hab; ram[95] = 8'h6f;
ram[96] = 8'h7c; ram[97] = 8'haa; ram[98] = 8'h67; ram[99] = 8'hc9;
ram[100] = 8'h7d; ram[101] = 8'ha3; ram[102] = 8'h6f; ram[103] = 8'h7c;
ram[104] = 8'ha2; ram[105] = 8'h67; ram[106] = 8'hc9; ram[107] = 8'hcd;
ram[108] = 8'h91; ram[109] = 8'h00; ram[110] = 8'hc8; ram[111] = 8'h2b;
ram[112] = 8'hc9; ram[113] = 8'hcd; ram[114] = 8'h91; ram[115] = 8'h00;
ram[116] = 8'hc0; ram[117] = 8'h2b; ram[118] = 8'hc9; ram[119] = 8'heb;
ram[120] = 8'hcd; ram[121] = 8'h91; ram[122] = 8'h00; ram[123] = 8'hd8;
ram[124] = 8'h2b; ram[125] = 8'hc9; ram[126] = 8'hcd; ram[127] = 8'h91;
ram[128] = 8'h00; ram[129] = 8'hc8; ram[130] = 8'hd8; ram[131] = 8'h2b;
ram[132] = 8'hc9; ram[133] = 8'hcd; ram[134] = 8'h91; ram[135] = 8'h00;
ram[136] = 8'hd0; ram[137] = 8'h2b; ram[138] = 8'hc9; ram[139] = 8'hcd;
ram[140] = 8'h91; ram[141] = 8'h00; ram[142] = 8'hd8; ram[143] = 8'h2b;
ram[144] = 8'hc9; ram[145] = 8'h7b; ram[146] = 8'h95; ram[147] = 8'h5f;
ram[148] = 8'h7a; ram[149] = 8'h9c; ram[150] = 8'h21; ram[151] = 8'h01;
ram[152] = 8'h00; ram[153] = 8'hfa; ram[154] = 8'h9e; ram[155] = 8'h00;
ram[156] = 8'hb3; ram[157] = 8'hc9; ram[158] = 8'hb3; ram[159] = 8'h37;
ram[160] = 8'hc9; ram[161] = 8'hcd; ram[162] = 8'hbb; ram[163] = 8'h00;
ram[164] = 8'hd0; ram[165] = 8'h2b; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hbb; ram[169] = 8'h00; ram[170] = 8'hd8; ram[171] = 8'h2b;
ram[172] = 8'hc9; ram[173] = 8'heb; ram[174] = 8'hcd; ram[175] = 8'hbb;
ram[176] = 8'h00; ram[177] = 8'hd8; ram[178] = 8'h2b; ram[179] = 8'hc9;
ram[180] = 8'hcd; ram[181] = 8'hbb; ram[182] = 8'h00; ram[183] = 8'hc8;
ram[184] = 8'hd8; ram[185] = 8'h2b; ram[186] = 8'hc9; ram[187] = 8'h7a;
ram[188] = 8'hbc; ram[189] = 8'hc2; ram[190] = 8'hc2; ram[191] = 8'h00;
ram[192] = 8'h7b; ram[193] = 8'hbd; ram[194] = 8'h21; ram[195] = 8'h01;
ram[196] = 8'h00; ram[197] = 8'hc9; ram[198] = 8'heb; ram[199] = 8'h7c;
ram[200] = 8'h17; ram[201] = 8'h7c; ram[202] = 8'h1f; ram[203] = 8'h67;
ram[204] = 8'h7d; ram[205] = 8'h1f; ram[206] = 8'h6f; ram[207] = 8'h1d;
ram[208] = 8'hc2; ram[209] = 8'hc7; ram[210] = 8'h00; ram[211] = 8'hc9;
ram[212] = 8'heb; ram[213] = 8'h29; ram[214] = 8'h1d; ram[215] = 8'hc2;
ram[216] = 8'hd5; ram[217] = 8'h00; ram[218] = 8'hc9; ram[219] = 8'h7b;
ram[220] = 8'h95; ram[221] = 8'h6f; ram[222] = 8'h7a; ram[223] = 8'h9c;
ram[224] = 8'h67; ram[225] = 8'hc9; ram[226] = 8'hcd; ram[227] = 8'he7;
ram[228] = 8'h00; ram[229] = 8'h23; ram[230] = 8'hc9; ram[231] = 8'h7c;
ram[232] = 8'h2f; ram[233] = 8'h67; ram[234] = 8'h7d; ram[235] = 8'h2f;
ram[236] = 8'h6f; ram[237] = 8'hc9; ram[238] = 8'h44; ram[239] = 8'h4d;
ram[240] = 8'h21; ram[241] = 8'h00; ram[242] = 8'h00; ram[243] = 8'h79;
ram[244] = 8'h0f; ram[245] = 8'hd2; ram[246] = 8'hf9; ram[247] = 8'h00;
ram[248] = 8'h19; ram[249] = 8'haf; ram[250] = 8'h78; ram[251] = 8'h1f;
ram[252] = 8'h47; ram[253] = 8'h79; ram[254] = 8'h1f; ram[255] = 8'h4f;
ram[256] = 8'hb0; ram[257] = 8'hc8; ram[258] = 8'haf; ram[259] = 8'h7b;
ram[260] = 8'h17; ram[261] = 8'h5f; ram[262] = 8'h7a; ram[263] = 8'h17;
ram[264] = 8'h57; ram[265] = 8'hb3; ram[266] = 8'hc8; ram[267] = 8'hc3;
ram[268] = 8'hf3; ram[269] = 8'h00; ram[270] = 8'h44; ram[271] = 8'h4d;
ram[272] = 8'h7a; ram[273] = 8'ha8; ram[274] = 8'hf5; ram[275] = 8'h7a;
ram[276] = 8'hb7; ram[277] = 8'hfc; ram[278] = 8'h4f; ram[279] = 8'h01;
ram[280] = 8'h78; ram[281] = 8'hb7; ram[282] = 8'hfc; ram[283] = 8'h57;
ram[284] = 8'h01; ram[285] = 8'h3e; ram[286] = 8'h10; ram[287] = 8'hf5;
ram[288] = 8'heb; ram[289] = 8'h11; ram[290] = 8'h00; ram[291] = 8'h00;
ram[292] = 8'h29; ram[293] = 8'hcd; ram[294] = 8'h5f; ram[295] = 8'h01;
ram[296] = 8'hca; ram[297] = 8'h3b; ram[298] = 8'h01; ram[299] = 8'hcd;
ram[300] = 8'h67; ram[301] = 8'h01; ram[302] = 8'hfa; ram[303] = 8'h3b;
ram[304] = 8'h01; ram[305] = 8'h7d; ram[306] = 8'hf6; ram[307] = 8'h01;
ram[308] = 8'h6f; ram[309] = 8'h7b; ram[310] = 8'h91; ram[311] = 8'h5f;
ram[312] = 8'h7a; ram[313] = 8'h98; ram[314] = 8'h57; ram[315] = 8'hf1;
ram[316] = 8'h3d; ram[317] = 8'hca; ram[318] = 8'h44; ram[319] = 8'h01;
ram[320] = 8'hf5; ram[321] = 8'hc3; ram[322] = 8'h24; ram[323] = 8'h01;
ram[324] = 8'hf1; ram[325] = 8'hf0; ram[326] = 8'hcd; ram[327] = 8'h4f;
ram[328] = 8'h01; ram[329] = 8'heb; ram[330] = 8'hcd; ram[331] = 8'h4f;
ram[332] = 8'h01; ram[333] = 8'heb; ram[334] = 8'hc9; ram[335] = 8'h7a;
ram[336] = 8'h2f; ram[337] = 8'h57; ram[338] = 8'h7b; ram[339] = 8'h2f;
ram[340] = 8'h5f; ram[341] = 8'h13; ram[342] = 8'hc9; ram[343] = 8'h78;
ram[344] = 8'h2f; ram[345] = 8'h47; ram[346] = 8'h79; ram[347] = 8'h2f;
ram[348] = 8'h4f; ram[349] = 8'h03; ram[350] = 8'hc9; ram[351] = 8'h7b;
ram[352] = 8'h17; ram[353] = 8'h5f; ram[354] = 8'h7a; ram[355] = 8'h17;
ram[356] = 8'h57; ram[357] = 8'hb3; ram[358] = 8'hc9; ram[359] = 8'h7b;
ram[360] = 8'h91; ram[361] = 8'h7a; ram[362] = 8'h98; ram[363] = 8'hc9;
ram[364] = 8'hdb; ram[365] = 8'h83; ram[366] = 8'hcd; ram[367] = 8'h43;
ram[368] = 8'h00; ram[369] = 8'he5; ram[370] = 8'h21; ram[371] = 8'h01;
ram[372] = 8'h00; ram[373] = 8'hd1; ram[374] = 8'hcd; ram[375] = 8'h64;
ram[376] = 8'h00; ram[377] = 8'h7c; ram[378] = 8'hb5; ram[379] = 8'hca;
ram[380] = 8'h81; ram[381] = 8'h01; ram[382] = 8'hc3; ram[383] = 8'h6c;
ram[384] = 8'h01; ram[385] = 8'h21; ram[386] = 8'h02; ram[387] = 8'h00;
ram[388] = 8'h39; ram[389] = 8'hcd; ram[390] = 8'h42; ram[391] = 8'h00;
ram[392] = 8'h7d; ram[393] = 8'hd3; ram[394] = 8'h80; ram[395] = 8'hc9;
ram[396] = 8'hdb; ram[397] = 8'h83; ram[398] = 8'hcd; ram[399] = 8'h43;
ram[400] = 8'h00; ram[401] = 8'he5; ram[402] = 8'h21; ram[403] = 8'h10;
ram[404] = 8'h00; ram[405] = 8'hd1; ram[406] = 8'hcd; ram[407] = 8'h64;
ram[408] = 8'h00; ram[409] = 8'h7c; ram[410] = 8'hb5; ram[411] = 8'hca;
ram[412] = 8'hae; ram[413] = 8'h01; ram[414] = 8'hdb; ram[415] = 8'h80;
ram[416] = 8'hcd; ram[417] = 8'h43; ram[418] = 8'h00; ram[419] = 8'h7d;
ram[420] = 8'h32; ram[421] = 8'h2c; ram[422] = 8'h04; ram[423] = 8'h21;
ram[424] = 8'h01; ram[425] = 8'h00; ram[426] = 8'hc9; ram[427] = 8'hc3;
ram[428] = 8'hb2; ram[429] = 8'h01; ram[430] = 8'h21; ram[431] = 8'h00;
ram[432] = 8'h00; ram[433] = 8'hc9; ram[434] = 8'hc9; ram[435] = 8'h21;
ram[436] = 8'h0d; ram[437] = 8'h00; ram[438] = 8'he5; ram[439] = 8'hcd;
ram[440] = 8'h6c; ram[441] = 8'h01; ram[442] = 8'hc1; ram[443] = 8'h21;
ram[444] = 8'h0a; ram[445] = 8'h00; ram[446] = 8'he5; ram[447] = 8'hcd;
ram[448] = 8'h6c; ram[449] = 8'h01; ram[450] = 8'hc1; ram[451] = 8'hc9;
ram[452] = 8'h21; ram[453] = 8'h02; ram[454] = 8'h00; ram[455] = 8'h39;
ram[456] = 8'hcd; ram[457] = 8'h48; ram[458] = 8'h00; ram[459] = 8'hcd;
ram[460] = 8'h42; ram[461] = 8'h00; ram[462] = 8'he5; ram[463] = 8'h21;
ram[464] = 8'h00; ram[465] = 8'h00; ram[466] = 8'hd1; ram[467] = 8'hcd;
ram[468] = 8'h71; ram[469] = 8'h00; ram[470] = 8'h7c; ram[471] = 8'hb5;
ram[472] = 8'hca; ram[473] = 8'hf4; ram[474] = 8'h01; ram[475] = 8'h21;
ram[476] = 8'h02; ram[477] = 8'h00; ram[478] = 8'h39; ram[479] = 8'he5;
ram[480] = 8'hcd; ram[481] = 8'h48; ram[482] = 8'h00; ram[483] = 8'h23;
ram[484] = 8'hd1; ram[485] = 8'hcd; ram[486] = 8'h50; ram[487] = 8'h00;
ram[488] = 8'h2b; ram[489] = 8'hcd; ram[490] = 8'h42; ram[491] = 8'h00;
ram[492] = 8'he5; ram[493] = 8'hcd; ram[494] = 8'h6c; ram[495] = 8'h01;
ram[496] = 8'hc1; ram[497] = 8'hc3; ram[498] = 8'hc4; ram[499] = 8'h01;
ram[500] = 8'hc9; ram[501] = 8'h21; ram[502] = 8'h02; ram[503] = 8'h00;
ram[504] = 8'h39; ram[505] = 8'hcd; ram[506] = 8'h48; ram[507] = 8'h00;
ram[508] = 8'he5; ram[509] = 8'h21; ram[510] = 8'h00; ram[511] = 8'h00;
ram[512] = 8'hd1; ram[513] = 8'hcd; ram[514] = 8'h8b; ram[515] = 8'h00;
ram[516] = 8'h7c; ram[517] = 8'hb5; ram[518] = 8'hca; ram[519] = 8'h24;
ram[520] = 8'h02; ram[521] = 8'h21; ram[522] = 8'h2d; ram[523] = 8'h00;
ram[524] = 8'he5; ram[525] = 8'hcd; ram[526] = 8'h6c; ram[527] = 8'h01;
ram[528] = 8'hc1; ram[529] = 8'h21; ram[530] = 8'h02; ram[531] = 8'h00;
ram[532] = 8'h39; ram[533] = 8'he5; ram[534] = 8'h21; ram[535] = 8'h04;
ram[536] = 8'h00; ram[537] = 8'h39; ram[538] = 8'hcd; ram[539] = 8'h48;
ram[540] = 8'h00; ram[541] = 8'hcd; ram[542] = 8'he2; ram[543] = 8'h00;
ram[544] = 8'hd1; ram[545] = 8'hcd; ram[546] = 8'h50; ram[547] = 8'h00;
ram[548] = 8'h21; ram[549] = 8'h02; ram[550] = 8'h00; ram[551] = 8'h39;
ram[552] = 8'hcd; ram[553] = 8'h48; ram[554] = 8'h00; ram[555] = 8'he5;
ram[556] = 8'hcd; ram[557] = 8'h31; ram[558] = 8'h02; ram[559] = 8'hc1;
ram[560] = 8'hc9; ram[561] = 8'hc5; ram[562] = 8'h21; ram[563] = 8'h00;
ram[564] = 8'h00; ram[565] = 8'h39; ram[566] = 8'he5; ram[567] = 8'h21;
ram[568] = 8'h06; ram[569] = 8'h00; ram[570] = 8'h39; ram[571] = 8'hcd;
ram[572] = 8'h48; ram[573] = 8'h00; ram[574] = 8'he5; ram[575] = 8'h21;
ram[576] = 8'h0a; ram[577] = 8'h00; ram[578] = 8'hd1; ram[579] = 8'hcd;
ram[580] = 8'h0e; ram[581] = 8'h01; ram[582] = 8'hd1; ram[583] = 8'hcd;
ram[584] = 8'h50; ram[585] = 8'h00; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'hcd; ram[591] = 8'h48;
ram[592] = 8'h00; ram[593] = 8'h7c; ram[594] = 8'hb5; ram[595] = 8'hca;
ram[596] = 8'h62; ram[597] = 8'h02; ram[598] = 8'h21; ram[599] = 8'h00;
ram[600] = 8'h00; ram[601] = 8'h39; ram[602] = 8'hcd; ram[603] = 8'h48;
ram[604] = 8'h00; ram[605] = 8'he5; ram[606] = 8'hcd; ram[607] = 8'h31;
ram[608] = 8'h02; ram[609] = 8'hc1; ram[610] = 8'h21; ram[611] = 8'h30;
ram[612] = 8'h00; ram[613] = 8'he5; ram[614] = 8'h21; ram[615] = 8'h06;
ram[616] = 8'h00; ram[617] = 8'h39; ram[618] = 8'hcd; ram[619] = 8'h48;
ram[620] = 8'h00; ram[621] = 8'he5; ram[622] = 8'h21; ram[623] = 8'h04;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h48;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'h21; ram[631] = 8'h0a;
ram[632] = 8'h00; ram[633] = 8'hd1; ram[634] = 8'hcd; ram[635] = 8'hee;
ram[636] = 8'h00; ram[637] = 8'hd1; ram[638] = 8'hcd; ram[639] = 8'hdb;
ram[640] = 8'h00; ram[641] = 8'hd1; ram[642] = 8'h19; ram[643] = 8'he5;
ram[644] = 8'hcd; ram[645] = 8'h6c; ram[646] = 8'h01; ram[647] = 8'hc1;
ram[648] = 8'hc1; ram[649] = 8'hc9; ram[650] = 8'hc5; ram[651] = 8'h21;
ram[652] = 8'h00; ram[653] = 8'h00; ram[654] = 8'h39; ram[655] = 8'he5;
ram[656] = 8'h21; ram[657] = 8'h06; ram[658] = 8'h00; ram[659] = 8'h39;
ram[660] = 8'hcd; ram[661] = 8'h48; ram[662] = 8'h00; ram[663] = 8'he5;
ram[664] = 8'h21; ram[665] = 8'h10; ram[666] = 8'h00; ram[667] = 8'hd1;
ram[668] = 8'hcd; ram[669] = 8'h0e; ram[670] = 8'h01; ram[671] = 8'hd1;
ram[672] = 8'hcd; ram[673] = 8'h50; ram[674] = 8'h00; ram[675] = 8'h21;
ram[676] = 8'h00; ram[677] = 8'h00; ram[678] = 8'h39; ram[679] = 8'hcd;
ram[680] = 8'h48; ram[681] = 8'h00; ram[682] = 8'h7c; ram[683] = 8'hb5;
ram[684] = 8'hca; ram[685] = 8'hbb; ram[686] = 8'h02; ram[687] = 8'h21;
ram[688] = 8'h00; ram[689] = 8'h00; ram[690] = 8'h39; ram[691] = 8'hcd;
ram[692] = 8'h48; ram[693] = 8'h00; ram[694] = 8'he5; ram[695] = 8'hcd;
ram[696] = 8'h8a; ram[697] = 8'h02; ram[698] = 8'hc1; ram[699] = 8'h21;
ram[700] = 8'h00; ram[701] = 8'h00; ram[702] = 8'h39; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h06; ram[706] = 8'h00; ram[707] = 8'h39;
ram[708] = 8'hcd; ram[709] = 8'h48; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'h21; ram[713] = 8'h04; ram[714] = 8'h00; ram[715] = 8'h39;
ram[716] = 8'hcd; ram[717] = 8'h48; ram[718] = 8'h00; ram[719] = 8'he5;
ram[720] = 8'h21; ram[721] = 8'h10; ram[722] = 8'h00; ram[723] = 8'hd1;
ram[724] = 8'hcd; ram[725] = 8'hee; ram[726] = 8'h00; ram[727] = 8'hd1;
ram[728] = 8'hcd; ram[729] = 8'hdb; ram[730] = 8'h00; ram[731] = 8'hd1;
ram[732] = 8'hcd; ram[733] = 8'h50; ram[734] = 8'h00; ram[735] = 8'h21;
ram[736] = 8'h00; ram[737] = 8'h00; ram[738] = 8'h39; ram[739] = 8'hcd;
ram[740] = 8'h48; ram[741] = 8'h00; ram[742] = 8'he5; ram[743] = 8'h21;
ram[744] = 8'h09; ram[745] = 8'h00; ram[746] = 8'hd1; ram[747] = 8'hcd;
ram[748] = 8'h77; ram[749] = 8'h00; ram[750] = 8'h7c; ram[751] = 8'hb5;
ram[752] = 8'hca; ram[753] = 8'h10; ram[754] = 8'h03; ram[755] = 8'h21;
ram[756] = 8'h41; ram[757] = 8'h00; ram[758] = 8'he5; ram[759] = 8'h21;
ram[760] = 8'h02; ram[761] = 8'h00; ram[762] = 8'h39; ram[763] = 8'hcd;
ram[764] = 8'h48; ram[765] = 8'h00; ram[766] = 8'hd1; ram[767] = 8'h19;
ram[768] = 8'he5; ram[769] = 8'h21; ram[770] = 8'h0a; ram[771] = 8'h00;
ram[772] = 8'hd1; ram[773] = 8'hcd; ram[774] = 8'hdb; ram[775] = 8'h00;
ram[776] = 8'he5; ram[777] = 8'hcd; ram[778] = 8'h6c; ram[779] = 8'h01;
ram[780] = 8'hc1; ram[781] = 8'hc3; ram[782] = 8'h22; ram[783] = 8'h03;
ram[784] = 8'h21; ram[785] = 8'h30; ram[786] = 8'h00; ram[787] = 8'he5;
ram[788] = 8'h21; ram[789] = 8'h02; ram[790] = 8'h00; ram[791] = 8'h39;
ram[792] = 8'hcd; ram[793] = 8'h48; ram[794] = 8'h00; ram[795] = 8'hd1;
ram[796] = 8'h19; ram[797] = 8'he5; ram[798] = 8'hcd; ram[799] = 8'h6c;
ram[800] = 8'h01; ram[801] = 8'hc1; ram[802] = 8'hc1; ram[803] = 8'hc9;
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5;
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1;
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9;
ram[816] = 8'h21; ram[817] = 8'h01; ram[818] = 8'h00; ram[819] = 8'h7d;
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00;
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82;
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d;
ram[832] = 8'hd3; ram[833] = 8'h84; ram[834] = 8'h21; ram[835] = 8'hff;
ram[836] = 8'h00; ram[837] = 8'h7d; ram[838] = 8'hd3; ram[839] = 8'h85;
ram[840] = 8'h21; ram[841] = 8'h00; ram[842] = 8'h00; ram[843] = 8'h7d;
ram[844] = 8'hd3; ram[845] = 8'h86; ram[846] = 8'h21; ram[847] = 8'hff;
ram[848] = 8'h00; ram[849] = 8'h7d; ram[850] = 8'hd3; ram[851] = 8'h87;
ram[852] = 8'h21; ram[853] = 8'h01; ram[854] = 8'h00; ram[855] = 8'h7d;
ram[856] = 8'hd3; ram[857] = 8'h88; ram[858] = 8'hfb; ram[859] = 8'h21;
ram[860] = 8'hea; ram[861] = 8'h03; ram[862] = 8'he5; ram[863] = 8'hcd;
ram[864] = 8'hc4; ram[865] = 8'h01; ram[866] = 8'hc1; ram[867] = 8'hcd;
ram[868] = 8'hb3; ram[869] = 8'h01; ram[870] = 8'h21; ram[871] = 8'hf9;
ram[872] = 8'h03; ram[873] = 8'he5; ram[874] = 8'hcd; ram[875] = 8'hc4;
ram[876] = 8'h01; ram[877] = 8'hc1; ram[878] = 8'h21; ram[879] = 8'h2d;
ram[880] = 8'h04; ram[881] = 8'he5; ram[882] = 8'h21; ram[883] = 8'h01;
ram[884] = 8'h00; ram[885] = 8'h29; ram[886] = 8'hd1; ram[887] = 8'h19;
ram[888] = 8'hcd; ram[889] = 8'h48; ram[890] = 8'h00; ram[891] = 8'he5;
ram[892] = 8'hcd; ram[893] = 8'hf5; ram[894] = 8'h01; ram[895] = 8'hc1;
ram[896] = 8'hcd; ram[897] = 8'hb3; ram[898] = 8'h01; ram[899] = 8'h21;
ram[900] = 8'h05; ram[901] = 8'h04; ram[902] = 8'he5; ram[903] = 8'hcd;
ram[904] = 8'hc4; ram[905] = 8'h01; ram[906] = 8'hc1; ram[907] = 8'h21;
ram[908] = 8'h2d; ram[909] = 8'h04; ram[910] = 8'he5; ram[911] = 8'h21;
ram[912] = 8'h00; ram[913] = 8'h00; ram[914] = 8'h29; ram[915] = 8'hd1;
ram[916] = 8'h19; ram[917] = 8'hcd; ram[918] = 8'h48; ram[919] = 8'h00;
ram[920] = 8'he5; ram[921] = 8'hcd; ram[922] = 8'h8a; ram[923] = 8'h02;
ram[924] = 8'hc1; ram[925] = 8'hcd; ram[926] = 8'hb3; ram[927] = 8'h01;
ram[928] = 8'h21; ram[929] = 8'h01; ram[930] = 8'h00; ram[931] = 8'h7d;
ram[932] = 8'hd3; ram[933] = 8'h84; ram[934] = 8'h21; ram[935] = 8'h13;
ram[936] = 8'h04; ram[937] = 8'he5; ram[938] = 8'hcd; ram[939] = 8'hc4;
ram[940] = 8'h01; ram[941] = 8'hc1; ram[942] = 8'hcd; ram[943] = 8'hb3;
ram[944] = 8'h01; ram[945] = 8'h21; ram[946] = 8'h01; ram[947] = 8'h00;
ram[948] = 8'h7c; ram[949] = 8'hb5; ram[950] = 8'hca; ram[951] = 8'hcf;
ram[952] = 8'h03; ram[953] = 8'hcd; ram[954] = 8'h8c; ram[955] = 8'h01;
ram[956] = 8'h7c; ram[957] = 8'hb5; ram[958] = 8'hca; ram[959] = 8'hcc;
ram[960] = 8'h03; ram[961] = 8'h3a; ram[962] = 8'h2c; ram[963] = 8'h04;
ram[964] = 8'hcd; ram[965] = 8'h43; ram[966] = 8'h00; ram[967] = 8'he5;
ram[968] = 8'hcd; ram[969] = 8'h6c; ram[970] = 8'h01; ram[971] = 8'hc1;
ram[972] = 8'hc3; ram[973] = 8'hb1; ram[974] = 8'h03; ram[975] = 8'hc9;
ram[976] = 8'h49; ram[977] = 8'h6e; ram[978] = 8'h74; ram[979] = 8'h65;
ram[980] = 8'h72; ram[981] = 8'h72; ram[982] = 8'h75; ram[983] = 8'h70;
ram[984] = 8'h74; ram[985] = 8'h20; ram[986] = 8'h30; ram[987] = 8'h20;
ram[988] = 8'h77; ram[989] = 8'h61; ram[990] = 8'h73; ram[991] = 8'h20;
ram[992] = 8'h61; ram[993] = 8'h73; ram[994] = 8'h73; ram[995] = 8'h65;
ram[996] = 8'h72; ram[997] = 8'h74; ram[998] = 8'h65; ram[999] = 8'h64;
ram[1000] = 8'h2e; ram[1001] = 8'h00; ram[1002] = 8'h48; ram[1003] = 8'h65;
ram[1004] = 8'h6c; ram[1005] = 8'h6c; ram[1006] = 8'h6f; ram[1007] = 8'h20;
ram[1008] = 8'h57; ram[1009] = 8'h6f; ram[1010] = 8'h72; ram[1011] = 8'h6c;
ram[1012] = 8'h64; ram[1013] = 8'h21; ram[1014] = 8'h21; ram[1015] = 8'h21;
ram[1016] = 8'h00; ram[1017] = 8'h44; ram[1018] = 8'h65; ram[1019] = 8'h63;
ram[1020] = 8'h20; ram[1021] = 8'h76; ram[1022] = 8'h61; ram[1023] = 8'h6c;
ram[1024] = 8'h75; ram[1025] = 8'h65; ram[1026] = 8'h3a; ram[1027] = 8'h20;
ram[1028] = 8'h00; ram[1029] = 8'h48; ram[1030] = 8'h65; ram[1031] = 8'h78;
ram[1032] = 8'h20; ram[1033] = 8'h76; ram[1034] = 8'h61; ram[1035] = 8'h6c;
ram[1036] = 8'h75; ram[1037] = 8'h65; ram[1038] = 8'h3a; ram[1039] = 8'h20;
ram[1040] = 8'h30; ram[1041] = 8'h78; ram[1042] = 8'h00; ram[1043] = 8'h45;
ram[1044] = 8'h63; ram[1045] = 8'h68; ram[1046] = 8'h6f; ram[1047] = 8'h69;
ram[1048] = 8'h6e; ram[1049] = 8'h67; ram[1050] = 8'h20; ram[1051] = 8'h72;
ram[1052] = 8'h65; ram[1053] = 8'h63; ram[1054] = 8'h65; ram[1055] = 8'h69;
ram[1056] = 8'h76; ram[1057] = 8'h65; ram[1058] = 8'h64; ram[1059] = 8'h20;
ram[1060] = 8'h62; ram[1061] = 8'h79; ram[1062] = 8'h74; ram[1063] = 8'h65;
ram[1064] = 8'h73; ram[1065] = 8'h3a; ram[1066] = 8'h20; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'hd2; ram[1070] = 8'h04; ram[1071] = 8'h2e;
ram[1072] = 8'h16; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
/trunk/c/HELLO.HEX
1,31 → 1,39
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:110420007665642062797465733A200000D2042E16D1
:00000001FF
/trunk/verilog/bench/tb_l80soc.v
35,7 → 35,6
// the following define selects between CPU instruction trace and uart transmitted bytes
//`define CPU_TRACE 1
 
 
//---------------------------------------------------------------------------------------
// internal signals
reg clock; // global clock
44,6 → 43,8
// UUT interfaces
wire rxd, txd;
wire [7:0] p1dio, p2dio;
wire [3:0] extint;
reg sp1dio0;
 
//---------------------------------------------------------------------------------------
// test bench implementation
93,7 → 94,8
.txd(txd),
.rxd(rxd),
.p1dio(p1dio),
.p2dio(p2dio)
.p2dio(p2dio),
.extint(extint)
);
 
//------------------------------------------------------------------
100,6 → 102,24
// uart receive is not used in this test becnch
assign rxd = 1'b1;
 
// external interrupt 0 is connected to the p1dio[0] rising edge
assign extint[3:1] = 3'b0;
assign extint[0] = ((sp1dio0 == 1'b0) && (p1dio[0] == 1'b1)) ? 1'b1 : 1'b0;
 
// p1dio[0] rising edge detection
always @ (posedge reset or posedge clock)
begin
if (reset)
sp1dio0 <= 1'b0;
else if (p1dio[0] == 1'b1)
sp1dio0 <= 1'b1;
else
sp1dio0 <= 1'b0;
end
 
//------------------------------------------------------------------
// test bench output log selection - either simple CPU trace or UART
// transmit port log
`ifdef CPU_TRACE
// display executed instructions
reg [15:0] saddr;
/trunk/verilog/rtl/intr_ctrl.v
0,0 → 1,171
//---------------------------------------------------------------------------------------
// Project: light8080 SOC WiCores Solutions
//
// File name: intr_ctrl.v (March 02, 2012)
//
// Writer: Moti Litochevski
//
// Description:
// This file contains the light8080 SOC interrupt controller. The controller
// supports 4 external interrupt requests with fixed interrupt vector addresses.
// The interrupt vectors code is implemented in the "intr_vec.h" file included in
// the projects C directory.
// Note that the controller clears the interrupt request after the CPU read the
// interrupt vector.
//
// Revision History:
//
// Rev <revnumber> <Date> <owner>
// <comment>
//
//---------------------------------------------------------------------------------------
//
// Copyright (C) 2012 Moti Litochevski
//
// This source file may be used and distributed without restriction provided that this
// copyright statement is not removed from the file and that any derivative work
// contains the original copyright notice and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
// FITNESS FOR A PARTICULAR PURPOSE.
//
//---------------------------------------------------------------------------------------
 
module intr_ctrl
(
clock, reset,
ext_intr, cpu_intr,
cpu_inte, cpu_inta,
cpu_rd, cpu_inst,
intr_ena
);
//---------------------------------------------------------------------------------------
// module interfaces
// global signals
input clock; // global clock input
input reset; // global reset input
// external interrupt sources
// least significant bit has the highest priority, most significant bit has the lowest
// priority.
input [3:0] ext_intr; // active high
// CPU interface
output cpu_intr; // CPU interrupt request
input cpu_inte; // CPU interrupt enable - just to mask
input cpu_inta; // CPU interrupt acknowledge
input cpu_rd; // CPU read signal
output [7:0] cpu_inst; // interrupt calling instruction
 
// interrupt enable register
input [3:0] intr_ena; // set high to enable respective interrupt
 
//---------------------------------------------------------------------------------------
// 8080 assembly code constants
// call instruction opcode used to call interrupt routine
`define CALL_INST 8'hcd
// interrupt vectors fixed addresses - high address byte is 0
`define INT0_VEC 8'h08
`define INT1_VEC 8'h18
`define INT2_VEC 8'h28
`define INT3_VEC 8'h38
 
//---------------------------------------------------------------------------------------
// internal declarations
// registered output
reg [7:0] cpu_inst;
 
// internals
reg [1:0] intSq, intSel;
reg [3:0] act_int, int_clr;
reg [7:0] int_vec;
 
//---------------------------------------------------------------------------------------
// module implementation
// main interrupt controller control process
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
intSq <= 2'b0;
intSel <= 2'b0;
cpu_inst <= 8'b0;
end
else
begin
// interrupt controller state machine
case (intSq)
2'd0: // idle state - wait for active interrupt
if ((act_int != 4'b0) && cpu_inte)
begin
// latch the index of the active interrupt according to priority
if (act_int[0]) intSel <= 2'd0;
else if (act_int[2]) intSel <= 2'd1;
else if (act_int[3]) intSel <= 2'd2;
else intSel <= 2'd3;
// switch to next state
intSq <= 2'd1;
end
default: // all other states increment the state register on inta read
if (cpu_inta && cpu_rd)
begin
// update state
intSq <= intSq + 1;
// update instruction opcode for each byte read during inta
case (intSq)
2'd1: cpu_inst <= `CALL_INST;
2'd2: cpu_inst <= int_vec;
default: cpu_inst <= 8'd0;
endcase
end
else if (!cpu_inta)
begin
intSq <= 2'd0;
cpu_inst <= 8'd0;
end
endcase
end
end
 
// assign interrupt vector address according to selected interrupt
always @ (intSel)
begin
case (intSel)
2'd0: int_vec <= `INT0_VEC;
2'd1: int_vec <= `INT1_VEC;
2'd2: int_vec <= `INT2_VEC;
2'd3: int_vec <= `INT3_VEC;
endcase
end
 
// latch active interrupt on rising edge
always @ (posedge reset or posedge clock)
begin
if (reset)
act_int <= 4'b0;
else
act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
end
// CPU interrupt is asserted when at least one interrupt is active
assign cpu_intr = |act_int;
 
// clear serviced interrupt
always @ (cpu_inta or cpu_rd or intSq or intSel)
begin
if (cpu_inta && cpu_rd && (intSq == 2'd3))
begin
case (intSel)
2'd0: int_clr <= 4'b0001;
2'd1: int_clr <= 4'b0010;
2'd2: int_clr <= 4'b0100;
2'd3: int_clr <= 4'b1000;
endcase
end
else
int_clr <= 4'b0;
end
 
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
/trunk/verilog/rtl/ram_image.v
21,274 → 21,274
initial
begin
ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
ram[4] = 8'hcd; ram[5] = 8'he3; ram[6] = 8'h02; ram[7] = 8'h7e;
ram[8] = 8'h6f; ram[9] = 8'h07; ram[10] = 8'h9f; ram[11] = 8'h67;
ram[12] = 8'hc9; ram[13] = 8'h7e; ram[14] = 8'h23; ram[15] = 8'h66;
ram[16] = 8'h6f; ram[17] = 8'hc9; ram[18] = 8'h7d; ram[19] = 8'h12;
ram[20] = 8'hc9; ram[21] = 8'h7d; ram[22] = 8'h12; ram[23] = 8'h13;
ram[24] = 8'h7c; ram[25] = 8'h12; ram[26] = 8'hc9; ram[27] = 8'h7d;
ram[28] = 8'hb3; ram[29] = 8'h6f; ram[30] = 8'h7c; ram[31] = 8'hb2;
ram[32] = 8'h67; ram[33] = 8'hc9; ram[34] = 8'h7d; ram[35] = 8'hab;
ram[36] = 8'h6f; ram[37] = 8'h7c; ram[38] = 8'haa; ram[39] = 8'h67;
ram[40] = 8'hc9; ram[41] = 8'h7d; ram[42] = 8'ha3; ram[43] = 8'h6f;
ram[44] = 8'h7c; ram[45] = 8'ha2; ram[46] = 8'h67; ram[47] = 8'hc9;
ram[48] = 8'hcd; ram[49] = 8'h56; ram[50] = 8'h00; ram[51] = 8'hc8;
ram[52] = 8'h2b; ram[53] = 8'hc9; ram[54] = 8'hcd; ram[55] = 8'h56;
ram[56] = 8'h00; ram[57] = 8'hc0; ram[58] = 8'h2b; ram[59] = 8'hc9;
ram[60] = 8'heb; ram[61] = 8'hcd; ram[62] = 8'h56; ram[63] = 8'h00;
ram[64] = 8'hd8; ram[65] = 8'h2b; ram[66] = 8'hc9; ram[67] = 8'hcd;
ram[68] = 8'h56; ram[69] = 8'h00; ram[70] = 8'hc8; ram[71] = 8'hd8;
ram[72] = 8'h2b; ram[73] = 8'hc9; ram[74] = 8'hcd; ram[75] = 8'h56;
ram[76] = 8'h00; ram[77] = 8'hd0; ram[78] = 8'h2b; ram[79] = 8'hc9;
ram[80] = 8'hcd; ram[81] = 8'h56; ram[82] = 8'h00; ram[83] = 8'hd8;
ram[84] = 8'h2b; ram[85] = 8'hc9; ram[86] = 8'h7b; ram[87] = 8'h95;
ram[88] = 8'h5f; ram[89] = 8'h7a; ram[90] = 8'h9c; ram[91] = 8'h21;
ram[92] = 8'h01; ram[93] = 8'h00; ram[94] = 8'hfa; ram[95] = 8'h63;
ram[96] = 8'h00; ram[97] = 8'hb3; ram[98] = 8'hc9; ram[99] = 8'hb3;
ram[100] = 8'h37; ram[101] = 8'hc9; ram[102] = 8'hcd; ram[103] = 8'h80;
ram[104] = 8'h00; ram[105] = 8'hd0; ram[106] = 8'h2b; ram[107] = 8'hc9;
ram[108] = 8'hcd; ram[109] = 8'h80; ram[110] = 8'h00; ram[111] = 8'hd8;
ram[112] = 8'h2b; ram[113] = 8'hc9; ram[114] = 8'heb; ram[115] = 8'hcd;
ram[116] = 8'h80; ram[117] = 8'h00; ram[118] = 8'hd8; ram[119] = 8'h2b;
ram[120] = 8'hc9; ram[121] = 8'hcd; ram[122] = 8'h80; ram[123] = 8'h00;
ram[124] = 8'hc8; ram[125] = 8'hd8; ram[126] = 8'h2b; ram[127] = 8'hc9;
ram[128] = 8'h7a; ram[129] = 8'hbc; ram[130] = 8'hc2; ram[131] = 8'h87;
ram[132] = 8'h00; ram[133] = 8'h7b; ram[134] = 8'hbd; ram[135] = 8'h21;
ram[136] = 8'h01; ram[137] = 8'h00; ram[138] = 8'hc9; ram[139] = 8'heb;
ram[140] = 8'h7c; ram[141] = 8'h17; ram[142] = 8'h7c; ram[143] = 8'h1f;
ram[144] = 8'h67; ram[145] = 8'h7d; ram[146] = 8'h1f; ram[147] = 8'h6f;
ram[148] = 8'h1d; ram[149] = 8'hc2; ram[150] = 8'h8c; ram[151] = 8'h00;
ram[152] = 8'hc9; ram[153] = 8'heb; ram[154] = 8'h29; ram[155] = 8'h1d;
ram[156] = 8'hc2; ram[157] = 8'h9a; ram[158] = 8'h00; ram[159] = 8'hc9;
ram[160] = 8'h7b; ram[161] = 8'h95; ram[162] = 8'h6f; ram[163] = 8'h7a;
ram[164] = 8'h9c; ram[165] = 8'h67; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hac; ram[169] = 8'h00; ram[170] = 8'h23; ram[171] = 8'hc9;
ram[172] = 8'h7c; ram[173] = 8'h2f; ram[174] = 8'h67; ram[175] = 8'h7d;
ram[176] = 8'h2f; ram[177] = 8'h6f; ram[178] = 8'hc9; ram[179] = 8'h44;
ram[180] = 8'h4d; ram[181] = 8'h21; ram[182] = 8'h00; ram[183] = 8'h00;
ram[184] = 8'h79; ram[185] = 8'h0f; ram[186] = 8'hd2; ram[187] = 8'hbe;
ram[188] = 8'h00; ram[189] = 8'h19; ram[190] = 8'haf; ram[191] = 8'h78;
ram[192] = 8'h1f; ram[193] = 8'h47; ram[194] = 8'h79; ram[195] = 8'h1f;
ram[196] = 8'h4f; ram[197] = 8'hb0; ram[198] = 8'hc8; ram[199] = 8'haf;
ram[200] = 8'h7b; ram[201] = 8'h17; ram[202] = 8'h5f; ram[203] = 8'h7a;
ram[204] = 8'h17; ram[205] = 8'h57; ram[206] = 8'hb3; ram[207] = 8'hc8;
ram[208] = 8'hc3; ram[209] = 8'hb8; ram[210] = 8'h00; ram[211] = 8'h44;
ram[212] = 8'h4d; ram[213] = 8'h7a; ram[214] = 8'ha8; ram[215] = 8'hf5;
ram[216] = 8'h7a; ram[217] = 8'hb7; ram[218] = 8'hfc; ram[219] = 8'h14;
ram[220] = 8'h01; ram[221] = 8'h78; ram[222] = 8'hb7; ram[223] = 8'hfc;
ram[224] = 8'h1c; ram[225] = 8'h01; ram[226] = 8'h3e; ram[227] = 8'h10;
ram[228] = 8'hf5; ram[229] = 8'heb; ram[230] = 8'h11; ram[231] = 8'h00;
ram[232] = 8'h00; ram[233] = 8'h29; ram[234] = 8'hcd; ram[235] = 8'h24;
ram[236] = 8'h01; ram[237] = 8'hca; ram[238] = 8'h00; ram[239] = 8'h01;
ram[240] = 8'hcd; ram[241] = 8'h2c; ram[242] = 8'h01; ram[243] = 8'hfa;
ram[244] = 8'h00; ram[245] = 8'h01; ram[246] = 8'h7d; ram[247] = 8'hf6;
ram[248] = 8'h01; ram[249] = 8'h6f; ram[250] = 8'h7b; ram[251] = 8'h91;
ram[252] = 8'h5f; ram[253] = 8'h7a; ram[254] = 8'h98; ram[255] = 8'h57;
ram[256] = 8'hf1; ram[257] = 8'h3d; ram[258] = 8'hca; ram[259] = 8'h09;
ram[260] = 8'h01; ram[261] = 8'hf5; ram[262] = 8'hc3; ram[263] = 8'he9;
ram[264] = 8'h00; ram[265] = 8'hf1; ram[266] = 8'hf0; ram[267] = 8'hcd;
ram[268] = 8'h14; ram[269] = 8'h01; ram[270] = 8'heb; ram[271] = 8'hcd;
ram[272] = 8'h14; ram[273] = 8'h01; ram[274] = 8'heb; ram[275] = 8'hc9;
ram[276] = 8'h7a; ram[277] = 8'h2f; ram[278] = 8'h57; ram[279] = 8'h7b;
ram[280] = 8'h2f; ram[281] = 8'h5f; ram[282] = 8'h13; ram[283] = 8'hc9;
ram[284] = 8'h78; ram[285] = 8'h2f; ram[286] = 8'h47; ram[287] = 8'h79;
ram[288] = 8'h2f; ram[289] = 8'h4f; ram[290] = 8'h03; ram[291] = 8'hc9;
ram[292] = 8'h7b; ram[293] = 8'h17; ram[294] = 8'h5f; ram[295] = 8'h7a;
ram[296] = 8'h17; ram[297] = 8'h57; ram[298] = 8'hb3; ram[299] = 8'hc9;
ram[300] = 8'h7b; ram[301] = 8'h91; ram[302] = 8'h7a; ram[303] = 8'h98;
ram[304] = 8'hc9; ram[305] = 8'hdb; ram[306] = 8'h83; ram[307] = 8'hcf;
ram[308] = 8'he5; ram[309] = 8'h21; ram[310] = 8'h01; ram[311] = 8'h00;
ram[312] = 8'hd1; ram[313] = 8'hcd; ram[314] = 8'h29; ram[315] = 8'h00;
ram[316] = 8'h7c; ram[317] = 8'hb5; ram[318] = 8'hca; ram[319] = 8'h44;
ram[320] = 8'h01; ram[321] = 8'hc3; ram[322] = 8'h31; ram[323] = 8'h01;
ram[324] = 8'h21; ram[325] = 8'h02; ram[326] = 8'h00; ram[327] = 8'h39;
ram[328] = 8'hcd; ram[329] = 8'h07; ram[330] = 8'h00; ram[331] = 8'h7d;
ram[332] = 8'hd3; ram[333] = 8'h80; ram[334] = 8'hc9; ram[335] = 8'hdb;
ram[336] = 8'h83; ram[337] = 8'hcf; ram[338] = 8'he5; ram[339] = 8'h21;
ram[340] = 8'h10; ram[341] = 8'h00; ram[342] = 8'hd1; ram[343] = 8'hcd;
ram[344] = 8'h29; ram[345] = 8'h00; ram[346] = 8'h7c; ram[347] = 8'hb5;
ram[348] = 8'hca; ram[349] = 8'h6d; ram[350] = 8'h01; ram[351] = 8'hdb;
ram[352] = 8'h80; ram[353] = 8'hcf; ram[354] = 8'h7d; ram[355] = 8'h32;
ram[356] = 8'h9e; ram[357] = 8'h03; ram[358] = 8'h21; ram[359] = 8'h01;
ram[360] = 8'h00; ram[361] = 8'hc9; ram[362] = 8'hc3; ram[363] = 8'h71;
ram[364] = 8'h01; ram[365] = 8'h21; ram[366] = 8'h00; ram[367] = 8'h00;
ram[368] = 8'hc9; ram[369] = 8'hc9; ram[370] = 8'h21; ram[371] = 8'h0d;
ram[372] = 8'h00; ram[373] = 8'he5; ram[374] = 8'hcd; ram[375] = 8'h31;
ram[376] = 8'h01; ram[377] = 8'hc1; ram[378] = 8'h21; ram[379] = 8'h0a;
ram[380] = 8'h00; ram[381] = 8'he5; ram[382] = 8'hcd; ram[383] = 8'h31;
ram[384] = 8'h01; ram[385] = 8'hc1; ram[386] = 8'hc9; ram[387] = 8'h21;
ram[388] = 8'h02; ram[389] = 8'h00; ram[390] = 8'h39; ram[391] = 8'hcd;
ram[392] = 8'h0d; ram[393] = 8'h00; ram[394] = 8'hcd; ram[395] = 8'h07;
ram[396] = 8'h00; ram[397] = 8'he5; ram[398] = 8'h21; ram[399] = 8'h00;
ram[400] = 8'h00; ram[401] = 8'hd1; ram[402] = 8'hcd; ram[403] = 8'h36;
ram[404] = 8'h00; ram[405] = 8'h7c; ram[406] = 8'hb5; ram[407] = 8'hca;
ram[408] = 8'hb3; ram[409] = 8'h01; ram[410] = 8'h21; ram[411] = 8'h02;
ram[412] = 8'h00; ram[413] = 8'h39; ram[414] = 8'he5; ram[415] = 8'hcd;
ram[416] = 8'h0d; ram[417] = 8'h00; ram[418] = 8'h23; ram[419] = 8'hd1;
ram[420] = 8'hcd; ram[421] = 8'h15; ram[422] = 8'h00; ram[423] = 8'h2b;
ram[424] = 8'hcd; ram[425] = 8'h07; ram[426] = 8'h00; ram[427] = 8'he5;
ram[428] = 8'hcd; ram[429] = 8'h31; ram[430] = 8'h01; ram[431] = 8'hc1;
ram[432] = 8'hc3; ram[433] = 8'h83; ram[434] = 8'h01; ram[435] = 8'hc9;
ram[436] = 8'h21; ram[437] = 8'h02; ram[438] = 8'h00; ram[439] = 8'h39;
ram[440] = 8'hcd; ram[441] = 8'h0d; ram[442] = 8'h00; ram[443] = 8'he5;
ram[444] = 8'h21; ram[445] = 8'h00; ram[446] = 8'h00; ram[447] = 8'hd1;
ram[448] = 8'hcd; ram[449] = 8'h50; ram[450] = 8'h00; ram[451] = 8'h7c;
ram[452] = 8'hb5; ram[453] = 8'hca; ram[454] = 8'he3; ram[455] = 8'h01;
ram[456] = 8'h21; ram[457] = 8'h2d; ram[458] = 8'h00; ram[459] = 8'he5;
ram[460] = 8'hcd; ram[461] = 8'h31; ram[462] = 8'h01; ram[463] = 8'hc1;
ram[464] = 8'h21; ram[465] = 8'h02; ram[466] = 8'h00; ram[467] = 8'h39;
ram[468] = 8'he5; ram[469] = 8'h21; ram[470] = 8'h04; ram[471] = 8'h00;
ram[472] = 8'h39; ram[473] = 8'hcd; ram[474] = 8'h0d; ram[475] = 8'h00;
ram[476] = 8'hcd; ram[477] = 8'ha7; ram[478] = 8'h00; ram[479] = 8'hd1;
ram[480] = 8'hcd; ram[481] = 8'h15; ram[482] = 8'h00; ram[483] = 8'h21;
ram[484] = 8'h02; ram[485] = 8'h00; ram[486] = 8'h39; ram[487] = 8'hcd;
ram[488] = 8'h0d; ram[489] = 8'h00; ram[490] = 8'he5; ram[491] = 8'hcd;
ram[492] = 8'hf0; ram[493] = 8'h01; ram[494] = 8'hc1; ram[495] = 8'hc9;
ram[496] = 8'hc5; ram[497] = 8'h21; ram[498] = 8'h00; ram[499] = 8'h00;
ram[500] = 8'h39; ram[501] = 8'he5; ram[502] = 8'h21; ram[503] = 8'h06;
ram[504] = 8'h00; ram[505] = 8'h39; ram[506] = 8'hcd; ram[507] = 8'h0d;
ram[508] = 8'h00; ram[509] = 8'he5; ram[510] = 8'h21; ram[511] = 8'h0a;
ram[512] = 8'h00; ram[513] = 8'hd1; ram[514] = 8'hcd; ram[515] = 8'hd3;
ram[516] = 8'h00; ram[517] = 8'hd1; ram[518] = 8'hcd; ram[519] = 8'h15;
ram[520] = 8'h00; ram[521] = 8'h21; ram[522] = 8'h00; ram[523] = 8'h00;
ram[524] = 8'h39; ram[525] = 8'hcd; ram[526] = 8'h0d; ram[527] = 8'h00;
ram[528] = 8'h7c; ram[529] = 8'hb5; ram[530] = 8'hca; ram[531] = 8'h21;
ram[532] = 8'h02; ram[533] = 8'h21; ram[534] = 8'h00; ram[535] = 8'h00;
ram[536] = 8'h39; ram[537] = 8'hcd; ram[538] = 8'h0d; ram[539] = 8'h00;
ram[540] = 8'he5; ram[541] = 8'hcd; ram[542] = 8'hf0; ram[543] = 8'h01;
ram[544] = 8'hc1; ram[545] = 8'h21; ram[546] = 8'h30; ram[547] = 8'h00;
ram[548] = 8'he5; ram[549] = 8'h21; ram[550] = 8'h06; ram[551] = 8'h00;
ram[552] = 8'h39; ram[553] = 8'hcd; ram[554] = 8'h0d; ram[555] = 8'h00;
ram[556] = 8'he5; ram[557] = 8'h21; ram[558] = 8'h04; ram[559] = 8'h00;
ram[560] = 8'h39; ram[561] = 8'hcd; ram[562] = 8'h0d; ram[563] = 8'h00;
ram[564] = 8'he5; ram[565] = 8'h21; ram[566] = 8'h0a; ram[567] = 8'h00;
ram[568] = 8'hd1; ram[569] = 8'hcd; ram[570] = 8'hb3; ram[571] = 8'h00;
ram[572] = 8'hd1; ram[573] = 8'hcd; ram[574] = 8'ha0; ram[575] = 8'h00;
ram[576] = 8'hd1; ram[577] = 8'h19; ram[578] = 8'he5; ram[579] = 8'hcd;
ram[580] = 8'h31; ram[581] = 8'h01; ram[582] = 8'hc1; ram[583] = 8'hc1;
ram[584] = 8'hc9; ram[585] = 8'hc5; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'he5; ram[591] = 8'h21;
ram[592] = 8'h06; ram[593] = 8'h00; ram[594] = 8'h39; ram[595] = 8'hcd;
ram[596] = 8'h0d; ram[597] = 8'h00; ram[598] = 8'he5; ram[599] = 8'h21;
ram[600] = 8'h10; ram[601] = 8'h00; ram[602] = 8'hd1; ram[603] = 8'hcd;
ram[604] = 8'hd3; ram[605] = 8'h00; ram[606] = 8'hd1; ram[607] = 8'hcd;
ram[608] = 8'h15; ram[609] = 8'h00; ram[610] = 8'h21; ram[611] = 8'h00;
ram[612] = 8'h00; ram[613] = 8'h39; ram[614] = 8'hcd; ram[615] = 8'h0d;
ram[616] = 8'h00; ram[617] = 8'h7c; ram[618] = 8'hb5; ram[619] = 8'hca;
ram[620] = 8'h7a; ram[621] = 8'h02; ram[622] = 8'h21; ram[623] = 8'h00;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h0d;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'hcd; ram[631] = 8'h49;
ram[632] = 8'h02; ram[633] = 8'hc1; ram[634] = 8'h21; ram[635] = 8'h00;
ram[636] = 8'h00; ram[637] = 8'h39; ram[638] = 8'he5; ram[639] = 8'h21;
ram[640] = 8'h06; ram[641] = 8'h00; ram[642] = 8'h39; ram[643] = 8'hcd;
ram[644] = 8'h0d; ram[645] = 8'h00; ram[646] = 8'he5; ram[647] = 8'h21;
ram[648] = 8'h04; ram[649] = 8'h00; ram[650] = 8'h39; ram[651] = 8'hcd;
ram[652] = 8'h0d; ram[653] = 8'h00; ram[654] = 8'he5; ram[655] = 8'h21;
ram[656] = 8'h10; ram[657] = 8'h00; ram[658] = 8'hd1; ram[659] = 8'hcd;
ram[660] = 8'hb3; ram[661] = 8'h00; ram[662] = 8'hd1; ram[663] = 8'hcd;
ram[664] = 8'ha0; ram[665] = 8'h00; ram[666] = 8'hd1; ram[667] = 8'hcd;
ram[668] = 8'h15; ram[669] = 8'h00; ram[670] = 8'h21; ram[671] = 8'h00;
ram[672] = 8'h00; ram[673] = 8'h39; ram[674] = 8'hcd; ram[675] = 8'h0d;
ram[676] = 8'h00; ram[677] = 8'he5; ram[678] = 8'h21; ram[679] = 8'h09;
ram[680] = 8'h00; ram[681] = 8'hd1; ram[682] = 8'hcd; ram[683] = 8'h3c;
ram[684] = 8'h00; ram[685] = 8'h7c; ram[686] = 8'hb5; ram[687] = 8'hca;
ram[688] = 8'hcf; ram[689] = 8'h02; ram[690] = 8'h21; ram[691] = 8'h41;
ram[692] = 8'h00; ram[693] = 8'he5; ram[694] = 8'h21; ram[695] = 8'h02;
ram[696] = 8'h00; ram[697] = 8'h39; ram[698] = 8'hcd; ram[699] = 8'h0d;
ram[700] = 8'h00; ram[701] = 8'hd1; ram[702] = 8'h19; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h0a; ram[706] = 8'h00; ram[707] = 8'hd1;
ram[708] = 8'hcd; ram[709] = 8'ha0; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'hcd; ram[713] = 8'h31; ram[714] = 8'h01; ram[715] = 8'hc1;
ram[716] = 8'hc3; ram[717] = 8'he1; ram[718] = 8'h02; ram[719] = 8'h21;
ram[720] = 8'h30; ram[721] = 8'h00; ram[722] = 8'he5; ram[723] = 8'h21;
ram[724] = 8'h02; ram[725] = 8'h00; ram[726] = 8'h39; ram[727] = 8'hcd;
ram[728] = 8'h0d; ram[729] = 8'h00; ram[730] = 8'hd1; ram[731] = 8'h19;
ram[732] = 8'he5; ram[733] = 8'hcd; ram[734] = 8'h31; ram[735] = 8'h01;
ram[736] = 8'hc1; ram[737] = 8'hc1; ram[738] = 8'hc9; ram[739] = 8'h21;
ram[740] = 8'hc3; ram[741] = 8'h00; ram[742] = 8'h7d; ram[743] = 8'hd3;
ram[744] = 8'h81; ram[745] = 8'h21; ram[746] = 8'h00; ram[747] = 8'h00;
ram[748] = 8'h7d; ram[749] = 8'hd3; ram[750] = 8'h82; ram[751] = 8'h21;
ram[752] = 8'h5c; ram[753] = 8'h03; ram[754] = 8'he5; ram[755] = 8'hcd;
ram[756] = 8'h83; ram[757] = 8'h01; ram[758] = 8'hc1; ram[759] = 8'hcd;
ram[760] = 8'h72; ram[761] = 8'h01; ram[762] = 8'h21; ram[763] = 8'h6b;
ram[764] = 8'h03; ram[765] = 8'he5; ram[766] = 8'hcd; ram[767] = 8'h83;
ram[768] = 8'h01; ram[769] = 8'hc1; ram[770] = 8'h21; ram[771] = 8'h9f;
ram[772] = 8'h03; ram[773] = 8'he5; ram[774] = 8'h21; ram[775] = 8'h01;
ram[776] = 8'h00; ram[777] = 8'h29; ram[778] = 8'hd1; ram[779] = 8'h19;
ram[780] = 8'hcd; ram[781] = 8'h0d; ram[782] = 8'h00; ram[783] = 8'he5;
ram[784] = 8'hcd; ram[785] = 8'hb4; ram[786] = 8'h01; ram[787] = 8'hc1;
ram[788] = 8'hcd; ram[789] = 8'h72; ram[790] = 8'h01; ram[791] = 8'h21;
ram[792] = 8'h77; ram[793] = 8'h03; ram[794] = 8'he5; ram[795] = 8'hcd;
ram[796] = 8'h83; ram[797] = 8'h01; ram[798] = 8'hc1; ram[799] = 8'h21;
ram[800] = 8'h9f; ram[801] = 8'h03; ram[802] = 8'he5; ram[803] = 8'h21;
ram[804] = 8'h00; ram[805] = 8'h00; ram[806] = 8'h29; ram[807] = 8'hd1;
ram[808] = 8'h19; ram[809] = 8'hcd; ram[810] = 8'h0d; ram[811] = 8'h00;
ram[812] = 8'he5; ram[813] = 8'hcd; ram[814] = 8'h49; ram[815] = 8'h02;
ram[816] = 8'hc1; ram[817] = 8'hcd; ram[818] = 8'h72; ram[819] = 8'h01;
ram[820] = 8'h21; ram[821] = 8'h85; ram[822] = 8'h03; ram[823] = 8'he5;
ram[824] = 8'hcd; ram[825] = 8'h83; ram[826] = 8'h01; ram[827] = 8'hc1;
ram[828] = 8'hcd; ram[829] = 8'h72; ram[830] = 8'h01; ram[831] = 8'h21;
ram[832] = 8'h01; ram[833] = 8'h00; ram[834] = 8'h7c; ram[835] = 8'hb5;
ram[836] = 8'hca; ram[837] = 8'h5b; ram[838] = 8'h03; ram[839] = 8'hcd;
ram[840] = 8'h4f; ram[841] = 8'h01; ram[842] = 8'h7c; ram[843] = 8'hb5;
ram[844] = 8'hca; ram[845] = 8'h58; ram[846] = 8'h03; ram[847] = 8'h3a;
ram[848] = 8'h9e; ram[849] = 8'h03; ram[850] = 8'hcf; ram[851] = 8'he5;
ram[852] = 8'hcd; ram[853] = 8'h31; ram[854] = 8'h01; ram[855] = 8'hc1;
ram[856] = 8'hc3; ram[857] = 8'h3f; ram[858] = 8'h03; ram[859] = 8'hc9;
ram[860] = 8'h48; ram[861] = 8'h65; ram[862] = 8'h6c; ram[863] = 8'h6c;
ram[864] = 8'h6f; ram[865] = 8'h20; ram[866] = 8'h57; ram[867] = 8'h6f;
ram[868] = 8'h72; ram[869] = 8'h6c; ram[870] = 8'h64; ram[871] = 8'h21;
ram[872] = 8'h21; ram[873] = 8'h21; ram[874] = 8'h00; ram[875] = 8'h44;
ram[876] = 8'h65; ram[877] = 8'h63; ram[878] = 8'h20; ram[879] = 8'h76;
ram[880] = 8'h61; ram[881] = 8'h6c; ram[882] = 8'h75; ram[883] = 8'h65;
ram[884] = 8'h3a; ram[885] = 8'h20; ram[886] = 8'h00; ram[887] = 8'h48;
ram[888] = 8'h65; ram[889] = 8'h78; ram[890] = 8'h20; ram[891] = 8'h76;
ram[892] = 8'h61; ram[893] = 8'h6c; ram[894] = 8'h75; ram[895] = 8'h65;
ram[896] = 8'h3a; ram[897] = 8'h20; ram[898] = 8'h30; ram[899] = 8'h78;
ram[900] = 8'h00; ram[901] = 8'h45; ram[902] = 8'h63; ram[903] = 8'h68;
ram[904] = 8'h6f; ram[905] = 8'h69; ram[906] = 8'h6e; ram[907] = 8'h67;
ram[908] = 8'h20; ram[909] = 8'h72; ram[910] = 8'h65; ram[911] = 8'h63;
ram[912] = 8'h65; ram[913] = 8'h69; ram[914] = 8'h76; ram[915] = 8'h65;
ram[916] = 8'h64; ram[917] = 8'h20; ram[918] = 8'h62; ram[919] = 8'h79;
ram[920] = 8'h74; ram[921] = 8'h65; ram[922] = 8'h73; ram[923] = 8'h3a;
ram[924] = 8'h20; ram[925] = 8'h00; ram[926] = 8'h00; ram[927] = 8'hd2;
ram[928] = 8'h04; ram[929] = 8'h2e; ram[930] = 8'h16; ram[931] = 8'h00;
ram[932] = 8'h00; ram[933] = 8'h00; ram[934] = 8'h00; ram[935] = 8'h00;
ram[936] = 8'h00; ram[937] = 8'h00; ram[938] = 8'h00; ram[939] = 8'h00;
ram[940] = 8'h00; ram[941] = 8'h00; ram[942] = 8'h00; ram[943] = 8'h00;
ram[944] = 8'h00; ram[945] = 8'h00; ram[946] = 8'h00; ram[947] = 8'h00;
ram[948] = 8'h00; ram[949] = 8'h00; ram[950] = 8'h00; ram[951] = 8'h00;
ram[952] = 8'h00; ram[953] = 8'h00; ram[954] = 8'h00; ram[955] = 8'h00;
ram[956] = 8'h00; ram[957] = 8'h00; ram[958] = 8'h00; ram[959] = 8'h00;
ram[960] = 8'h00; ram[961] = 8'h00; ram[962] = 8'h00; ram[963] = 8'h00;
ram[964] = 8'h00; ram[965] = 8'h00; ram[966] = 8'h00; ram[967] = 8'h00;
ram[968] = 8'h00; ram[969] = 8'h00; ram[970] = 8'h00; ram[971] = 8'h00;
ram[972] = 8'h00; ram[973] = 8'h00; ram[974] = 8'h00; ram[975] = 8'h00;
ram[976] = 8'h00; ram[977] = 8'h00; ram[978] = 8'h00; ram[979] = 8'h00;
ram[980] = 8'h00; ram[981] = 8'h00; ram[982] = 8'h00; ram[983] = 8'h00;
ram[984] = 8'h00; ram[985] = 8'h00; ram[986] = 8'h00; ram[987] = 8'h00;
ram[988] = 8'h00; ram[989] = 8'h00; ram[990] = 8'h00; ram[991] = 8'h00;
ram[992] = 8'h00; ram[993] = 8'h00; ram[994] = 8'h00; ram[995] = 8'h00;
ram[996] = 8'h00; ram[997] = 8'h00; ram[998] = 8'h00; ram[999] = 8'h00;
ram[1000] = 8'h00; ram[1001] = 8'h00; ram[1002] = 8'h00; ram[1003] = 8'h00;
ram[1004] = 8'h00; ram[1005] = 8'h00; ram[1006] = 8'h00; ram[1007] = 8'h00;
ram[1008] = 8'h00; ram[1009] = 8'h00; ram[1010] = 8'h00; ram[1011] = 8'h00;
ram[1012] = 8'h00; ram[1013] = 8'h00; ram[1014] = 8'h00; ram[1015] = 8'h00;
ram[1016] = 8'h00; ram[1017] = 8'h00; ram[1018] = 8'h00; ram[1019] = 8'h00;
ram[1020] = 8'h00; ram[1021] = 8'h00; ram[1022] = 8'h00; ram[1023] = 8'h00;
ram[1024] = 8'h00; ram[1025] = 8'h00; ram[1026] = 8'h00; ram[1027] = 8'h00;
ram[1028] = 8'h00; ram[1029] = 8'h00; ram[1030] = 8'h00; ram[1031] = 8'h00;
ram[1032] = 8'h00; ram[1033] = 8'h00; ram[1034] = 8'h00; ram[1035] = 8'h00;
ram[1036] = 8'h00; ram[1037] = 8'h00; ram[1038] = 8'h00; ram[1039] = 8'h00;
ram[1040] = 8'h00; ram[1041] = 8'h00; ram[1042] = 8'h00; ram[1043] = 8'h00;
ram[1044] = 8'h00; ram[1045] = 8'h00; ram[1046] = 8'h00; ram[1047] = 8'h00;
ram[1048] = 8'h00; ram[1049] = 8'h00; ram[1050] = 8'h00; ram[1051] = 8'h00;
ram[1052] = 8'h00; ram[1053] = 8'h00; ram[1054] = 8'h00; ram[1055] = 8'h00;
ram[1056] = 8'h00; ram[1057] = 8'h00; ram[1058] = 8'h00; ram[1059] = 8'h00;
ram[1060] = 8'h00; ram[1061] = 8'h00; ram[1062] = 8'h00; ram[1063] = 8'h00;
ram[1064] = 8'h00; ram[1065] = 8'h00; ram[1066] = 8'h00; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'h00; ram[1070] = 8'h00; ram[1071] = 8'h00;
ram[1072] = 8'h00; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[4] = 8'hcd; ram[5] = 8'h30; ram[6] = 8'h03; ram[7] = 8'h00;
ram[8] = 8'hf5; ram[9] = 8'hc5; ram[10] = 8'hd5; ram[11] = 8'he5;
ram[12] = 8'hcd; ram[13] = 8'h24; ram[14] = 8'h03; ram[15] = 8'he1;
ram[16] = 8'hd1; ram[17] = 8'hc1; ram[18] = 8'hf1; ram[19] = 8'hfb;
ram[20] = 8'hc9; ram[21] = 8'h00; ram[22] = 8'h00; ram[23] = 8'h00;
ram[24] = 8'hf5; ram[25] = 8'hc5; ram[26] = 8'hd5; ram[27] = 8'he5;
ram[28] = 8'he1; ram[29] = 8'hd1; ram[30] = 8'hc1; ram[31] = 8'hf1;
ram[32] = 8'hfb; ram[33] = 8'hc9; ram[34] = 8'h00; ram[35] = 8'h00;
ram[36] = 8'h00; ram[37] = 8'h00; ram[38] = 8'h00; ram[39] = 8'h00;
ram[40] = 8'hf5; ram[41] = 8'hc5; ram[42] = 8'hd5; ram[43] = 8'he5;
ram[44] = 8'he1; ram[45] = 8'hd1; ram[46] = 8'hc1; ram[47] = 8'hf1;
ram[48] = 8'hfb; ram[49] = 8'hc9; ram[50] = 8'h00; ram[51] = 8'h00;
ram[52] = 8'h00; ram[53] = 8'h00; ram[54] = 8'h00; ram[55] = 8'h00;
ram[56] = 8'hf5; ram[57] = 8'hc5; ram[58] = 8'hd5; ram[59] = 8'he5;
ram[60] = 8'he1; ram[61] = 8'hd1; ram[62] = 8'hc1; ram[63] = 8'hf1;
ram[64] = 8'hfb; ram[65] = 8'hc9; ram[66] = 8'h7e; ram[67] = 8'h6f;
ram[68] = 8'h07; ram[69] = 8'h9f; ram[70] = 8'h67; ram[71] = 8'hc9;
ram[72] = 8'h7e; ram[73] = 8'h23; ram[74] = 8'h66; ram[75] = 8'h6f;
ram[76] = 8'hc9; ram[77] = 8'h7d; ram[78] = 8'h12; ram[79] = 8'hc9;
ram[80] = 8'h7d; ram[81] = 8'h12; ram[82] = 8'h13; ram[83] = 8'h7c;
ram[84] = 8'h12; ram[85] = 8'hc9; ram[86] = 8'h7d; ram[87] = 8'hb3;
ram[88] = 8'h6f; ram[89] = 8'h7c; ram[90] = 8'hb2; ram[91] = 8'h67;
ram[92] = 8'hc9; ram[93] = 8'h7d; ram[94] = 8'hab; ram[95] = 8'h6f;
ram[96] = 8'h7c; ram[97] = 8'haa; ram[98] = 8'h67; ram[99] = 8'hc9;
ram[100] = 8'h7d; ram[101] = 8'ha3; ram[102] = 8'h6f; ram[103] = 8'h7c;
ram[104] = 8'ha2; ram[105] = 8'h67; ram[106] = 8'hc9; ram[107] = 8'hcd;
ram[108] = 8'h91; ram[109] = 8'h00; ram[110] = 8'hc8; ram[111] = 8'h2b;
ram[112] = 8'hc9; ram[113] = 8'hcd; ram[114] = 8'h91; ram[115] = 8'h00;
ram[116] = 8'hc0; ram[117] = 8'h2b; ram[118] = 8'hc9; ram[119] = 8'heb;
ram[120] = 8'hcd; ram[121] = 8'h91; ram[122] = 8'h00; ram[123] = 8'hd8;
ram[124] = 8'h2b; ram[125] = 8'hc9; ram[126] = 8'hcd; ram[127] = 8'h91;
ram[128] = 8'h00; ram[129] = 8'hc8; ram[130] = 8'hd8; ram[131] = 8'h2b;
ram[132] = 8'hc9; ram[133] = 8'hcd; ram[134] = 8'h91; ram[135] = 8'h00;
ram[136] = 8'hd0; ram[137] = 8'h2b; ram[138] = 8'hc9; ram[139] = 8'hcd;
ram[140] = 8'h91; ram[141] = 8'h00; ram[142] = 8'hd8; ram[143] = 8'h2b;
ram[144] = 8'hc9; ram[145] = 8'h7b; ram[146] = 8'h95; ram[147] = 8'h5f;
ram[148] = 8'h7a; ram[149] = 8'h9c; ram[150] = 8'h21; ram[151] = 8'h01;
ram[152] = 8'h00; ram[153] = 8'hfa; ram[154] = 8'h9e; ram[155] = 8'h00;
ram[156] = 8'hb3; ram[157] = 8'hc9; ram[158] = 8'hb3; ram[159] = 8'h37;
ram[160] = 8'hc9; ram[161] = 8'hcd; ram[162] = 8'hbb; ram[163] = 8'h00;
ram[164] = 8'hd0; ram[165] = 8'h2b; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hbb; ram[169] = 8'h00; ram[170] = 8'hd8; ram[171] = 8'h2b;
ram[172] = 8'hc9; ram[173] = 8'heb; ram[174] = 8'hcd; ram[175] = 8'hbb;
ram[176] = 8'h00; ram[177] = 8'hd8; ram[178] = 8'h2b; ram[179] = 8'hc9;
ram[180] = 8'hcd; ram[181] = 8'hbb; ram[182] = 8'h00; ram[183] = 8'hc8;
ram[184] = 8'hd8; ram[185] = 8'h2b; ram[186] = 8'hc9; ram[187] = 8'h7a;
ram[188] = 8'hbc; ram[189] = 8'hc2; ram[190] = 8'hc2; ram[191] = 8'h00;
ram[192] = 8'h7b; ram[193] = 8'hbd; ram[194] = 8'h21; ram[195] = 8'h01;
ram[196] = 8'h00; ram[197] = 8'hc9; ram[198] = 8'heb; ram[199] = 8'h7c;
ram[200] = 8'h17; ram[201] = 8'h7c; ram[202] = 8'h1f; ram[203] = 8'h67;
ram[204] = 8'h7d; ram[205] = 8'h1f; ram[206] = 8'h6f; ram[207] = 8'h1d;
ram[208] = 8'hc2; ram[209] = 8'hc7; ram[210] = 8'h00; ram[211] = 8'hc9;
ram[212] = 8'heb; ram[213] = 8'h29; ram[214] = 8'h1d; ram[215] = 8'hc2;
ram[216] = 8'hd5; ram[217] = 8'h00; ram[218] = 8'hc9; ram[219] = 8'h7b;
ram[220] = 8'h95; ram[221] = 8'h6f; ram[222] = 8'h7a; ram[223] = 8'h9c;
ram[224] = 8'h67; ram[225] = 8'hc9; ram[226] = 8'hcd; ram[227] = 8'he7;
ram[228] = 8'h00; ram[229] = 8'h23; ram[230] = 8'hc9; ram[231] = 8'h7c;
ram[232] = 8'h2f; ram[233] = 8'h67; ram[234] = 8'h7d; ram[235] = 8'h2f;
ram[236] = 8'h6f; ram[237] = 8'hc9; ram[238] = 8'h44; ram[239] = 8'h4d;
ram[240] = 8'h21; ram[241] = 8'h00; ram[242] = 8'h00; ram[243] = 8'h79;
ram[244] = 8'h0f; ram[245] = 8'hd2; ram[246] = 8'hf9; ram[247] = 8'h00;
ram[248] = 8'h19; ram[249] = 8'haf; ram[250] = 8'h78; ram[251] = 8'h1f;
ram[252] = 8'h47; ram[253] = 8'h79; ram[254] = 8'h1f; ram[255] = 8'h4f;
ram[256] = 8'hb0; ram[257] = 8'hc8; ram[258] = 8'haf; ram[259] = 8'h7b;
ram[260] = 8'h17; ram[261] = 8'h5f; ram[262] = 8'h7a; ram[263] = 8'h17;
ram[264] = 8'h57; ram[265] = 8'hb3; ram[266] = 8'hc8; ram[267] = 8'hc3;
ram[268] = 8'hf3; ram[269] = 8'h00; ram[270] = 8'h44; ram[271] = 8'h4d;
ram[272] = 8'h7a; ram[273] = 8'ha8; ram[274] = 8'hf5; ram[275] = 8'h7a;
ram[276] = 8'hb7; ram[277] = 8'hfc; ram[278] = 8'h4f; ram[279] = 8'h01;
ram[280] = 8'h78; ram[281] = 8'hb7; ram[282] = 8'hfc; ram[283] = 8'h57;
ram[284] = 8'h01; ram[285] = 8'h3e; ram[286] = 8'h10; ram[287] = 8'hf5;
ram[288] = 8'heb; ram[289] = 8'h11; ram[290] = 8'h00; ram[291] = 8'h00;
ram[292] = 8'h29; ram[293] = 8'hcd; ram[294] = 8'h5f; ram[295] = 8'h01;
ram[296] = 8'hca; ram[297] = 8'h3b; ram[298] = 8'h01; ram[299] = 8'hcd;
ram[300] = 8'h67; ram[301] = 8'h01; ram[302] = 8'hfa; ram[303] = 8'h3b;
ram[304] = 8'h01; ram[305] = 8'h7d; ram[306] = 8'hf6; ram[307] = 8'h01;
ram[308] = 8'h6f; ram[309] = 8'h7b; ram[310] = 8'h91; ram[311] = 8'h5f;
ram[312] = 8'h7a; ram[313] = 8'h98; ram[314] = 8'h57; ram[315] = 8'hf1;
ram[316] = 8'h3d; ram[317] = 8'hca; ram[318] = 8'h44; ram[319] = 8'h01;
ram[320] = 8'hf5; ram[321] = 8'hc3; ram[322] = 8'h24; ram[323] = 8'h01;
ram[324] = 8'hf1; ram[325] = 8'hf0; ram[326] = 8'hcd; ram[327] = 8'h4f;
ram[328] = 8'h01; ram[329] = 8'heb; ram[330] = 8'hcd; ram[331] = 8'h4f;
ram[332] = 8'h01; ram[333] = 8'heb; ram[334] = 8'hc9; ram[335] = 8'h7a;
ram[336] = 8'h2f; ram[337] = 8'h57; ram[338] = 8'h7b; ram[339] = 8'h2f;
ram[340] = 8'h5f; ram[341] = 8'h13; ram[342] = 8'hc9; ram[343] = 8'h78;
ram[344] = 8'h2f; ram[345] = 8'h47; ram[346] = 8'h79; ram[347] = 8'h2f;
ram[348] = 8'h4f; ram[349] = 8'h03; ram[350] = 8'hc9; ram[351] = 8'h7b;
ram[352] = 8'h17; ram[353] = 8'h5f; ram[354] = 8'h7a; ram[355] = 8'h17;
ram[356] = 8'h57; ram[357] = 8'hb3; ram[358] = 8'hc9; ram[359] = 8'h7b;
ram[360] = 8'h91; ram[361] = 8'h7a; ram[362] = 8'h98; ram[363] = 8'hc9;
ram[364] = 8'hdb; ram[365] = 8'h83; ram[366] = 8'hcd; ram[367] = 8'h43;
ram[368] = 8'h00; ram[369] = 8'he5; ram[370] = 8'h21; ram[371] = 8'h01;
ram[372] = 8'h00; ram[373] = 8'hd1; ram[374] = 8'hcd; ram[375] = 8'h64;
ram[376] = 8'h00; ram[377] = 8'h7c; ram[378] = 8'hb5; ram[379] = 8'hca;
ram[380] = 8'h81; ram[381] = 8'h01; ram[382] = 8'hc3; ram[383] = 8'h6c;
ram[384] = 8'h01; ram[385] = 8'h21; ram[386] = 8'h02; ram[387] = 8'h00;
ram[388] = 8'h39; ram[389] = 8'hcd; ram[390] = 8'h42; ram[391] = 8'h00;
ram[392] = 8'h7d; ram[393] = 8'hd3; ram[394] = 8'h80; ram[395] = 8'hc9;
ram[396] = 8'hdb; ram[397] = 8'h83; ram[398] = 8'hcd; ram[399] = 8'h43;
ram[400] = 8'h00; ram[401] = 8'he5; ram[402] = 8'h21; ram[403] = 8'h10;
ram[404] = 8'h00; ram[405] = 8'hd1; ram[406] = 8'hcd; ram[407] = 8'h64;
ram[408] = 8'h00; ram[409] = 8'h7c; ram[410] = 8'hb5; ram[411] = 8'hca;
ram[412] = 8'hae; ram[413] = 8'h01; ram[414] = 8'hdb; ram[415] = 8'h80;
ram[416] = 8'hcd; ram[417] = 8'h43; ram[418] = 8'h00; ram[419] = 8'h7d;
ram[420] = 8'h32; ram[421] = 8'h2c; ram[422] = 8'h04; ram[423] = 8'h21;
ram[424] = 8'h01; ram[425] = 8'h00; ram[426] = 8'hc9; ram[427] = 8'hc3;
ram[428] = 8'hb2; ram[429] = 8'h01; ram[430] = 8'h21; ram[431] = 8'h00;
ram[432] = 8'h00; ram[433] = 8'hc9; ram[434] = 8'hc9; ram[435] = 8'h21;
ram[436] = 8'h0d; ram[437] = 8'h00; ram[438] = 8'he5; ram[439] = 8'hcd;
ram[440] = 8'h6c; ram[441] = 8'h01; ram[442] = 8'hc1; ram[443] = 8'h21;
ram[444] = 8'h0a; ram[445] = 8'h00; ram[446] = 8'he5; ram[447] = 8'hcd;
ram[448] = 8'h6c; ram[449] = 8'h01; ram[450] = 8'hc1; ram[451] = 8'hc9;
ram[452] = 8'h21; ram[453] = 8'h02; ram[454] = 8'h00; ram[455] = 8'h39;
ram[456] = 8'hcd; ram[457] = 8'h48; ram[458] = 8'h00; ram[459] = 8'hcd;
ram[460] = 8'h42; ram[461] = 8'h00; ram[462] = 8'he5; ram[463] = 8'h21;
ram[464] = 8'h00; ram[465] = 8'h00; ram[466] = 8'hd1; ram[467] = 8'hcd;
ram[468] = 8'h71; ram[469] = 8'h00; ram[470] = 8'h7c; ram[471] = 8'hb5;
ram[472] = 8'hca; ram[473] = 8'hf4; ram[474] = 8'h01; ram[475] = 8'h21;
ram[476] = 8'h02; ram[477] = 8'h00; ram[478] = 8'h39; ram[479] = 8'he5;
ram[480] = 8'hcd; ram[481] = 8'h48; ram[482] = 8'h00; ram[483] = 8'h23;
ram[484] = 8'hd1; ram[485] = 8'hcd; ram[486] = 8'h50; ram[487] = 8'h00;
ram[488] = 8'h2b; ram[489] = 8'hcd; ram[490] = 8'h42; ram[491] = 8'h00;
ram[492] = 8'he5; ram[493] = 8'hcd; ram[494] = 8'h6c; ram[495] = 8'h01;
ram[496] = 8'hc1; ram[497] = 8'hc3; ram[498] = 8'hc4; ram[499] = 8'h01;
ram[500] = 8'hc9; ram[501] = 8'h21; ram[502] = 8'h02; ram[503] = 8'h00;
ram[504] = 8'h39; ram[505] = 8'hcd; ram[506] = 8'h48; ram[507] = 8'h00;
ram[508] = 8'he5; ram[509] = 8'h21; ram[510] = 8'h00; ram[511] = 8'h00;
ram[512] = 8'hd1; ram[513] = 8'hcd; ram[514] = 8'h8b; ram[515] = 8'h00;
ram[516] = 8'h7c; ram[517] = 8'hb5; ram[518] = 8'hca; ram[519] = 8'h24;
ram[520] = 8'h02; ram[521] = 8'h21; ram[522] = 8'h2d; ram[523] = 8'h00;
ram[524] = 8'he5; ram[525] = 8'hcd; ram[526] = 8'h6c; ram[527] = 8'h01;
ram[528] = 8'hc1; ram[529] = 8'h21; ram[530] = 8'h02; ram[531] = 8'h00;
ram[532] = 8'h39; ram[533] = 8'he5; ram[534] = 8'h21; ram[535] = 8'h04;
ram[536] = 8'h00; ram[537] = 8'h39; ram[538] = 8'hcd; ram[539] = 8'h48;
ram[540] = 8'h00; ram[541] = 8'hcd; ram[542] = 8'he2; ram[543] = 8'h00;
ram[544] = 8'hd1; ram[545] = 8'hcd; ram[546] = 8'h50; ram[547] = 8'h00;
ram[548] = 8'h21; ram[549] = 8'h02; ram[550] = 8'h00; ram[551] = 8'h39;
ram[552] = 8'hcd; ram[553] = 8'h48; ram[554] = 8'h00; ram[555] = 8'he5;
ram[556] = 8'hcd; ram[557] = 8'h31; ram[558] = 8'h02; ram[559] = 8'hc1;
ram[560] = 8'hc9; ram[561] = 8'hc5; ram[562] = 8'h21; ram[563] = 8'h00;
ram[564] = 8'h00; ram[565] = 8'h39; ram[566] = 8'he5; ram[567] = 8'h21;
ram[568] = 8'h06; ram[569] = 8'h00; ram[570] = 8'h39; ram[571] = 8'hcd;
ram[572] = 8'h48; ram[573] = 8'h00; ram[574] = 8'he5; ram[575] = 8'h21;
ram[576] = 8'h0a; ram[577] = 8'h00; ram[578] = 8'hd1; ram[579] = 8'hcd;
ram[580] = 8'h0e; ram[581] = 8'h01; ram[582] = 8'hd1; ram[583] = 8'hcd;
ram[584] = 8'h50; ram[585] = 8'h00; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'hcd; ram[591] = 8'h48;
ram[592] = 8'h00; ram[593] = 8'h7c; ram[594] = 8'hb5; ram[595] = 8'hca;
ram[596] = 8'h62; ram[597] = 8'h02; ram[598] = 8'h21; ram[599] = 8'h00;
ram[600] = 8'h00; ram[601] = 8'h39; ram[602] = 8'hcd; ram[603] = 8'h48;
ram[604] = 8'h00; ram[605] = 8'he5; ram[606] = 8'hcd; ram[607] = 8'h31;
ram[608] = 8'h02; ram[609] = 8'hc1; ram[610] = 8'h21; ram[611] = 8'h30;
ram[612] = 8'h00; ram[613] = 8'he5; ram[614] = 8'h21; ram[615] = 8'h06;
ram[616] = 8'h00; ram[617] = 8'h39; ram[618] = 8'hcd; ram[619] = 8'h48;
ram[620] = 8'h00; ram[621] = 8'he5; ram[622] = 8'h21; ram[623] = 8'h04;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h48;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'h21; ram[631] = 8'h0a;
ram[632] = 8'h00; ram[633] = 8'hd1; ram[634] = 8'hcd; ram[635] = 8'hee;
ram[636] = 8'h00; ram[637] = 8'hd1; ram[638] = 8'hcd; ram[639] = 8'hdb;
ram[640] = 8'h00; ram[641] = 8'hd1; ram[642] = 8'h19; ram[643] = 8'he5;
ram[644] = 8'hcd; ram[645] = 8'h6c; ram[646] = 8'h01; ram[647] = 8'hc1;
ram[648] = 8'hc1; ram[649] = 8'hc9; ram[650] = 8'hc5; ram[651] = 8'h21;
ram[652] = 8'h00; ram[653] = 8'h00; ram[654] = 8'h39; ram[655] = 8'he5;
ram[656] = 8'h21; ram[657] = 8'h06; ram[658] = 8'h00; ram[659] = 8'h39;
ram[660] = 8'hcd; ram[661] = 8'h48; ram[662] = 8'h00; ram[663] = 8'he5;
ram[664] = 8'h21; ram[665] = 8'h10; ram[666] = 8'h00; ram[667] = 8'hd1;
ram[668] = 8'hcd; ram[669] = 8'h0e; ram[670] = 8'h01; ram[671] = 8'hd1;
ram[672] = 8'hcd; ram[673] = 8'h50; ram[674] = 8'h00; ram[675] = 8'h21;
ram[676] = 8'h00; ram[677] = 8'h00; ram[678] = 8'h39; ram[679] = 8'hcd;
ram[680] = 8'h48; ram[681] = 8'h00; ram[682] = 8'h7c; ram[683] = 8'hb5;
ram[684] = 8'hca; ram[685] = 8'hbb; ram[686] = 8'h02; ram[687] = 8'h21;
ram[688] = 8'h00; ram[689] = 8'h00; ram[690] = 8'h39; ram[691] = 8'hcd;
ram[692] = 8'h48; ram[693] = 8'h00; ram[694] = 8'he5; ram[695] = 8'hcd;
ram[696] = 8'h8a; ram[697] = 8'h02; ram[698] = 8'hc1; ram[699] = 8'h21;
ram[700] = 8'h00; ram[701] = 8'h00; ram[702] = 8'h39; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h06; ram[706] = 8'h00; ram[707] = 8'h39;
ram[708] = 8'hcd; ram[709] = 8'h48; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'h21; ram[713] = 8'h04; ram[714] = 8'h00; ram[715] = 8'h39;
ram[716] = 8'hcd; ram[717] = 8'h48; ram[718] = 8'h00; ram[719] = 8'he5;
ram[720] = 8'h21; ram[721] = 8'h10; ram[722] = 8'h00; ram[723] = 8'hd1;
ram[724] = 8'hcd; ram[725] = 8'hee; ram[726] = 8'h00; ram[727] = 8'hd1;
ram[728] = 8'hcd; ram[729] = 8'hdb; ram[730] = 8'h00; ram[731] = 8'hd1;
ram[732] = 8'hcd; ram[733] = 8'h50; ram[734] = 8'h00; ram[735] = 8'h21;
ram[736] = 8'h00; ram[737] = 8'h00; ram[738] = 8'h39; ram[739] = 8'hcd;
ram[740] = 8'h48; ram[741] = 8'h00; ram[742] = 8'he5; ram[743] = 8'h21;
ram[744] = 8'h09; ram[745] = 8'h00; ram[746] = 8'hd1; ram[747] = 8'hcd;
ram[748] = 8'h77; ram[749] = 8'h00; ram[750] = 8'h7c; ram[751] = 8'hb5;
ram[752] = 8'hca; ram[753] = 8'h10; ram[754] = 8'h03; ram[755] = 8'h21;
ram[756] = 8'h41; ram[757] = 8'h00; ram[758] = 8'he5; ram[759] = 8'h21;
ram[760] = 8'h02; ram[761] = 8'h00; ram[762] = 8'h39; ram[763] = 8'hcd;
ram[764] = 8'h48; ram[765] = 8'h00; ram[766] = 8'hd1; ram[767] = 8'h19;
ram[768] = 8'he5; ram[769] = 8'h21; ram[770] = 8'h0a; ram[771] = 8'h00;
ram[772] = 8'hd1; ram[773] = 8'hcd; ram[774] = 8'hdb; ram[775] = 8'h00;
ram[776] = 8'he5; ram[777] = 8'hcd; ram[778] = 8'h6c; ram[779] = 8'h01;
ram[780] = 8'hc1; ram[781] = 8'hc3; ram[782] = 8'h22; ram[783] = 8'h03;
ram[784] = 8'h21; ram[785] = 8'h30; ram[786] = 8'h00; ram[787] = 8'he5;
ram[788] = 8'h21; ram[789] = 8'h02; ram[790] = 8'h00; ram[791] = 8'h39;
ram[792] = 8'hcd; ram[793] = 8'h48; ram[794] = 8'h00; ram[795] = 8'hd1;
ram[796] = 8'h19; ram[797] = 8'he5; ram[798] = 8'hcd; ram[799] = 8'h6c;
ram[800] = 8'h01; ram[801] = 8'hc1; ram[802] = 8'hc1; ram[803] = 8'hc9;
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5;
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1;
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9;
ram[816] = 8'h21; ram[817] = 8'h01; ram[818] = 8'h00; ram[819] = 8'h7d;
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00;
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82;
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d;
ram[832] = 8'hd3; ram[833] = 8'h84; ram[834] = 8'h21; ram[835] = 8'hff;
ram[836] = 8'h00; ram[837] = 8'h7d; ram[838] = 8'hd3; ram[839] = 8'h85;
ram[840] = 8'h21; ram[841] = 8'h00; ram[842] = 8'h00; ram[843] = 8'h7d;
ram[844] = 8'hd3; ram[845] = 8'h86; ram[846] = 8'h21; ram[847] = 8'hff;
ram[848] = 8'h00; ram[849] = 8'h7d; ram[850] = 8'hd3; ram[851] = 8'h87;
ram[852] = 8'h21; ram[853] = 8'h01; ram[854] = 8'h00; ram[855] = 8'h7d;
ram[856] = 8'hd3; ram[857] = 8'h88; ram[858] = 8'hfb; ram[859] = 8'h21;
ram[860] = 8'hea; ram[861] = 8'h03; ram[862] = 8'he5; ram[863] = 8'hcd;
ram[864] = 8'hc4; ram[865] = 8'h01; ram[866] = 8'hc1; ram[867] = 8'hcd;
ram[868] = 8'hb3; ram[869] = 8'h01; ram[870] = 8'h21; ram[871] = 8'hf9;
ram[872] = 8'h03; ram[873] = 8'he5; ram[874] = 8'hcd; ram[875] = 8'hc4;
ram[876] = 8'h01; ram[877] = 8'hc1; ram[878] = 8'h21; ram[879] = 8'h2d;
ram[880] = 8'h04; ram[881] = 8'he5; ram[882] = 8'h21; ram[883] = 8'h01;
ram[884] = 8'h00; ram[885] = 8'h29; ram[886] = 8'hd1; ram[887] = 8'h19;
ram[888] = 8'hcd; ram[889] = 8'h48; ram[890] = 8'h00; ram[891] = 8'he5;
ram[892] = 8'hcd; ram[893] = 8'hf5; ram[894] = 8'h01; ram[895] = 8'hc1;
ram[896] = 8'hcd; ram[897] = 8'hb3; ram[898] = 8'h01; ram[899] = 8'h21;
ram[900] = 8'h05; ram[901] = 8'h04; ram[902] = 8'he5; ram[903] = 8'hcd;
ram[904] = 8'hc4; ram[905] = 8'h01; ram[906] = 8'hc1; ram[907] = 8'h21;
ram[908] = 8'h2d; ram[909] = 8'h04; ram[910] = 8'he5; ram[911] = 8'h21;
ram[912] = 8'h00; ram[913] = 8'h00; ram[914] = 8'h29; ram[915] = 8'hd1;
ram[916] = 8'h19; ram[917] = 8'hcd; ram[918] = 8'h48; ram[919] = 8'h00;
ram[920] = 8'he5; ram[921] = 8'hcd; ram[922] = 8'h8a; ram[923] = 8'h02;
ram[924] = 8'hc1; ram[925] = 8'hcd; ram[926] = 8'hb3; ram[927] = 8'h01;
ram[928] = 8'h21; ram[929] = 8'h01; ram[930] = 8'h00; ram[931] = 8'h7d;
ram[932] = 8'hd3; ram[933] = 8'h84; ram[934] = 8'h21; ram[935] = 8'h13;
ram[936] = 8'h04; ram[937] = 8'he5; ram[938] = 8'hcd; ram[939] = 8'hc4;
ram[940] = 8'h01; ram[941] = 8'hc1; ram[942] = 8'hcd; ram[943] = 8'hb3;
ram[944] = 8'h01; ram[945] = 8'h21; ram[946] = 8'h01; ram[947] = 8'h00;
ram[948] = 8'h7c; ram[949] = 8'hb5; ram[950] = 8'hca; ram[951] = 8'hcf;
ram[952] = 8'h03; ram[953] = 8'hcd; ram[954] = 8'h8c; ram[955] = 8'h01;
ram[956] = 8'h7c; ram[957] = 8'hb5; ram[958] = 8'hca; ram[959] = 8'hcc;
ram[960] = 8'h03; ram[961] = 8'h3a; ram[962] = 8'h2c; ram[963] = 8'h04;
ram[964] = 8'hcd; ram[965] = 8'h43; ram[966] = 8'h00; ram[967] = 8'he5;
ram[968] = 8'hcd; ram[969] = 8'h6c; ram[970] = 8'h01; ram[971] = 8'hc1;
ram[972] = 8'hc3; ram[973] = 8'hb1; ram[974] = 8'h03; ram[975] = 8'hc9;
ram[976] = 8'h49; ram[977] = 8'h6e; ram[978] = 8'h74; ram[979] = 8'h65;
ram[980] = 8'h72; ram[981] = 8'h72; ram[982] = 8'h75; ram[983] = 8'h70;
ram[984] = 8'h74; ram[985] = 8'h20; ram[986] = 8'h30; ram[987] = 8'h20;
ram[988] = 8'h77; ram[989] = 8'h61; ram[990] = 8'h73; ram[991] = 8'h20;
ram[992] = 8'h61; ram[993] = 8'h73; ram[994] = 8'h73; ram[995] = 8'h65;
ram[996] = 8'h72; ram[997] = 8'h74; ram[998] = 8'h65; ram[999] = 8'h64;
ram[1000] = 8'h2e; ram[1001] = 8'h00; ram[1002] = 8'h48; ram[1003] = 8'h65;
ram[1004] = 8'h6c; ram[1005] = 8'h6c; ram[1006] = 8'h6f; ram[1007] = 8'h20;
ram[1008] = 8'h57; ram[1009] = 8'h6f; ram[1010] = 8'h72; ram[1011] = 8'h6c;
ram[1012] = 8'h64; ram[1013] = 8'h21; ram[1014] = 8'h21; ram[1015] = 8'h21;
ram[1016] = 8'h00; ram[1017] = 8'h44; ram[1018] = 8'h65; ram[1019] = 8'h63;
ram[1020] = 8'h20; ram[1021] = 8'h76; ram[1022] = 8'h61; ram[1023] = 8'h6c;
ram[1024] = 8'h75; ram[1025] = 8'h65; ram[1026] = 8'h3a; ram[1027] = 8'h20;
ram[1028] = 8'h00; ram[1029] = 8'h48; ram[1030] = 8'h65; ram[1031] = 8'h78;
ram[1032] = 8'h20; ram[1033] = 8'h76; ram[1034] = 8'h61; ram[1035] = 8'h6c;
ram[1036] = 8'h75; ram[1037] = 8'h65; ram[1038] = 8'h3a; ram[1039] = 8'h20;
ram[1040] = 8'h30; ram[1041] = 8'h78; ram[1042] = 8'h00; ram[1043] = 8'h45;
ram[1044] = 8'h63; ram[1045] = 8'h68; ram[1046] = 8'h6f; ram[1047] = 8'h69;
ram[1048] = 8'h6e; ram[1049] = 8'h67; ram[1050] = 8'h20; ram[1051] = 8'h72;
ram[1052] = 8'h65; ram[1053] = 8'h63; ram[1054] = 8'h65; ram[1055] = 8'h69;
ram[1056] = 8'h76; ram[1057] = 8'h65; ram[1058] = 8'h64; ram[1059] = 8'h20;
ram[1060] = 8'h62; ram[1061] = 8'h79; ram[1062] = 8'h74; ram[1063] = 8'h65;
ram[1064] = 8'h73; ram[1065] = 8'h3a; ram[1066] = 8'h20; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'hd2; ram[1070] = 8'h04; ram[1071] = 8'h2e;
ram[1072] = 8'h16; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
/trunk/verilog/rtl/l80soc.v
32,7 → 32,8
(
clock, reset,
txd, rxd,
p1dio, p2dio
p1dio, p2dio,
extint
);
//---------------------------------------------------------------------------------------
// module interfaces
45,6 → 46,8
// digital IO ports
inout [7:0] p1dio; // port 1 digital IO
inout [7:0] p2dio; // port 2 digital IO
// external interrupt sources
input [3:0] extint; // external interrupt sources
 
//---------------------------------------------------------------------------------------
// io space registers addresses
58,6 → 61,8
`define P1_DIR_REG 8'h85 // port 1 direction register
`define P2_DATA_REG 8'h86 // port 2 data register
`define P2_DIR_REG 8'h87 // port 2 direction register
// interrupt controller register
`define INTR_EN_REG 8'h88 // interrupts enable register
 
//---------------------------------------------------------------------------------------
// internal declarations
65,14 → 70,14
 
// internals
wire [15:0] cpu_addr;
wire [7:0] cpu_din, cpu_dout, ram_dout;
wire cpu_io, cpu_rd, cpu_wr;
wire [7:0] txData;
wire txValid, txBusy, rxValid, lcd_clk;
wire [7:0] rxData;
wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
wire [7:0] txData, rxData;
wire txValid, txBusy, rxValid;
reg [15:0] uartbaud;
reg rxfull, scpu_io;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
reg [3:0] intr_ena;
 
//---------------------------------------------------------------------------------------
// module implementation
89,13 → 94,13
.fetch(/* nu */),
.data_in(cpu_din),
.data_out(cpu_dout),
.inta(/* nu */),
.inte(/* nu */),
.inta(cpu_inta),
.inte(cpu_inte),
.halt(/* nu */),
.intr(1'b0)
.intr(cpu_intr)
);
// cpu data input selection
assign cpu_din = scpu_io ? io_dout : ram_dout;
assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
 
// program and data Xilinx RAM memory
ram_image ram
118,6 → 123,7
p1dir <= 8'b0;
p2reg <= 8'b0;
p2dir <= 8'b0;
intr_ena <= 4'b0;
end
else
begin
130,6 → 136,7
if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
if (cpu_addr[7:0] == `INTR_EN_REG) intr_ena <= cpu_dout[3:0];
end
// receiver full flag
166,6 → 173,20
end
end
 
// interrupt controller
intr_ctrl intrc
(
.clock(clock),
.reset(reset),
.ext_intr(extint),
.cpu_intr(cpu_intr),
.cpu_inte(cpu_inte),
.cpu_inta(cpu_inta),
.cpu_rd(cpu_rd),
.cpu_inst(intr_dout),
.intr_ena(intr_ena)
);
 
// uart module mapped to the io space
uart uart
(
/trunk/verilog/sim/icarus/block.cfg
1,6 → 1,7
../../rtl/uart.v
../../rtl/ram_image.v
../../rtl/micro_rom.v
../../rtl/intr_ctrl.v
../../rtl/light8080.v
../../rtl/l80soc.v
../../bench/tb_l80soc.v
/trunk/verilog/syn/xilinx_s3/xilinx_s3.xise
38,6 → 38,10
<file xil_pn:name="l80soc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../rtl/intr_ctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
/trunk/verilog/syn/xilinx_s3/l80soc_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (02/21/2012 - 11:58:43)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (03/03/2012 - 19:50:25)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>xilinx_s3.ise</TD>
20,7 → 20,7
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s200-4ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>33 Warnings</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>26 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.4</TD>
51,43 → 51,43
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>211</TD>
<TD ALIGN=RIGHT>233</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>5%</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>327</TD>
<TD ALIGN=RIGHT>377</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>1,920</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>328</TD>
<TD ALIGN=RIGHT>378</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>311</TD>
<TD ALIGN=RIGHT>361</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
105,9 → 105,9
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>173</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD>
123,7 → 123,7
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.29</TD>
<TD ALIGN=RIGHT>3.36</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
160,12 → 160,12
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:54:55 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>31 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>6 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:21 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:40 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:01 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>24 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>9 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:23 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:25 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
174,5 → 174,5
</TABLE>
 
 
<br><center><b>Date Generated:</b> 02/21/2012 - 11:58:43</center>
<br><center><b>Date Generated:</b> 03/03/2012 - 19:50:25</center>
</BODY></HTML>
/trunk/verilog/syn/altera_c2/l80soc.qsf
49,11 → 49,6
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
62,4 → 57,10
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name FMAX_REQUIREMENT "15 ns"
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/verilog/syn/altera_c2/l80soc.fit.rpt
1,5 → 1,5
Fitter report for l80soc
Tue Feb 21 12:01:11 2012
Sat Mar 03 19:54:03 2012
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
 
 
63,7 → 63,7
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
; Fitter Status ; Successful - Tue Feb 21 12:01:11 2012 ;
; Fitter Status ; Successful - Sat Mar 03 19:54:03 2012 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; l80soc ;
; Top-level Entity Name ; l80soc ;
70,11 → 70,11
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Total logic elements ; 596 / 8,256 ( 7 % ) ;
; Total combinational functions ; 452 / 8,256 ( 5 % ) ;
; Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
; Total registers ; 339 ;
; Total pins ; 20 / 138 ( 14 % ) ;
; Total logic elements ; 646 / 8,256 ( 8 % ) ;
; Total combinational functions ; 496 / 8,256 ( 6 % ) ;
; Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;
; Total registers ; 361 ;
; Total pins ; 24 / 138 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 47,616 / 165,888 ( 29 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
152,8 → 152,8
; Type ; Value ;
+-------------------------+--------------------+
; Placement ; ;
; -- Requested ; 0 / 854 ( 0.00 % ) ;
; -- Achieved ; 0 / 854 ( 0.00 % ) ;
; -- Requested ; 0 / 924 ( 0.00 % ) ;
; -- Achieved ; 0 / 924 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
175,7 → 175,7
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top ; 854 ; 0 ; N/A ; Source File ;
; Top ; 924 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
 
 
190,29 → 190,29
+---------------------------------------------+---------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------+
; Total logic elements ; 596 / 8,256 ( 7 % ) ;
; -- Combinational with no register ; 257 ;
; -- Register only ; 144 ;
; -- Combinational with a register ; 195 ;
; Total logic elements ; 646 / 8,256 ( 8 % ) ;
; -- Combinational with no register ; 285 ;
; -- Register only ; 150 ;
; -- Combinational with a register ; 211 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 275 ;
; -- 3 input functions ; 68 ;
; -- <=2 input functions ; 109 ;
; -- Register only ; 144 ;
; -- 4 input functions ; 325 ;
; -- 3 input functions ; 72 ;
; -- <=2 input functions ; 99 ;
; -- Register only ; 150 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 406 ;
; -- normal mode ; 450 ;
; -- arithmetic mode ; 46 ;
; ; ;
; Total registers* ; 339 / 8,646 ( 4 % ) ;
; -- Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
; Total registers* ; 361 / 8,646 ( 4 % ) ;
; -- Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;
; -- I/O registers ; 0 / 390 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 47 / 516 ( 9 % ) ;
; Total LABs: partially or completely used ; 53 / 516 ( 10 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 20 / 138 ( 14 % ) ;
; I/O pins ; 24 / 138 ( 17 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; Global signals ; 2 ;
; M4Ks ; 12 / 36 ( 33 % ) ;
224,28 → 224,32
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 2% / 2% / 3% ;
; Peak interconnect usage (total/H/V) ; 6% / 6% / 7% ;
; Average interconnect usage (total/H/V) ; 2% / 3% / 2% ;
; Peak interconnect usage (total/H/V) ; 8% / 8% / 7% ;
; Maximum fan-out node ; clock~clkctrl ;
; Maximum fan-out ; 351 ;
; Maximum fan-out ; 373 ;
; Highest non-global fan-out signal ; reset ;
; Highest non-global fan-out ; 50 ;
; Total fan-out ; 2865 ;
; Average fan-out ; 3.16 ;
; Highest non-global fan-out ; 54 ;
; Total fan-out ; 3136 ;
; Average fan-out ; 3.18 ;
+---------------------------------------------+---------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
 
 
 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 51 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; rxd ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[0] ; 14 ; 1 ; 0 ; 14 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[1] ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[2] ; 145 ; 3 ; 34 ; 14 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[3] ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 55 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; rxd ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
 
 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
253,7 → 257,7
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; txd ; 61 ; 4 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
; txd ; 192 ; 2 ; 9 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
 
 
262,22 → 266,22
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; p1dio[0] ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;
; p1dio[1] ; 189 ; 2 ; 12 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;
; p1dio[2] ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;
; p1dio[3] ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;
; p1dio[4] ; 35 ; 1 ; 0 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;
; p1dio[5] ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;
; p1dio[6] ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;
; p1dio[7] ; 187 ; 2 ; 14 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;
; p2dio[0] ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;
; p2dio[1] ; 60 ; 4 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;
; p2dio[2] ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;
; p2dio[3] ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;
; p2dio[4] ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;
; p2dio[5] ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;
; p2dio[6] ; 64 ; 4 ; 5 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;
; p2dio[7] ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;
; p1dio[0] ; 189 ; 2 ; 12 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;
; p1dio[1] ; 187 ; 2 ; 14 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;
; p1dio[2] ; 149 ; 3 ; 34 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;
; p1dio[3] ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;
; p1dio[4] ; 171 ; 2 ; 28 ; 19 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;
; p1dio[5] ; 182 ; 2 ; 18 ; 19 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;
; p1dio[6] ; 150 ; 3 ; 34 ; 16 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;
; p1dio[7] ; 180 ; 2 ; 18 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;
; p2dio[0] ; 191 ; 2 ; 12 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;
; p2dio[1] ; 188 ; 2 ; 12 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;
; p2dio[2] ; 176 ; 2 ; 23 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;
; p2dio[3] ; 185 ; 2 ; 14 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;
; p2dio[4] ; 173 ; 2 ; 25 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;
; p2dio[5] ; 179 ; 2 ; 18 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;
; p2dio[6] ; 181 ; 2 ; 18 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;
; p2dio[7] ; 175 ; 2 ; 23 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
 
 
286,10 → 290,10
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 8 / 32 ( 25 % ) ; 3.3V ; -- ;
; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
; 4 ; 12 / 36 ( 33 % ) ; 3.3V ; -- ;
; 1 ; 7 / 32 ( 22 % ) ; 3.3V ; -- ;
; 2 ; 14 / 35 ( 40 % ) ; 3.3V ; -- ;
; 3 ; 4 / 35 ( 11 % ) ; 3.3V ; -- ;
; 4 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
 
 
311,7 → 315,7
; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; extint[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
324,17 → 328,17
; 24 ; 28 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 27 ; 30 ; 1 ; rxd ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 27 ; 30 ; 1 ; extint[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; extint[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 34 ; 36 ; 1 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 34 ; 36 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
357,24 → 361,24
; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 61 ; 59 ; 4 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 64 ; 61 ; 4 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 67 ; 69 ; 4 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 68 ; 70 ; 4 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 69 ; 71 ; 4 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 70 ; 74 ; 4 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 72 ; 75 ; 4 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 74 ; 76 ; 4 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 75 ; 77 ; 4 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 76 ; 78 ; 4 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 77 ; 79 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 74 ; 76 ; 4 ; rxd ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 75 ; 77 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
442,12 → 446,12
; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; extint[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 149 ; 151 ; 3 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 150 ; 152 ; 3 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
468,28 → 472,28
; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 173 ; 165 ; 2 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 175 ; 168 ; 2 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 176 ; 169 ; 2 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 179 ; 173 ; 2 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 180 ; 174 ; 2 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 181 ; 175 ; 2 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 182 ; 176 ; 2 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 185 ; 180 ; 2 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 187 ; 181 ; 2 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 189 ; 183 ; 2 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 187 ; 181 ; 2 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 188 ; 182 ; 2 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 189 ; 183 ; 2 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 191 ; 184 ; 2 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 192 ; 185 ; 2 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
552,88 → 556,100
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
; |l80soc ; 596 (90) ; 339 (58) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 20 ; 0 ; 257 (32) ; 144 (37) ; 195 (15) ; |l80soc ; work ;
; |light8080:cpu| ; 422 (422) ; 218 (218) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 204 (204) ; 89 (89) ; 129 (129) ; |l80soc|light8080:cpu ; ;
; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; ;
; |l80soc ; 646 (101) ; 361 (62) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 24 ; 0 ; 285 (39) ; 150 (39) ; 211 (15) ; |l80soc ; work ;
; |intr_ctrl:intrc| ; 27 (27) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 13 (13) ; |l80soc|intr_ctrl:intrc ; work ;
; |light8080:cpu| ; 435 (435) ; 222 (222) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 213 (213) ; 92 (92) ; 130 (130) ; |l80soc|light8080:cpu ; ;
; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; work ;
; |altsyncram:Ram0_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0 ; ;
; |altsyncram_ts61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated ; ;
; |ram_image:ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram ; work ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_9il1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated ; ;
; |uart:uart| ; 91 (91) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 18 (18) ; 52 (52) ; |l80soc|uart:uart ; ;
; |uart:uart| ; 91 (91) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 18 (18) ; 53 (53) ; |l80soc|uart:uart ; work ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
+-----------------------------------------------------------------------------------+
; Delay Chain Summary ;
+----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+----------+----------+---------------+---------------+-----------------------+-----+
; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[2] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[4] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[0] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p2dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; txd ; Output ; -- ; -- ; -- ; -- ;
; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; rxd ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
+----------+----------+---------------+---------------+-----------------------+-----+
+------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[6] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[2] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; txd ; Output ; -- ; -- ; -- ; -- ;
; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[1] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[3] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[2] ; Input ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; extint[0] ; Input ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; rxd ; Input ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+-----------+----------+---------------+---------------+-----------------------+-----+
 
 
+---------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; p1dio[0] ; ; ;
; - io_dout~3 ; 0 ; 6 ;
; p1dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p1dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p1dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p1dio[4] ; ; ;
; - io_dout~14 ; 1 ; 6 ;
; p1dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p1dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p1dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; p2dio[0] ; ; ;
; - io_dout~2 ; 0 ; 6 ;
; p2dio[1] ; ; ;
; - io_dout~7 ; 1 ; 6 ;
; p2dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p2dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p2dio[4] ; ; ;
; - io_dout~13 ; 0 ; 6 ;
; p2dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p2dio[6] ; ; ;
; - io_dout~17 ; 1 ; 6 ;
; p2dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; clock ; ; ;
; reset ; ; ;
; rxd ; ; ;
+---------------------+-------------------+---------+
+----------------------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+----------------------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+----------------------------------+-------------------+---------+
; p1dio[0] ; ; ;
; - io_dout~3 ; 1 ; 6 ;
; p1dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p1dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p1dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p1dio[4] ; ; ;
; - io_dout~14 ; 1 ; 6 ;
; p1dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p1dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p1dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; p2dio[0] ; ; ;
; - io_dout~2 ; 0 ; 6 ;
; p2dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p2dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p2dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p2dio[4] ; ; ;
; - io_dout~13 ; 1 ; 6 ;
; p2dio[5] ; ; ;
; - io_dout~15 ; 1 ; 6 ;
; p2dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p2dio[7] ; ; ;
; - io_dout~19 ; 1 ; 6 ;
; clock ; ; ;
; reset ; ; ;
; extint[1] ; ; ;
; extint[3] ; ; ;
; extint[2] ; ; ;
; - intr_ctrl:intrc|act_int~5 ; 1 ; 6 ;
; extint[0] ; ; ;
; - intr_ctrl:intrc|act_int~7 ; 0 ; 6 ;
; rxd ; ; ;
; - uart:uart|sserIn~feeder ; 0 ; 6 ;
+----------------------------------+-------------------+---------+
 
 
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
641,67 → 657,72
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; clock ; PIN_23 ; 351 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
; comb~0 ; LCCOMB_X12_Y8_N22 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
; io_dout[0]~5 ; LCCOMB_X13_Y6_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|Equal18~0 ; LCCOMB_X14_Y12_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;
; light8080:cpu|T1[2]~3 ; LCCOMB_X15_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|T2[0]~3 ; LCCOMB_X15_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|addr_low[1]~1 ; LCCOMB_X12_Y8_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|flag_reg[2]~8 ; LCCOMB_X15_Y8_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~209 ; LCCOMB_X14_Y9_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~211 ; LCCOMB_X14_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~213 ; LCCOMB_X12_Y13_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~215 ; LCCOMB_X16_Y11_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~217 ; LCCOMB_X13_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~219 ; LCCOMB_X16_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~221 ; LCCOMB_X14_Y9_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~223 ; LCCOMB_X13_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~225 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~227 ; LCCOMB_X14_Y9_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~229 ; LCCOMB_X14_Y9_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~231 ; LCCOMB_X16_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~233 ; LCCOMB_X13_Y11_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~235 ; LCCOMB_X13_Y11_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~237 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~239 ; LCCOMB_X16_Y11_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_decode~0 ; LCCOMB_X16_Y9_N26 ; 21 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_ret_addr[4]~1 ; LCCOMB_X16_Y7_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|ucode_field2[7] ; LCFF_X17_Y9_N17 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[0] ; LCFF_X14_Y7_N31 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[0]~1 ; LCCOMB_X14_Y7_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[1] ; LCFF_X14_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[2] ; LCFF_X14_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[3] ; LCFF_X14_Y7_N15 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[4] ; LCFF_X14_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[5] ; LCFF_X14_Y7_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[6] ; LCFF_X14_Y7_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[7] ; LCFF_X14_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1reg[0]~0 ; LCCOMB_X14_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[0] ; LCFF_X13_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[0]~0 ; LCCOMB_X13_Y7_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[1] ; LCFF_X13_Y7_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[2] ; LCFF_X13_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[3] ; LCFF_X13_Y7_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[4] ; LCFF_X13_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[5] ; LCFF_X13_Y7_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[6] ; LCFF_X13_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[7] ; LCFF_X13_Y7_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2reg[0]~0 ; LCCOMB_X12_Y7_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 51 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 120 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
; uart:uart|Equal5~10 ; LCCOMB_X9_Y6_N2 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxBaudCnt[3]~1 ; LCCOMB_X8_Y6_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBitCnt[0]~12 ; LCCOMB_X9_Y6_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBusy ; LCFF_X8_Y6_N29 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxData[0]~0 ; LCCOMB_X9_Y6_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X9_Y6_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBitCnt[0]~6 ; LCCOMB_X8_Y8_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBusy ; LCFF_X9_Y8_N15 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg[3]~6 ; LCCOMB_X10_Y8_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg~14 ; LCCOMB_X10_Y8_N10 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[15]~1 ; LCCOMB_X10_Y7_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[7]~0 ; LCCOMB_X10_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; clock ; PIN_23 ; 373 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
; comb~0 ; LCCOMB_X18_Y14_N0 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|Equal3~0 ; LCCOMB_X15_Y14_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|cpu_inst[4]~8 ; LCCOMB_X15_Y14_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|intSel~15 ; LCCOMB_X15_Y14_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ena[0]~1 ; LCCOMB_X18_Y14_N8 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; io_dout[0]~5 ; LCCOMB_X17_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|Equal18~0 ; LCCOMB_X23_Y14_N8 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
; light8080:cpu|T1[6]~3 ; LCCOMB_X13_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|T2[2]~3 ; LCCOMB_X13_Y14_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|addr_low[1]~1 ; LCCOMB_X17_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|flag_reg[6]~12 ; LCCOMB_X21_Y14_N28 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|inta_reg ; LCFF_X14_Y14_N17 ; 41 ; Sync. clear ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~209 ; LCCOMB_X24_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~211 ; LCCOMB_X23_Y13_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~213 ; LCCOMB_X24_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~215 ; LCCOMB_X24_Y11_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~217 ; LCCOMB_X24_Y16_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~219 ; LCCOMB_X24_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~221 ; LCCOMB_X24_Y16_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~223 ; LCCOMB_X24_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~225 ; LCCOMB_X24_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~227 ; LCCOMB_X23_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~229 ; LCCOMB_X24_Y16_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~231 ; LCCOMB_X23_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~233 ; LCCOMB_X24_Y16_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~235 ; LCCOMB_X24_Y16_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~237 ; LCCOMB_X24_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~239 ; LCCOMB_X24_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_decode~0 ; LCCOMB_X12_Y14_N20 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_ret_addr[4]~1 ; LCCOMB_X13_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|ucode_field2[7] ; LCFF_X19_Y13_N1 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[0] ; LCFF_X18_Y14_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[0]~0 ; LCCOMB_X18_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[1] ; LCFF_X18_Y16_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[2] ; LCFF_X18_Y14_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[3] ; LCFF_X18_Y14_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[4] ; LCFF_X18_Y14_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[5] ; LCFF_X18_Y14_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[6] ; LCFF_X18_Y16_N17 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[7] ; LCFF_X18_Y14_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1reg[0]~0 ; LCCOMB_X18_Y16_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[0] ; LCFF_X19_Y16_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[0]~0 ; LCCOMB_X19_Y16_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[1] ; LCFF_X19_Y16_N9 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[2] ; LCFF_X19_Y16_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[3] ; LCFF_X19_Y16_N17 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[4] ; LCFF_X19_Y16_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[5] ; LCFF_X19_Y16_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[6] ; LCFF_X19_Y16_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[7] ; LCFF_X19_Y16_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2reg[0]~0 ; LCCOMB_X18_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 55 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 138 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
; uart:uart|Equal5~10 ; LCCOMB_X17_Y15_N10 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxBaudCnt[1]~1 ; LCCOMB_X17_Y13_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBitCnt[1]~12 ; LCCOMB_X16_Y13_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBusy ; LCFF_X17_Y13_N11 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxData[0]~0 ; LCCOMB_X16_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X16_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBitCnt[3]~6 ; LCCOMB_X15_Y15_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBusy ; LCFF_X17_Y15_N27 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg[5]~4 ; LCCOMB_X17_Y15_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg~2 ; LCCOMB_X17_Y15_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[15]~3 ; LCCOMB_X18_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[7]~2 ; LCCOMB_X21_Y15_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
 
 
710,8 → 731,8
+-------+----------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; clock ; PIN_23 ; 351 ; Global Clock ; GCLK2 ; -- ;
; reset ; PIN_24 ; 120 ; Global Clock ; GCLK1 ; -- ;
; clock ; PIN_23 ; 373 ; Global Clock ; GCLK2 ; -- ;
; reset ; PIN_24 ; 138 ; Global Clock ; GCLK1 ; -- ;
+-------+----------+---------+----------------------+------------------+---------------------------+
 
 
720,24 → 741,24
+------------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+------------------------------------------------------------------------------------------------+---------+
; reset ; 50 ;
; reset ; 54 ;
; light8080:cpu|inta_reg ; 41 ;
; light8080:cpu|Mux10~1 ; 31 ;
; light8080:cpu|Mux11~1 ; 31 ;
; light8080:cpu|Mux8~1 ; 31 ;
; light8080:cpu|Mux9~1 ; 31 ;
; light8080:cpu|addr_low[0] ; 26 ;
; light8080:cpu|ucode_field2[4] ; 25 ;
; light8080:cpu|ucode_field2[4] ; 24 ;
; light8080:cpu|addr_low[1] ; 24 ;
; uart:uart|txBusy ; 24 ;
; light8080:cpu|addr_low[1] ; 23 ;
; light8080:cpu|addr_low[3] ; 23 ;
; light8080:cpu|addr_low[2] ; 23 ;
; light8080:cpu|addr_low[0] ; 23 ;
; light8080:cpu|uc_decode~0 ; 22 ;
; light8080:cpu|ucode_field2[0] ; 21 ;
; light8080:cpu|ucode_field2[1] ; 21 ;
; light8080:cpu|uc_decode~0 ; 21 ;
; light8080:cpu|addr_low[2] ; 21 ;
; light8080:cpu|DO[4]~1 ; 21 ;
; light8080:cpu|Mux20~3 ; 20 ;
; light8080:cpu|Mux27~1 ; 20 ;
; light8080:cpu|ucode_field2[2] ; 20 ;
; light8080:cpu|addr_low[3] ; 20 ;
; light8080:cpu|DO[4]~1 ; 20 ;
; light8080:cpu|Mux22~5 ; 19 ;
; light8080:cpu|Mux21~3 ; 19 ;
; light8080:cpu|rbank~207 ; 19 ;
747,40 → 768,40
; light8080:cpu|DO[2]~0 ; 19 ;
; light8080:cpu|Mux24~7 ; 18 ;
; light8080:cpu|Mux26~8 ; 18 ;
; light8080:cpu|ucode_field2[18] ; 17 ;
; light8080:cpu|ucode_field2[17] ; 17 ;
; light8080:cpu|ucode_field2[16] ; 17 ;
; light8080:cpu|ucode_field2[18] ; 18 ;
; light8080:cpu|ucode_field2[17] ; 18 ;
; light8080:cpu|ucode_field2[16] ; 18 ;
; light8080:cpu|ucode_field2[6] ; 17 ;
; light8080:cpu|ucode_field2[15] ; 17 ;
; light8080:cpu|ucode_field2[6] ; 17 ;
; light8080:cpu|Mux20~3 ; 17 ;
; uart:uart|Equal5~10 ; 17 ;
; light8080:cpu|addr_low[4] ; 17 ;
; light8080:cpu|addr_low[5] ; 17 ;
; light8080:cpu|addr_low[6] ; 17 ;
; light8080:cpu|addr_low[7] ; 17 ;
; light8080:cpu|we_rb~0 ; 16 ;
; uart:uart|rxBusy ; 13 ;
; light8080:cpu|Equal13~0 ; 13 ;
; light8080:cpu|ucode_field2[3] ; 12 ;
; uart:uart|baudCE16 ; 12 ;
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 11 ;
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 12 ;
; intr_ctrl:intrc|intSq[0] ; 11 ;
; intr_ctrl:intrc|always0~0 ; 11 ;
; intr_ctrl:intrc|intSq[1] ; 11 ;
; light8080:cpu|T1[2] ; 9 ;
; io_dout[0]~0 ; 9 ;
; light8080:cpu|T1[2] ; 9 ;
; light8080:cpu|Equal19~1 ; 9 ;
; light8080:cpu|ucode_field2[5] ; 9 ;
; light8080:cpu|T1[0] ; 9 ;
; uart:uart|rxShiftReg[0]~0 ; 8 ;
; uart:uart|rxData[0]~0 ; 8 ;
; light8080:cpu|T2[0]~3 ; 8 ;
+------------------------------------------------------------------------------------------------+---------+
 
 
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X11_Y9, M4K_X11_Y5, M4K_X27_Y9, M4K_X27_Y7 ;
; ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X11_Y11, M4K_X11_Y14, M4K_X11_Y13, M4K_X11_Y6, M4K_X11_Y7, M4K_X11_Y12, M4K_X11_Y8, M4K_X11_Y10 ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X11_Y14, M4K_X11_Y15, M4K_X11_Y13, M4K_X11_Y12 ;
; ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X27_Y17, M4K_X27_Y12, M4K_X27_Y13, M4K_X27_Y14, M4K_X27_Y11, M4K_X27_Y16, M4K_X11_Y16, M4K_X27_Y15 ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
 
 
789,14 → 810,14
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------------+
; Block interconnects ; 1,076 / 26,052 ( 4 % ) ;
; C16 interconnects ; 8 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 558 / 17,952 ( 3 % ) ;
; Direct links ; 135 / 26,052 ( < 1 % ) ;
; Block interconnects ; 1,081 / 26,052 ( 4 % ) ;
; C16 interconnects ; 4 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 469 / 17,952 ( 3 % ) ;
; Direct links ; 175 / 26,052 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; Local interconnects ; 275 / 8,256 ( 3 % ) ;
; R24 interconnects ; 12 / 1,020 ( 1 % ) ;
; R4 interconnects ; 533 / 22,440 ( 2 % ) ;
; Local interconnects ; 306 / 8,256 ( 4 % ) ;
; R24 interconnects ; 23 / 1,020 ( 2 % ) ;
; R4 interconnects ; 621 / 22,440 ( 3 % ) ;
+----------------------------+------------------------+
 
 
803,24 → 824,24
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 12.68) ; Number of LABs (Total = 47) ;
; Number of Logic Elements (Average = 12.19) ; Number of LABs (Total = 53) ;
+---------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 1 ; 5 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 3 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 2 ;
; 14 ; 1 ;
; 15 ; 4 ;
; 16 ; 24 ;
; 13 ; 1 ;
; 14 ; 3 ;
; 15 ; 3 ;
; 16 ; 27 ;
+---------------------------------------------+------------------------------+
 
 
827,13 → 848,13
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.98) ; Number of LABs (Total = 47) ;
; LAB-wide Signals (Average = 1.87) ; Number of LABs (Total = 53) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 13 ;
; 1 Clock ; 47 ;
; 1 Clock enable ; 13 ;
; 1 Sync. clear ; 4 ;
; 2 Clock enables ; 16 ;
; 1 Async. clear ; 17 ;
; 1 Clock ; 49 ;
; 1 Clock enable ; 17 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 14 ;
+------------------------------------+------------------------------+
 
 
840,41 → 861,41
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 18.47) ; Number of LABs (Total = 47) ;
; Number of Signals Sourced (Average = 17.79) ; Number of LABs (Total = 53) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 1 ; 3 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 2 ;
; 16 ; 3 ;
; 17 ; 4 ;
; 18 ; 4 ;
; 19 ; 3 ;
; 20 ; 3 ;
; 19 ; 1 ;
; 20 ; 1 ;
; 21 ; 2 ;
; 22 ; 4 ;
; 23 ; 3 ;
; 24 ; 3 ;
; 25 ; 3 ;
; 26 ; 1 ;
; 24 ; 7 ;
; 25 ; 2 ;
; 26 ; 3 ;
; 27 ; 1 ;
; 28 ; 2 ;
; 28 ; 0 ;
; 29 ; 1 ;
; 30 ; 0 ;
; 31 ; 0 ;
; 32 ; 1 ;
; 32 ; 2 ;
+----------------------------------------------+------------------------------+
 
 
881,25 → 902,27
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 9.00) ; Number of LABs (Total = 47) ;
; Number of Signals Sourced Out (Average = 8.58) ; Number of LABs (Total = 53) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 4 ;
; 5 ; 0 ;
; 1 ; 6 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 5 ;
; 8 ; 1 ;
; 9 ; 5 ;
; 10 ; 2 ;
; 11 ; 7 ;
; 12 ; 5 ;
; 13 ; 6 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 3 ;
; 8 ; 6 ;
; 9 ; 4 ;
; 10 ; 4 ;
; 11 ; 3 ;
; 12 ; 3 ;
; 13 ; 2 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 6 ;
; 17 ; 0 ;
; 18 ; 1 ;
+-------------------------------------------------+------------------------------+
 
 
906,15 → 929,15
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 18.77) ; Number of LABs (Total = 47) ;
; Number of Distinct Inputs (Average = 16.68) ; Number of LABs (Total = 53) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 4 ;
; 5 ; 3 ;
; 6 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
923,22 → 946,22
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 4 ;
; 18 ; 2 ;
; 19 ; 0 ;
; 20 ; 1 ;
; 21 ; 2 ;
; 22 ; 1 ;
; 23 ; 3 ;
; 15 ; 4 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 4 ;
; 19 ; 1 ;
; 20 ; 2 ;
; 21 ; 1 ;
; 22 ; 2 ;
; 23 ; 5 ;
; 24 ; 2 ;
; 25 ; 1 ;
; 26 ; 4 ;
; 27 ; 1 ;
; 28 ; 5 ;
; 29 ; 0 ;
; 30 ; 2 ;
; 25 ; 2 ;
; 26 ; 1 ;
; 27 ; 0 ;
; 28 ; 2 ;
; 29 ; 2 ;
; 30 ; 1 ;
; 31 ; 3 ;
+----------------------------------------------+------------------------------+
 
985,7 → 1008,7
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Tue Feb 21 12:01:04 2012
Info: Processing started: Sat Mar 03 19:53:56 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off l80soc -c l80soc
Info: Selected device EP2C8Q208C8 for design "l80soc"
Info: Low junction temperature is 0 degrees C
1001,7 → 1024,7
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning: No exact pin location assignment(s) for 20 pins of 20 total pins
Critical Warning: No exact pin location assignment(s) for 24 pins of 24 total pins
Info: Pin p1dio[0] not assigned to an exact location on the device
Info: Pin p1dio[1] not assigned to an exact location on the device
Info: Pin p1dio[2] not assigned to an exact location on the device
1021,6 → 1044,10
Info: Pin txd not assigned to an exact location on the device
Info: Pin clock not assigned to an exact location on the device
Info: Pin reset not assigned to an exact location on the device
Info: Pin extint[1] not assigned to an exact location on the device
Info: Pin extint[3] not assigned to an exact location on the device
Info: Pin extint[2] not assigned to an exact location on the device
Info: Pin extint[0] not assigned to an exact location on the device
Info: Pin rxd not assigned to an exact location on the device
Info: Timing-driven compilation is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
1029,16 → 1056,16
Info: Automatically promoted node reset (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node light8080:cpu|inte_reg
Info: Destination node light8080:cpu|condition_reg
Info: Destination node light8080:cpu|inta_reg
Info: Destination node light8080:cpu|delayed_ei
Info: Destination node light8080:cpu|flag_reg[0]
Info: Destination node light8080:cpu|flag_reg[6]
Info: Destination node light8080:cpu|flag_reg[2]
Info: Destination node light8080:cpu|int_pending
Info: Destination node light8080:cpu|daa_res9[1]
Info: Destination node light8080:cpu|daa_res9[2]
Info: Destination node light8080:cpu|daa_res9[3]
Info: Destination node light8080:cpu|daa_res9[4]
Info: Destination node light8080:cpu|flag_reg[4]
Info: Destination node light8080:cpu|daa_res9[5]
Info: Non-global destination nodes limited to 10 nodes
Info: Starting register packing
Extra Info: Performing register packing on registers with non-logic cell location assignments
1050,7 → 1077,7
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 18 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 16 bidirectional)
Info: Number of I/O pins in group: 22 (unused VREF, 3.3V VCCIO, 5 input, 1 output, 16 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
1064,22 → 1091,21
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is memory to register delay of 13.149 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16~porta_address_reg8'
Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16'
Info: 3: + IC(0.892 ns) + CELL(0.624 ns) = 5.277 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'light8080:cpu|Mux10~0'
Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 6.088 ns; Loc. = LAB_X12_Y9; Fanout = 31; COMB Node = 'light8080:cpu|Mux10~1'
Info: 5: + IC(1.157 ns) + CELL(0.370 ns) = 7.615 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~172'
Info: 6: + IC(1.173 ns) + CELL(0.366 ns) = 9.154 ns; Loc. = LAB_X13_Y13; Fanout = 1; COMB Node = 'light8080:cpu|rbank~173'
Info: 7: + IC(1.337 ns) + CELL(0.206 ns) = 10.697 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~174'
Info: 8: + IC(0.441 ns) + CELL(0.366 ns) = 11.504 ns; Loc. = LAB_X12_Y10; Fanout = 19; COMB Node = 'light8080:cpu|rbank~177'
Info: 9: + IC(0.887 ns) + CELL(0.650 ns) = 13.041 ns; Loc. = LAB_X13_Y12; Fanout = 1; COMB Node = 'light8080:cpu|T2~9'
Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 13.149 ns; Loc. = LAB_X13_Y12; Fanout = 3; REG Node = 'light8080:cpu|T2[2]'
Info: Total cell delay = 7.102 ns ( 54.01 % )
Info: Total interconnect delay = 6.047 ns ( 45.99 % )
Info: Estimated most critical path is memory to memory delay of 14.801 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y13; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16~porta_address_reg8'
Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y13; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16'
Info: 3: + IC(2.001 ns) + CELL(0.624 ns) = 6.386 ns; Loc. = LAB_X24_Y15; Fanout = 1; COMB Node = 'light8080:cpu|Mux10~0'
Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 7.197 ns; Loc. = LAB_X24_Y15; Fanout = 31; COMB Node = 'light8080:cpu|Mux10~1'
Info: 5: + IC(1.158 ns) + CELL(0.370 ns) = 8.725 ns; Loc. = LAB_X24_Y14; Fanout = 1; COMB Node = 'light8080:cpu|rbank~182'
Info: 6: + IC(0.441 ns) + CELL(0.366 ns) = 9.532 ns; Loc. = LAB_X24_Y14; Fanout = 1; COMB Node = 'light8080:cpu|rbank~183'
Info: 7: + IC(1.697 ns) + CELL(0.206 ns) = 11.435 ns; Loc. = LAB_X26_Y15; Fanout = 1; COMB Node = 'light8080:cpu|rbank~184'
Info: 8: + IC(0.441 ns) + CELL(0.366 ns) = 12.242 ns; Loc. = LAB_X26_Y15; Fanout = 19; COMB Node = 'light8080:cpu|rbank~187'
Info: 9: + IC(2.383 ns) + CELL(0.176 ns) = 14.801 ns; Loc. = M4K_X11_Y16; Fanout = 0; MEM Node = 'ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ram_block1a6~porta_address_reg10'
Info: Total cell delay = 6.520 ns ( 44.05 % )
Info: Total interconnect delay = 8.281 ns ( 55.95 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources
Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9
Info: Peak interconnect usage is 7% of the available device resources in the region that extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
1107,8 → 1133,8
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 208 megabytes
Info: Processing ended: Tue Feb 21 12:01:11 2012
Info: Peak virtual memory: 207 megabytes
Info: Processing ended: Sat Mar 03 19:54:03 2012
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:06
 

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