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URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

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    /light8080
    from Rev 81 to Rev 82
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Rev 81 → Rev 82

/trunk/vhdl/demos/4kbasic/rs232_rx.vhdl
0,0 → 1,224
--##############################################################################
-- RS-232 receiver, parametrizable bit rate through generics.
-- Bit rate defaults to 19200 bps @50MHz.
-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing!
-- I don't advise using this in for any general purpose.
--##############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity rs232_rx is
generic (
BAUD_RATE : integer := 19200;
CLOCK_FREQ : integer := 50000000);
port (
rxd : in std_logic;
data_rx : out std_logic_vector(7 downto 0);
rx_rdy : out std_logic;
read_rx : in std_logic;
clk : in std_logic;
reset : in std_logic);
end rs232_rx;
 
architecture hardwired of rs232_rx is
 
-- Bit sampling period is 1/16 of the baud rate
constant SAMPLING_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE) / 16;
 
 
--##############################################################################
 
-- Serial port signals
signal rxd_q : std_logic;
signal tick_ctr : std_logic_vector(3 downto 0);
signal state : std_logic_vector(3 downto 0);
signal next_state : std_logic_vector(3 downto 0);
signal start_bit_detected : std_logic;
signal reset_tick_ctr : std_logic;
signal stop_bit_sampled : std_logic;
signal load_rx_buffer : std_logic;
signal stop_error : std_logic;
signal samples : std_logic_vector(2 downto 0);
signal sampled_bit : std_logic;
signal do_shift : std_logic;
signal rx_buffer : std_logic_vector(7 downto 0);
signal rx_shift_reg : std_logic_vector(9 downto 0);
signal tick_ctr_enable : std_logic;
signal tick_baud_ctr : std_logic_vector(10 downto 0);
 
signal rx_rdy_flag : std_logic;
signal set_rx_rdy_flag : std_logic;
 
 
begin
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_baud_ctr <= (others => '0');
else
if conv_integer(tick_baud_ctr)=SAMPLING_PERIOD then -- 325 for 9600 bps
tick_baud_ctr <= (others => '0');
else
tick_baud_ctr <= tick_baud_ctr + 1;
end if;
end if;
end if;
end process;
 
tick_ctr_enable<= '1' when conv_integer(tick_baud_ctr)=SAMPLING_PERIOD else '0';
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rxd_q <= '0';
else
if tick_ctr_enable='1' then
rxd_q <= rxd;
end if;
end if;
end if;
end process;
 
 
start_bit_detected <= '1' when state="0000" and rxd_q='1' and rxd='0' else '0';
reset_tick_ctr <= '1' when start_bit_detected='1' else '0';
 
stop_bit_sampled <= '1' when state="1010" and tick_ctr="1011" else '0';
load_rx_buffer <= '1' when stop_bit_sampled='1' and sampled_bit='1' else '0';
stop_error <= '1' when stop_bit_sampled='1' and sampled_bit='0' else '0';
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_ctr <= "0000";
else
if tick_ctr_enable='1' then
if tick_ctr="1111" or reset_tick_ctr='1' then
tick_ctr <= "0000";
else
tick_ctr <= tick_ctr + 1;
end if;
end if;
end if;
end if;
end process;
 
next_state <=
"0001" when state="0000" and start_bit_detected='1' else
"0000" when state="0001" and tick_ctr="1010" and sampled_bit='1' else
"0000" when state="1010" and tick_ctr="1111" else
state + 1 when tick_ctr="1111" and do_shift='1' else
state;
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
state <= "0000";
else
if tick_ctr_enable='1' then
state <= next_state;
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
samples <= "000";
else
if tick_ctr_enable='1' then
if tick_ctr="0111" then
samples(0) <= rxd;
end if;
if tick_ctr="1000" then
samples(1) <= rxd;
end if;
if tick_ctr="1001" then
samples(2) <= rxd;
end if;
end if;
end if;
end if;
end process;
 
with samples select
sampled_bit <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'0' when "100",
'1' when "101",
'1' when "110",
'1' when others;
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_buffer <= "00000000";
set_rx_rdy_flag <= '0';
else
if tick_ctr_enable='1' and load_rx_buffer='1' and rx_rdy_flag='0' then
rx_buffer <= rx_shift_reg(8 downto 1);
set_rx_rdy_flag <= '1';
else
set_rx_rdy_flag <= '0';
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_rdy_flag <= '0';
else
if set_rx_rdy_flag='1' then
rx_rdy_flag <= '1';
else
if read_rx = '1' then
rx_rdy_flag <= '0';
end if;
end if;
end if;
end if;
end process;
 
do_shift <= state(0) or state(1) or state(2) or state(3);
 
-- reception shift register
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_shift_reg <= "1111111111";
else
if tick_ctr_enable='1' then
if tick_ctr="1010" and do_shift='1' then
rx_shift_reg(9) <= sampled_bit;
rx_shift_reg(8 downto 0) <= rx_shift_reg(9 downto 1);
end if;
end if;
end if;
end if;
end process;
 
rx_rdy <= rx_rdy_flag;
 
data_rx <= rx_buffer;
 
end hardwired;
/trunk/vhdl/demos/4kbasic/c2sb_4kbasic_rom.vhdl
0,0 → 1,310
-- This is a block of initialized BRAM that contains the whole 4K Altair basic
-- image upon startup. The program starts at address zero so upon reset the
-- CPU will enter the 4K Basic code exactly as if it had been loaded from
-- external media.
-- If the code in this block ever becomes corrupt, the only way to restore it
-- is reloading the FPGA.
-- This memory block is RAM; actually, it all the RAM the 4K demo needs to run.
-- The ROM identifiers below are a leftover from a previous version.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity c2sb_4kbasic_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(15 downto 0);
we : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end c2sb_4kbasic_rom;
 
architecture internal of c2sb_4kbasic_rom is
 
signal rom_addr : std_logic_vector(11 downto 0);
type t_rom is array(0 to 4095) of std_logic_vector(7 downto 0);
 
signal rom : t_rom := (
 
-- Altair 4K Basic ROM as per file '4kbas32.bin' in the SIMH simulator
 
X"F3", X"C3", X"21", X"0D", X"90", X"04", X"F9", X"07", X"7E", X"E3", X"BE", X"23", X"E3", X"C2", X"D0", X"01",
X"23", X"7E", X"FE", X"3A", X"D0", X"C3", X"5E", X"04", X"F5", X"3A", X"27", X"00", X"C3", X"6E", X"03", X"00",
X"7C", X"92", X"C0", X"7D", X"93", X"C9", X"01", X"00", X"3A", X"72", X"01", X"B7", X"C2", X"DA", X"09", X"C9",
X"E3", X"22", X"3B", X"00", X"E1", X"4E", X"23", X"46", X"23", X"C5", X"C3", X"3A", X"00", X"E4", X"09", X"A2",
X"0A", X"F8", X"09", X"98", X"04", X"21", X"0C", X"5F", X"0C", X"95", X"0C", X"79", X"10", X"08", X"79", X"0A",
X"08", X"7C", X"E3", X"08", X"7C", X"2F", X"09", X"45", X"4E", X"C4", X"46", X"4F", X"D2", X"4E", X"45", X"58",
X"D4", X"44", X"41", X"54", X"C1", X"49", X"4E", X"50", X"55", X"D4", X"44", X"49", X"CD", X"52", X"45", X"41",
X"C4", X"4C", X"45", X"D4", X"47", X"4F", X"54", X"CF", X"52", X"55", X"CE", X"49", X"C6", X"52", X"45", X"53",
X"54", X"4F", X"52", X"C5", X"47", X"4F", X"53", X"55", X"C2", X"52", X"45", X"54", X"55", X"52", X"CE", X"52",
X"45", X"CD", X"53", X"54", X"4F", X"D0", X"50", X"52", X"49", X"4E", X"D4", X"4C", X"49", X"53", X"D4", X"43",
X"4C", X"45", X"41", X"D2", X"4E", X"45", X"D7", X"54", X"41", X"42", X"A8", X"54", X"CF", X"54", X"48", X"45",
X"CE", X"53", X"54", X"45", X"D0", X"AB", X"AD", X"AA", X"AF", X"BE", X"BD", X"BC", X"53", X"47", X"CE", X"49",
X"4E", X"D4", X"41", X"42", X"D3", X"55", X"53", X"D2", X"53", X"51", X"D2", X"52", X"4E", X"C4", X"53", X"49",
X"CE", X"00", X"F7", X"01", X"D5", X"03", X"49", X"06", X"F5", X"04", X"E4", X"05", X"16", X"07", X"F6", X"05",
X"02", X"05", X"CF", X"04", X"A1", X"02", X"16", X"05", X"69", X"04", X"BE", X"04", X"DF", X"04", X"F7", X"04",
X"F7", X"01", X"57", X"05", X"8E", X"03", X"A6", X"02", X"95", X"02", X"4E", X"C6", X"53", X"CE", X"52", X"C7",
X"4F", X"C4", X"46", X"C3", X"4F", X"D6", X"4F", X"CD", X"55", X"D3", X"42", X"D3", X"44", X"C4", X"2F", X"B0",
X"49", X"C4", X"2C", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"1A", X"0F", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"20", X"45", X"52", X"52", X"4F", X"D2", X"00", X"20", X"49", X"4E", X"A0", X"00", X"0D", X"4F", X"CB",
X"0D", X"00", X"21", X"04", X"00", X"39", X"7E", X"23", X"FE", X"81", X"C0", X"F7", X"E3", X"E7", X"01", X"0D",
X"00", X"E1", X"C8", X"09", X"C3", X"96", X"01", X"CD", X"C3", X"01", X"C5", X"E3", X"C1", X"E7", X"7E", X"02",
X"C8", X"0B", X"2B", X"C3", X"AD", X"01", X"E5", X"2A", X"6B", X"01", X"06", X"00", X"09", X"09", X"CD", X"C3",
X"01", X"E1", X"C9", X"D5", X"EB", X"21", X"DE", X"FF", X"39", X"E7", X"EB", X"D1", X"D0", X"1E", X"0C", X"01",
X"1E", X"02", X"01", X"1E", X"14", X"CD", X"B5", X"02", X"CD", X"8A", X"05", X"21", X"FA", X"00", X"57", X"3E",
X"3F", X"DF", X"19", X"7E", X"DF", X"D7", X"DF", X"21", X"81", X"01", X"CD", X"A3", X"05", X"2A", X"61", X"01",
X"7C", X"A5", X"3C", X"C4", X"2F", X"0B", X"01", X"C0", X"C1", X"21", X"8D", X"01", X"CD", X"21", X"0D", X"21",
X"FF", X"FF", X"22", X"61", X"01", X"CD", X"3C", X"03", X"D7", X"3C", X"3D", X"CA", X"FF", X"01", X"F5", X"CD",
X"9D", X"04", X"D5", X"CD", X"CC", X"02", X"47", X"D1", X"F1", X"D2", X"3E", X"04", X"D5", X"C5", X"D7", X"B7",
X"F5", X"CD", X"7D", X"02", X"C5", X"D2", X"39", X"02", X"EB", X"2A", X"67", X"01", X"1A", X"02", X"03", X"13",
X"E7", X"C2", X"2C", X"02", X"60", X"69", X"22", X"67", X"01", X"D1", X"F1", X"CA", X"60", X"02", X"2A", X"67",
X"01", X"E3", X"C1", X"09", X"E5", X"CD", X"A7", X"01", X"E1", X"22", X"67", X"01", X"EB", X"74", X"23", X"23",
X"D1", X"73", X"23", X"72", X"23", X"11", X"13", X"01", X"1A", X"77", X"23", X"13", X"B7", X"C2", X"58", X"02",
X"CD", X"A2", X"02", X"23", X"EB", X"62", X"6B", X"7E", X"23", X"B6", X"CA", X"FF", X"01", X"23", X"23", X"23",
X"AF", X"BE", X"23", X"C2", X"71", X"02", X"EB", X"73", X"23", X"72", X"C3", X"65", X"02", X"2A", X"65", X"01",
X"44", X"4D", X"7E", X"23", X"B6", X"2B", X"C8", X"C5", X"F7", X"F7", X"E1", X"E7", X"E1", X"C1", X"3F", X"C8",
X"3F", X"D0", X"C3", X"80", X"02", X"C0", X"2A", X"65", X"01", X"AF", X"77", X"23", X"77", X"23", X"22", X"67",
X"01", X"C0", X"2A", X"65", X"01", X"2B", X"22", X"5D", X"01", X"CD", X"69", X"04", X"2A", X"67", X"01", X"22",
X"69", X"01", X"22", X"6B", X"01", X"C1", X"2A", X"63", X"01", X"F9", X"AF", X"6F", X"E5", X"C5", X"2A", X"5D",
X"01", X"C9", X"3E", X"3F", X"DF", X"3E", X"20", X"DF", X"CD", X"3C", X"03", X"23", X"0E", X"05", X"11", X"13",
X"01", X"7E", X"FE", X"20", X"CA", X"02", X"03", X"47", X"FE", X"22", X"CA", X"15", X"03", X"B7", X"CA", X"29",
X"03", X"D5", X"06", X"00", X"11", X"56", X"00", X"E5", X"3E", X"D7", X"13", X"1A", X"E6", X"7F", X"CA", X"FF",
X"02", X"BE", X"C2", X"1C", X"03", X"1A", X"B7", X"F2", X"E9", X"02", X"F1", X"78", X"F6", X"80", X"F2", X"E1",
X"7E", X"D1", X"23", X"12", X"13", X"0C", X"D6", X"8E", X"C2", X"D1", X"02", X"47", X"7E", X"B7", X"CA", X"29",
X"03", X"B8", X"CA", X"02", X"03", X"23", X"12", X"0C", X"13", X"C3", X"0C", X"03", X"E1", X"E5", X"04", X"EB",
X"B6", X"23", X"F2", X"20", X"03", X"EB", X"C3", X"EB", X"02", X"21", X"12", X"01", X"12", X"13", X"12", X"13",
X"12", X"C9", X"05", X"2B", X"DF", X"C2", X"41", X"03", X"DF", X"CD", X"8A", X"05", X"21", X"13", X"01", X"06",
X"01", X"CD", X"82", X"03", X"FE", X"0D", X"CA", X"85", X"05", X"FE", X"20", X"DA", X"41", X"03", X"FE", X"7D",
X"D2", X"41", X"03", X"FE", X"40", X"CA", X"38", X"03", X"FE", X"5F", X"CA", X"32", X"03", X"4F", X"78", X"FE",
X"48", X"3E", X"07", X"D2", X"6A", X"03", X"79", X"71", X"23", X"04", X"DF", X"C3", X"41", X"03", X"FE", X"48",
X"CC", X"8A", X"05", X"3C", X"32", X"27", X"00", X"DB", X"00", X"E6", X"80", X"C2", X"77", X"03", X"F1", X"D3",
X"01", X"C9", X"DB", X"00", X"E6", X"01", X"C2", X"82", X"03", X"DB", X"01", X"E6", X"7F", X"C9", X"CD", X"9D",
X"04", X"C0", X"C1", X"CD", X"7D", X"02", X"C5", X"E1", X"F7", X"C1", X"78", X"B1", X"CA", X"F9", X"01", X"CD",
X"73", X"04", X"C5", X"CD", X"8A", X"05", X"F7", X"E3", X"CD", X"37", X"0B", X"3E", X"20", X"E1", X"DF", X"7E",
X"B7", X"23", X"CA", X"97", X"03", X"F2", X"AE", X"03", X"D6", X"7F", X"4F", X"E5", X"11", X"57", X"00", X"D5",
X"1A", X"13", X"B7", X"F2", X"C0", X"03", X"0D", X"E1", X"C2", X"BF", X"03", X"7E", X"B7", X"FA", X"AD", X"03",
X"DF", X"23", X"C3", X"CB", X"03", X"CD", X"02", X"05", X"E3", X"CD", X"92", X"01", X"D1", X"C2", X"E2", X"03",
X"09", X"F9", X"EB", X"0E", X"08", X"CD", X"B6", X"01", X"E5", X"CD", X"F5", X"04", X"E3", X"E5", X"2A", X"61",
X"01", X"E3", X"CF", X"95", X"CD", X"8A", X"06", X"E5", X"CD", X"1D", X"0A", X"E1", X"C5", X"D5", X"01", X"00",
X"81", X"51", X"5A", X"7E", X"FE", X"97", X"3E", X"01", X"C2", X"14", X"04", X"CD", X"8B", X"06", X"E5", X"CD",
X"1D", X"0A", X"EF", X"E1", X"C5", X"D5", X"F5", X"33", X"E5", X"2A", X"5D", X"01", X"E3", X"06", X"81", X"C5",
X"33", X"CD", X"73", X"04", X"7E", X"FE", X"3A", X"CA", X"3E", X"04", X"B7", X"C2", X"D0", X"01", X"23", X"7E",
X"23", X"B6", X"23", X"CA", X"F9", X"01", X"5E", X"23", X"56", X"EB", X"22", X"61", X"01", X"EB", X"D7", X"11",
X"21", X"04", X"D5", X"C8", X"D6", X"80", X"DA", X"02", X"05", X"FE", X"14", X"D2", X"D0", X"01", X"07", X"4F",
X"06", X"00", X"EB", X"21", X"D2", X"00", X"09", X"4E", X"23", X"46", X"C5", X"EB", X"D7", X"C9", X"FE", X"20",
X"CA", X"10", X"00", X"FE", X"30", X"3F", X"3C", X"3D", X"C9", X"EB", X"2A", X"65", X"01", X"2B", X"22", X"6D",
X"01", X"EB", X"C9", X"DB", X"00", X"E6", X"01", X"C0", X"CD", X"82", X"03", X"FE", X"03", X"C3", X"F7", X"01",
X"7E", X"FE", X"41", X"D8", X"FE", X"5B", X"3F", X"C9", X"D7", X"CD", X"8A", X"06", X"EF", X"FA", X"98", X"04",
X"3A", X"72", X"01", X"FE", X"90", X"DA", X"77", X"0A", X"1E", X"08", X"C3", X"D5", X"01", X"2B", X"11", X"00",
X"00", X"D7", X"D0", X"E5", X"F5", X"21", X"98", X"19", X"E7", X"DA", X"D0", X"01", X"62", X"6B", X"19", X"29",
X"19", X"29", X"F1", X"D6", X"30", X"5F", X"16", X"00", X"19", X"EB", X"E1", X"C3", X"A1", X"04", X"0E", X"03",
X"CD", X"B6", X"01", X"C1", X"E5", X"E5", X"2A", X"61", X"01", X"E3", X"16", X"8C", X"D5", X"33", X"C5", X"CD",
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X"0A", X"CD", X"12", X"0A", X"01", X"06", X"02", X"F1", X"81", X"FA", X"95", X"0B", X"FE", X"07", X"D2", X"95",
X"0B", X"3C", X"47", X"3E", X"01", X"3D", X"E1", X"F5", X"11", X"0F", X"0C", X"05", X"36", X"2E", X"CC", X"27",
X"0A", X"C5", X"E5", X"D5", X"CD", X"1D", X"0A", X"E1", X"06", X"2F", X"04", X"7B", X"96", X"5F", X"23", X"7A",
X"9E", X"57", X"23", X"79", X"9E", X"4F", X"2B", X"2B", X"D2", X"AA", X"0B", X"CD", X"A9", X"08", X"23", X"CD",
X"12", X"0A", X"EB", X"E1", X"70", X"23", X"C1", X"0D", X"C2", X"9B", X"0B", X"05", X"CA", X"DB", X"0B", X"2B",
X"7E", X"FE", X"30", X"CA", X"CF", X"0B", X"FE", X"2E", X"C4", X"27", X"0A", X"F1", X"CA", X"FA", X"0B", X"36",
X"45", X"23", X"36", X"2B", X"F2", X"EB", X"0B", X"36", X"2D", X"2F", X"3C", X"06", X"2F", X"04", X"D6", X"0A",
X"D2", X"ED", X"0B", X"C6", X"3A", X"23", X"70", X"23", X"77", X"23", X"71", X"E1", X"C9", X"01", X"74", X"94",
X"11", X"F7", X"23", X"CD", X"4C", X"0A", X"E1", X"E2", X"71", X"0B", X"E9", X"00", X"00", X"00", X"80", X"A0",
X"86", X"01", X"10", X"27", X"00", X"E8", X"03", X"00", X"64", X"00", X"00", X"0A", X"00", X"00", X"01", X"00",
X"00", X"EF", X"FA", X"98", X"04", X"C8", X"21", X"72", X"01", X"7E", X"1F", X"F5", X"E5", X"3E", X"40", X"17",
X"77", X"21", X"74", X"01", X"CD", X"29", X"0A", X"3E", X"04", X"F5", X"CD", X"02", X"0A", X"21", X"74", X"01",
X"CD", X"20", X"0A", X"CD", X"31", X"09", X"C1", X"D1", X"CD", X"12", X"08", X"01", X"00", X"80", X"51", X"59",
X"CD", X"E5", X"08", X"F1", X"3D", X"C2", X"39", X"0C", X"E1", X"F1", X"C6", X"C0", X"86", X"77", X"C9", X"EF",
X"FA", X"7C", X"0C", X"21", X"91", X"0C", X"CD", X"0F", X"0A", X"C8", X"01", X"35", X"98", X"11", X"7A", X"44",
X"CD", X"E5", X"08", X"01", X"28", X"68", X"11", X"46", X"B1", X"CD", X"12", X"08", X"CD", X"1D", X"0A", X"7B",
X"59", X"4F", X"36", X"80", X"2B", X"46", X"36", X"80", X"CD", X"5E", X"08", X"21", X"91", X"0C", X"C3", X"29",
X"0A", X"52", X"C7", X"4F", X"80", X"CD", X"02", X"0A", X"01", X"49", X"83", X"11", X"DB", X"0F", X"CD", X"12",
X"0A", X"C1", X"D1", X"CD", X"31", X"09", X"CD", X"02", X"0A", X"CD", X"A2", X"0A", X"C1", X"D1", X"CD", X"0C",
X"08", X"01", X"00", X"7F", X"51", X"59", X"CD", X"0C", X"08", X"EF", X"37", X"F2", X"C3", X"0C", X"CD", X"01",
X"08", X"EF", X"B7", X"F5", X"F4", X"FA", X"09", X"01", X"00", X"7F", X"51", X"59", X"CD", X"12", X"08", X"F1",
X"D4", X"FA", X"09", X"CD", X"02", X"0A", X"CD", X"1D", X"0A", X"CD", X"E5", X"08", X"CD", X"02", X"0A", X"21",
X"03", X"0D", X"CD", X"0F", X"0A", X"C1", X"D1", X"3E", X"04", X"F5", X"D5", X"C5", X"E5", X"CD", X"E5", X"08",
X"E1", X"CD", X"20", X"0A", X"E5", X"CD", X"12", X"08", X"E1", X"C1", X"D1", X"F1", X"3D", X"C2", X"E9", X"0C",
X"C3", X"E3", X"08", X"BA", X"D7", X"1E", X"86", X"64", X"26", X"99", X"87", X"58", X"34", X"23", X"87", X"E0",
X"5D", X"A5", X"86", X"DA", X"0F", X"49", X"83", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"21", X"1A", X"0F", X"F9", X"22", X"63", X"01", X"DB", X"01", X"0E", X"FF", X"11", X"8E", X"0D", X"D5",
X"3A", X"FF", X"0F", X"47", X"DB", X"FF", X"1F", X"DA", X"41", X"0D", X"E6", X"0C", X"CA", X"42", X"0D", X"06",
X"10", X"78", X"32", X"8C", X"0D", X"DB", X"FF", X"17", X"17", X"06", X"20", X"11", X"02", X"CA", X"D8", X"17",
X"43", X"1D", X"D8", X"17", X"DA", X"6F", X"0D", X"43", X"11", X"80", X"C2", X"17", X"D0", X"17", X"3E", X"03",
X"CD", X"8B", X"0D", X"3D", X"8F", X"87", X"87", X"3C", X"CD", X"8B", X"0D", X"37", X"C3", X"4B", X"0D", X"AF",
X"CD", X"8B", X"0D", X"CD", X"87", X"0D", X"CD", X"87", X"0D", X"4B", X"2F", X"CD", X"87", X"0D", X"3E", X"04",
X"35", X"CD", X"8B", X"0D", X"35", X"35", X"35", X"21", X"8C", X"0D", X"34", X"D3", X"10", X"C9", X"62", X"68",
X"22", X"85", X"03", X"7C", X"E6", X"C8", X"67", X"22", X"76", X"04", X"EB", X"22", X"7A", X"03", X"3A", X"8C",
X"0D", X"32", X"83", X"03", X"32", X"74", X"04", X"3C", X"32", X"8A", X"03", X"81", X"32", X"78", X"03", X"3C",
X"32", X"80", X"03", X"21", X"FF", X"FF", X"22", X"61", X"01", X"CD", X"8A", X"05", X"21", X"F0", X"0E", X"CD",
X"A3", X"05", X"CD", X"C2", X"02", X"D7", X"B7", X"C2", X"DE", X"0D", X"21", X"FC", X"0E", X"23", X"3E", X"37",
X"77", X"BE", X"C2", X"EA", X"0D", X"3D", X"77", X"BE", X"CA", X"CD", X"0D", X"C3", X"EA", X"0D", X"21", X"13",
X"01", X"CD", X"9D", X"04", X"B7", X"C2", X"D0", X"01", X"EB", X"2B", X"2B", X"E5", X"21", X"B4", X"0E", X"CD",
X"A3", X"05", X"CD", X"C2", X"02", X"D7", X"B7", X"CA", X"1B", X"0E", X"21", X"13", X"01", X"CD", X"9D", X"04",
X"7A", X"B7", X"C2", X"EC", X"0D", X"7B", X"FE", X"10", X"DA", X"EC", X"0D", X"32", X"6F", X"03", X"D6", X"0E",
X"D2", X"0E", X"0E", X"C6", X"1C", X"2F", X"3C", X"83", X"32", X"B7", X"05", X"21", X"85", X"0E", X"F7", X"11",
X"99", X"0E", X"E7", X"CA", X"32", X"0E", X"F7", X"E3", X"CD", X"A3", X"05", X"CD", X"C2", X"02", X"D7", X"E1",
X"FE", X"59", X"D1", X"CA", X"47", X"0E", X"FE", X"4E", X"C2", X"1B", X"0E", X"F7", X"E3", X"11", X"98", X"04",
X"73", X"23", X"72", X"E1", X"C3", X"1E", X"0E", X"EB", X"36", X"00", X"23", X"22", X"65", X"01", X"E3", X"11",
X"1A", X"0F", X"E7", X"DA", X"CD", X"01", X"D1", X"F9", X"22", X"63", X"01", X"EB", X"CD", X"C3", X"01", X"7B",
X"95", X"6F", X"7A", X"9C", X"67", X"01", X"F0", X"FF", X"09", X"CD", X"8A", X"05", X"CD", X"37", X"0B", X"21",
X"C3", X"0E", X"CD", X"A3", X"05", X"21", X"A3", X"05", X"22", X"FD", X"01", X"CD", X"96", X"02", X"21", X"F9",
X"01", X"22", X"02", X"00", X"E9", X"17", X"0D", X"99", X"0E", X"49", X"00", X"95", X"0C", X"A2", X"0E", X"47",
X"00", X"5F", X"0C", X"AB", X"0E", X"45", X"00", X"21", X"0C", X"57", X"41", X"4E", X"54", X"20", X"53", X"49",
X"CE", X"00", X"57", X"41", X"4E", X"54", X"20", X"52", X"4E", X"C4", X"00", X"57", X"41", X"4E", X"54", X"20",
X"53", X"51", X"D2", X"00", X"54", X"45", X"52", X"4D", X"49", X"4E", X"41", X"4C", X"20", X"57", X"49", X"44",
X"54", X"C8", X"00", X"20", X"42", X"59", X"54", X"45", X"53", X"20", X"46", X"52", X"45", X"C5", X"0D", X"0D",
X"42", X"41", X"53", X"49", X"43", X"20", X"56", X"45", X"52", X"53", X"49", X"4F", X"4E", X"20", X"33", X"2E",
X"B2", X"0D", X"5B", X"34", X"4B", X"20", X"56", X"45", X"52", X"53", X"49", X"4F", X"4E", X"DD", X"0D", X"00",
X"4D", X"45", X"4D", X"4F", X"52", X"59", X"20", X"53", X"49", X"5A", X"C5", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
 
);
 
 
begin
 
 
rom_addr <= addr(11 downto 0);
process(clk)
begin
if (clk'event and clk='1') then
if we='1' then
rom(conv_integer(rom_addr)) <= data_in;
end if;
data_out <= rom(conv_integer(rom_addr));
end if;
end process;
 
end internal;
/trunk/vhdl/demos/4kbasic/rs232_tx.vhdl
0,0 → 1,73
--##############################################################################
-- RS-232 transmitter, parametrizable bit rate through generics.
-- Bit rate defaults to 19200 bps @50MHz.
-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing!
-- I don't advise using this in for any general purpose.
--##############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity rs232_tx is
generic (
BAUD_RATE : integer := 19200;
CLOCK_FREQ : integer := 50000000);
port (
clk : in std_logic;
reset : in std_logic;
rdy : out std_logic;
load : in std_logic;
data_i : in std_logic_vector(7 downto 0);
txd : out std_logic);
end rs232_tx;
 
architecture hardwired of rs232_tx is
 
-- Bit period expressed in master clock cycles
constant BIT_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE);
 
signal counter : std_logic_vector(13 downto 0);
signal data : std_logic_vector(10 downto 0);
signal ctr_bit : std_logic_vector(3 downto 0);
signal tx : std_logic;
 
begin
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
data <= "10111111111";
tx <= '0';
ctr_bit <= "0000";
counter <= (others => '0');
elsif load='1' and tx='0' then
data <= "1"&data_i&"01";
tx <= '1';
else
if tx='1' then
if conv_integer(counter) = BIT_PERIOD then --e.g. 5200 for 9600 bps
counter <= (others => '0');
data(9 downto 0) <= data(10 downto 1);
data(10) <= '1';
if ctr_bit = "1010" then
tx <= '0';
ctr_bit <= "0000";
else
ctr_bit <= ctr_bit + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end if;
end if;
end process;
 
rdy <= not tx;
txd <= data(0);
 
end hardwired;
/trunk/vhdl/demos/4kbasic/c2sb_4kbasic.csv
0,0 → 1,505
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
# Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# File: C:\altera\Kits\CycloneII_Starter_Kit-v1.0.0\proyectos\demo_tutorial\pin_assignment\c2sb_demo.csv
# Generated on: Sun Jul 19 05:05:49 2009
 
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.
 
To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Group,Current Strength,PCB layer
buttons[3],Input,PIN_T21,6,B6_N0,,,buttons[3..0],,
buttons[2],Input,PIN_T22,6,B6_N0,,,buttons[3..0],,
buttons[1],Input,PIN_R21,6,B6_N0,,,buttons[3..0],,
buttons[0],Input,PIN_R22,6,B6_N0,,,buttons[3..0],,
flash_addr[21],Output,PIN_R13,7,B7_N0,,,flash_addr[21..0],,
flash_addr[20],Output,PIN_U13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[19],Output,PIN_V14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[18],Output,PIN_U14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[17],Output,PIN_AA20,7,B7_N0,,,flash_addr[21..0],,
flash_addr[16],Output,PIN_AB12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[15],Output,PIN_AA12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[14],Output,PIN_AB13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[13],Output,PIN_AA13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[12],Output,PIN_AB14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[11],Output,PIN_T12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[10],Output,PIN_R12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[9],Output,PIN_Y13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[8],Output,PIN_R14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[7],Output,PIN_W15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[6],Output,PIN_V15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[5],Output,PIN_U15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[4],Output,PIN_T15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[3],Output,PIN_R15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[2],Output,PIN_Y16,7,B7_N0,,,flash_addr[21..0],,
flash_addr[1],Output,PIN_AA14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[0],Output,PIN_AB20,7,B7_N0,,,flash_addr[21..0],,
flash_data[7],Input,PIN_AA19,7,B7_N0,,,flash_data[7..0],,
flash_data[6],Input,PIN_AB19,7,B7_N0,,,flash_data[7..0],,
flash_data[5],Input,PIN_AA18,7,B7_N0,,,flash_data[7..0],,
flash_data[4],Input,PIN_AB18,7,B7_N0,,,flash_data[7..0],,
flash_data[3],Input,PIN_AA17,7,B7_N1,,,flash_data[7..0],,
flash_data[2],Input,PIN_AB17,7,B7_N1,,,flash_data[7..0],,
flash_data[1],Input,PIN_AA16,7,B7_N1,,,flash_data[7..0],,
flash_data[0],Input,PIN_AB16,7,B7_N1,,,flash_data[7..0],,
flash_oe_n,Output,PIN_AA15,7,B7_N1,,,,,
flash_reset_n,Output,PIN_W14,7,B7_N1,,,,,
flash_we_n,Output,PIN_Y14,7,B7_N0,,,,,
green_leds[7],Output,PIN_Y21,6,B6_N1,,,green_leds[7..0],,
green_leds[6],Output,PIN_Y22,6,B6_N1,,,green_leds[7..0],,
green_leds[5],Output,PIN_W21,6,B6_N1,,,green_leds[7..0],,
green_leds[4],Output,PIN_W22,6,B6_N1,,,green_leds[7..0],,
green_leds[3],Output,PIN_V21,6,B6_N1,,,green_leds[7..0],,
green_leds[2],Output,PIN_V22,6,B6_N1,,,green_leds[7..0],,
green_leds[1],Output,PIN_U21,6,B6_N1,,,green_leds[7..0],,
green_leds[0],Output,PIN_U22,6,B6_N1,,,green_leds[7..0],,
hex0[0],Output,PIN_J2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[1],Output,PIN_J1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[2],Output,PIN_H2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[3],Output,PIN_H1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[4],Output,PIN_F2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[5],Output,PIN_F1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[6],Output,PIN_E2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex1[0],Output,PIN_E1,2,B2_N1,3.3-V LVTTL,,hex1[0..6],,
hex1[1],Output,PIN_H6,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[2],Output,PIN_H5,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[3],Output,PIN_H4,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[4],Output,PIN_G3,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[5],Output,PIN_D2,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[6],Output,PIN_D1,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex2[0],Output,PIN_G5,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[1],Output,PIN_G6,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[2],Output,PIN_C2,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[3],Output,PIN_C1,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[4],Output,PIN_E3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[5],Output,PIN_E4,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[6],Output,PIN_D3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex3[0],Output,PIN_F4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[1],Output,PIN_D5,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[2],Output,PIN_D6,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[3],Output,PIN_J4,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[4],Output,PIN_L8,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[5],Output,PIN_F3,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[6],Output,PIN_D4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
red_leds[9],Output,PIN_R17,6,B6_N1,,,red_leds[9..0],,
red_leds[8],Output,PIN_R18,6,B6_N0,,,red_leds[9..0],,
red_leds[7],Output,PIN_U18,6,B6_N1,,,red_leds[9..0],,
red_leds[6],Output,PIN_Y18,6,B6_N1,,,red_leds[9..0],,
red_leds[5],Output,PIN_V19,6,B6_N1,,,red_leds[9..0],,
red_leds[4],Output,PIN_T18,6,B6_N1,,,red_leds[9..0],,
red_leds[3],Output,PIN_Y19,6,B6_N1,,,red_leds[9..0],,
red_leds[2],Output,PIN_U19,6,B6_N1,,,red_leds[9..0],,
red_leds[1],Output,PIN_R19,6,B6_N0,,,red_leds[9..0],,
red_leds[0],Output,PIN_R20,6,B6_N0,,,red_leds[9..0],,
rxd,Input,PIN_F14,4,B4_N1,,,,,
sd_clk,Output,PIN_V20,6,B6_N1,,,,,
sd_cmd,Output,PIN_Y20,6,B6_N1,,,,,
sd_cs,Output,PIN_U20,6,B6_N1,,,,,
sd_data,Input,PIN_W20,6,B6_N1,,,,,
sram_addr[17],Output,PIN_Y5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[16],Output,PIN_Y6,8,B8_N1,,,sram_addr[17..0],,
sram_addr[15],Output,PIN_T7,8,B8_N1,,,sram_addr[17..0],,
sram_addr[14],Output,PIN_R10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[13],Output,PIN_U10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[12],Output,PIN_Y10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[11],Output,PIN_T11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[10],Output,PIN_R11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[9],Output,PIN_W11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[8],Output,PIN_V11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[7],Output,PIN_AB11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[6],Output,PIN_AA11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[5],Output,PIN_AB10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[4],Output,PIN_AA5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[3],Output,PIN_AB4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[2],Output,PIN_AA4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[1],Output,PIN_AB3,8,B8_N1,,,sram_addr[17..0],,
sram_addr[0],Output,PIN_AA3,8,B8_N1,,,sram_addr[17..0],,
sram_ce_n,Output,PIN_AB5,8,B8_N1,,,,,
sram_data[15],Bidir,PIN_U8,8,B8_N1,,,sram_data[15..0],,
sram_data[14],Bidir,PIN_V8,8,B8_N1,,,sram_data[15..0],,
sram_data[13],Bidir,PIN_W8,8,B8_N1,,,sram_data[15..0],,
sram_data[12],Bidir,PIN_R9,8,B8_N0,,,sram_data[15..0],,
sram_data[11],Bidir,PIN_U9,8,B8_N0,,,sram_data[15..0],,
sram_data[10],Bidir,PIN_V9,8,B8_N1,,,sram_data[15..0],,
sram_data[9],Bidir,PIN_W9,8,B8_N0,,,sram_data[15..0],,
sram_data[8],Bidir,PIN_Y9,8,B8_N0,,,sram_data[15..0],,
sram_data[7],Bidir,PIN_AB9,8,B8_N0,,,sram_data[15..0],,
sram_data[6],Bidir,PIN_AA9,8,B8_N0,,,sram_data[15..0],,
sram_data[5],Bidir,PIN_AB8,8,B8_N0,,,sram_data[15..0],,
sram_data[4],Bidir,PIN_AA8,8,B8_N0,,,sram_data[15..0],,
sram_data[3],Bidir,PIN_AB7,8,B8_N1,,,sram_data[15..0],,
sram_data[2],Bidir,PIN_AA7,8,B8_N1,,,sram_data[15..0],,
sram_data[1],Bidir,PIN_AB6,8,B8_N1,,,sram_data[15..0],,
sram_data[0],Bidir,PIN_AA6,8,B8_N1,,,sram_data[15..0],,
sram_lb_n,Output,PIN_Y7,8,B8_N1,,,,,
sram_oe_n,Output,PIN_T8,8,B8_N1,,,,,
sram_ub_n,Output,PIN_W7,8,B8_N1,,,,,
sram_we_n,Output,PIN_AA10,8,B8_N0,,,,,
switches[9],Input,PIN_L2,2,B2_N1,,,switches[9..0],,
switches[8],Input,PIN_M1,1,B1_N0,,,switches[9..0],,
switches[7],Input,PIN_M2,1,B1_N0,,,switches[9..0],,
switches[6],Input,PIN_U11,8,B8_N0,,,switches[9..0],,
switches[5],Input,PIN_U12,8,B8_N0,,,switches[9..0],,
switches[4],Input,PIN_W12,7,B7_N1,,,switches[9..0],,
switches[3],Input,PIN_V12,7,B7_N1,,,switches[9..0],,
switches[2],Input,PIN_M22,6,B6_N0,,,switches[9..0],,
switches[1],Input,PIN_L21,5,B5_N1,,,switches[9..0],,
switches[0],Input,PIN_L22,5,B5_N1,,,switches[9..0],,
txd,Output,PIN_G12,4,B4_N1,,,,,
clk_50MHz,Unknown,PIN_L1,2,B2_N1,,,,,
,Unknown,PIN_F5,,,,,,,
,Unknown,PIN_E5,,,,,,,
,Unknown,PIN_F6,,,,,,,
,Unknown,PIN_C4,2,B2_N0,,,,,
,Unknown,PIN_C3,2,B2_N0,,,,,
,Unknown,PIN_H3,2,B2_N1,,,,,
,Unknown,PIN_K5,2,B2_N1,,,,,
,Unknown,PIN_K2,2,B2_N1,,,,,
,Unknown,PIN_K6,2,B2_N1,,,,,
,Unknown,PIN_L5,2,B2_N1,,,,,
,Unknown,PIN_L6,2,B2_N1,,,,,
,Unknown,PIN_K4,2,B2_N1,,,,,
,Unknown,PIN_K1,2,B2_N1,,,,,
,Unknown,PIN_L4,2,B2_N1,,,,,
,Unknown,PIN_M5,1,B1_N0,,,,,
,Unknown,PIN_M6,1,B1_N0,,,,,
,Unknown,PIN_N1,1,B1_N0,,,,,
,Unknown,PIN_N2,1,B1_N0,,,,,
,Unknown,PIN_P1,1,B1_N0,,,,,
,Unknown,PIN_P2,1,B1_N0,,,,,
,Unknown,PIN_N6,1,B1_N0,,,,,
,Unknown,PIN_P3,1,B1_N0,,,,,
,Unknown,PIN_N3,1,B1_N0,,,,,
,Unknown,PIN_N4,1,B1_N0,,,,,
,Unknown,PIN_R8,1,B1_N0,,,,,
,Unknown,PIN_R7,1,B1_N0,,,,,
,Unknown,PIN_P5,1,B1_N0,,,,,
,Unknown,PIN_P6,1,B1_N0,,,,,
,Unknown,PIN_R1,1,B1_N0,,,,,
,Unknown,PIN_R2,1,B1_N0,,,,,
,Unknown,PIN_T1,1,B1_N0,,,,,
,Unknown,PIN_T2,1,B1_N0,,,,,
,Unknown,PIN_U1,1,B1_N1,,,,,
,Unknown,PIN_U2,1,B1_N1,,,,,
,Unknown,PIN_R5,1,B1_N1,,,,,
,Unknown,PIN_R6,1,B1_N1,,,,,
,Unknown,PIN_V1,1,B1_N1,,,,,
,Unknown,PIN_V2,1,B1_N1,,,,,
,Unknown,PIN_T5,1,B1_N1,,,,,
,Unknown,PIN_T6,1,B1_N1,,,,,
,Unknown,PIN_T3,1,B1_N1,,,,,
,Unknown,PIN_U3,1,B1_N1,,,,,
,Unknown,PIN_W1,1,B1_N1,,,,,
,Unknown,PIN_W2,1,B1_N1,,,,,
,Unknown,PIN_Y1,1,B1_N1,,,,,
,Unknown,PIN_Y2,1,B1_N1,,,,,
,Unknown,PIN_W3,1,B1_N1,,,,,
,Unknown,PIN_W4,1,B1_N1,,,,,
,Unknown,PIN_Y3,1,B1_N1,,,,,
,Unknown,PIN_Y4,1,B1_N1,,,,,
,Unknown,PIN_W5,1,B1_N1,,,,,
,Unknown,PIN_U4,1,B1_N1,,,,,
,Unknown,PIN_V4,1,B1_N1,,,,,
,Unknown,PIN_U5,,,,,,,
,Unknown,PIN_U6,,,,,,,
,Unknown,PIN_V5,,,,,,,
,Unknown,PIN_U7,,,,,,,
,Unknown,PIN_V7,,,,,,,
,Unknown,PIN_P9,8,B8_N1,,,,,
,Unknown,PIN_P8,,,,,,,
,Unknown,PIN_AB15,7,B7_N1,,,,,
,Unknown,PIN_R16,7,B7_N0,,,,,
,Unknown,PIN_T16,7,B7_N0,,,,,
,Unknown,PIN_Y17,7,B7_N0,,,,,
,Unknown,PIN_W16,7,B7_N0,,,,,
,Unknown,PIN_V16,,,,,,,
,Unknown,PIN_U16,,,,,,,
,Unknown,PIN_V18,,,,,,,
,Unknown,PIN_U17,,,,,,,
,Unknown,PIN_T17,,,,,,,
,Unknown,PIN_P17,6,B6_N0,,,,,
,Unknown,PIN_P18,6,B6_N0,,,,,
,Unknown,PIN_P15,6,B6_N0,,,,,
,Unknown,PIN_N15,6,B6_N0,,,,,
,Unknown,PIN_N20,6,B6_N0,,,,,
,Unknown,PIN_N18,6,B6_N0,,,,,
,Unknown,PIN_N17,6,B6_N0,,,,,
,Unknown,PIN_M17,6,B6_N0,,,,,
,Unknown,PIN_N21,6,B6_N0,,,,,
,Unknown,PIN_N22,6,B6_N0,,,,,
,Unknown,PIN_M19,6,B6_N0,,,,,
,Unknown,PIN_M18,6,B6_N0,,,,,
,Unknown,PIN_M21,6,B6_N0,,,,,
,Unknown,PIN_L19,5,B5_N1,,,,,
,Unknown,PIN_L18,5,B5_N1,,,,,
,Unknown,PIN_K21,5,B5_N1,,,,,
,Unknown,PIN_K22,5,B5_N1,,,,,
,Unknown,PIN_J21,5,B5_N1,,,,,
,Unknown,PIN_J22,5,B5_N1,,,,,
,Unknown,PIN_J20,5,B5_N1,,,,,
,Unknown,PIN_H19,5,B5_N1,,,,,
,Unknown,PIN_K20,5,B5_N1,,,,,
,Unknown,PIN_J19,5,B5_N1,,,,,
,Unknown,PIN_J18,5,B5_N1,,,,,
,Unknown,PIN_J17,5,B5_N1,,,,,
,Unknown,PIN_H16,5,B5_N1,,,,,
,Unknown,PIN_J15,5,B5_N1,,,,,
,Unknown,PIN_G21,5,B5_N1,,,,,
,Unknown,PIN_G22,5,B5_N1,,,,,
,Unknown,PIN_F21,5,B5_N0,,,,,
,Unknown,PIN_F22,5,B5_N0,,,,,
,Unknown,PIN_H18,5,B5_N0,,,,,
,Unknown,PIN_H17,5,B5_N0,,,,,
,Unknown,PIN_E21,,,,,,,
,Unknown,PIN_E22,5,B5_N0,,,,,
,Unknown,PIN_D21,,,,,,,
,Unknown,PIN_D22,,,,,,,
,Unknown,PIN_G17,5,B5_N0,,,,,
,Unknown,PIN_G18,5,B5_N0,,,,,
,Unknown,PIN_G20,,,,,,,
,Unknown,PIN_E20,5,B5_N0,,,,,
,Unknown,PIN_F20,5,B5_N0,,,,,
,Unknown,PIN_C21,5,B5_N0,,,,,
,Unknown,PIN_C22,,,,,,,
,Unknown,PIN_C19,5,B5_N0,,,,,
,Unknown,PIN_C20,,,,,,,
,Unknown,PIN_D19,,,,,,,
,Unknown,PIN_D20,5,B5_N0,,,,,
,Unknown,PIN_E19,5,B5_N0,,,,,
,Unknown,PIN_E18,,,,,,,
,Unknown,PIN_F18,,,,,,,
,Unknown,PIN_F17,,,,,,,
,Unknown,PIN_E17,,,,,,,
,Unknown,PIN_F16,,,,,,,
,Unknown,PIN_E16,,,,,,,
,Unknown,PIN_C18,4,B4_N0,,,,,
,Unknown,PIN_C17,4,B4_N0,,,,,
,Unknown,PIN_B20,4,B4_N0,,,,,
,Unknown,PIN_A20,4,B4_N0,,,,,
,Unknown,PIN_B19,4,B4_N0,,,,,
,Unknown,PIN_A19,4,B4_N0,,,,,
,Unknown,PIN_B18,4,B4_N0,,,,,
,Unknown,PIN_A18,4,B4_N0,,,,,
,Unknown,PIN_G16,4,B4_N0,,,,,
,Unknown,PIN_H15,4,B4_N0,,,,,
,Unknown,PIN_C16,4,B4_N0,,,,,
,Unknown,PIN_D16,4,B4_N0,,,,,
,Unknown,PIN_E15,4,B4_N0,,,,,
,Unknown,PIN_H14,4,B4_N0,,,,,
,Unknown,PIN_J14,4,B4_N0,,,,,
,Unknown,PIN_D15,4,B4_N0,,,,,
,Unknown,PIN_C14,4,B4_N0,,,,,
,Unknown,PIN_G15,4,B4_N0,,,,,
,Unknown,PIN_F15,4,B4_N0,,,,,
,Unknown,PIN_H13,4,B4_N1,,,,,
,Unknown,PIN_B17,4,B4_N1,,,,,
,Unknown,PIN_A17,4,B4_N1,,,,,
,Unknown,PIN_E14,4,B4_N1,,,,,
,Unknown,PIN_D14,4,B4_N1,,,,,
,Unknown,PIN_F13,4,B4_N1,,,,,
,Unknown,PIN_B16,4,B4_N1,,,,,
,Unknown,PIN_A16,4,B4_N1,,,,,
,Unknown,PIN_B15,,,,,,,
,Unknown,PIN_A15,4,B4_N1,,,,,
,Unknown,PIN_H12,4,B4_N1,,,,,
,Unknown,PIN_C13,4,B4_N1,,,,,
,Unknown,PIN_F12,,,,,,,
,Unknown,PIN_B14,4,B4_N1,,,,,
,Unknown,PIN_A14,4,B4_N1,,,,,
,Unknown,PIN_B13,4,B4_N1,,,,,
,Unknown,PIN_A13,4,B4_N1,,,,,
,Unknown,PIN_B12,4,B4_N1,,,,,
,Unknown,PIN_A12,,,,,,,
,Unknown,PIN_D12,3,B3_N0,,,,,
,Unknown,PIN_E12,3,B3_N0,,,,,
,Unknown,PIN_B11,3,B3_N0,,,,,
,Unknown,PIN_A11,,,,,,,
,Unknown,PIN_E11,3,B3_N0,,,,,
,Unknown,PIN_D11,3,B3_N0,,,,,
,Unknown,PIN_H11,,,,,,,
,Unknown,PIN_G11,3,B3_N0,,,,,
,Unknown,PIN_B10,3,B3_N0,,,,,
,Unknown,PIN_A10,3,B3_N0,,,,,
,Unknown,PIN_F11,,,,,,,
,Unknown,PIN_F10,3,B3_N0,,,,,
,Unknown,PIN_C10,,,,,,,
,Unknown,PIN_B9,3,B3_N0,,,,,
,Unknown,PIN_A9,3,B3_N0,,,,,
,Unknown,PIN_H10,,,,,,,
,Unknown,PIN_H9,,,,,,,
,Unknown,PIN_E9,3,B3_N0,,,,,
,Unknown,PIN_D9,3,B3_N0,,,,,
,Unknown,PIN_B8,3,B3_N0,,,,,
,Unknown,PIN_A8,,,,,,,
,Unknown,PIN_B7,3,B3_N1,,,,,
,Unknown,PIN_A7,3,B3_N1,,,,,
,Unknown,PIN_F9,3,B3_N1,,,,,
,Unknown,PIN_E8,3,B3_N1,,,,,
,Unknown,PIN_D8,3,B3_N1,,,,,
,Unknown,PIN_C9,,,,,,,
,Unknown,PIN_D7,3,B3_N1,,,,,
,Unknown,PIN_F8,3,B3_N1,,,,,
,Unknown,PIN_G8,3,B3_N1,,,,,
,Unknown,PIN_H8,3,B3_N1,,,,,
,Unknown,PIN_C7,3,B3_N1,,,,,
,Unknown,PIN_E7,3,B3_N1,,,,,
,Unknown,PIN_G7,3,B3_N1,,,,,
,Unknown,PIN_H7,3,B3_N1,,,,,
,Unknown,PIN_B6,3,B3_N1,,,,,
,Unknown,PIN_A6,3,B3_N1,,,,,
,Unknown,PIN_B5,3,B3_N1,,,,,
,Unknown,PIN_A5,3,B3_N1,,,,,
,Unknown,PIN_B4,3,B3_N1,,,,,
,Unknown,PIN_A4,3,B3_N1,,,,,
,Unknown,PIN_A3,3,B3_N1,,,,,
,Unknown,PIN_B3,3,B3_N1,,,,,
,Unknown,PIN_F7,,,,,,,
,Unknown,PIN_E6,,,,,,,
,Unknown,PIN_J10,,,,,,,
,Unknown,PIN_J11,,,,,,,
,Unknown,PIN_J12,,,,,,,
,Unknown,PIN_J13,,,,,,,
,Unknown,PIN_K9,,,,,,,
,Unknown,PIN_K14,,,,,,,
,Unknown,PIN_L9,,,,,,,
,Unknown,PIN_L14,,,,,,,
,Unknown,PIN_M9,,,,,,,
,Unknown,PIN_M14,,,,,,,
,Unknown,PIN_N9,,,,,,,
,Unknown,PIN_N14,,,,,,,
,Unknown,PIN_P10,,,,,,,
,Unknown,PIN_P11,,,,,,,
,Unknown,PIN_P12,,,,,,,
,Unknown,PIN_P13,,,,,,,
,Unknown,PIN_B1,2,,,,,,
,Unknown,PIN_J7,2,,,,,,
,Unknown,PIN_L3,2,,,,,,
,Unknown,PIN_AA1,,,,,,,
,Unknown,PIN_M3,1,,,,,,
,Unknown,PIN_P7,1,,,,,,
,Unknown,PIN_T4,1,,,,,,
,Unknown,PIN_AB2,8,,,,,,
,Unknown,PIN_T9,8,,,,,,
,Unknown,PIN_V10,,,,,,,
,Unknown,PIN_W6,8,,,,,,
,Unknown,PIN_Y11,8,,,,,,
,Unknown,PIN_AB21,7,,,,,,
,Unknown,PIN_T14,7,,,,,,
,Unknown,PIN_V13,7,,,,,,
,Unknown,PIN_W17,7,,,,,,
,Unknown,PIN_Y12,7,,,,,,
,Unknown,PIN_AA22,6,,,,,,
,Unknown,PIN_M20,6,,,,,,
,Unknown,PIN_P16,6,,,,,,
,Unknown,PIN_T19,6,,,,,,
,Unknown,PIN_B22,5,,,,,,
,Unknown,PIN_G19,5,,,,,,
,Unknown,PIN_J16,5,,,,,,
,Unknown,PIN_L20,5,,,,,,
,Unknown,PIN_A21,4,,,,,,
,Unknown,PIN_C12,4,,,,,,
,Unknown,PIN_D17,4,,,,,,
,Unknown,PIN_E13,4,,,,,,
,Unknown,PIN_G14,4,,,,,,
,Unknown,PIN_A2,3,,,,,,
,Unknown,PIN_C6,3,,,,,,
,Unknown,PIN_C11,3,,,,,,
,Unknown,PIN_E10,3,,,,,,
,Unknown,PIN_G9,3,,,,,,
,Unknown,PIN_K10,,,,,,,
,Unknown,PIN_K11,,,,,,,
,Unknown,PIN_K12,,,,,,,
,Unknown,PIN_K13,,,,,,,
,Unknown,PIN_L10,,,,,,,
,Unknown,PIN_L11,,,,,,,
,Unknown,PIN_L12,,,,,,,
,Unknown,PIN_L13,,,,,,,
,Unknown,PIN_M10,,,,,,,
,Unknown,PIN_M11,,,,,,,
,Unknown,PIN_M12,,,,,,,
,Unknown,PIN_M13,,,,,,,
,Unknown,PIN_N10,,,,,,,
,Unknown,PIN_N11,,,,,,,
,Unknown,PIN_N12,,,,,,,
,Unknown,PIN_N13,,,,,,,
,Unknown,PIN_A1,,,,,,,
,Unknown,PIN_A22,,,,,,,
,Unknown,PIN_AA2,,,,,,,
,Unknown,PIN_AA21,,,,,,,
,Unknown,PIN_AB1,,,,,,,
,Unknown,PIN_AB22,,,,,,,
,Unknown,PIN_B2,,,,,,,
,Unknown,PIN_B21,,,,,,,
,Unknown,PIN_C5,,,,,,,
,Unknown,PIN_C8,,,,,,,
,Unknown,PIN_C15,,,,,,,
,Unknown,PIN_D10,,,,,,,
,Unknown,PIN_D13,,,,,,,
,Unknown,PIN_D18,,,,,,,
,Unknown,PIN_F19,,,,,,,
,Unknown,PIN_G4,,,,,,,
,Unknown,PIN_G10,,,,,,,
,Unknown,PIN_G13,,,,,,,
,Unknown,PIN_H20,,,,,,,
,Unknown,PIN_K3,,,,,,,
,Unknown,PIN_K7,,,,,,,
,Unknown,PIN_K16,,,,,,,
,Unknown,PIN_K19,,,,,,,
,Unknown,PIN_M4,,,,,,,
,Unknown,PIN_N7,,,,,,,
,Unknown,PIN_N16,,,,,,,
,Unknown,PIN_N19,,,,,,,
,Unknown,PIN_R3,,,,,,,
,Unknown,PIN_T10,,,,,,,
,Unknown,PIN_T13,,,,,,,
,Unknown,PIN_T20,,,,,,,
,Unknown,PIN_V3,,,,,,,
,Unknown,PIN_V6,,,,,,,
,Unknown,PIN_V17,,,,,,,
,Unknown,PIN_W10,,,,,,,
,Unknown,PIN_W13,,,,,,,
,Unknown,PIN_W19,,,,,,,
,Unknown,PIN_Y8,,,,,,,
,Unknown,PIN_Y15,,,,,,,
,Unknown,PIN_G1,,,,,,,
,Unknown,PIN_G2,,,,,,,
,Unknown,PIN_H21,,,,,,,
,Unknown,PIN_H22,,,,,,,
,Unknown,PIN_J3,,,,,,,
,Unknown,PIN_J5,,,,,,,
,Unknown,PIN_J6,,,,,,,
,Unknown,PIN_J8,,,,,,,
,Unknown,PIN_J9,,,,,,,
,Unknown,PIN_K8,,,,,,,
,Unknown,PIN_K15,,,,,,,
,Unknown,PIN_K17,,,,,,,
,Unknown,PIN_K18,,,,,,,
,Unknown,PIN_L7,,,,,,,
,Unknown,PIN_L15,,,,,,,
,Unknown,PIN_L16,,,,,,,
,Unknown,PIN_L17,,,,,,,
,Unknown,PIN_M7,,,,,,,
,Unknown,PIN_M8,,,,,,,
,Unknown,PIN_M15,,,,,,,
,Unknown,PIN_M16,,,,,,,
,Unknown,PIN_N5,,,,,,,
,Unknown,PIN_N8,,,,,,,
,Unknown,PIN_P4,,,,,,,
,Unknown,PIN_P14,,,,,,,
,Unknown,PIN_P19,,,,,,,
,Unknown,PIN_P20,,,,,,,
,Unknown,PIN_P21,,,,,,,
,Unknown,PIN_P22,,,,,,,
,Unknown,PIN_R4,,,,,,,
,Unknown,PIN_W18,,,,,,,
/trunk/vhdl/demos/4kbasic/c2sb_4kbasic_cpu.vhdl
0,0 → 1,552
--#############################################################################
-- Altair 4K Basic on DE-1 board demo
--#############################################################################
-- This is enough to run the Altair 4K Basic from internal FPGA RAM.
-- The output signals of the DE-1 board are unused except for a reset button,
-- a clock input and two seral pins (txd/rxd). it should be easy to port the
-- Altair Basic demo to any other FPGA starter kit.
--
-- The Altair Basic code is pre-loaded in an internal 4K RAM block. If the code
-- becomes corrupted, there's no way to restore it other than reloading the
-- FPGA -- a reset will not do.
--
-- Note there are a few unused registers here and there. They are remnants of
-- an unfinished CP/M-on-SD-card demo on which I based the Altair Basic demo.
-- You may just ignore them.
--#############################################################################
-- PORT ADDRESSES:
-- 00h : in status serial port
-- 01h : in/out data serial port
-- 23h : out HEX display, L (not used)
-- 24h : out HEX display, H (not used)
-- 40h : in switches (not used)
-- 40h : out green leds (not used)
--
-- Serial port status port:
-- 01h : '1' => serial port RX busy
-- 80h : '1' => serial port TX busy
--#############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- Many of the board's i/o devices will go unused
entity c2sb_4kbasic_cpu is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
 
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
 
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
 
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
 
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
 
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
 
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
 
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end c2sb_4kbasic_cpu;
 
architecture minimal of c2sb_4kbasic_cpu is
 
component light8080
port (
addr_out : out std_logic_vector(15 downto 0);
 
inta : out std_logic;
inte : out std_logic;
halt : out std_logic;
intr : in std_logic;
vma : out std_logic;
io : out std_logic;
rd : out std_logic;
wr : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
 
clk : in std_logic;
reset : in std_logic );
end component;
 
-- Serial port, RX
component rs232_rx
port(
rxd : IN std_logic;
read_rx : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
data_rx : OUT std_logic_vector(7 downto 0);
rx_rdy : OUT std_logic
);
end component;
 
-- Serial port, TX
component rs232_tx
port(
clk : in std_logic;
reset : in std_logic;
load : in std_logic;
data_i : in std_logic_vector(7 downto 0);
rdy : out std_logic;
txd : out std_logic
);
end component;
 
-- Program ROM
component c2sb_4kbasic_rom
port(
clk : in std_logic;
addr : in std_logic_vector(15 downto 0);
we : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
--##############################################################################
-- light8080 CPU system signals
 
signal data_in : std_logic_vector(7 downto 0);
signal vma : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal io : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal addr : std_logic_vector(15 downto 0);
signal inta : std_logic;
signal inte : std_logic;
signal intr : std_logic;
signal halt : std_logic;
 
-- signals for sram 'synchronization'
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg
signal sram_write : std_logic; -- sram we register
 
-- signals for debug
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus
 
signal rs_tx_data : std_logic_vector(7 downto 0);
 
--##############################################################################
-- General I/O control signals
 
signal io_q : std_logic;
signal rd_q : std_logic;
signal io_read : std_logic;
signal io_write : std_logic;
signal low_ram_we : std_logic;
 
--##############################################################################
-- RS232 signals
 
signal rx_rdy : std_logic;
signal tx_rdy : std_logic;
signal rs232_data_rx : std_logic_vector(7 downto 0);
signal rs232_status : std_logic_vector(7 downto 0);
signal data_io_out : std_logic_vector(7 downto 0);
signal io_port : std_logic_vector(7 downto 0);
signal read_rx : std_logic;
signal write_tx : std_logic;
 
 
--##############################################################################
-- Application signals
 
-- general control port (rom paging)
signal reg_control : std_logic_vector(7 downto 0);
 
-- CPU access to hex display (unused by Altair SW)
signal reg_display_h : std_logic_vector(7 downto 0);
signal reg_display_l : std_logic_vector(7 downto 0);
 
 
--##############################################################################
-- Quad 7-segment display (non multiplexed) & LEDS
 
signal display_data : std_logic_vector(15 downto 0);
signal reg_gleds : std_logic_vector(7 downto 0);
 
-- i/o signals
signal data_io_in : std_logic_vector(7 downto 0);
signal data_mem_in : std_logic_vector(7 downto 0);
signal data_rom_in : std_logic_vector(7 downto 0);
signal rom_access : std_logic;
signal rom_space : std_logic;
signal breakpoint : std_logic;
 
 
-- Clock & reset signals
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal counter_1hz : std_logic_vector(25 downto 0);
signal reset : std_logic;
signal clk : std_logic;
 
-- SD control signals
signal sd_in : std_logic;
signal reg_sd_dout : std_logic;
signal reg_sd_clk : std_logic;
signal reg_sd_cs : std_logic;
 
begin
 
-- CS for the lowest 4K block
low_ram_we <= '1' when wr='1' and io='0' and addr(15 downto 12)="0000" else '0';
 
-- program ROM. Note the 'ROM' is actually initialized RAM
program_rom : c2sb_4kbasic_rom port map(
clk => clk,
addr => addr,
we => low_ram_we,
data_in => data_out,
data_out => data_rom_in
);
 
-- rom CS decoder
rom_space <= '1' when (reg_control(0)='0' and addr(15 downto 12) = "0000")
else '0';
 
-- registered rom CS
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
rom_access <= '1';
breakpoint <= '0';
else
if rd='1' and rom_space='1' then
rom_access <= '1';
else
rom_access <= '0';
end if;
end if;
end if;
end process;
 
-- rom vs ram mux: hardwired to always use the internal RAM (or ROM)
data_mem_in <= data_rom_in; -- when rom_access='1' else
--sram_data(7 downto 0);
 
 
-- output port registers, all unused except for the serial io
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
reg_gleds <= X"00";
reg_control <= X"00";
reg_display_h <= X"00";
reg_display_l <= X"00";
reg_sd_dout <= '0';
reg_sd_clk <= '0';
reg_sd_cs <= '0';
else
if io_write='1' then
if addr(7 downto 0)=X"40" then
reg_gleds <= data_out;
end if;
if addr(7 downto 0)=X"23" then
reg_display_l <= data_out;
end if;
if addr(7 downto 0)=X"24" then
reg_display_h <= data_out;
end if;
end if;
end if;
end if;
end process;
 
 
-- The interrupt is unused in the Altair 4K Basic demo
intr <= '0';
 
-- CPU instance
cpu: light8080 port map(
clk => clk,
reset => reset,
vma => vma,
rd => rd,
wr => wr,
io => io,
addr_out => addr,
data_in => data_in,
data_out => data_out,
intr => intr,
inte => inte,
inta => inta,
halt => halt
);
 
 
-- delayed (registered) control signals, plus data synchronization registers
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
io_q <= '0';
rd_q <= '0';
io_port <= X"00";
data_io_out <= X"00";
else
io_q <= io;
rd_q <= rd;
io_port <= addr(7 downto 0);
data_io_out <= data_out;
end if;
end if;
end process;
 
-- red leds (light with '1') -- some CPU control signals
red_leds(0) <= halt;
red_leds(1) <= inte;
red_leds(2) <= vma;
red_leds(3) <= rd;
red_leds(4) <= wr;
 
red_leds(5) <= inta;
red_leds(6) <= clk_1hz;-- intr;
red_leds(7) <= rom_space;
red_leds(8) <= rx_rdy;
red_leds(9) <= tx_rdy;
 
 
--##### Input ports ###########################################################
 
-- mem vs. io input mux (note IRQ vector is hardwired to FFh)
data_in <= data_io_in when io_q='1' and inta='0' else -- I/O port data
data_mem_in when io_q='0' and inta='0' else -- MEM data
X"ff"; -- IRQ vector (RST 7)
 
-- io read enable (for async io ports; data read in cycle following io='1')
io_read <= '1' when io_q='1' and rd_q='1' else '0';
 
-- io write enable (for sync io ports; data written in cycle following io='1')
io_write <= '1' when io='1' and wr='1' else '0';
 
-- read/write signals for rs232 modules
read_rx <= '1' when io_read='1' and addr(7 downto 0)=X"01" else '0';
write_tx <= '1' when io_write='1' and addr(7 downto 0)=X"01" else '0';
 
-- synchronized input port mux (using registered port address)
with io_port(7 downto 0) select data_io_in <=
-- Altair serial input status port
rs232_status when X"00",
-- Altair serial input data port, with MSB cleared
"0" & rs232_data_rx(6 DOWNTO 0) when X"01",
-- Some other ports unused by the 4K Basic code
--sd_in & "0000000" when X"88",
switches(7 downto 0) when others;
 
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD
--##############################################################################
 
--##############################################################################
-- FLASH (flash is unused in this demo)
--##############################################################################
 
flash_addr <= (others => '0');
 
flash_we_n <= '1'; -- all enable signals inactive
flash_oe_n <= '1';
flash_reset_n <= '1';
 
 
--##############################################################################
-- SRAM (used as 64K x 8)
--
-- NOTE: All writes go to SRAM independent of rom paging status
--##############################################################################
 
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
sram_addr <= "000000000000000000";
address_reg <= "0000000000000000";
sram_data_out <= X"00";
sram_write <= '0';
else
-- load address register
if vma='1' and io='0' then
sram_addr <= "00" & addr;
address_reg <= addr;
end if;
-- load data and write enable registers
if vma='1' and wr='1' and io='0' then
sram_data_out <= data_out;
sram_write <= '1';
else
sram_write <= '0';
end if;
end if;
end if;
end process;
 
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out;
-- (the X"ZZ" will physically be the read input data)
 
-- sram access controlled by WE_N
sram_oe_n <= '0';
sram_ce_n <= '0';
sram_we_n <= not sram_write;
sram_ub_n <= '1'; -- always disable
sram_lb_n <= '0';
 
--##############################################################################
-- RESET, CLOCK
--##############################################################################
 
-- Use button 3 as reset
reset <= not buttons(3);
 
 
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
begin
if clk_50MHz'event and clk_50MHz='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if conv_integer(counter_1hz) = 50000000 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
 
-- Master clock is external 50MHz oscillator
clk <= clk_50MHz;
 
 
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
 
-- Display the contents of a debug register at the green leds bar
green_leds <= reg_gleds;
 
 
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
 
-- We'll be displaying valid memory addresses in the hex display.
process(clk)
begin
if clk'event and clk='1' then
if vma = '1' then
display_data <= addr(15 downto 0);
end if;
end if;
end process;
-- alternatively, we might display the contents of some debug registers
--display_data <= addr(15 downto 0) when switches(9)='1' else
-- reg_display_h & reg_display_l;
 
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
with display_data(15 downto 12) select hex3 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
with display_data(11 downto 8) select hex2 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
with display_data(7 downto 4) select hex1 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
with display_data(3 downto 0) select hex0 <=
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
--##############################################################################
-- SD card interface
--##############################################################################
 
-- unused in this demo, but I did not bother to cut away the attached registers
sd_cs <= reg_sd_cs;
sd_cmd <= reg_sd_dout;
sd_clk <= reg_sd_clk;
sd_in <= sd_data;
 
 
--##############################################################################
-- SERIAL
--##############################################################################
 
serial_rx : rs232_rx port map(
rxd => rxd,
data_rx => rs232_data_rx,
rx_rdy => rx_rdy,
read_rx => read_rx,
clk => clk,
reset => reset
);
 
-- Clear the MSB so the terminal gets clean ASCII codes
rs_tx_data <= "0" & data_out(6 downto 0);
 
serial_tx : rs232_tx port map(
clk => clk,
reset => reset,
rdy => tx_rdy,
load => write_tx,
data_i => rs_tx_data,
txd => txd
);
 
rs232_status <= (not tx_rdy) & "000000" & (not rx_rdy);
 
end minimal;

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