URL
https://opencores.org/ocsvn/m1_core/m1_core/trunk
Subversion Repositories m1_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 45 to Rev 46
- ↔ Reverse comparison
Rev 45 → Rev 46
/trunk/hdl/rtl/m1_core/m1_cpu.v
58,10 → 58,11
*/ |
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// Register file |
reg[31:0] GPR[31:0]; // General Purpose Registers |
reg[31:0] PC; // Program Counter |
reg[31:0] HI, LO; // HI and LO registers (for multiplication/division) |
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reg[31:0] GPR[31:0]; // General Purpose Registers |
reg[31:0] PC; // Program Counter |
reg[31:0] HI, LO; // HI and LO registers (for multiplication/division) |
reg[31:0] SysCon[0:31]; // System Control registers |
|
/* |
* Pipeline latches |
*/ |
84,6 → 85,7
reg[31:0] id_ex_store_value; // Store value |
reg[4:0] id_ex_destreg; // Destination register (GPR number) |
reg id_ex_desthi, id_ex_destlo; // Destination register (HI/LO) |
reg[4:0] id_ex_destsyscon; // Destination register (System Control) |
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// Latch 3: EX/MEM |
reg[31:0] ex_mem_opcode; |
97,7 → 99,8
reg[3:0] ex_mem_store_sel; // Byte Selector on Stores |
reg[4:0] ex_mem_destreg; |
reg ex_mem_desthi, ex_mem_destlo; |
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reg[4:0] ex_mem_destsyscon; |
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// Latch 4: MEM/WB |
reg[31:0] mem_wb_opcode; |
reg[31:0] mem_wb_addr, mem_wb_addrnext; |
104,11 → 107,11
reg[63:0] mem_wb_value; // Write-back value |
reg[4:0] mem_wb_destreg; |
reg mem_wb_desthi, mem_wb_destlo; |
reg [4:0] mem_wb_destsyscon; |
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/* |
* Combinational logic |
*/ |
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*/ |
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// ALU |
assign alu_a_o = id_ex_alu_a; |
219,6 → 222,13
assign mem_stall = wb_stall || ( (dmem_read_o||dmem_write_o) && !dmem_done_i); |
assign wb_stall = 0; |
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// Name the System Configuration registers |
wire[31:0] BadVAddr = SysCon[`SYSCON_BADVADDR]; |
wire[31:0] Status = SysCon[`SYSCON_STATUS]; |
wire[31:0] Cause = SysCon[`SYSCON_CAUSE]; |
wire[31:0] EPC = SysCon[`SYSCON_EPC]; |
wire[31:0] PrID = SysCon[`SYSCON_PRID]; |
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// Index for GPR initialization |
integer i; |
|
239,6 → 249,9
HI <= 0; |
LO <= 0; |
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// Initialize system configuration registers |
for(i=0; i<=31; i=i+1) SysCon[i] <= 32'h00000000; |
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// Initialize ABP requests to instantiated modules |
mul_req_o <= 0; |
div_req_o <= 0; |
1892,6 → 1905,12
LO <= mem_wb_value[31:0]; |
end |
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// SysCon |
if(mem_wb_destsyscon!=0) begin |
$display("INFO: CPU(%m)-WB: Writing Back SysCon[%d]=%X", mem_wb_destsyscon, mem_wb_value[31:0]); |
SysCon[mem_wb_destsyscon] <= mem_wb_value[31:0]; |
end |
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// Idle |
if(mem_wb_destreg==0 & mem_wb_desthi==0 & mem_wb_destlo==0) |
$display("INFO: CPU(%m)-WB: Write-Back has nothing to do"); |
/trunk/hdl/rtl/m1_core/m1_defs.vh
15,6 → 15,13
`define SIZE_LEFT 3'b100 |
`define SIZE_RIGHT 3'b101 |
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// System Configuration Coprocessor (CP0) registers for TLB-less systems |
`define SYSCON_BADVADDR 8 |
`define SYSCON_STATUS 12 |
`define SYSCON_CAUSE 13 |
`define SYSCON_EPC 14 |
`define SYSCON_PRID 15 |
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// Opcodes (ordered by binary value) |
`define OPCODE_SPECIAL 6'b000000 // SPECIAL instruction class |
`define OPCODE_BCOND 6'b000001 // BCOND instruction class |