URL
https://opencores.org/ocsvn/m1_core/m1_core/trunk
Subversion Repositories m1_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 63 to Rev 64
- ↔ Reverse comparison
Rev 63 → Rev 64
/m1_core/trunk/doc/TODO.txt
1,5 → 1,5
Simply RISC M1 Core ("Mistral") TODO List |
========================================= |
M1 Core ("Mistral") TODO List |
============================= |
|
Implementation |
-------------- |
/m1_core/trunk/hdl/behav/testbench/testbench.v
1,5 → 1,5
/* |
* Simply RISC M1 Core Testbench |
* M1 Core Testbench |
*/ |
|
`include "ddr_include.v" |
120,7 → 120,7
initial begin |
|
// Display start message |
$display("INFO: TBENCH(%m): Starting Simply RISC M1 Core simulation..."); |
$display("INFO: TBENCH(%m): Starting M1 Core simulation..."); |
|
// Create VCD trace file |
$dumpfile("trace.vcd"); |
132,7 → 132,7
#1000 |
sys_reset <= 0; |
#99000 |
$display("INFO: TBENCH(%m): Completed Simply RISC M1 Core simulation!"); |
$display("INFO: TBENCH(%m): Completed M1 Core simulation!"); |
$finish; |
|
end |
/m1_core/trunk/hdl/rtl/m1_core/m1_alu.v
1,5 → 1,5
/* |
* Simply RISC M1 Arithmetic-Logic Unit |
* M1 Arithmetic-Logic Unit |
* |
* Simple RTL-level ALU with Alternating Bit Protocol (ABP) interface. |
*/ |
/m1_core/trunk/hdl/rtl/m1_core/m1_core.v
1,5 → 1,5
/* |
* Simply RISC M1 Core Top-Level |
* M1 Core Top-Level |
* |
* Schematic with instances of CPU, ALU, Mul, Div and MMU |
*/ |
/m1_core/trunk/hdl/rtl/m1_core/m1_cpu.v
1,5 → 1,5
/* |
* Simply RISC M1 Central Processing Unit |
* M1 Central Processing Unit |
*/ |
|
`include "m1_defs.vh" |
/m1_core/trunk/hdl/rtl/m1_core/m1_defs.vh
1,5 → 1,5
/* |
* Simply RISC M1 Defines |
* M1 Defines |
*/ |
|
// Useful constants |
/m1_core/trunk/hdl/rtl/m1_core/m1_div.v
1,5 → 1,5
/* |
* Simply RISC M1 Divider |
* M1 Divider |
* |
* Simple RTL-level divider with Alternating Bit Protocol (ABP) interface. |
*/ |
/m1_core/trunk/hdl/rtl/m1_core/m1_mmu.v
1,5 → 1,5
/* |
* Simply RISC M1 Memory Management Unit |
* M1 Memory Management Unit |
* |
* This block converts Harvard architecture requests to access the |
* small internal prefetch buffer, and just in case the external |
/m1_core/trunk/hdl/rtl/m1_core/m1_mul.v
1,5 → 1,5
/* |
* Simply RISC M1 Multiplier |
* M1 Multiplier |
* |
* Simple RTL-level Multiplier with Alternating Bit Protocol (ABP) interface. |
*/ |
/m1_core/trunk/hdl/rtl/spartan3esk_top/spartan3esk_top.v
1,5 → 1,5
/* |
* Simply RISC M1 Core System for Xilinx Spartan-3E 500 Starter Kit |
* M1 Core System for Xilinx Spartan-3E 500 Starter Kit |
*/ |
|
`include "ddr_include.v" |
/m1_core/trunk/hdl/rtl/wb_text_vga/fontmap_rom.v~
File deleted
/m1_core/trunk/hdl/rtl/wb_text_vga/fontmap_rom.v
6,7 → 6,7
* number of the line [2:0] contained into the char (starting from the top). |
* It should use only one 2KByte Block RAM on a Xilinx FPGA device. |
* The font design is (C) 2005 by Brian Cassidy and released under the Perl license. |
* All the rest is (C) 2008 by Simply RISC LLP and released under the GPL license. |
* All the rest is (C) 2008 by Fabrizio Fazzino and released under the GPL license. |
*/ |
|
// synthesis attribute rom_style of fontmap_rom is block; |
/m1_core/trunk/tools/bin/compile_test
5,7 → 5,7
# Parameter is test name without extension (e.g. to compile |
# $M1_ROOT/tests/hello.c) run "compile_test hello". |
# |
# Requires mipsel-linux-gcc (see Download section on srisc.com). |
# Requires mipsel-linux-gcc |
|
if [ -z "$M1_ROOT" ]; then echo "***ERROR***: M1_ROOT variable is undefined, please set it and run 'source sourceme'."; exit 1; fi |
if ! [ -d "$M1_ROOT" ]; then echo "***ERROR***: directory '$M1_ROOT' does not exist, please check it and run 'source sourceme' again."; exit 1; fi |
16,8 → 16,6
echo "" |
echo "compile_test - Script to compile a test for the M1 Core" |
echo "" |
echo "(C)2008 Simply RISC" |
echo "" |
echo "Usage:" |
echo "" |
echo " compile_test <TEST_NAME>" |