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URL https://opencores.org/ocsvn/mblite/mblite/trunk

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  • This comparison shows the changes necessary to convert path 
    /mblite/trunk/designs/core_syn
    from Rev 8 to Rev 6
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  •

Rev 8 → Rev 6

/testbench.vhd
11,52 → 11,52
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
library std;
use std.textio.all;
LIBRARY std;
USE std.textio.ALL;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
LIBRARY mblite;
USE mblite.config_Pkg.ALL;
USE mblite.core_Pkg.ALL;
USE mblite.std_Pkg.ALL;
 
entity testbench is
end testbench;
ENTITY testbench IS
END testbench;
 
architecture arch of testbench is
ARCHITECTURE arch OF testbench IS
 
component mblite_soc is port
COMPONENT mblite_soc IS PORT
(
sys_clk_i : in std_logic := 'x';
dbg_dmem_o_we_o : out std_logic;
dbg_dmem_o_ena_o : out std_logic;
sys_rst_i : in std_logic := 'x';
sys_ena_i : in std_logic := 'x';
sys_int_i : in std_logic := 'x';
dbg_dmem_o_adr_o : out std_logic_vector(31 downto 0);
dbg_dmem_o_dat_o : out std_logic_vector(31 downto 0);
dbg_dmem_o_sel_o : out std_logic_vector( 3 downto 0)
sys_clk_i : in STD_LOGIC := 'X';
dbg_dmem_o_we_o : out STD_LOGIC;
dbg_dmem_o_ena_o : out STD_LOGIC;
sys_rst_i : in STD_LOGIC := 'X';
sys_ena_i : in STD_LOGIC := 'X';
sys_int_i : in STD_LOGIC := 'X';
dbg_dmem_o_adr_o : out STD_LOGIC_VECTOR(31 downto 0);
dbg_dmem_o_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
dbg_dmem_o_sel_o : out STD_LOGIC_VECTOR( 3 downto 0)
);
end component;
END COMPONENT;
 
signal sys_clk_i : std_logic := '0';
signal sys_int_i : std_logic := '0';
signal sys_rst_i : std_logic := '0';
signal sys_ena_i : std_logic := '1';
SIGNAL sys_clk_i : std_logic := '0';
SIGNAL sys_int_i : std_logic := '0';
SIGNAL sys_rst_i : std_logic := '0';
SIGNAL sys_ena_i : std_logic := '1';
 
signal dmem_o : dmem_out_type;
SIGNAL dmem_o : dmem_out_type;
 
constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
begin
CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
BEGIN
 
sys_clk_i <= not sys_clk_i after 10000 ps;
sys_rst_i <= '1' after 0 ps, '0' after 150000 ps;
sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
 
soc : mblite_soc port map
soc : mblite_soc PORT MAP
(
sys_clk_i => sys_clk_i,
dbg_dmem_o_we_o => dmem_o.we_o,
69,45 → 69,45
dbg_dmem_o_sel_o => dmem_o.sel_o
);
 
timeout: process(sys_clk_i)
begin
if NOW = 10 ms then
report "TIMEOUT" severity FAILURE;
end if;
end process;
timeout: PROCESS(sys_clk_i)
BEGIN
IF NOW = 10 ms THEN
REPORT "TIMEOUT" SEVERITY FAILURE;
END IF;
END PROCESS;
 
-- Character device
stdio: process(sys_clk_i)
variable s : line;
variable byte : std_logic_vector(7 downto 0);
variable char : character;
begin
stdio: PROCESS(sys_clk_i)
VARIABLE s : line;
VARIABLE byte : std_logic_vector(7 DOWNTO 0);
VARIABLE char : character;
BEGIN
 
if rising_edge(sys_clk_i) then
if (not sys_rst_i and dmem_o.ena_o and compare(dmem_o.adr_o, std_out_adr)) = '1' then
if dmem_o.we_o = '1' then
IF rising_edge(sys_clk_i) THEN
IF (NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr)) = '1' THEN
IF dmem_o.we_o = '1' THEN
-- WRITE STDOUT
case dmem_o.sel_o is
when "0001" => byte := dmem_o.dat_o( 7 downto 0);
when "0010" => byte := dmem_o.dat_o(15 downto 8);
when "0100" => byte := dmem_o.dat_o(23 downto 16);
when "1000" => byte := dmem_o.dat_o(31 downto 24);
when others => null;
end case;
CASE dmem_o.sel_o IS
WHEN "0001" => byte := dmem_o.dat_o( 7 DOWNTO 0);
WHEN "0010" => byte := dmem_o.dat_o(15 DOWNTO 8);
WHEN "0100" => byte := dmem_o.dat_o(23 DOWNTO 16);
WHEN "1000" => byte := dmem_o.dat_o(31 DOWNTO 24);
WHEN OTHERS => NULL;
END CASE;
char := character'val(my_conv_integer(byte));
if byte = X"0D" then
IF byte = X"0D" THEN
-- Ignore character 13
elsif byte = X"0A" then
ELSIF byte = X"0A" THEN
-- Writeline on character 10 (newline)
writeline(output, s);
else
ELSE
-- Write to buffer
write(s, char);
end if;
end if;
end if;
end if;
END IF;
END IF;
END IF;
END IF;
 
end process;
END PROCESS;
 
end arch;
END arch;
/mblite_soc.vhd
11,76 → 11,76
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
LIBRARY mblite;
USE mblite.config_Pkg.ALL;
USE mblite.core_Pkg.ALL;
USE mblite.std_Pkg.ALL;
 
entity mblite_soc is port
ENTITY mblite_soc IS PORT
(
sys_clk_i : in std_logic;
dbg_dmem_o_we_o : out std_logic;
dbg_dmem_o_ena_o : out std_logic;
sys_rst_i : in std_logic;
sys_ena_i : in std_logic;
sys_int_i : in std_logic;
dbg_dmem_o_adr_o : out std_logic_vector (31 downto 0);
dbg_dmem_o_dat_o : out std_logic_vector (31 downto 0);
dbg_dmem_o_sel_o : out std_logic_vector ( 3 downto 0)
sys_clk_i : IN std_logic;
dbg_dmem_o_we_o : OUT std_logic;
dbg_dmem_o_ena_o : OUT std_logic;
sys_rst_i : IN std_logic;
sys_ena_i : IN std_logic;
sys_int_i : IN std_logic;
dbg_dmem_o_adr_o : OUT std_logic_vector (31 DOWNTO 0);
dbg_dmem_o_dat_o : OUT std_logic_vector (31 DOWNTO 0);
dbg_dmem_o_sel_o : OUT std_logic_vector ( 3 DOWNTO 0)
);
end mblite_soc;
END mblite_soc;
 
architecture arch of mblite_soc is
ARCHITECTURE arch OF mblite_soc IS
 
component sram_init is generic
COMPONENT sram_init IS GENERIC
(
WIDTH : integer;
SIZE : integer
);
port
PORT
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic;
ena_i : IN std_logic;
clk_i : IN std_logic
);
end component;
END COMPONENT;
 
component sram_4en_init is generic
COMPONENT sram_4en_init IS GENERIC
(
WIDTH : integer;
SIZE : integer
);
port
PORT
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic_vector(3 DOWNTO 0);
ena_i : IN std_logic;
clk_i : IN std_logic
);
end component;
END COMPONENT;
 
signal dmem_o : dmem_out_type;
signal imem_o : imem_out_type;
signal dmem_i : dmem_in_type;
signal imem_i : imem_in_type;
SIGNAL dmem_o : dmem_out_type;
SIGNAL imem_o : imem_out_type;
SIGNAL dmem_i : dmem_in_type;
SIGNAL imem_i : imem_in_type;
 
signal mem_enable : std_logic;
signal sel_o : std_logic_vector(3 downto 0);
SIGNAL mem_enable : std_logic;
SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
 
constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
constant rom_size : integer := 13;
constant ram_size : integer := 13;
CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
CONSTANT rom_size : integer := 13;
CONSTANT ram_size : integer := 13;
 
begin
BEGIN
 
dbg_dmem_o_we_o <= dmem_o.we_o;
dbg_dmem_o_ena_o <= dmem_o.ena_o;
88,34 → 88,34
dbg_dmem_o_dat_o <= dmem_o.dat_o;
dbg_dmem_o_sel_o <= dmem_o.sel_o;
 
imem : sram generic map
imem : sram GENERIC MAP
(
WIDTH => CFG_IMEM_WIDTH,
SIZE => rom_size - 2
)
port map
PORT MAP
(
dat_o => imem_i.dat_i,
dat_i => "00000000000000000000000000000000",
adr_i => imem_o.adr_o(rom_size - 1 downto 2),
adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
wre_i => '0',
ena_i => imem_o.ena_o,
clk_i => sys_clk_i
);
 
mem_enable <= not sys_rst_i and dmem_o.ena_o and not compare(dmem_o.adr_o, std_out_adr);
sel_o <= dmem_o.sel_o when dmem_o.we_o = '1' else (others => '0');
mem_enable <= NOT sys_rst_i AND dmem_o.ena_o AND NOT compare(dmem_o.adr_o, std_out_adr);
sel_o <= dmem_o.sel_o WHEN dmem_o.we_o = '1' ELSE (OTHERS => '0');
 
dmem : sram_4en generic map
dmem : sram_4en GENERIC MAP
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => ram_size - 2
)
port map
PORT MAP
(
dat_o => dmem_i.dat_i,
dat_i => dmem_o.dat_o,
adr_i => dmem_o.adr_o(ram_size - 1 downto 2),
adr_i => dmem_o.adr_o(ram_size - 1 DOWNTO 2),
wre_i => sel_o,
ena_i => mem_enable,
clk_i => sys_clk_i
123,7 → 123,7
 
dmem_i.ena_i <= sys_ena_i;
 
core0 : core port map
core0 : core PORT MAP
(
imem_o => imem_o,
dmem_o => dmem_o,
133,4 → 133,4
rst_i => sys_rst_i,
clk_i => sys_clk_i
);
end arch;
END arch;
/sram_init.vhd
11,32 → 11,32
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
library mblite;
use mblite.std_Pkg.all;
LIBRARY mblite;
USE mblite.std_Pkg.ALL;
 
entity sram_init is generic
ENTITY sram_init IS GENERIC
(
WIDTH : integer := 32;
SIZE : integer := 11
);
port
PORT
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic;
ena_i : IN std_logic;
clk_i : IN std_logic
);
end sram_init;
END sram_init;
 
architecture arch of sram_init is
type ram_type is array (0 to 2 ** SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type := (
ARCHITECTURE arch OF sram_init IS
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type := (
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
294,16 → 294,16
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
 
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if notx(adr_i) and ena_i = '1' then
if wre_i = '1' then
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF notx(adr_i) AND ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_i)) <= dat_i;
end if;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
END IF;
END IF;
END PROCESS;
END arch;
/config_Pkg.vhd
11,52 → 11,52
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
package config_Pkg is
PACKAGE config_Pkg IS
 
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
 
-- Implement hardware multiplier
constant CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
 
-- Implement hardware barrel shifter
constant CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
 
-- Debug mode
constant CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
 
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
 
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
 
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
 
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
 
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2;
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
 
END config_Pkg;
/sram_4en_init.vhd
13,32 → 13,32
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
library mblite;
use mblite.std_Pkg.all;
LIBRARY mblite;
USE mblite.std_Pkg.ALL;
 
entity sram_4en_init is generic
ENTITY sram_4en_init IS GENERIC
(
WIDTH : integer := 32;
SIZE : integer := 11
);
port
PORT
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic_vector(3 DOWNTO 0);
ena_i : IN std_logic;
clk_i : IN std_logic
);
end sram_4en_init;
END sram_4en_init;
 
architecture arch of sram_4en_init is
type ram_type is array (0 to 2 ** size - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type := (
ARCHITECTURE arch OF sram_4en_init IS
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type := (
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
296,32 → 296,32
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
 
signal di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 downto 0);
begin
SIGNAL di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 DOWNTO 0);
BEGIN
process(wre_i, dat_i, adr_i)
begin
if wre_i(0) = '1' then
di0 <= dat_i(WIDTH/4 - 1 downto 0);
di0 <= dat_i(WIDTH/4 - 1 DOWNTO 0);
else
di0 <= ram(my_conv_integer(adr_i))(WIDTH/4 - 1 downto 0);
di0 <= ram(my_conv_integer(adr_i))(WIDTH/4 - 1 DOWNTO 0);
end if;
 
if wre_i(1) = '1' then
di1 <= dat_i(WIDTH/2 - 1 downto WIDTH/4);
di1 <= dat_i(WIDTH/2 - 1 DOWNTO WIDTH/4);
else
di1 <= ram(my_conv_integer(adr_i))(WIDTH/2 - 1 downto WIDTH/4);
di1 <= ram(my_conv_integer(adr_i))(WIDTH/2 - 1 DOWNTO WIDTH/4);
end if;
 
if wre_i(2) = '1' then
di2 <= dat_i(3*WIDTH/4 - 1 downto WIDTH/2);
di2 <= dat_i(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
else
di2 <= ram(my_conv_integer(adr_i))(3*WIDTH/4 - 1 downto WIDTH/2);
di2 <= ram(my_conv_integer(adr_i))(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
end if;
 
if wre_i(3) = '1' then
di3 <= dat_i(WIDTH-1 downto 3*WIDTH/4);
di3 <= dat_i(WIDTH-1 DOWNTO 3*WIDTH/4);
else
di3 <= ram(my_conv_integer(adr_i))(WIDTH-1 downto 3*WIDTH/4);
di3 <= ram(my_conv_integer(adr_i))(WIDTH-1 DOWNTO 3*WIDTH/4);
end if;
end process;
 
334,4 → 334,4
dat_o <= ram(my_conv_integer(adr_i));
end if;
end process;
end arch;
END arch;

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