URL
https://opencores.org/ocsvn/mblite/mblite/trunk
Subversion Repositories mblite
Compare Revisions
- This comparison shows the changes necessary to convert path
/mblite/trunk/designs/core_decoder_wb
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/testbench.vhd
45,15 → 45,15
SIGNAL s_wb_i : wb_slv_in_type; |
SIGNAL s_wb_o : wb_slv_out_type; |
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SIGNAL sys_clk_i : std_ulogic := '0'; |
SIGNAL sys_int_i : std_ulogic; |
SIGNAL sys_rst_i : std_ulogic; |
SIGNAL sys_clk_i : std_logic := '0'; |
SIGNAL sys_int_i : std_logic; |
SIGNAL sys_rst_i : std_logic; |
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CONSTANT rom_size : integer := 16; |
CONSTANT ram_size : integer := 16; |
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SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0); |
SIGNAL ena_o : std_ulogic; |
SIGNAL sel_o : std_logic_vector(3 DOWNTO 0); |
SIGNAL ena_o : std_logic; |
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BEGIN |
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/config_Pkg.vhd
55,7 → 55,7
-- BUS PARAMETERS |
---------------------------------------------------------------------------------------------- |
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TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); |
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); |
CONSTANT CFG_NUM_SLAVES : positive := 2; |
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF"); |
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/wb_stdio.vhd
32,8 → 32,8
ARCHITECTURE arch OF wb_stdio IS |
CONSTANT ack_assert_delay : TIME := 2 ns; |
CONSTANT ack_deassert_delay : TIME := 2 ns; |
SIGNAL ack : std_ulogic; |
SIGNAL chr_dat : std_ulogic_vector(31 DOWNTO 0); |
SIGNAL ack : std_logic; |
SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0); |
SIGNAL chr_cnt : natural := 0; |
BEGIN |
wb_o.int_o <= '0'; |
41,7 → 41,7
-- Character device |
stdio: PROCESS(wb_i.clk_i) |
VARIABLE s : line; |
VARIABLE byte : std_ulogic_vector(7 DOWNTO 0); |
VARIABLE byte : std_logic_vector(7 DOWNTO 0); |
VARIABLE char : character; |
BEGIN |
IF rising_edge(wb_i.clk_i) THEN |