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/bench/bench_minimips.vhd
0,0 → 1,203
-------------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Superscalar Processor : testbench --
-- based on miniMIPS Processor --
-- --
-- --
-- Author : Miguel Cafruni --
-- miguel_cafruni@hotmail.com --
-- December 2018 --
-------------------------------------------------------------------------------
 
-- If you encountered any problem, please contact :
--
-- lmouton@enserg.fr (2003 version)
-- oschneid@enserg.fr (2003 version)
-- shangoue@enserg.fr (2003 version)
-- miguel_cafruni@hotmail.com (Superscalar version 2018)
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library std;
use std.textio.all;
 
library work;
use work.pack_mips.all;
 
entity sim_minimips is
end;
 
architecture bench of sim_minimips is
 
component minimips is
port (
clock : in std_logic;
clock2 : in std_logic;
reset : in std_logic;
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
 
ram_req2 : out std_logic;
ram_adr2 : out bus32;
ram_r_w2 : out std_logic;
ram_data2 : inout bus32;
ram_ack2 : in std_logic;
it_mat : in std_logic
);
end component;
 
component ram is
generic (mem_size : natural := 256;
latency : time := 10 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic;
 
req2 : in std_logic;
adr2 : in bus32;
data_inout2 : inout bus32;
r_w2 : in std_logic;
ready2 : out std_logic
);
end component;
 
component rom is
generic (mem_size : natural := 256;
start : natural := 0;
latency : time := 10 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
 
adr2 : in bus32;
donnee2 : out bus32;
ack2 : out std_logic;
 
load : in std_logic;
fname : in string
);
end component;
signal clock : std_logic := '0';
signal clock2 : std_logic := '0';
signal reset : std_logic;
 
signal it_mat : std_logic := '0';
 
-- Connexion with the code memory
signal load : std_logic;
signal fichier : string(1 to 7);
 
-- Connexion with the Ram
signal ram_req : std_logic;
signal ram_adr : bus32;
signal ram_r_w : std_logic;
signal ram_data : bus32;
signal ram_rdy : std_logic;
 
signal ram_req2 : std_logic;
signal ram_adr2 : bus32;
signal ram_r_w2 : std_logic;
signal ram_data2 : bus32;
signal ram_rdy2 : std_logic;
 
begin
 
U_minimips : minimips port map (
clock => clock,
clock2 => clock2,
reset => reset,
ram_req => ram_req,
ram_adr => ram_adr,
ram_r_w => ram_r_w,
ram_data => ram_data,
ram_ack => ram_rdy,
 
ram_req2 => ram_req2,
ram_adr2 => ram_adr2,
ram_r_w2 => ram_r_w2,
ram_data2 => ram_data2,
ram_ack2 => ram_rdy2,
 
it_mat => it_mat
);
 
U_ram : ram port map (
req => ram_req,
adr => ram_adr,
data_inout => ram_data,
r_w => ram_r_w,
ready => ram_rdy,
 
req2 => ram_req2,
adr2 => ram_adr2,
data_inout2 => ram_data2,
r_w2 => ram_r_w2,
ready2 => ram_rdy2
);
 
U_rom : rom port map (
adr => ram_adr,
donnee => ram_data,
ack => ram_rdy,
 
adr2 => ram_adr2,
donnee2 => ram_data2,
ack2 => ram_rdy2,
 
load => load,
fname => fichier
);
 
clock <= not clock after 10 ns;
clock2 <= not clock2 after 10 ns;
reset <= '0', '1' after 5 ns, '0' after 25 ns;
ram_data <= (others => 'L');
ram_data2 <= (others => 'L');
process
variable command : line;
variable nomfichier : string(1 to 3);
begin
--write (output, "Enter the filename : ");
--readline(input, command);
--read(command, nomfichier);
 
fichier <= "msx.bin";
 
load <= '1';
--wait;
end process;
 
-- Memory Mapping --
-- 0000 - 00FF ROM
 
process (ram_adr, ram_r_w, ram_data)
begin -- Emulation of an I/O controller
ram_data <= (others => 'Z');
 
case ram_adr is
when X"00001000" => -- declenche une lecture avec interruption
it_mat <= '1' after 1000 ns;
ram_rdy <= '1' after 5 ns;
when X"00001001" => -- fournit la donnee et lache l'it
it_mat <= '0';
ram_data <= X"FFFFFFFF";
ram_rdy <= '1' after 5 ns;
when others => ram_rdy <= 'L';
end case;
end process;
 
end bench;
/bench/ram.vhd
0,0 → 1,106
-------------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Superscalar Processor : testbench --
-- based on miniMIPS Processor --
-- --
-- --
-- Author : Miguel Cafruni --
-- miguel_cafruni@hotmail.com --
-- December 2018 --
-------------------------------------------------------------------------------
 
-- If you encountered any problem, please contact :
--
-- lmouton@enserg.fr (2003 version)
-- oschneid@enserg.fr (2003 version)
-- shangoue@enserg.fr (2003 version)
-- miguel_cafruni@hotmail.com (Superscalar version 2018)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.pack_mips.all;
 
entity ram is
generic (mem_size : natural := 256; -- Size of the memory in words
latency : time := 0 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic;
 
req2 : in std_logic;
adr2 : in bus32;
data_inout2 : inout bus32;
r_w2 : in std_logic;
ready2 : out std_logic
);
end;
 
 
architecture bench of ram is
type storage_array is array(natural range 1024 to 1024+4*mem_size - 1) of bus8;
signal storage : storage_array; -- The memory
begin
 
process(adr, data_inout, r_w, adr2, data_inout2, r_w2)
variable inadr : integer;
variable i : natural;
variable inadr2 : integer;
variable j : natural;
begin
inadr := to_integer(unsigned(adr));
 
if (inadr>=storage'low) and (inadr<=storage'high) then
ready <= '0', '1' after latency;
if req = '1' then
if r_w /= '1' then -- Reading in memory
for i in 0 to 3 loop
data_inout(8*(i+1)-1 downto 8*i) <= storage(inadr+(3-i)) after latency;
end loop;
else
for i in 0 to 3 loop
storage(inadr+(3-i)) <= data_inout(8*(i+1)-1 downto 8*i) after latency;
end loop;
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
ready <= 'L';
end if;
 
inadr2 := to_integer(unsigned(adr2));
 
if (inadr2>=storage'low) and (inadr2<=storage'high) then
ready2 <= '0', '1' after latency;
if req2 = '1' then
if r_w2 /= '1' then -- Reading in memory
for j in 0 to 3 loop
data_inout2(8*(j+1)-1 downto 8*j) <= storage(inadr2+(3-j)) after latency;
end loop;
else
for j in 0 to 3 loop
storage(inadr2+(3-j)) <= data_inout2(8*(j+1)-1 downto 8*j) after latency; --report "Valor j = " & integer'image(j);-- 04/09/18
end loop;
data_inout2 <= (others => 'Z');
end if;
else
data_inout2 <= (others => 'Z');
end if;
else
data_inout2 <= (others => 'Z');
ready2 <= 'L';
end if;
end process;
 
end bench;
/bench/rom.vhd
0,0 → 1,186
-------------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Superscalar Processor : testbench --
-- based on miniMIPS Processor --
-- --
-- --
-- Author : Miguel Cafruni --
-- miguel_cafruni@hotmail.com --
-- December 2018 --
-------------------------------------------------------------------------------
 
-- If you encountered any problem, please contact :
--
-- lmouton@enserg.fr (2003 version)
-- oschneid@enserg.fr (2003 version)
-- shangoue@enserg.fr (2003 version)
-- miguel_cafruni@hotmail.com (Superscalar version 2018)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
library work;
use work.pack_mips.all;
 
entity rom is
generic (mem_size : natural := 256; -- Size of the memory in words
start : natural := 32768;
latency : time := 0 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
adr2 : in bus32;
donnee2 : out bus32;
ack2 : out std_logic;
load : in std_logic;
fname : in string
);
end;
 
 
architecture bench of rom is
type storage_array is array(natural range start to start+4*mem_size - 1) of bus8;
signal storage : storage_array := (others => (others => '0')); -- The memory
signal adresse : bus16;
signal taille : bus16;
begin
 
 
process (load)
-- Variables for loading the memory
-- The reading is done by blocks
type bin is file of integer; -- Binary type file
file load_file : bin;
 
variable c : integer ; -- Integer (32 bits) read in the file
variable index : integer range storage'range; -- Index for loading
variable word : bus32; -- Word read in the file
variable taille_bloc : integer; -- Current size of the block to load
variable tmp : bus16;
variable status : file_open_status;
 
variable s : line;
variable big_endian : boolean := true; -- Define if the processor (on which we work) is little or big endian
begin
 
if load='1' then
 
-- Reading of the file de fill the memory at the defined address
file_open(status, load_file, fname, read_mode);
 
if status=open_ok then
 
while not endfile(load_file) loop
 
-- Read the header of the block
read(load_file, c); -- Read a 32 bit long word
word := bus32(to_unsigned(c, 32)); -- Conversion to a bit vector
 
if big_endian then
tmp := word(7 downto 0) & word(15 downto 8);
else
tmp := word(31 downto 16);
end if;
 
index := to_integer(unsigned(tmp));
adresse <= tmp;
 
if big_endian then
tmp := word(23 downto 16) & word(31 downto 24);
else
tmp := word(15 downto 0);
end if;
 
 
taille_bloc := to_integer(unsigned(tmp)) / 4;
taille <= tmp;
 
-- Load the block in the ROM
for n in 1 to taille_bloc loop
 
-- The header file is not correct (block too small, ROM to small ...)
-- The simulation is stopped
assert (not endfile(load_file) and (index<=storage'high))
report "L'image n'a pas le bon format ou ne rentre pas dans la rom."
severity error;
 
if not endfile(load_file) and (index<=storage'high) then
read(load_file, c);
word := bus32(to_unsigned(c, 32));
if (c < 0) then
word := not(word);
word := std_logic_vector(unsigned(word)+1);
end if;
for i in 0 to 3 loop
 
if big_endian then
storage(index+i) <= word(8*(i+1)-1 downto 8*i);
else
storage(index+(3-i)) <= word(8*(i+1)-1 downto 8*i);
end if;
 
end loop;
index := index + 4;
end if;
end loop;
 
end loop;
 
file_close(load_file);
 
else
assert false
report "Impossible d'ouvrir le fichier specifie."
severity error;
 
end if;
 
end if;
 
end process;
 
 
process(adr) -- Request for reading the ROM
variable inadr : integer;
variable i : natural;
begin
inadr := to_integer(unsigned(adr));
 
if (inadr>=storage'low) and (inadr<=storage'high) then
for i in 0 to 3 loop
donnee(8*(i+1)-1 downto 8*i) <= storage(inadr+3-i) after latency;
end loop;
ack <= '0', '1' after latency;
else
donnee <= (others => 'Z');
ack <= 'L';
end if;
end process;
 
 
process(adr2) -- Request for reading the ROM
variable inadr2 : integer;
variable i2 : natural;
begin
inadr2 := to_integer(unsigned(adr2));
 
if (inadr2>=storage'low) and (inadr2<=storage'high) then
for i2 in 0 to 3 loop
donnee2(8*(i2+1)-1 downto 8*i2) <= storage(inadr2+3-i2) after latency;
end loop;
ack2 <= '0', '1' after latency;
else
donnee2 <= (others => 'Z');
ack2 <= 'L';
end if;
end process;
 
end bench;
 
 
 

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