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Rev 5 → Rev 6

/trunk/verilog/core/primitives.v
39,10 → 39,10
 
// CVS Log
//
// $Id: primitives.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: primitives.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,6 → 61,7
//
//
//
//
 
`timescale 1ns / 10ps
 
71,7 → 74,7
reg [7:0] out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
case(sel) // synopsys full_case parallel_case
0: out = in0;
1: out = in1;
2: out = in2;
128,7 → 131,7
reg [7:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
case(sel) // synopsys full_case parallel_case
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
168,7 → 171,7
input [10:0] in;
output [10:0] out;
 
assign out = in + 1;
assign out = in + 11'h1;
 
endmodule
 
177,7 → 180,7
input [7:0] in;
output [7:0] out;
 
assign out = in + 1;
assign out = in + 8'h1;
 
endmodule
 
213,28 → 216,3
endmodule
 
 
// Synchrounous SRAM
// 128 bytes by 8 bits
// 1 read port, 1 write port
module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data);
input clk;
input [6:0] rd_addr;
output [7:0] rd_data;
input we;
input [6:0] wr_addr;
input [7:0] wr_data;
 
reg [7:0] rf_mem[0:128]; // Actual Memory
 
reg [7:0] rd_data;
 
always @(posedge clk) // Synchrounous Read Logic
rd_data <= #1 rf_mem[rd_addr];
 
always @(posedge clk) // Synchrounous Write Logic
if(we)
rf_mem[wr_addr] <= #1 wr_data;
 
endmodule
 
 
/trunk/verilog/core/alu.v
39,10 → 39,10
 
// CVS Log
//
// $Id: alu.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: alu.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,6 → 61,7
//
//
//
//
 
 
`timescale 1ns / 10ps
108,7 → 111,7
begin
cout = 0;
case(op) // synopsys full_case parallel_case
ALU_ADD: {cout, out} = s1 + s2;
ALU_ADD: {cout, out_t} = s1 + s2;
ALU_AND: out_t = s1 & s2;
ALU_CLR: out_t = 8'h00;
ALU_NOT: out_t = ~s1;
/trunk/verilog/core/register_file.v
39,10 → 39,10
 
// CVS Log
//
// $Id: register_file.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: register_file.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,6 → 61,7
//
//
//
//
 
`timescale 1ns / 10ps
 
82,26 → 85,21
wire [7:0] rf_rd_data_mem;
reg [7:0] wr_data_tmp;
reg rd_wr_addr_equal;
wire rd_wr_addr_equal_tmp;
//reg [6:0] rd_adr_r, wr_adr_r;
 
// Simple Read & Write Address Mapping to memory address
assign rd_addr[6] = ~rf_rd_addr[4];
assign rd_addr[5:3] = rf_rd_addr[4] ? {rf_rd_bnk, rf_rd_addr[3]} : 3'h0;
assign rd_addr[2:0] = rf_rd_addr[2:0];
 
assign rd_addr = rf_rd_addr[4] ?
{1'b0, rf_rd_bnk, rf_rd_addr[3:0]} :
{1'b1, 2'b00, 1'b0, rf_rd_addr[2:0]};
assign wr_addr[6] = ~rf_wr_addr[4];
assign wr_addr[5:3] = rf_wr_addr[4] ? {rf_wr_bnk, rf_wr_addr[3]} : 3'h0;
assign wr_addr[2:0] = rf_wr_addr[2:0];
 
assign wr_addr = rf_wr_addr[4] ?
{1'b0, rf_wr_bnk, rf_wr_addr[3:0]} :
{1'b1, 2'b00, 1'b0, rf_wr_addr[2:0]};
 
// This logic is to bypass the register file if we are reading and
// writing (in previous instruction) to the same register
always @(posedge clk)
rd_wr_addr_equal <= #1 rd_wr_addr_equal_tmp;
rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we;
 
assign rd_wr_addr_equal_tmp = (rd_addr==wr_addr) & rf_we;
 
assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem;
 
always @(posedge clk)
/trunk/verilog/core/primitives_xilinx.v
39,10 → 39,10
 
// CVS Log
//
// $Id: primitives_xilinx.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: primitives_xilinx.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,12 → 61,12
//
//
//
//
 
`timescale 1ns / 10ps
 
// LIB_TAG
// synopsys translate_off
// synthesis translate_off
`include "XilinxCoreLib/C_ADDSUB_V1_0.v"
`include "XilinxCoreLib/C_MUX_BUS_V1_0.v"
`include "XilinxCoreLib/C_COMPARE_V1_0.v"
71,7 → 73,6
`include "XilinxCoreLib/C_MUX_BIT_V1_0.v"
`include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v"
`include "XilinxCoreLib/C_REG_FD_V1_0.v"
// synthesis translate_on
// synopsys translate_on
// LIB_TAG_END
 
/trunk/verilog/core/risc_core.v
39,10 → 39,10
 
// CVS Log
//
// $Id: risc_core.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: risc_core.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,6 → 61,7
//
//
//
//
 
`timescale 1ns / 10ps
 
303,8 → 306,16
 
////////////////////////////////////////////////////////////////////////
// Synchrounous Register File
register_file u0( .clk(clk), .rst(rst), .rf_rd_bnk(rf_rd_bnk), .rf_rd_addr(rf_rd_addr), .rf_rd_data(rf_rd_data),
.rf_we(rf_we), .rf_wr_bnk(rf_wr_bnk), .rf_wr_addr(rf_wr_addr), .rf_wr_data(rf_wr_data) );
register_file u0( .clk( clk ),
.rst( rst ),
.rf_rd_bnk( rf_rd_bnk ),
.rf_rd_addr( rf_rd_addr ),
.rf_rd_data( rf_rd_data ),
.rf_we( rf_we ),
.rf_wr_bnk( rf_wr_bnk ),
.rf_wr_addr( rf_wr_addr ),
.rf_wr_data( rf_wr_data )
);
 
////////////////////////////////////////////////////////////////////////
// Always Fetch Next Instruction
324,9 → 335,11
always @(posedge clk)
valid_1 <= #1 valid;
 
always @(posedge clk)
instr_1 <= #1 instr_0;
 
always @(posedge clk) // Basic Decode extracted directly from the instruction
begin
instr_1 <= #1 instr_0;
// Mask for bit modification instructions
case(instr_0[7:5]) // synopsys full_case parallel_case
0: mask <= #1 8'h01;
343,7 → 356,6
always @(posedge clk)
pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline
 
/*
always @(posedge clk) // SFR Read Operands
if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0];
else
356,8 → 368,9
6: sfr_rd_data <= #1 portb_r;
7: sfr_rd_data <= #1 portc_r;
endcase
*/
 
 
/*
always @(posedge clk)
sfr_rd_data <= #1 sfr_rd_data_tmp1;
 
389,16 → 402,20
 
mux2_8 u2b( .sel(instr_0[0]), .out(sfr_rd_data_tmp3),
.in0(portb_r), .in1(portc_r) );
*/
 
reg instd_zero;
 
always @(posedge clk)
instd_zero <= #1 !(|inst_data[4:0]);
 
// Register File Read Port
assign rf_rd_bnk = fsr_next[6:5];
assign rf_rd_addr = (instr_0[4:0]==0) ? fsr_next[4:0] : instr_0[4:0];
assign rf_rd_addr = instd_zero ? fsr_next[4:0] : instr_0[4:0];
 
 
// ALU OP
always @(posedge clk)
casex(instr_0) // synopsys full_case
casex(instr_0) // synopsys full_case parallel_case
// Byte Oriented RF Operations
I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF
I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF
429,7 → 446,6
endcase
 
 
 
// Source Select
// This CPU source 1 can be one of: rf (or sfr) or k,
// second source (if any) is always w
442,7 → 458,7
I_MOVLW: src1_sel_ = K_SEL;
I_RETLW: src1_sel_ = K_SEL;
I_XORLW: src1_sel_ = K_SEL;
default: src1_sel_ = (instr_0[4:3]==2'h0 & instr_0[2:0] != 0) ? SFR_SEL : RF_SEL;
default: src1_sel_ = ( (instr_0[4:3]==2'h0) & (instr_0[2:0] != 3'h0 )) ? SFR_SEL : RF_SEL;
endcase
 
always @(posedge clk)
502,44 → 518,26
 
// Stage 2 destination encoder
// write enable outputs are registered now
always @(posedge clk)
w_we <= #1 w_we_; // working register write 0 enable
always @(posedge clk) w_we <= #1 w_we_; // working register write 0 enable
 
always @(posedge clk)
w_we1 <= #1 w_we1_; // working register write 1 enable
always @(posedge clk) w_we1 <= #1 w_we1_; // working register write 1 enable
 
 
// Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f);
// 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing
// The logic has been partitioned and balanced between the decode and execute stage ...
/*
assign rf_we = (valid_1 & rf_we1) | (valid_1 & rf_we2 & rf_we3);// register file write enable Composite
assign rf_we = rf_we1 | (rf_we2 & rf_we3); // register file write enable Composite
 
always @(posedge clk)
rf_we1 <= #1 rf_we_; // register file write enable 1
rf_we1 <= #1 valid & rf_we_; // register file write enable 1
 
always @(posedge clk)
rf_we2 <= #1 fsr_next[4] | fsr_next[3]; // register file write enable 2
rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]);// register file write enable 2
 
always @(posedge clk)
rf_we3 <= #1 indf_we_; // register file write enable 3
*/
 
assign rf_we = rf_we1 | (rf_we2 & rf_we3);// register file write enable Composite
 
always @(posedge clk)
rf_we1 <= #1 valid & rf_we_; // register file write enable 1
 
always @(posedge clk)
rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]); // register file write enable 2
 
always @(posedge clk)
rf_we3 <= #1 indf_we_; // register file write enable 3
 
 
 
 
always @(posedge clk)
wdt_clr <= #1 instr_0[11:0] == I_CLRWDT;
 
 
592,7 → 590,6
endcase
end
 
 
always @(posedge clk)
begin
pc_skz <= #1 valid & pc_skz_;
646,8 → 643,16
//assign src1 = src1_sel ? rf_rd_data : sfr_rd_data;
mux2_8 u3( .sel(src1_sel), .in0(sfr_rd_data), .in1(rf_rd_data), .out(src1) );
 
alu u4( .s1(src1), .s2(w), .mask(mask), .out(dout),
.op(alu_op), .c_in(status[0]), .c(c_out), .dc(dc_out), .z(z_out) );
alu u4( .s1( src1 ),
.s2( w ),
.mask( mask ),
.out( dout ),
.op( alu_op ),
.c_in( status[0] ),
.c( c_out ),
.dc( dc_out ),
.z( z_out )
);
 
// Register file connections
assign rf_wr_bnk = fsr[6:5];
679,7 → 684,6
 
mux2_8 u21( .sel(stat_we), .in1( {dout | 8'h18} ), .in0( {status[7:3],status_next2[2:0]} ), .out(status_next) );
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) status <= #1 STAT_RST_VALUE;
else status <= #1 status_next;
688,7 → 692,6
 
mux2_7 u31( .sel(fsr_we), .in1(dout[6:0]), .in0(fsr), .out(fsr_next) );
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) fsr <= #1 FSR_RST_VALUE;
else fsr <= #1 fsr_next;
696,25 → 699,21
always @(posedge clk)
if(valid_1 & (w_we | (w_we1 & ~instr_1[5])) ) w <= #1 dout;
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) trisa <= #1 TRIS_RST_VALUE;
else
if(trisa_we & valid_1) trisa <= #1 w;
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) trisb <= #1 TRIS_RST_VALUE;
else
if(trisb_we & valid_1) trisb <= #1 w;
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) trisc <= #1 TRIS_RST_VALUE;
else
if(trisc_we & valid_1) trisc <= #1 w;
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) option <= #1 OPT_RST_VALUE;
else
743,20 → 742,28
//assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? (tmr0 + 1) : tmr0;
 
 
mux2_8 u5( .sel(tmr0_we & valid_1), .in0(tmr0_next1), .in1(dout), .out(tmr0_next) );
mux2_8 u6( .sel(tmr0_cnt_en), .in0(tmr0), .in1(tmr0_plus_1), .out(tmr0_next1) );
inc8 u7( .in(tmr0), .out(tmr0_plus_1) );
mux2_8 u5( .sel(tmr0_we & valid_1),
.in0(tmr0_next1), .in1(dout),
.out(tmr0_next) );
mux2_8 u6( .sel(tmr0_cnt_en),
.in0(tmr0), .in1(tmr0_plus_1),
.out(tmr0_next1) );
 
inc8 u7( .in(tmr0), .out(tmr0_plus_1) );
 
always @(posedge clk)
tmr0 <= #1 tmr0_next;
 
presclr_wdt u8( .clk(clk), .rst(rst), .tcki(tcki),
.option(option[5:0]),
.tmr0_we(tmr0_we & valid_1),
.tmr0_cnt_en(tmr0_cnt_en), .wdt_en(wdt_en),
.wdt_clr(wdt_clr & valid_1),
.wdt_to(wdt_to));
presclr_wdt u8( .clk( clk ),
.rst( rst ),
.tcki( tcki ),
.option( option[5:0] ),
.tmr0_we( tmr0_we & valid_1 ),
.tmr0_cnt_en( tmr0_cnt_en ),
.wdt_en( wdt_en ),
.wdt_clr( wdt_clr & valid_1 ),
.wdt_to( wdt_to )
);
 
 
////////////////////////////////////////////////////////////////////////
772,12 → 779,10
// registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to
// make the correct decission either way, and gett rid of unneded logic ...
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) inst_addr <= #1 PC_RST_VECTOR;
else inst_addr <= #1 pc_next;
 
//synopsys sync_set_reset "rst"
always @(posedge clk)
if(rst) pc <= #1 PC_RST_VECTOR;
else pc <= #1 pc_next;
/trunk/verilog/core/risc_core_top.v
39,10 → 39,10
 
// CVS Log
//
// $Id: risc_core_top.v,v 1.2 2002-09-27 15:35:40 rudi Exp $
// $Id: risc_core_top.v,v 1.3 2002-10-01 12:44:24 rudi Exp $
//
// $Date: 2002-09-27 15:35:40 $
// $Revision: 1.2 $
// $Date: 2002-10-01 12:44:24 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/27 15:35:40 rudi
// Minor update to newer devices ...
//
//
//
59,8 → 61,8
//
//
//
//
 
 
`timescale 1ns / 10ps
 
module mrisc_top(
67,7 → 69,7
clk, rst_in,
porta, portb, portc,
tcki,
wdt_en );
wdt_en ); // synthesis syn_useioff=1 syn_hier="flatten,remove"
 
// Basic Core I/O.
input clk;
101,14 → 103,6
wire [7:0] trisb;
wire [7:0] trisc;
 
wire block0, block1, wr_block0, wr_block1;
 
wire [10:0] wr_adr; // This signals can be used to optionally
wire [11:0] wr_data; // fill the internal ram from external memory
wire we;
 
wire [11:0] dout_unused;
 
////////////////////////////////////////////////////////////////////////
//
// IO Buffers
178,17 → 172,6
// Program memory
//
 
// Optional interface to fill the memory from external ROM
assign wr_adr = 11'h0;
assign wr_data = 12'h0;
assign we = 1'b0;
 
// Block selects
assign block0 = ~inst_addr[10];
assign block1 = inst_addr[10];
assign wr_block0 = ~wr_adr[10];
assign wr_block1 = wr_adr[10];
 
generic_spram #(11,12) imem(
.clk( clk ),
.rst( rst_in ),
196,8 → 179,8
.we( 1'b0 ),
.oe( 1'b1 ),
.addr( inst_addr ),
.di( ),
.di( 12'h0 ),
.do( inst_data )
);
);
 
endmodule

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