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Project Name: Mini-Risc core
+(See change Log at bottom of page for changes/updates)
++
Description:
+This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 + from Microchip. Additional information about the instruction set and capabilities + can be found at: www.microchip.com
++
+Legal Notice
+PIC, Microchip, etc. are Trademarks of Microchip Technology + Inc. I have no idea if implementing this core will or will not violate patents, + copyrights or cause any other type of lawsuits. I provide this core AS IS, without + any warranties. If you decide to build this core, you are responsible for any + legal resolutions, such as patents and copyrights, and perhaps others .... + This source files may be used and distributed without + restriction provided that all copyright statement are + not removed from the files and that any derivative + work contains the original copyright notices and + the associated disclaimer.
+++++THIS SOURCE FILES ARE PROVIDED + "AS IS" AND WITHOUT ANY
+
+ EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, WITHOUT
+ LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
+ FITNESS FOR A PARTICULAR PURPOSE.
+
Motivation
+-
+
- A PIC compatible Microcontroller that runs a lot faster +
- Synthesisable and technology independent design +
- Separate (External to the core) Program Memory +
- Options to extend the core + +
Compatibility
+This design should be fully software compatible to the Microchip Implementation + of the PIC 16C57, except for the following extensions:
+-
+
- Port A is full 8 bits wide +
- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded) +
- Executions of instructions that modify the PC has became a lot more expensive
+ due to the pipeline and execution of instructions on every cycle. Any instruction
+ that writes to the PC (PC as destination (f), call, goto, retlw) now takes
+ 4 cycles to execute (instead of 2 in the original implementation).
+ The 4 'skip' instructions, remain as in the original implementation: 1 cycle + if not skipped, 2 cycles if skipped.
+ - Sampling of IO ports might be off +
- Timer and watchdog might be off a few cycles +
Performance
+-
+
- Single cycle instruction execution, except as noted above for PC modifications. +
- I estimate about 22K gates with the xilinx primitives, (excluding Register + File and Program Memory). A Xilinx Vertex XCV100 can hold 4 of this cores + and program memory, and still have some room left. +
Implementing the Core
+The only file you should edit if you really want to implement this core, is + the 'primitives.v' file. It contains all parts that can be optimized, depending + on the technology used. It includes memories, and arithmetic modules. I added + a primitives_xilinx,v file and xilinx_primitives.zip which contain primitives + for xilinx.
+ +Status
+First version of the core is released. Included with the release is also a + small test bench and several test programs written in assembly. MPLAB from Microchip, + can be used to compile and develop additional code.
+The core can be downloaded from OpenCores CVS via cvsweb + or via cvsget (use minirisc for module name) +
+Development Tools
+A very nice(and free) development environment with a software simulator is + provided by Microchip on their web site. This environment works only on PCs. + Various free and chimerical tools are available from third party, just Search + the web !
+Here is a link + to the Microchip Development environment (http://www.microchip.com/10/Tools/PICmicro/DevEnv/)
+To-Do
+Things that need to be done
+-
+
- Write more test/compliance test vectors
+
-
+
- Verify that all instructions after a goto/call/retlw/write to PCL are + not executed +
- Verify ALU +
- Timer and Watchdog tests +
+ - Perhaps some other areas ? +
- Extensions ?
+
-
+
- guess this is on a "as needed" basis +
- Would be nice to extend the register file and have a few registers that + are shared between two or more of this cores in a MP implementation ! +
+
-
+
Author / Maintainer
+I have been doing ASIC design, verification and synthesis for over 15 years. + This core is only a "midnight hack", and should be used with caution. I'd also + like to know if anyone will actually use this core. Please send me a note if + you will !
+Rudolf Usselmann rudi@asics.ws_NOSPAM
+Feel free to send me comments, suggestions and bug reports.
+Change Log
+6/18/200 RU
+ - Added this Change Log
+ - Added "Development Tools" Section|
+ - Removed speed claims from the "Performance" Section: Need to re-synthsise
+ the core and resolve synthesis tool/backend tool issues.
+ - added "risc_core_top.v", a top level with tri-state buffers and
+ program memory, to make it look like a real PIC !
+ - Updated the primitives_xilinx.v so it will work correctly with Synplify and
+ Synopsys FPGA compiler