OpenCores
URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

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    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/trunk/impl/Xilinx/log/map.rtf
0,0 → 1,143
{\rtf1\ansi\ansicpg1252\deff0\deflang1036{\fonttbl {\f0\fnil\fcharset0 Courier New;}}
{\colortbl ;\red255\green0\blue0;}
\uc1\pard\ulnone\f0\fs20 Release 3.1i - Par D.19\par
\par
Sat May 04 18:33:07 2002\par
\par
par -w -ol 2 -d 0 map.ncd uartimpl.ncd uartimpl.pcf\par
\par
\par
Constraints file: uartimpl.pcf\par
\par
Loading device database for application par from file "map.ncd".\par
"uartimpl" is an NCD, version 2.32, device xcs10, package tq144, speed -3\par
Loading device for application par from file '4005e.nph' in environment\par
C:/Fndtn.\par
Device speed data version: x1_0.14.2.2 1.7 PRELIMINARY.\par
\par
\par
\cf1 Device utilization summary:\par
\par
Number of External IOBs 28 out of 112 25%\par
Flops: 0\par
Latches: 0\par
Number of IOBs driving Global Buffers 2 out of 8 25%\par
\par
Number of CLBs 44 out of 196 22%\par
Total CLB Flops: 63 out of 392 16%\par
4 input LUTs: 63 out of 392 16%\par
3 input LUTs: 20 out of 196 10%\par
\par
Number of PRI-CLKs 2 out of 4 50%\cf0\par
\par
\par
\par
Overall effort level (-ol): 2 (set by user)\par
Placer effort level (-pl): 2 (set by user)\par
Placer cost table entry (-t): 1\par
Router effort level (-rl): 2 (set by user)\par
\par
Starting initial Placement phase. REAL time: 0 secs \par
Finished initial Placement phase. REAL time: 0 secs \par
\par
Starting Constructive Placer. REAL time: 0 secs \par
Placer score = 68880\par
Placer score = 44100\par
Placer score = 35940\par
Placer score = 32580\par
Placer score = 28320\par
Placer score = 27540\par
Placer score = 26760\par
Placer score = 25740\par
Placer score = 25080\par
Placer score = 25020\par
Placer score = 24840\par
Placer score = 24600\par
Placer score = 24180\par
Placer score = 24060\par
Finished Constructive Placer. REAL time: 2 secs \par
\par
Writing design to file "uartimpl.ncd".\par
\par
Starting Optimizing Placer. REAL time: 2 secs \par
Optimizing \par
Swapped 26 comps.\par
Xilinx Placer [1] 22320 REAL time: 2 secs \par
\par
Finished Optimizing Placer. REAL time: 2 secs \par
\par
Writing design to file "uartimpl.ncd".\par
\par
Total REAL time to Placer completion: 2 secs \par
Total CPU time to Placer completion: 2 secs \par
\par
0 connection(s) routed; 315 unrouted active, 3 unrouted PWR/GND.\par
Starting router resource preassignment\par
Completed router resource preassignment. REAL time: 2 secs \par
Starting iterative routing. \par
Routing active signals.\par
End of iteration 1 \par
315 successful; 0 unrouted active,\par
3 unrouted PWR/GND; (0) REAL time: 3 secs \par
End of iteration 2 \par
315 successful; 0 unrouted active,\par
3 unrouted PWR/GND; (0) REAL time: 3 secs \par
Constraints are met. \par
Routing PWR/GND nets.\par
Power and ground nets completely routed. \par
Writing design to file "uartimpl.ncd".\par
Starting cleanup \par
Improving routing.\par
End of cleanup iteration 1 \par
318 successful; 0 unrouted; (0) REAL time: 4 secs \par
Writing design to file "uartimpl.ncd".\par
Total REAL time: 4 secs \par
Total CPU time: 4 secs \par
End of route. 318 routed (100.00%); 0 unrouted.\par
No errors found. \par
Completely routed. \par
\par
This design was run without timing constraints. It is likely that much better\par
circuit performance can be obtained by trying either or both of the following:\par
\par
- Enabling the Delay Based Cleanup router pass, if not already enabled\par
- Supplying timing constraints in the input design\par
\par
\par
Total REAL time to Router completion: 4 secs \par
Total CPU time to Router completion: 4 secs \par
\par
Generating PAR statistics.\par
\par
The Delay Summary Report\par
\par
The Score for this design is: 306\par
\par
\par
The Number of signals not completely routed for this design is: 0\par
\par
The Average Connection Delay for this design is: 2.041 ns\par
The Maximum Pin Delay is: 9.391 ns\par
The Average Connection Delay on the 10 Worst Nets is: 5.097 ns\par
\par
Listing Pin Delays by value: (ns)\par
\par
d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 10.00 d >= 10.00\par
--------- --------- --------- --------- --------- ---------\par
202 89 25 0 2 0\par
\par
Writing design to file "uartimpl.ncd".\par
\par
\par
All signals are completely routed.\par
\par
Total REAL time to PAR completion: 4 secs \par
Total CPU time to PAR completion: 5 secs \par
\par
Placement: Completed - No errors found.\par
Routing: Completed - No errors found.\par
\par
PAR done.\par
\par
}
/trunk/impl/Xilinx/log/par.rtf
0,0 → 1,250
{\rtf1\ansi\ansicpg1252\deff0\deflang1036{\fonttbl {\f0\fnil\fcharset0 Courier New;}}
{\colortbl ;\red255\green0\blue0;}
\uc1\pard\ulnone\f0\fs20\par
Xilinx Mapping Report File for Design 'uartimpl'\par
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.\par
\par
Design Information\par
------------------\par
Command Line : m1map -p xcs10-3-tq144 -o map.ncd uartimpl.ngd uartimpl.pcf \par
Target Device : xs10\par
Target Package : tq144\par
Target Speed : -3\par
Mapper Version : spartan -- D.19\par
\par
\cf1 Design Summary\par
--------------\par
Number of errors: 0\par
Number of warnings: 1\par
Number of CLBs: 44 out of 196 22%\par
CLB Flip Flops: 63\par
4 input LUTs: 63\par
3 input LUTs: 20 (17 used as route-throughs)\par
Number of bonded IOBs: 28 out of 111 25%\par
IOB Flops: 0\par
IOB Latches: 0\par
Number of clock IOB pads: 2 out of 8 25%\par
Number of primary CLKs: 2 out of 4 50%\par
Total equivalent gate count for design: 769\par
Additional JTAG gate count for IOBs: 1344\cf0\par
\par
Table of Contents\par
-----------------\par
Section 1 - Errors\par
Section 2 - Warnings\par
Section 3 - Design Attributes\par
Section 4 - Removed Logic Summary\par
Section 5 - Removed Logic\par
Section 6 - Added Logic\par
Section 7 - Expanded Logic\par
Section 8 - Signal Cross-Reference\par
Section 9 - Symbol Cross-Reference\par
Section 10 - IOB Properties\par
Section 11 - RPMs\par
Section 12 - Guide Report\par
Section 13 - Area Group Summary\par
\par
Section 1 - Errors\par
------------------\par
\par
Section 2 - Warnings\par
--------------------\par
WARNING:OldMap:78 - All of the external outputs in this design are using\par
slew-rate-limited output drivers. The delay on speed critical outputs can be\par
dramatically reduced by designating them as fast outputs in the original\par
design. Please see your vendor interface documentation for specific\par
information on how to do this within your design-entry tool.\par
Note: You should be careful not to designate too many outputs which switch\par
together as fast, because this can cause excessive ground bounce. For more\par
information on this subject, please refer to the IOB switching characteristic\par
guidelines for the device you are using in the Programmable Logic Data Book.\par
\par
Section 3 - Design Attributes\par
-----------------------------\par
\par
Section 4 - Removed Logic Summary\par
---------------------------------\par
58 block(s) removed\par
13 block(s) optimized away\par
58 signal(s) removed\par
\par
Section 5 - Removed Logic\par
-------------------------\par
\par
The trimmed logic reported below is either:\par
1. part of a cycle\par
2. part of disabled logic\par
3. a side-effect of other trimmed logic\par
\par
The signal "U1/N255" is unused and has been removed.\par
Unused block "U1/C576" (GND) removed.\par
The signal "U1/N256" is unused and has been removed.\par
Unused block "U1/C577" (GND) removed.\par
The signal "U1/N257" is unused and has been removed.\par
Unused block "U1/C578" (GND) removed.\par
The signal "U1/N258" is unused and has been removed.\par
Unused block "U1/C579" (GND) removed.\par
The signal "U1/N259" is unused and has been removed.\par
Unused block "U1/C580" (GND) removed.\par
The signal "U1/N260" is unused and has been removed.\par
Unused block "U1/C581" (GND) removed.\par
The signal "U1/N261" is unused and has been removed.\par
Unused block "U1/C582" (GND) removed.\par
The signal "U1/N262" is unused and has been removed.\par
Unused block "U1/C583" (GND) removed.\par
The signal "U1/N263" is unused and has been removed.\par
Unused block "U1/C584" (GND) removed.\par
The signal "U1/N264" is unused and has been removed.\par
Unused block "U1/C585" (GND) removed.\par
The signal "U1/N265" is unused and has been removed.\par
Unused block "U1/C586" (GND) removed.\par
The signal "U1/N266" is unused and has been removed.\par
Unused block "U1/C587" (GND) removed.\par
The signal "U1/N267" is unused and has been removed.\par
Unused block "U1/C588" (GND) removed.\par
The signal "U1/N268" is unused and has been removed.\par
Unused block "U1/C589" (GND) removed.\par
The signal "U1/N269" is unused and has been removed.\par
Unused block "U1/C590" (GND) removed.\par
The signal "U1/N270" is unused and has been removed.\par
Unused block "U1/C591" (GND) removed.\par
The signal "U1/N271" is unused and has been removed.\par
Unused block "U1/C592" (GND) removed.\par
The signal "U1/N272" is unused and has been removed.\par
Unused block "U1/C593" (GND) removed.\par
The signal "U1/N273" is unused and has been removed.\par
Unused block "U1/C594" (GND) removed.\par
The signal "U1/N274" is unused and has been removed.\par
Unused block "U1/C595" (GND) removed.\par
The signal "U1/N275" is unused and has been removed.\par
Unused block "U1/C596" (GND) removed.\par
The signal "U1/N276" is unused and has been removed.\par
Unused block "U1/C597" (GND) removed.\par
The signal "U1/N277" is unused and has been removed.\par
Unused block "U1/C598" (GND) removed.\par
The signal "U1/N278" is unused and has been removed.\par
Unused block "U1/C599" (GND) removed.\par
The signal "U1/N279" is unused and has been removed.\par
Unused block "U1/C600" (GND) removed.\par
The signal "U1/N280" is unused and has been removed.\par
Unused block "U1/C601" (GND) removed.\par
The signal "U1/N281" is unused and has been removed.\par
Unused block "U1/C602" (GND) removed.\par
The signal "U1/N282" is unused and has been removed.\par
Unused block "U1/C603" (GND) removed.\par
The signal "U1/N283" is unused and has been removed.\par
Unused block "U1/C604" (GND) removed.\par
The signal "U1/N284" is unused and has been removed.\par
Unused block "U1/C605" (GND) removed.\par
The signal "U1/N285" is unused and has been removed.\par
Unused block "U1/C606" (GND) removed.\par
The signal "U1/N286" is unused and has been removed.\par
Unused block "U1/C607" (GND) removed.\par
The signal "U1/N287" is unused and has been removed.\par
Unused block "U1/C608" (GND) removed.\par
The signal "U1/N288" is unused and has been removed.\par
Unused block "U1/C609" (GND) removed.\par
The signal "U1/N289" is unused and has been removed.\par
Unused block "U1/C610" (GND) removed.\par
The signal "U1/N290" is unused and has been removed.\par
Unused block "U1/C611" (GND) removed.\par
The signal "U1/N291" is unused and has been removed.\par
Unused block "U1/C612" (GND) removed.\par
The signal "U1/N292" is unused and has been removed.\par
Unused block "U1/C613" (GND) removed.\par
The signal "U1/N293" is unused and has been removed.\par
Unused block "U1/C614" (GND) removed.\par
The signal "U1/N294" is unused and has been removed.\par
Unused block "U1/C615" (GND) removed.\par
The signal "U1/N295" is unused and has been removed.\par
Unused block "U1/C616" (GND) removed.\par
The signal "U1/N296" is unused and has been removed.\par
Unused block "U1/C617" (GND) removed.\par
The signal "U1/N297" is unused and has been removed.\par
Unused block "U1/C618" (GND) removed.\par
The signal "U1/N298" is unused and has been removed.\par
Unused block "U1/C619" (GND) removed.\par
The signal "U1/N299" is unused and has been removed.\par
Unused block "U1/C620" (GND) removed.\par
The signal "U1/N300" is unused and has been removed.\par
Unused block "U1/C621" (GND) removed.\par
The signal "U1/N301" is unused and has been removed.\par
Unused block "U1/C622" (GND) removed.\par
The signal "U1/N302" is unused and has been removed.\par
Unused block "U1/C623" (GND) removed.\par
The signal "U1/N303" is unused and has been removed.\par
Unused block "U1/C624" (GND) removed.\par
The signal "U1/N304" is unused and has been removed.\par
Unused block "U1/C625" (GND) removed.\par
The signal "U1/N305" is unused and has been removed.\par
Unused block "U1/C626" (GND) removed.\par
The signal "U1/N306" is unused and has been removed.\par
Unused block "U1/C627" (GND) removed.\par
The signal "U1/N307" is unused and has been removed.\par
Unused block "U1/C628" (GND) removed.\par
The signal "U1/N308" is unused and has been removed.\par
Unused block "U1/C629" (GND) removed.\par
The signal "U1/N309" is unused and has been removed.\par
Unused block "U1/C630" (GND) removed.\par
The signal "U1/N310" is unused and has been removed.\par
Unused block "U1/C631" (GND) removed.\par
The signal "U1/N311" is unused and has been removed.\par
Unused block "U1/C632" (GND) removed.\par
The signal "U1/N312" is unused and has been removed.\par
Unused block "U1/C633" (GND) removed.\par
\par
Optimized Block(s):\par
TYPE \tab\tab BLOCK\par
vcc \tab\tab U1/LoadA_reg/$1I37\par
vcc \tab\tab U1/ReadA_reg/$1I37\par
vcc \tab\tab U1/Uart_Rxrate/Cnt_reg/$1I37\par
vcc \tab\tab U1/Uart_Rxrate/O_reg/$1I37\par
vcc \tab\tab U1/Uart_RxUnit/RxAv_reg/$1I37\par
vcc \tab\tab U1/Uart_Txrate/O_reg/$1I37\par
vcc \tab\tab U1/Uart_TxUnit/SyncLoad/C1A_reg/$1I37\par
vcc \tab\tab U1/Uart_TxUnit/SyncLoad/C1S_reg/$1I37\par
vcc \tab\tab U1/Uart_TxUnit/SyncLoad/R_reg/$1I37\par
fdce \tab\tab U1/Uart_Rxrate/Cnt_reg/I$1\par
GND \tab\tab U1/C575\par
INV \tab\tab U1/C515\par
VCC \tab\tab U1/C574\par
\par
Section 6 - Added Logic\par
-----------------------\par
\par
Section 7 - Expanded Logic\par
--------------------------\par
To enable this section, set the detailed map report option and rerun map.\par
\par
Section 8 - Signal Cross-Reference\par
----------------------------------\par
To enable this section, set the detailed map report option and rerun map.\par
\par
Section 9 - Symbol Cross-Reference\par
----------------------------------\par
To enable this section, set the detailed map report option and rerun map.\par
\par
Section 10 - IOB Properties\par
---------------------------\par
"$Net00010_" (IOB) : SLEW=SLOW\par
"$Net00011_" (IOB) : SLEW=SLOW\par
"$Net00012_" (IOB) : SLEW=SLOW\par
"$Net00013_" (IOB) : SLEW=SLOW\par
"&__A__10" (IOB) : SLEW=SLOW\par
"&__A__11" (IOB) : SLEW=SLOW\par
"&__A__12" (IOB) : SLEW=SLOW\par
"&__A__13" (IOB) : SLEW=SLOW\par
"&__A__14" (IOB) : SLEW=SLOW\par
"&__A__15" (IOB) : SLEW=SLOW\par
"&__A__16" (IOB) : SLEW=SLOW\par
"&__A__9" (IOB) : SLEW=SLOW\par
\par
Section 11 - RPMs\par
-----------------\par
\par
Section 12 - Guide Report\par
-------------------------\par
Guide not run on this design.\par
\par
}
/trunk/impl/Xilinx/out/miniuart.edf
0,0 → 1,16524
(edif UART
(edifVersion 2 0 0)
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(author "Test")
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(direction INPUT)
)
(port
(rename WB_DAT_I_3 "WB_DAT_I<3>")
(direction INPUT)
)
(port
(rename WB_DAT_I_2 "WB_DAT_I<2>")
(direction INPUT)
)
(port
(rename WB_DAT_I_1 "WB_DAT_I<1>")
(direction INPUT)
)
(port
(rename WB_DAT_I_0 "WB_DAT_I<0>")
(direction INPUT)
)
(port
(rename WB_DAT_O_7 "WB_DAT_O<7>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_6 "WB_DAT_O<6>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_5 "WB_DAT_O<5>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_4 "WB_DAT_O<4>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_3 "WB_DAT_O<3>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_2 "WB_DAT_O<2>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_1 "WB_DAT_O<1>")
(direction OUTPUT)
)
(port
(rename WB_DAT_O_0 "WB_DAT_O<0>")
(direction OUTPUT)
)
(port WB_WE_I
(direction INPUT)
)
(port WB_STB_I
(direction INPUT)
)
(port WB_ACK_O
(direction OUTPUT)
)
(port IntTx_O
(direction OUTPUT)
)
(port IntRx_O
(direction OUTPUT)
)
(port BR_Clk_I
(direction INPUT)
)
(port TxD_PAD_O
(direction OUTPUT)
)
(port RxD_PAD_I
(direction INPUT)
)
)
(contents
(instance
(rename Uart_Rxrate_C126_C0_C1 "Uart_Rxrate/C126/C0/C1")
(viewRef Netlist_representation
(cellRef CY4
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "dec_rpl_8_33_0")
)
(property RLOC
(string "R0C0")
)
)
(instance
(rename Uart_Rxrate_C126_C0_C2 "Uart_Rxrate/C126/C0/C2")
(viewRef Netlist_representation
(cellRef CY4_27
(libraryRef SPARTAN)
)
)
(property CYMODE
(string "DEC-G-0")
)
)
(instance
(rename Uart_Rxrate_C126_C1_C2 "Uart_Rxrate/C126/C1/C2")
(viewRef Netlist_representation
(cellRef CY4
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "dec_rpl_8_33_1")
)
(property RLOC
(string "R0C0")
)
)
(instance
(rename Uart_Rxrate_C126_C1_C3 "Uart_Rxrate/C126/C1/C3")
(viewRef Netlist_representation
(cellRef CY4_25
(libraryRef SPARTAN)
)
)
(property CYMODE
(string "DEC-FG-CI")
)
)
(instance
(rename Uart_Rxrate_C126_C2_C2 "Uart_Rxrate/C126/C2/C2")
(viewRef Netlist_representation
(cellRef CY4
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "dec_rpl_8_33_2")
)
(property RLOC
(string "R0C0")
)
)
(instance
(rename Uart_Rxrate_C126_C2_C3 "Uart_Rxrate/C126/C2/C3")
(viewRef Netlist_representation
(cellRef CY4_25
(libraryRef SPARTAN)
)
)
(property CYMODE
(string "DEC-FG-CI")
)
)
(instance
(rename Uart_Rxrate_C126_C3_C2 "Uart_Rxrate/C126/C3/C2")
(viewRef Netlist_representation
(cellRef CY4
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "dec_rpl_8_33_3")
)
(property RLOC
(string "R0C0")
)
)
(instance
(rename Uart_Rxrate_C126_C3_C3 "Uart_Rxrate/C126/C3/C3")
(viewRef Netlist_representation
(cellRef CY4_25
(libraryRef SPARTAN)
)
)
(property CYMODE
(string "DEC-FG-CI")
)
)
(instance ReadA_reg
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance LoadA_reg
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_0 "TxData_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_1 "TxData_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_2 "TxData_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_3 "TxData_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_4 "TxData_reg<4>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_5 "TxData_reg<5>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_6 "TxData_reg<6>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename TxData_reg_7 "TxData_reg<7>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_0 "Uart_Rxrate/Cnt_reg<0>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "dec_rpl_8_33_0")
)
(property RLOC
(string "R0C0.FFY")
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_4 "Uart_Rxrate/Cnt_reg<4>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_O_reg "Uart_Rxrate/O_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_6 "Uart_Rxrate/Cnt_reg<6>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_2 "Uart_Rxrate/Cnt_reg<2>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_3 "Uart_Rxrate/Cnt_reg<3>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_7 "Uart_Rxrate/Cnt_reg<7>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_5 "Uart_Rxrate/Cnt_reg<5>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Rxrate_Cnt_reg_1 "Uart_Rxrate/Cnt_reg<1>")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Txrate_O_reg "Uart_Txrate/O_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Txrate_Cnt_reg_1 "Uart_Txrate/Cnt_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_Txrate_Cnt_reg_0 "Uart_Txrate/Cnt_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TxD_reg "Uart_TxUnit/TxD_reg")
(viewRef Netlist_representation
(cellRef FDPE
(libraryRef SPARTAN)
)
)
(property INIT
(string "S")
)
)
(instance
(rename Uart_TxUnit_TBufL_reg "Uart_TxUnit/TBufL_reg")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_0 "Uart_TxUnit/TReg_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_1 "Uart_TxUnit/TReg_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_2 "Uart_TxUnit/TReg_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_3 "Uart_TxUnit/TReg_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_4 "Uart_TxUnit/TReg_reg<4>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_5 "Uart_TxUnit/TReg_reg<5>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_6 "Uart_TxUnit/TReg_reg<6>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TReg_reg_7 "Uart_TxUnit/TReg_reg<7>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_0 "Uart_TxUnit/TBuff_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_1 "Uart_TxUnit/TBuff_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_2 "Uart_TxUnit/TBuff_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_3 "Uart_TxUnit/TBuff_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_4 "Uart_TxUnit/TBuff_reg<4>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_5 "Uart_TxUnit/TBuff_reg<5>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_6 "Uart_TxUnit/TBuff_reg<6>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_TBuff_reg_7 "Uart_TxUnit/TBuff_reg<7>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_BitPos_reg_3 "Uart_TxUnit/BitPos_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_BitPos_reg_2 "Uart_TxUnit/BitPos_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_BitPos_reg_1 "Uart_TxUnit/BitPos_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_BitPos_reg_0 "Uart_TxUnit/BitPos_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RRegL_reg "Uart_RxUnit/RRegL_reg")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RxAv_reg "Uart_RxUnit/RxAv_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_0 "Uart_RxUnit/RReg_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_1 "Uart_RxUnit/RReg_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_2 "Uart_RxUnit/RReg_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_3 "Uart_RxUnit/RReg_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_4 "Uart_RxUnit/RReg_reg<4>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_5 "Uart_RxUnit/RReg_reg<5>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_6 "Uart_RxUnit/RReg_reg<6>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_RReg_reg_7 "Uart_RxUnit/RReg_reg<7>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_0 "Uart_RxUnit/DataO_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_1 "Uart_RxUnit/DataO_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_2 "Uart_RxUnit/DataO_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_3 "Uart_RxUnit/DataO_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_4 "Uart_RxUnit/DataO_reg<4>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_5 "Uart_RxUnit/DataO_reg<5>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_6 "Uart_RxUnit/DataO_reg<6>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_DataO_reg_7 "Uart_RxUnit/DataO_reg<7>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_SampleCnt_reg_1 "Uart_RxUnit/SampleCnt_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_SampleCnt_reg_0 "Uart_RxUnit/SampleCnt_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_BitPos_reg_3 "Uart_RxUnit/BitPos_reg<3>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_BitPos_reg_2 "Uart_RxUnit/BitPos_reg<2>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_BitPos_reg_1 "Uart_RxUnit/BitPos_reg<1>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_RxUnit_BitPos_reg_0 "Uart_RxUnit/BitPos_reg<0>")
(viewRef Netlist_representation
(cellRef FDCE
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_SyncLoad_C1S_reg "Uart_TxUnit/SyncLoad/C1S_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_SyncLoad_R_reg "Uart_TxUnit/SyncLoad/R_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance
(rename Uart_TxUnit_SyncLoad_C1A_reg "Uart_TxUnit/SyncLoad/C1A_reg")
(viewRef Netlist_representation
(cellRef FDC
(libraryRef SPARTAN)
)
)
)
(instance C538
(viewRef Netlist_representation
(cellRef CY4
(libraryRef SPARTAN)
)
)
(property HU_SET
(string "UART_5")
)
(property RLOC
(string "R0C0")
)
)
(instance C539
(viewRef Netlist_representation
(cellRef CY4_42
(libraryRef SPARTAN)
)
)
(property CYMODE
(string "EXAMINE-CI")
)
)
(instance C540
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C541
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C604
(viewRef Netlist_representation
(cellRef VCC
(libraryRef SPARTAN)
)
)
)
(instance C605
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C606
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C607
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C608
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C609
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C610
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C611
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C612
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C613
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C614
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C615
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C616
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C617
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C618
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C619
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C620
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C621
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C622
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C623
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C624
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C625
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C626
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C627
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C628
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C629
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C630
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C631
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C632
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C633
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C634
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C635
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C636
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C637
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C638
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C639
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C640
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C641
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C642
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C643
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
(instance C644
(viewRef Netlist_representation
(cellRef GND
(libraryRef SPARTAN)
)
)
)
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(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C674
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C675
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C676
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C677
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C678
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C679
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C680
(viewRef Netlist_representation
(cellRef AND4
(libraryRef SPARTAN)
)
)
)
(instance C681
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C682
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C683
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C684
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C685
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C686
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C687
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C688
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C689
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C690
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C691
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C692
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C693
(viewRef Netlist_representation
(cellRef AND3
(libraryRef SPARTAN)
)
)
)
(instance C694
(viewRef Netlist_representation
(cellRef AND3
(libraryRef SPARTAN)
)
)
)
(instance C695
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C696
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C697
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C698
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C699
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C700
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C701
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C702
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C703
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C704
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C705
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C706
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C707
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C708
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C709
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C710
(viewRef Netlist_representation
(cellRef AND3
(libraryRef SPARTAN)
)
)
)
(instance C711
(viewRef Netlist_representation
(cellRef AND3
(libraryRef SPARTAN)
)
)
)
(instance C712
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C713
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C714
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C715
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C716
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C717
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C718
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C719
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C720
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C721
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C722
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C723
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C724
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C725
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C726
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C727
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C728
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C729
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C730
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C731
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C732
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C733
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C734
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C735
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C736
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C737
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C738
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C739
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C740
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C741
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(instance C742
(viewRef Netlist_representation
(cellRef FMAP
(libraryRef SPARTAN)
)
)
)
(instance C743
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C744
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C745
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C746
(viewRef Netlist_representation
(cellRef INV
(libraryRef SPARTAN)
)
)
)
(instance C747
(viewRef Netlist_representation
(cellRef BUF
(libraryRef SPARTAN)
)
)
)
(instance C748
(viewRef Netlist_representation
(cellRef AND2
(libraryRef SPARTAN)
)
)
)
(net WB_CLK_I
(joined
(portRef WB_CLK_I)
(portRef C
(instanceRef ReadA_reg)
)
(portRef C
(instanceRef LoadA_reg)
)
(portRef C
(instanceRef TxData_reg_0)
)
(portRef C
(instanceRef TxData_reg_1)
)
(portRef C
(instanceRef TxData_reg_2)
)
(portRef C
(instanceRef TxData_reg_3)
)
(portRef C
(instanceRef TxData_reg_4)
)
(portRef C
(instanceRef TxData_reg_5)
)
(portRef C
(instanceRef TxData_reg_6)
)
(portRef C
(instanceRef TxData_reg_7)
)
)
)
(net WB_RST_I
(joined
(portRef WB_RST_I)
(portRef PRE
(instanceRef Uart_TxUnit_TxD_reg)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBufL_reg)
)
(portRef CLR
(instanceRef Uart_TxUnit_BitPos_reg_3)
)
(portRef CLR
(instanceRef Uart_TxUnit_BitPos_reg_2)
)
(portRef CLR
(instanceRef Uart_TxUnit_BitPos_reg_1)
)
(portRef CLR
(instanceRef Uart_TxUnit_BitPos_reg_0)
)
(portRef CLR
(instanceRef Uart_RxUnit_RRegL_reg)
)
(portRef CLR
(instanceRef Uart_RxUnit_BitPos_reg_3)
)
(portRef CLR
(instanceRef Uart_RxUnit_BitPos_reg_2)
)
(portRef CLR
(instanceRef Uart_RxUnit_BitPos_reg_1)
)
(portRef CLR
(instanceRef Uart_RxUnit_BitPos_reg_0)
)
(portRef I1
(instanceRef C302)
)
(portRef I
(instanceRef C305)
)
(portRef I1
(instanceRef C334)
)
(portRef I
(instanceRef C339)
)
(portRef I2
(instanceRef C408)
)
(portRef I
(instanceRef C411)
)
(portRef I2
(instanceRef C414)
)
(portRef I
(instanceRef C418)
)
(portRef I3
(instanceRef C576)
)
(portRef I
(instanceRef C579)
)
(portRef I3
(instanceRef C582)
)
(portRef I
(instanceRef C586)
)
)
)
(net
(rename WB_ADR_I_1 "WB_ADR_I<1>")
(joined
(portRef WB_ADR_I_1)
(portRef I1
(instanceRef C685)
)
(portRef I
(instanceRef C689)
)
(portRef I
(instanceRef C691)
)
(portRef I1
(instanceRef C702)
)
(portRef I
(instanceRef C706)
)
(portRef I
(instanceRef C708)
)
(portRef I1
(instanceRef C742)
)
(portRef I
(instanceRef C745)
)
)
)
(net
(rename WB_ADR_I_0 "WB_ADR_I<0>")
(joined
(portRef WB_ADR_I_0)
(portRef I2
(instanceRef C685)
)
(portRef I
(instanceRef C690)
)
(portRef I1
(instanceRef C694)
)
(portRef I2
(instanceRef C702)
)
(portRef I
(instanceRef C707)
)
(portRef I1
(instanceRef C711)
)
(portRef I2
(instanceRef C742)
)
(portRef I
(instanceRef C746)
)
)
)
(net
(rename WB_DAT_I_7 "WB_DAT_I<7>")
(joined
(portRef WB_DAT_I_7)
(portRef D
(instanceRef TxData_reg_7)
)
)
)
(net
(rename WB_DAT_I_6 "WB_DAT_I<6>")
(joined
(portRef WB_DAT_I_6)
(portRef D
(instanceRef TxData_reg_6)
)
)
)
(net
(rename WB_DAT_I_5 "WB_DAT_I<5>")
(joined
(portRef WB_DAT_I_5)
(portRef D
(instanceRef TxData_reg_5)
)
)
)
(net
(rename WB_DAT_I_4 "WB_DAT_I<4>")
(joined
(portRef WB_DAT_I_4)
(portRef D
(instanceRef TxData_reg_4)
)
)
)
(net
(rename WB_DAT_I_3 "WB_DAT_I<3>")
(joined
(portRef WB_DAT_I_3)
(portRef D
(instanceRef TxData_reg_3)
)
)
)
(net
(rename WB_DAT_I_2 "WB_DAT_I<2>")
(joined
(portRef WB_DAT_I_2)
(portRef D
(instanceRef TxData_reg_2)
)
)
)
(net
(rename WB_DAT_I_1 "WB_DAT_I<1>")
(joined
(portRef WB_DAT_I_1)
(portRef D
(instanceRef TxData_reg_1)
)
)
)
(net
(rename WB_DAT_I_0 "WB_DAT_I<0>")
(joined
(portRef WB_DAT_I_0)
(portRef D
(instanceRef TxData_reg_0)
)
)
)
(net WB_WE_I
(joined
(portRef WB_WE_I)
(portRef I2
(instanceRef C576)
)
(portRef I1
(instanceRef C581)
)
(portRef I2
(instanceRef C582)
)
(portRef I
(instanceRef C585)
)
)
)
(net WB_STB_I
(joined
(portRef WB_STB_I)
(portRef WB_ACK_O)
(portRef I1
(instanceRef C576)
)
(portRef I0
(instanceRef C581)
)
(portRef I1
(instanceRef C582)
)
(portRef I0
(instanceRef C588)
)
)
)
(net IntRx_O
(joined
(portRef IntRx_O)
(portRef Q
(instanceRef Uart_RxUnit_RxAv_reg)
)
(portRef I4
(instanceRef C702)
)
(portRef I2
(instanceRef C711)
)
)
)
(net BR_Clk_I
(joined
(portRef BR_Clk_I)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_0)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_4)
)
(portRef C
(instanceRef Uart_Rxrate_O_reg)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_6)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_2)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_3)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_7)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_5)
)
(portRef C
(instanceRef Uart_Rxrate_Cnt_reg_1)
)
(portRef C
(instanceRef Uart_Txrate_O_reg)
)
(portRef C
(instanceRef Uart_Txrate_Cnt_reg_1)
)
(portRef C
(instanceRef Uart_Txrate_Cnt_reg_0)
)
(portRef C
(instanceRef Uart_TxUnit_TxD_reg)
)
(portRef C
(instanceRef Uart_TxUnit_TBufL_reg)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_0)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_1)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_2)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_3)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_4)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_5)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_6)
)
(portRef C
(instanceRef Uart_TxUnit_TReg_reg_7)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_0)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_1)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_2)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_3)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_4)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_5)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_6)
)
(portRef C
(instanceRef Uart_TxUnit_TBuff_reg_7)
)
(portRef C
(instanceRef Uart_TxUnit_BitPos_reg_3)
)
(portRef C
(instanceRef Uart_TxUnit_BitPos_reg_2)
)
(portRef C
(instanceRef Uart_TxUnit_BitPos_reg_1)
)
(portRef C
(instanceRef Uart_TxUnit_BitPos_reg_0)
)
(portRef C
(instanceRef Uart_RxUnit_RRegL_reg)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_0)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_1)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_2)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_3)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_4)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_5)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_6)
)
(portRef C
(instanceRef Uart_RxUnit_RReg_reg_7)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_0)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_1)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_2)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_3)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_4)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_5)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_6)
)
(portRef C
(instanceRef Uart_RxUnit_DataO_reg_7)
)
(portRef C
(instanceRef Uart_RxUnit_SampleCnt_reg_1)
)
(portRef C
(instanceRef Uart_RxUnit_SampleCnt_reg_0)
)
(portRef C
(instanceRef Uart_RxUnit_BitPos_reg_3)
)
(portRef C
(instanceRef Uart_RxUnit_BitPos_reg_2)
)
(portRef C
(instanceRef Uart_RxUnit_BitPos_reg_1)
)
(portRef C
(instanceRef Uart_RxUnit_BitPos_reg_0)
)
(portRef C
(instanceRef Uart_TxUnit_SyncLoad_C1S_reg)
)
(portRef C
(instanceRef Uart_TxUnit_SyncLoad_R_reg)
)
)
)
(net TxD_PAD_O
(joined
(portRef TxD_PAD_O)
(portRef Q
(instanceRef Uart_TxUnit_TxD_reg)
)
)
)
(net RxD_PAD_I
(joined
(portRef RxD_PAD_I)
(portRef I2
(instanceRef C111)
)
(portRef I
(instanceRef C115)
)
(portRef I4
(instanceRef C176)
)
(portRef I
(instanceRef C182)
)
(portRef I1
(instanceRef C197)
)
(portRef I0
(instanceRef C210)
)
(portRef I1
(instanceRef C211)
)
(portRef I0
(instanceRef C221)
)
(portRef I1
(instanceRef C222)
)
(portRef I0
(instanceRef C232)
)
(portRef I1
(instanceRef C233)
)
(portRef I0
(instanceRef C243)
)
(portRef I1
(instanceRef C244)
)
(portRef I0
(instanceRef C254)
)
(portRef I1
(instanceRef C261)
)
(portRef I0
(instanceRef C271)
)
(portRef I1
(instanceRef C279)
)
(portRef I0
(instanceRef C289)
)
(portRef I1
(instanceRef C308)
)
(portRef I0
(instanceRef C318)
)
)
)
(net EnabRx
(joined
(portRef Q
(instanceRef Uart_Rxrate_O_reg)
)
(portRef CE
(instanceRef Uart_Txrate_Cnt_reg_1)
)
(portRef CE
(instanceRef Uart_Txrate_Cnt_reg_0)
)
(portRef I1
(instanceRef C111)
)
(portRef I0
(instanceRef C117)
)
(portRef I0
(instanceRef C118)
)
(portRef I2
(instanceRef C302)
)
(portRef I1
(instanceRef C307)
)
(portRef I1
(instanceRef C341)
)
(portRef I0
(instanceRef C345)
)
(portRef I3
(instanceRef C561)
)
(portRef I2
(instanceRef C567)
)
)
)
(net
(rename RxData_0 "RxData<0>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_0)
)
(portRef I3
(instanceRef C685)
)
(portRef I2
(instanceRef C693)
)
)
)
(net
(rename RxData_1 "RxData<1>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_1)
)
(portRef I3
(instanceRef C702)
)
(portRef I2
(instanceRef C710)
)
)
)
(net
(rename RxData_2 "RxData<2>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_2)
)
(portRef I2
(instanceRef C712)
)
(portRef I1
(instanceRef C716)
)
)
)
(net
(rename RxData_3 "RxData<3>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_3)
)
(portRef I2
(instanceRef C717)
)
(portRef I1
(instanceRef C721)
)
)
)
(net
(rename RxData_4 "RxData<4>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_4)
)
(portRef I2
(instanceRef C722)
)
(portRef I1
(instanceRef C726)
)
)
)
(net
(rename RxData_5 "RxData<5>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_5)
)
(portRef I2
(instanceRef C727)
)
(portRef I1
(instanceRef C731)
)
)
)
(net
(rename RxData_6 "RxData<6>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_6)
)
(portRef I2
(instanceRef C732)
)
(portRef I1
(instanceRef C736)
)
)
)
(net
(rename RxData_7 "RxData<7>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_DataO_reg_7)
)
(portRef I2
(instanceRef C737)
)
(portRef I1
(instanceRef C741)
)
)
)
(net EnabTx
(joined
(portRef Q
(instanceRef Uart_Txrate_O_reg)
)
(portRef CE
(instanceRef Uart_TxUnit_TxD_reg)
)
(portRef I3
(instanceRef C384)
)
(portRef I1
(instanceRef C390)
)
(portRef I1
(instanceRef C391)
)
(portRef I0
(instanceRef C392)
)
(portRef I3
(instanceRef C429)
)
(portRef I
(instanceRef C436)
)
)
)
(net LoadA
(joined
(portRef Q
(instanceRef LoadA_reg)
)
(portRef C
(instanceRef Uart_TxUnit_SyncLoad_C1A_reg)
)
)
)
(net
(rename TxData_7 "TxData<7>")
(joined
(portRef Q
(instanceRef TxData_reg_7)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_7)
)
)
)
(net
(rename TxData_6 "TxData<6>")
(joined
(portRef Q
(instanceRef TxData_reg_6)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_6)
)
)
)
(net
(rename TxData_5 "TxData<5>")
(joined
(portRef Q
(instanceRef TxData_reg_5)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_5)
)
)
)
(net
(rename TxData_4 "TxData<4>")
(joined
(portRef Q
(instanceRef TxData_reg_4)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_4)
)
)
)
(net
(rename TxData_3 "TxData<3>")
(joined
(portRef Q
(instanceRef TxData_reg_3)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_3)
)
)
)
(net
(rename TxData_2 "TxData<2>")
(joined
(portRef Q
(instanceRef TxData_reg_2)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_2)
)
)
)
(net
(rename TxData_1 "TxData<1>")
(joined
(portRef Q
(instanceRef TxData_reg_1)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_1)
)
)
)
(net
(rename TxData_0 "TxData<0>")
(joined
(portRef Q
(instanceRef TxData_reg_0)
)
(portRef D
(instanceRef Uart_TxUnit_TBuff_reg_0)
)
)
)
(net ReadA
(joined
(portRef Q
(instanceRef ReadA_reg)
)
(portRef I2
(instanceRef C334)
)
(portRef I
(instanceRef C340)
)
)
)
(net
(rename C3_N5 "C3/N5")
(joined
(portRef D
(instanceRef ReadA_reg)
)
(portRef O
(instanceRef C582)
)
(portRef O
(instanceRef C583)
)
)
)
(net
(rename C5_N5 "C5/N5")
(joined
(portRef D
(instanceRef LoadA_reg)
)
(portRef CE
(instanceRef TxData_reg_0)
)
(portRef CE
(instanceRef TxData_reg_1)
)
(portRef CE
(instanceRef TxData_reg_2)
)
(portRef CE
(instanceRef TxData_reg_3)
)
(portRef CE
(instanceRef TxData_reg_4)
)
(portRef CE
(instanceRef TxData_reg_5)
)
(portRef CE
(instanceRef TxData_reg_6)
)
(portRef CE
(instanceRef TxData_reg_7)
)
(portRef O
(instanceRef C576)
)
(portRef O
(instanceRef C577)
)
)
)
(net
(rename C7_N4 "C7/N4")
(joined
(portRef WB_DAT_O_7)
(portRef O
(instanceRef C737)
)
(portRef O
(instanceRef C738)
)
)
)
(net
(rename C7_N11 "C7/N11")
(joined
(portRef WB_DAT_O_6)
(portRef O
(instanceRef C732)
)
(portRef O
(instanceRef C733)
)
)
)
(net
(rename C7_N17 "C7/N17")
(joined
(portRef WB_DAT_O_5)
(portRef O
(instanceRef C727)
)
(portRef O
(instanceRef C728)
)
)
)
(net
(rename C7_N23 "C7/N23")
(joined
(portRef WB_DAT_O_4)
(portRef O
(instanceRef C722)
)
(portRef O
(instanceRef C723)
)
)
)
(net
(rename C7_N29 "C7/N29")
(joined
(portRef WB_DAT_O_3)
(portRef O
(instanceRef C717)
)
(portRef O
(instanceRef C718)
)
)
)
(net
(rename C7_N35 "C7/N35")
(joined
(portRef WB_DAT_O_2)
(portRef O
(instanceRef C712)
)
(portRef O
(instanceRef C713)
)
)
)
(net
(rename C7_N45 "C7/N45")
(joined
(portRef WB_DAT_O_1)
(portRef O
(instanceRef C702)
)
(portRef O
(instanceRef C703)
)
)
)
(net
(rename C7_N52 "C7/N52")
(joined
(portRef WB_DAT_O_0)
(portRef O
(instanceRef C685)
)
(portRef O
(instanceRef C686)
)
)
)
(net
(rename Uart_Rxrate_Cnt_0 "Uart_Rxrate/Cnt<0>")
(joined
(portRef A1
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_0)
)
(portRef I1
(instanceRef C0)
)
(portRef I4
(instanceRef C0)
)
(portRef I
(instanceRef C1)
)
(portRef I
(instanceRef C5)
)
(portRef I4
(instanceRef C15)
)
(portRef I
(instanceRef C23)
)
(portRef I3
(instanceRef C24)
)
(portRef I
(instanceRef C32)
)
(portRef I4
(instanceRef C33)
)
(portRef I
(instanceRef C41)
)
(portRef I3
(instanceRef C42)
)
(portRef I
(instanceRef C50)
)
(portRef I4
(instanceRef C51)
)
(portRef I
(instanceRef C59)
)
(portRef I3
(instanceRef C60)
)
(portRef I
(instanceRef C68)
)
(portRef I4
(instanceRef C69)
)
(portRef I
(instanceRef C80)
)
(portRef I3
(instanceRef C568)
)
(portRef I
(instanceRef C573)
)
)
)
(net
(rename Uart_Rxrate_Cnt_4 "Uart_Rxrate/Cnt<4>")
(joined
(portRef A1
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_4)
)
(portRef I4
(instanceRef C42)
)
(portRef I1
(instanceRef C47)
)
(portRef I3
(instanceRef C674)
)
(portRef I
(instanceRef C683)
)
)
)
(net
(rename Uart_Rxrate_Cnt_6 "Uart_Rxrate/Cnt<6>")
(joined
(portRef A1
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_6)
)
(portRef I4
(instanceRef C60)
)
(portRef I1
(instanceRef C65)
)
(portRef I2
(instanceRef C603)
)
(portRef I
(instanceRef C673)
)
)
)
(net
(rename Uart_Rxrate_Cnt_2 "Uart_Rxrate/Cnt<2>")
(joined
(portRef A1
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_2)
)
(portRef I4
(instanceRef C24)
)
(portRef I1
(instanceRef C29)
)
(portRef I1
(instanceRef C674)
)
(portRef I
(instanceRef C681)
)
)
)
(net
(rename Uart_Rxrate_Cnt_3 "Uart_Rxrate/Cnt<3>")
(joined
(portRef A0
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_3)
)
(portRef I1
(instanceRef C33)
)
(portRef I0
(instanceRef C38)
)
(portRef I2
(instanceRef C674)
)
(portRef I
(instanceRef C682)
)
)
)
(net
(rename Uart_Rxrate_Cnt_7 "Uart_Rxrate/Cnt<7>")
(joined
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_7)
)
(portRef I1
(instanceRef C69)
)
(portRef I0
(instanceRef C76)
)
(portRef I1
(instanceRef C603)
)
(portRef I
(instanceRef C672)
)
)
)
(net
(rename Uart_Rxrate_Cnt_5 "Uart_Rxrate/Cnt<5>")
(joined
(portRef A0
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_5)
)
(portRef I1
(instanceRef C51)
)
(portRef I0
(instanceRef C56)
)
(portRef I4
(instanceRef C674)
)
(portRef I
(instanceRef C684)
)
)
)
(net
(rename Uart_Rxrate_Cnt_1 "Uart_Rxrate/Cnt<1>")
(joined
(portRef A0
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef Q
(instanceRef Uart_Rxrate_Cnt_reg_1)
)
(portRef I2
(instanceRef C0)
)
(portRef I
(instanceRef C8)
)
(portRef I1
(instanceRef C15)
)
(portRef I0
(instanceRef C20)
)
(portRef I1
(instanceRef C568)
)
(portRef I
(instanceRef C571)
)
(portRef I1
(instanceRef C589)
)
(portRef I
(instanceRef C594)
)
)
)
(net
(rename Uart_Rxrate_C64 "Uart_Rxrate/C64")
(joined
(portRef I2
(instanceRef C15)
)
(portRef I
(instanceRef C19)
)
(portRef I1
(instanceRef C24)
)
(portRef I
(instanceRef C28)
)
(portRef I2
(instanceRef C33)
)
(portRef I
(instanceRef C37)
)
(portRef I1
(instanceRef C42)
)
(portRef I
(instanceRef C46)
)
(portRef I2
(instanceRef C51)
)
(portRef I
(instanceRef C55)
)
(portRef I1
(instanceRef C60)
)
(portRef I
(instanceRef C64)
)
(portRef I2
(instanceRef C69)
)
(portRef I
(instanceRef C75)
)
(portRef O
(instanceRef C589)
)
(portRef O
(instanceRef C590)
)
)
)
(net
(rename Uart_Rxrate_C67 "Uart_Rxrate/C67")
(joined
(portRef I3
(instanceRef C0)
)
(portRef I
(instanceRef C9)
)
(portRef I2
(instanceRef C568)
)
(portRef I
(instanceRef C572)
)
(portRef I2
(instanceRef C589)
)
(portRef I
(instanceRef C595)
)
(portRef O
(instanceRef C596)
)
(portRef O
(instanceRef C597)
)
)
)
(net
(rename Uart_Txrate_C0_N3 "Uart_Txrate/C0/N3")
(joined
(portRef D
(instanceRef Uart_Txrate_O_reg)
)
(portRef O
(instanceRef C561)
)
(portRef O
(instanceRef C562)
)
)
)
(net
(rename Uart_Txrate_Cnt_1 "Uart_Txrate/Cnt<1>")
(joined
(portRef Q
(instanceRef Uart_Txrate_Cnt_reg_1)
)
(portRef I1
(instanceRef C552)
)
(portRef I
(instanceRef C556)
)
(portRef I0
(instanceRef C559)
)
(portRef I1
(instanceRef C561)
)
(portRef I
(instanceRef C564)
)
)
)
(net
(rename Uart_Txrate_Cnt_0 "Uart_Txrate/Cnt<0>")
(joined
(portRef Q
(instanceRef Uart_Txrate_Cnt_reg_0)
)
(portRef I
(instanceRef C541)
)
(portRef I2
(instanceRef C552)
)
(portRef I
(instanceRef C557)
)
(portRef I1
(instanceRef C559)
)
(portRef I2
(instanceRef C561)
)
(portRef I
(instanceRef C565)
)
)
)
(net
(rename Uart_TxUnit_LoadS "Uart_TxUnit/LoadS")
(joined
(portRef Q
(instanceRef Uart_TxUnit_SyncLoad_C1S_reg)
)
(portRef D
(instanceRef Uart_TxUnit_SyncLoad_R_reg)
)
(portRef I1
(instanceRef C408)
)
(portRef I0
(instanceRef C413)
)
(portRef I2
(instanceRef C421)
)
(portRef I
(instanceRef C427)
)
(portRef I1
(instanceRef C695)
)
(portRef I
(instanceRef C698)
)
)
)
(net
(rename Uart_TxUnit_TBufL "Uart_TxUnit/TBufL")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TBufL_reg)
)
(portRef I1
(instanceRef C384)
)
(portRef I0
(instanceRef C390)
)
(portRef I1
(instanceRef C429)
)
(portRef I
(instanceRef C435)
)
(portRef I2
(instanceRef C695)
)
(portRef I
(instanceRef C699)
)
)
)
(net
(rename Uart_TxUnit_TReg_7 "Uart_TxUnit/TReg<7>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_7)
)
(portRef I3
(instanceRef C469)
)
(portRef I1
(instanceRef C476)
)
)
)
(net
(rename Uart_TxUnit_TReg_6 "Uart_TxUnit/TReg<6>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_6)
)
(portRef I4
(instanceRef C507)
)
(portRef I1
(instanceRef C543)
)
)
)
(net
(rename Uart_TxUnit_TReg_5 "Uart_TxUnit/TReg<5>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_5)
)
(portRef I4
(instanceRef C486)
)
(portRef I2
(instanceRef C493)
)
)
)
(net
(rename Uart_TxUnit_TReg_4 "Uart_TxUnit/TReg<4>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_4)
)
(portRef I4
(instanceRef C544)
)
(portRef I2
(instanceRef C551)
)
)
)
(net
(rename Uart_TxUnit_TReg_3 "Uart_TxUnit/TReg<3>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_3)
)
(portRef I2
(instanceRef C469)
)
(portRef I1
(instanceRef C475)
)
)
)
(net
(rename Uart_TxUnit_TReg_2 "Uart_TxUnit/TReg<2>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_2)
)
(portRef I3
(instanceRef C544)
)
(portRef I2
(instanceRef C550)
)
)
)
(net
(rename Uart_TxUnit_TReg_1 "Uart_TxUnit/TReg<1>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_1)
)
(portRef I2
(instanceRef C494)
)
(portRef I
(instanceRef C500)
)
)
)
(net
(rename Uart_TxUnit_TReg_0 "Uart_TxUnit/TReg<0>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_TReg_reg_0)
)
(portRef I3
(instanceRef C507)
)
(portRef I1
(instanceRef C542)
)
)
)
(net
(rename Uart_TxUnit_BitPos_3 "Uart_TxUnit/BitPos<3>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_BitPos_reg_3)
)
(portRef I2
(instanceRef C359)
)
(portRef I
(instanceRef C366)
)
(portRef I3
(instanceRef C393)
)
(portRef I
(instanceRef C402)
)
(portRef I1
(instanceRef C404)
)
(portRef I1
(instanceRef C405)
)
(portRef I1
(instanceRef C406)
)
(portRef I2
(instanceRef C442)
)
(portRef I
(instanceRef C449)
)
(portRef I3
(instanceRef C477)
)
(portRef I2
(instanceRef C484)
)
(portRef I2
(instanceRef C507)
)
(portRef I
(instanceRef C513)
)
)
)
(net
(rename Uart_TxUnit_BitPos_2 "Uart_TxUnit/BitPos<2>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_BitPos_reg_2)
)
(portRef I3
(instanceRef C359)
)
(portRef I1
(instanceRef C371)
)
(portRef I3
(instanceRef C372)
)
(portRef I
(instanceRef C379)
)
(portRef I1
(instanceRef C381)
)
(portRef I1
(instanceRef C382)
)
(portRef I4
(instanceRef C393)
)
(portRef I
(instanceRef C401)
)
(portRef I2
(instanceRef C405)
)
(portRef I3
(instanceRef C407)
)
(portRef I3
(instanceRef C442)
)
(portRef I
(instanceRef C450)
)
(portRef I1
(instanceRef C469)
)
(portRef I
(instanceRef C473)
)
(portRef I0
(instanceRef C475)
)
(portRef I4
(instanceRef C477)
)
(portRef I2
(instanceRef C485)
)
(portRef I3
(instanceRef C486)
)
(portRef I
(instanceRef C490)
)
(portRef I1
(instanceRef C494)
)
(portRef I
(instanceRef C499)
)
(portRef I1
(instanceRef C501)
)
(portRef I
(instanceRef C504)
)
(portRef I2
(instanceRef C544)
)
(portRef I1
(instanceRef C550)
)
(portRef I1
(instanceRef C551)
)
)
)
(net
(rename Uart_TxUnit_BitPos_1 "Uart_TxUnit/BitPos<1>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_BitPos_reg_1)
)
(portRef I1
(instanceRef C359)
)
(portRef I
(instanceRef C365)
)
(portRef I
(instanceRef C367)
)
(portRef I0
(instanceRef C369)
)
(portRef I2
(instanceRef C372)
)
(portRef I
(instanceRef C378)
)
(portRef I1
(instanceRef C383)
)
(portRef I2
(instanceRef C393)
)
(portRef I
(instanceRef C400)
)
(portRef I0
(instanceRef C406)
)
(portRef I1
(instanceRef C407)
)
(portRef I1
(instanceRef C442)
)
(portRef I
(instanceRef C448)
)
(portRef I2
(instanceRef C477)
)
(portRef I
(instanceRef C481)
)
(portRef I
(instanceRef C482)
)
(portRef I2
(instanceRef C486)
)
(portRef I1
(instanceRef C492)
)
(portRef I1
(instanceRef C493)
)
(portRef I1
(instanceRef C507)
)
(portRef I
(instanceRef C512)
)
(portRef I
(instanceRef C516)
)
(portRef I0
(instanceRef C542)
)
(portRef I1
(instanceRef C544)
)
(portRef I
(instanceRef C548)
)
(portRef I0
(instanceRef C551)
)
)
)
(net
(rename Uart_TxUnit_BitPos_0 "Uart_TxUnit/BitPos<0>")
(joined
(portRef Q
(instanceRef Uart_TxUnit_BitPos_reg_0)
)
(portRef I
(instanceRef C540)
)
(portRef I4
(instanceRef C359)
)
(portRef I
(instanceRef C364)
)
(portRef I2
(instanceRef C370)
)
(portRef I2
(instanceRef C371)
)
(portRef I1
(instanceRef C372)
)
(portRef I
(instanceRef C377)
)
(portRef I0
(instanceRef C383)
)
(portRef I2
(instanceRef C384)
)
(portRef I0
(instanceRef C391)
)
(portRef I1
(instanceRef C393)
)
(portRef I
(instanceRef C399)
)
(portRef I0
(instanceRef C407)
)
(portRef I2
(instanceRef C429)
)
(portRef I
(instanceRef C439)
)
(portRef I1
(instanceRef C451)
)
(portRef I
(instanceRef C456)
)
(portRef I
(instanceRef C457)
)
(portRef I1
(instanceRef C477)
)
(portRef I0
(instanceRef C484)
)
(portRef I0
(instanceRef C485)
)
(portRef I1
(instanceRef C486)
)
(portRef I0
(instanceRef C492)
)
(portRef I0
(instanceRef C493)
)
)
)
(net
(rename Uart_TxUnit_C17_N9 "Uart_TxUnit/C17/N9")
(joined
(portRef D
(instanceRef Uart_TxUnit_TxD_reg)
)
(portRef O
(instanceRef C451)
)
(portRef O
(instanceRef C452)
)
)
)
(net
(rename Uart_TxUnit_C11_N6 "Uart_TxUnit/C11/N6")
(joined
(portRef CE
(instanceRef Uart_TxUnit_TBufL_reg)
)
(portRef O
(instanceRef C421)
)
(portRef O
(instanceRef C422)
)
)
)
(net
(rename Uart_TxUnit_C10_N6 "Uart_TxUnit/C10/N6")
(joined
(portRef D
(instanceRef Uart_TxUnit_TBufL_reg)
)
(portRef I1
(instanceRef C414)
)
(portRef I
(instanceRef C417)
)
(portRef I1
(instanceRef C421)
)
(portRef I
(instanceRef C425)
)
(portRef O
(instanceRef C429)
)
(portRef O
(instanceRef C430)
)
)
)
(net
(rename Uart_TxUnit_C9_N5 "Uart_TxUnit/C9/N5")
(joined
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_0)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_1)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_2)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_3)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_4)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_5)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_6)
)
(portRef CE
(instanceRef Uart_TxUnit_TReg_reg_7)
)
(portRef O
(instanceRef C414)
)
(portRef O
(instanceRef C415)
)
)
)
(net
(rename Uart_TxUnit_TBuff_0 "Uart_TxUnit/TBuff<0>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_0)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_0)
)
)
)
(net
(rename Uart_TxUnit_TBuff_1 "Uart_TxUnit/TBuff<1>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_1)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_1)
)
)
)
(net
(rename Uart_TxUnit_TBuff_2 "Uart_TxUnit/TBuff<2>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_2)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_2)
)
)
)
(net
(rename Uart_TxUnit_TBuff_3 "Uart_TxUnit/TBuff<3>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_3)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_3)
)
)
)
(net
(rename Uart_TxUnit_TBuff_4 "Uart_TxUnit/TBuff<4>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_4)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_4)
)
)
)
(net
(rename Uart_TxUnit_TBuff_5 "Uart_TxUnit/TBuff<5>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_5)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_5)
)
)
)
(net
(rename Uart_TxUnit_TBuff_6 "Uart_TxUnit/TBuff<6>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_6)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_6)
)
)
)
(net
(rename Uart_TxUnit_TBuff_7 "Uart_TxUnit/TBuff<7>")
(joined
(portRef D
(instanceRef Uart_TxUnit_TReg_reg_7)
)
(portRef Q
(instanceRef Uart_TxUnit_TBuff_reg_7)
)
)
)
(net
(rename Uart_TxUnit_C8_N5 "Uart_TxUnit/C8/N5")
(joined
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_0)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_1)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_2)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_3)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_4)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_5)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_6)
)
(portRef CE
(instanceRef Uart_TxUnit_TBuff_reg_7)
)
(portRef O
(instanceRef C408)
)
(portRef O
(instanceRef C409)
)
)
)
(net
(rename Uart_TxUnit_C14_N19 "Uart_TxUnit/C14/N19")
(joined
(portRef CE
(instanceRef Uart_TxUnit_BitPos_reg_3)
)
(portRef CE
(instanceRef Uart_TxUnit_BitPos_reg_2)
)
(portRef CE
(instanceRef Uart_TxUnit_BitPos_reg_1)
)
(portRef CE
(instanceRef Uart_TxUnit_BitPos_reg_0)
)
(portRef O
(instanceRef C384)
)
(portRef O
(instanceRef C385)
)
)
)
(net
(rename Uart_TxUnit_C4_N5 "Uart_TxUnit/C4/N5")
(joined
(portRef D
(instanceRef Uart_TxUnit_BitPos_reg_3)
)
(portRef O
(instanceRef C393)
)
(portRef O
(instanceRef C394)
)
)
)
(net
(rename Uart_TxUnit_C4_N10 "Uart_TxUnit/C4/N10")
(joined
(portRef D
(instanceRef Uart_TxUnit_BitPos_reg_2)
)
(portRef O
(instanceRef C372)
)
(portRef O
(instanceRef C373)
)
)
)
(net
(rename Uart_TxUnit_C4_N15 "Uart_TxUnit/C4/N15")
(joined
(portRef D
(instanceRef Uart_TxUnit_BitPos_reg_1)
)
(portRef O
(instanceRef C359)
)
(portRef O
(instanceRef C360)
)
)
)
(net
(rename Uart_TxUnit_C4_N20 "Uart_TxUnit/C4/N20")
(joined
(portRef D
(instanceRef Uart_TxUnit_BitPos_reg_0)
)
(portRef O
(instanceRef C540)
)
)
)
(net
(rename Uart_RxUnit_RReg_7 "Uart_RxUnit/RReg<7>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_7)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_7)
)
(portRef I4
(instanceRef C197)
)
(portRef I1
(instanceRef C208)
)
(portRef I1
(instanceRef C209)
)
)
)
(net
(rename Uart_RxUnit_larray413_7 "Uart_RxUnit/larray413<7>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_7)
)
(portRef O
(instanceRef C197)
)
(portRef O
(instanceRef C198)
)
)
)
(net
(rename Uart_RxUnit_RReg_6 "Uart_RxUnit/RReg<6>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_6)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_6)
)
(portRef I4
(instanceRef C211)
)
(portRef I1
(instanceRef C219)
)
(portRef I1
(instanceRef C220)
)
)
)
(net
(rename Uart_RxUnit_larray413_6 "Uart_RxUnit/larray413<6>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_6)
)
(portRef O
(instanceRef C211)
)
(portRef O
(instanceRef C212)
)
)
)
(net
(rename Uart_RxUnit_RReg_5 "Uart_RxUnit/RReg<5>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_5)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_5)
)
(portRef I4
(instanceRef C222)
)
(portRef I1
(instanceRef C230)
)
(portRef I1
(instanceRef C231)
)
)
)
(net
(rename Uart_RxUnit_larray413_5 "Uart_RxUnit/larray413<5>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_5)
)
(portRef O
(instanceRef C222)
)
(portRef O
(instanceRef C223)
)
)
)
(net
(rename Uart_RxUnit_RReg_4 "Uart_RxUnit/RReg<4>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_4)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_4)
)
(portRef I4
(instanceRef C233)
)
(portRef I1
(instanceRef C241)
)
(portRef I1
(instanceRef C242)
)
)
)
(net
(rename Uart_RxUnit_larray413_4 "Uart_RxUnit/larray413<4>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_4)
)
(portRef O
(instanceRef C233)
)
(portRef O
(instanceRef C234)
)
)
)
(net
(rename Uart_RxUnit_RReg_3 "Uart_RxUnit/RReg<3>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_3)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_3)
)
(portRef I4
(instanceRef C244)
)
(portRef I1
(instanceRef C252)
)
(portRef I1
(instanceRef C253)
)
)
)
(net
(rename Uart_RxUnit_larray413_3 "Uart_RxUnit/larray413<3>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_3)
)
(portRef O
(instanceRef C244)
)
(portRef O
(instanceRef C245)
)
)
)
(net
(rename Uart_RxUnit_RReg_2 "Uart_RxUnit/RReg<2>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_2)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_2)
)
(portRef I4
(instanceRef C261)
)
(portRef I1
(instanceRef C269)
)
(portRef I1
(instanceRef C270)
)
)
)
(net
(rename Uart_RxUnit_larray413_2 "Uart_RxUnit/larray413<2>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_2)
)
(portRef O
(instanceRef C261)
)
(portRef O
(instanceRef C262)
)
)
)
(net
(rename Uart_RxUnit_RReg_1 "Uart_RxUnit/RReg<1>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_1)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_1)
)
(portRef I4
(instanceRef C279)
)
(portRef I1
(instanceRef C287)
)
(portRef I1
(instanceRef C288)
)
)
)
(net
(rename Uart_RxUnit_larray413_1 "Uart_RxUnit/larray413<1>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_1)
)
(portRef O
(instanceRef C279)
)
(portRef O
(instanceRef C280)
)
)
)
(net
(rename Uart_RxUnit_RReg_0 "Uart_RxUnit/RReg<0>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RReg_reg_0)
)
(portRef D
(instanceRef Uart_RxUnit_DataO_reg_0)
)
(portRef I4
(instanceRef C308)
)
(portRef I1
(instanceRef C316)
)
(portRef I1
(instanceRef C317)
)
)
)
(net
(rename Uart_RxUnit_larray413_0 "Uart_RxUnit/larray413<0>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RReg_reg_0)
)
(portRef O
(instanceRef C308)
)
(portRef O
(instanceRef C309)
)
)
)
(net
(rename Uart_RxUnit_SampleCnt_1 "Uart_RxUnit/SampleCnt<1>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_SampleCnt_reg_1)
)
(portRef I1
(instanceRef C119)
)
(portRef I0
(instanceRef C126)
)
(portRef I3
(instanceRef C159)
)
(portRef I
(instanceRef C164)
)
(portRef I2
(instanceRef C169)
)
(portRef I1
(instanceRef C295)
)
(portRef I
(instanceRef C298)
)
)
)
(net
(rename Uart_RxUnit_SampleCnt_0 "Uart_RxUnit/SampleCnt<0>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_SampleCnt_reg_0)
)
(portRef I2
(instanceRef C119)
)
(portRef I1
(instanceRef C126)
)
(portRef I1
(instanceRef C151)
)
(portRef I
(instanceRef C155)
)
(portRef I1
(instanceRef C159)
)
(portRef I
(instanceRef C165)
)
(portRef I0
(instanceRef C168)
)
(portRef I2
(instanceRef C295)
)
(portRef I1
(instanceRef C301)
)
)
)
(net
(rename Uart_RxUnit_RRegL "Uart_RxUnit/RRegL")
(joined
(portRef Q
(instanceRef Uart_RxUnit_RRegL_reg)
)
(portRef C
(instanceRef Uart_RxUnit_RxAv_reg)
)
)
)
(net
(rename Uart_RxUnit_C13_N3 "Uart_RxUnit/C13/N3")
(joined
(portRef CE
(instanceRef Uart_RxUnit_RRegL_reg)
)
(portRef O
(instanceRef C341)
)
(portRef O
(instanceRef C342)
)
)
)
(net
(rename Uart_RxUnit_BitPos_3 "Uart_RxUnit/BitPos<3>")
(joined
(portRef D
(instanceRef Uart_RxUnit_RRegL_reg)
)
(portRef Q
(instanceRef Uart_RxUnit_BitPos_reg_3)
)
(portRef I1
(instanceRef C127)
)
(portRef I
(instanceRef C130)
)
(portRef I1
(instanceRef C136)
)
(portRef I
(instanceRef C145)
)
(portRef I0
(instanceRef C147)
)
(portRef I0
(instanceRef C148)
)
(portRef I0
(instanceRef C149)
)
(portRef I1
(instanceRef C170)
)
(portRef I
(instanceRef C173)
)
(portRef I1
(instanceRef C190)
)
(portRef I0
(instanceRef C196)
)
(portRef I1
(instanceRef C346)
)
(portRef I
(instanceRef C352)
)
(portRef I0
(instanceRef C357)
)
)
)
(net
(rename Uart_RxUnit_n551 "Uart_RxUnit/n551")
(joined
(portRef CLR
(instanceRef Uart_RxUnit_RxAv_reg)
)
(portRef O
(instanceRef C334)
)
(portRef O
(instanceRef C335)
)
)
)
(net
(rename Uart_RxUnit_C12_N5 "Uart_RxUnit/C12/N5")
(joined
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_0)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_1)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_2)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_3)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_4)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_5)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_6)
)
(portRef CE
(instanceRef Uart_RxUnit_RReg_reg_7)
)
(portRef O
(instanceRef C295)
)
(portRef O
(instanceRef C296)
)
)
)
(net
(rename Uart_RxUnit_C11_N5 "Uart_RxUnit/C11/N5")
(joined
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_0)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_1)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_2)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_3)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_4)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_5)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_6)
)
(portRef CE
(instanceRef Uart_RxUnit_DataO_reg_7)
)
(portRef O
(instanceRef C185)
)
(portRef O
(instanceRef C186)
)
)
)
(net
(rename Uart_RxUnit_C10_N10 "Uart_RxUnit/C10/N10")
(joined
(portRef CE
(instanceRef Uart_RxUnit_SampleCnt_reg_1)
)
(portRef CE
(instanceRef Uart_RxUnit_SampleCnt_reg_0)
)
(portRef I2
(instanceRef C185)
)
(portRef I1
(instanceRef C189)
)
(portRef I4
(instanceRef C295)
)
(portRef I3
(instanceRef C301)
)
(portRef O
(instanceRef C302)
)
(portRef O
(instanceRef C303)
)
)
)
(net
(rename Uart_RxUnit_C15_N19 "Uart_RxUnit/C15/N19")
(joined
(portRef CE
(instanceRef Uart_RxUnit_BitPos_reg_3)
)
(portRef CE
(instanceRef Uart_RxUnit_BitPos_reg_2)
)
(portRef CE
(instanceRef Uart_RxUnit_BitPos_reg_1)
)
(portRef CE
(instanceRef Uart_RxUnit_BitPos_reg_0)
)
(portRef O
(instanceRef C111)
)
(portRef O
(instanceRef C112)
)
)
)
(net
(rename Uart_RxUnit_BitPos_2 "Uart_RxUnit/BitPos<2>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_BitPos_reg_2)
)
(portRef I1
(instanceRef C102)
)
(portRef I
(instanceRef C106)
)
(portRef I0
(instanceRef C110)
)
(portRef I4
(instanceRef C127)
)
(portRef I
(instanceRef C133)
)
(portRef I4
(instanceRef C136)
)
(portRef I
(instanceRef C144)
)
(portRef I2
(instanceRef C148)
)
(portRef I3
(instanceRef C150)
)
(portRef I2
(instanceRef C176)
)
(portRef I
(instanceRef C180)
)
(portRef I4
(instanceRef C190)
)
(portRef I
(instanceRef C194)
)
(portRef I2
(instanceRef C319)
)
(portRef I
(instanceRef C324)
)
(portRef I1
(instanceRef C326)
)
(portRef I4
(instanceRef C346)
)
(portRef I
(instanceRef C351)
)
(portRef I
(instanceRef C355)
)
)
)
(net
(rename Uart_RxUnit_BitPos_1 "Uart_RxUnit/BitPos<1>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_BitPos_reg_1)
)
(portRef I3
(instanceRef C91)
)
(portRef I
(instanceRef C98)
)
(portRef I2
(instanceRef C100)
)
(portRef I3
(instanceRef C127)
)
(portRef I
(instanceRef C132)
)
(portRef I3
(instanceRef C136)
)
(portRef I
(instanceRef C142)
)
(portRef I2
(instanceRef C150)
)
(portRef I1
(instanceRef C176)
)
(portRef I
(instanceRef C179)
)
(portRef I3
(instanceRef C190)
)
(portRef I2
(instanceRef C196)
)
(portRef I2
(instanceRef C255)
)
(portRef I
(instanceRef C258)
)
(portRef I2
(instanceRef C272)
)
(portRef I
(instanceRef C276)
)
(portRef I2
(instanceRef C290)
)
(portRef I1
(instanceRef C294)
)
(portRef I1
(instanceRef C319)
)
(portRef I
(instanceRef C323)
)
(portRef I0
(instanceRef C327)
)
(portRef I2
(instanceRef C328)
)
(portRef I1
(instanceRef C333)
)
(portRef I3
(instanceRef C346)
)
(portRef I
(instanceRef C354)
)
(portRef I2
(instanceRef C357)
)
)
)
(net
(rename Uart_RxUnit_BitPos_0 "Uart_RxUnit/BitPos<0>")
(joined
(portRef Q
(instanceRef Uart_RxUnit_BitPos_reg_0)
)
(portRef I1
(instanceRef C81)
)
(portRef I
(instanceRef C85)
)
(portRef I
(instanceRef C86)
)
(portRef I1
(instanceRef C91)
)
(portRef I
(instanceRef C95)
)
(portRef I0
(instanceRef C101)
)
(portRef I2
(instanceRef C127)
)
(portRef I
(instanceRef C131)
)
(portRef I2
(instanceRef C136)
)
(portRef I
(instanceRef C143)
)
(portRef I1
(instanceRef C149)
)
(portRef I1
(instanceRef C150)
)
(portRef I3
(instanceRef C176)
)
(portRef I
(instanceRef C181)
)
(portRef I2
(instanceRef C190)
)
(portRef I
(instanceRef C193)
)
(portRef I1
(instanceRef C255)
)
(portRef I0
(instanceRef C260)
)
(portRef I1
(instanceRef C272)
)
(portRef I
(instanceRef C275)
)
(portRef I1
(instanceRef C290)
)
(portRef I0
(instanceRef C294)
)
(portRef I1
(instanceRef C328)
)
(portRef I
(instanceRef C331)
)
(portRef I2
(instanceRef C346)
)
(portRef I
(instanceRef C350)
)
(portRef I
(instanceRef C353)
)
)
)
(net
(rename Uart_Rxrate_C126_N2 "Uart_Rxrate/C126/N2")
(joined
(portRef COUT
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef CIN
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef I3
(instanceRef C15)
)
(portRef I1
(instanceRef C20)
)
)
)
(net
(rename Uart_Rxrate_C126_N7 "Uart_Rxrate/C126/N7")
(joined
(portRef COUT
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef CIN
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef I3
(instanceRef C33)
)
(portRef I1
(instanceRef C38)
)
)
)
(net
(rename Uart_Rxrate_C126_N12 "Uart_Rxrate/C126/N12")
(joined
(portRef COUT
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef CIN
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef I3
(instanceRef C51)
)
(portRef I1
(instanceRef C56)
)
)
)
(net
(rename Uart_Rxrate_C126_N17 "Uart_Rxrate/C126/N17")
(joined
(portRef COUT
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef CIN
(instanceRef C538)
)
(portRef I3
(instanceRef C69)
)
(portRef I1
(instanceRef C76)
)
)
)
(net
(rename Uart_Rxrate_C127_N6 "Uart_Rxrate/C127/N6")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_0)
)
(portRef O
(instanceRef C0)
)
(portRef O
(instanceRef C2)
)
)
)
(net
(rename Uart_Rxrate_C127_N11 "Uart_Rxrate/C127/N11")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_1)
)
(portRef O
(instanceRef C15)
)
(portRef O
(instanceRef C21)
)
)
)
(net
(rename Uart_Rxrate_C127_N16 "Uart_Rxrate/C127/N16")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_2)
)
(portRef O
(instanceRef C24)
)
(portRef O
(instanceRef C30)
)
)
)
(net
(rename Uart_Rxrate_C127_N21 "Uart_Rxrate/C127/N21")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_3)
)
(portRef O
(instanceRef C33)
)
(portRef O
(instanceRef C39)
)
)
)
(net
(rename Uart_Rxrate_C127_N26 "Uart_Rxrate/C127/N26")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_4)
)
(portRef O
(instanceRef C42)
)
(portRef O
(instanceRef C48)
)
)
)
(net
(rename Uart_Rxrate_C127_N31 "Uart_Rxrate/C127/N31")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_5)
)
(portRef O
(instanceRef C51)
)
(portRef O
(instanceRef C57)
)
)
)
(net
(rename Uart_Rxrate_C127_N36 "Uart_Rxrate/C127/N36")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_6)
)
(portRef O
(instanceRef C60)
)
(portRef O
(instanceRef C66)
)
)
)
(net
(rename Uart_Rxrate_C127_N42 "Uart_Rxrate/C127/N42")
(joined
(portRef D
(instanceRef Uart_Rxrate_Cnt_reg_7)
)
(portRef O
(instanceRef C69)
)
(portRef O
(instanceRef C71)
)
)
)
(net
(rename Uart_Txrate_C59_N6 "Uart_Txrate/C59/N6")
(joined
(portRef D
(instanceRef Uart_Txrate_Cnt_reg_0)
)
(portRef O
(instanceRef C541)
)
)
)
(net
(rename Uart_Txrate_C59_N11 "Uart_Txrate/C59/N11")
(joined
(portRef D
(instanceRef Uart_Txrate_Cnt_reg_1)
)
(portRef O
(instanceRef C552)
)
(portRef O
(instanceRef C553)
)
)
)
(net
(rename Uart_TxUnit_SyncLoad_R "Uart_TxUnit/SyncLoad/R")
(joined
(portRef CLR
(instanceRef Uart_TxUnit_SyncLoad_C1S_reg)
)
(portRef Q
(instanceRef Uart_TxUnit_SyncLoad_R_reg)
)
(portRef CLR
(instanceRef Uart_TxUnit_SyncLoad_C1A_reg)
)
)
)
(net
(rename Uart_TxUnit_SyncLoad_C1A "Uart_TxUnit/SyncLoad/C1A")
(joined
(portRef D
(instanceRef Uart_TxUnit_SyncLoad_C1S_reg)
)
(portRef Q
(instanceRef Uart_TxUnit_SyncLoad_C1A_reg)
)
)
)
(net
(rename Uart_RxUnit_C290_N9 "Uart_RxUnit/C290/N9")
(joined
(portRef D
(instanceRef Uart_RxUnit_BitPos_reg_0)
)
(portRef O
(instanceRef C81)
)
(portRef O
(instanceRef C82)
)
)
)
(net
(rename Uart_RxUnit_C290_N14 "Uart_RxUnit/C290/N14")
(joined
(portRef D
(instanceRef Uart_RxUnit_BitPos_reg_1)
)
(portRef O
(instanceRef C91)
)
(portRef O
(instanceRef C92)
)
)
)
(net
(rename Uart_RxUnit_C290_N20 "Uart_RxUnit/C290/N20")
(joined
(portRef D
(instanceRef Uart_RxUnit_BitPos_reg_2)
)
(portRef O
(instanceRef C102)
)
(portRef O
(instanceRef C103)
)
)
)
(net
(rename Uart_RxUnit_C290_N26 "Uart_RxUnit/C290/N26")
(joined
(portRef D
(instanceRef Uart_RxUnit_BitPos_reg_3)
)
(portRef O
(instanceRef C136)
)
(portRef O
(instanceRef C137)
)
)
)
(net
(rename Uart_RxUnit_C291_N5 "Uart_RxUnit/C291/N5")
(joined
(portRef D
(instanceRef Uart_RxUnit_SampleCnt_reg_0)
)
(portRef O
(instanceRef C151)
)
(portRef O
(instanceRef C152)
)
)
)
(net
(rename Uart_RxUnit_C291_N10 "Uart_RxUnit/C291/N10")
(joined
(portRef D
(instanceRef Uart_RxUnit_SampleCnt_reg_1)
)
(portRef O
(instanceRef C159)
)
(portRef O
(instanceRef C160)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N0 "Uart_Rxrate/C126/C0/N0")
(joined
(portRef C0
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C0
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N1 "Uart_Rxrate/C126/C0/N1")
(joined
(portRef C1
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C1
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N2 "Uart_Rxrate/C126/C0/N2")
(joined
(portRef C2
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C2
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N3 "Uart_Rxrate/C126/C0/N3")
(joined
(portRef C3
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C3
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N4 "Uart_Rxrate/C126/C0/N4")
(joined
(portRef C4
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C4
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N5 "Uart_Rxrate/C126/C0/N5")
(joined
(portRef C5
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C5
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N6 "Uart_Rxrate/C126/C0/N6")
(joined
(portRef C6
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C6
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C0_N7 "Uart_Rxrate/C126/C0/N7")
(joined
(portRef C7
(instanceRef Uart_Rxrate_C126_C0_C1)
)
(portRef C7
(instanceRef Uart_Rxrate_C126_C0_C2)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_cout0_net "Uart_Rxrate/C126/C1/cout0_net")
(joined
(portRef COUT0
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef I2
(instanceRef C24)
)
(portRef I0
(instanceRef C29)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N0 "Uart_Rxrate/C126/C1/N0")
(joined
(portRef C0
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C0
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N1 "Uart_Rxrate/C126/C1/N1")
(joined
(portRef C1
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C1
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N2 "Uart_Rxrate/C126/C1/N2")
(joined
(portRef C2
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C2
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N3 "Uart_Rxrate/C126/C1/N3")
(joined
(portRef C3
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C3
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N4 "Uart_Rxrate/C126/C1/N4")
(joined
(portRef C4
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C4
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N5 "Uart_Rxrate/C126/C1/N5")
(joined
(portRef C5
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C5
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N6 "Uart_Rxrate/C126/C1/N6")
(joined
(portRef C6
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C6
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C1_N7 "Uart_Rxrate/C126/C1/N7")
(joined
(portRef C7
(instanceRef Uart_Rxrate_C126_C1_C2)
)
(portRef C7
(instanceRef Uart_Rxrate_C126_C1_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_cout0_net "Uart_Rxrate/C126/C2/cout0_net")
(joined
(portRef COUT0
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef I2
(instanceRef C42)
)
(portRef I0
(instanceRef C47)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N0 "Uart_Rxrate/C126/C2/N0")
(joined
(portRef C0
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C0
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N1 "Uart_Rxrate/C126/C2/N1")
(joined
(portRef C1
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C1
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N2 "Uart_Rxrate/C126/C2/N2")
(joined
(portRef C2
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C2
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N3 "Uart_Rxrate/C126/C2/N3")
(joined
(portRef C3
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C3
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N4 "Uart_Rxrate/C126/C2/N4")
(joined
(portRef C4
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C4
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N5 "Uart_Rxrate/C126/C2/N5")
(joined
(portRef C5
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C5
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N6 "Uart_Rxrate/C126/C2/N6")
(joined
(portRef C6
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C6
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C2_N7 "Uart_Rxrate/C126/C2/N7")
(joined
(portRef C7
(instanceRef Uart_Rxrate_C126_C2_C2)
)
(portRef C7
(instanceRef Uart_Rxrate_C126_C2_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_cout0_net "Uart_Rxrate/C126/C3/cout0_net")
(joined
(portRef COUT0
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef I2
(instanceRef C60)
)
(portRef I0
(instanceRef C65)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N0 "Uart_Rxrate/C126/C3/N0")
(joined
(portRef C0
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C0
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N1 "Uart_Rxrate/C126/C3/N1")
(joined
(portRef C1
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C1
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N2 "Uart_Rxrate/C126/C3/N2")
(joined
(portRef C2
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C2
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N3 "Uart_Rxrate/C126/C3/N3")
(joined
(portRef C3
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C3
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N4 "Uart_Rxrate/C126/C3/N4")
(joined
(portRef C4
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C4
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N5 "Uart_Rxrate/C126/C3/N5")
(joined
(portRef C5
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C5
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N6 "Uart_Rxrate/C126/C3/N6")
(joined
(portRef C6
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C6
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net
(rename Uart_Rxrate_C126_C3_N7 "Uart_Rxrate/C126/C3/N7")
(joined
(portRef C7
(instanceRef Uart_Rxrate_C126_C3_C2)
)
(portRef C7
(instanceRef Uart_Rxrate_C126_C3_C3)
)
)
)
(net N191
(joined
(portRef D
(instanceRef Uart_RxUnit_RxAv_reg)
)
(portRef D
(instanceRef Uart_TxUnit_SyncLoad_C1A_reg)
)
(portRef P
(instanceRef C604)
)
)
)
(net N195
(joined
(portRef CLR
(instanceRef ReadA_reg)
)
(portRef CLR
(instanceRef LoadA_reg)
)
(portRef CLR
(instanceRef TxData_reg_0)
)
(portRef CLR
(instanceRef TxData_reg_1)
)
(portRef CLR
(instanceRef TxData_reg_2)
)
(portRef CLR
(instanceRef TxData_reg_3)
)
(portRef CLR
(instanceRef TxData_reg_4)
)
(portRef CLR
(instanceRef TxData_reg_5)
)
(portRef CLR
(instanceRef TxData_reg_6)
)
(portRef CLR
(instanceRef TxData_reg_7)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_0)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_4)
)
(portRef CLR
(instanceRef Uart_Rxrate_O_reg)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_6)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_2)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_3)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_7)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_5)
)
(portRef CLR
(instanceRef Uart_Rxrate_Cnt_reg_1)
)
(portRef CLR
(instanceRef Uart_Txrate_O_reg)
)
(portRef CLR
(instanceRef Uart_Txrate_Cnt_reg_1)
)
(portRef CLR
(instanceRef Uart_Txrate_Cnt_reg_0)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_0)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_1)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_2)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_3)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_4)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_5)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_6)
)
(portRef CLR
(instanceRef Uart_TxUnit_TReg_reg_7)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_0)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_1)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_2)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_3)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_4)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_5)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_6)
)
(portRef CLR
(instanceRef Uart_TxUnit_TBuff_reg_7)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_0)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_1)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_2)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_3)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_4)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_5)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_6)
)
(portRef CLR
(instanceRef Uart_RxUnit_RReg_reg_7)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_0)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_1)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_2)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_3)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_4)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_5)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_6)
)
(portRef CLR
(instanceRef Uart_RxUnit_DataO_reg_7)
)
(portRef CLR
(instanceRef Uart_RxUnit_SampleCnt_reg_1)
)
(portRef CLR
(instanceRef Uart_RxUnit_SampleCnt_reg_0)
)
(portRef CLR
(instanceRef Uart_TxUnit_SyncLoad_R_reg)
)
(portRef G
(instanceRef C605)
)
)
)
(net N255
(joined
(portRef D
(instanceRef Uart_Rxrate_O_reg)
)
(portRef O
(instanceRef C568)
)
(portRef O
(instanceRef C569)
)
)
)
(net N256
(joined
(portRef IntTx_O)
(portRef I4
(instanceRef C685)
)
(portRef I2
(instanceRef C694)
)
(portRef O
(instanceRef C695)
)
(portRef O
(instanceRef C696)
)
)
)
(net syn825
(joined
(portRef I2
(instanceRef C81)
)
(portRef I
(instanceRef C87)
)
(portRef I2
(instanceRef C91)
)
(portRef I
(instanceRef C96)
)
(portRef I
(instanceRef C97)
)
(portRef I3
(instanceRef C119)
)
(portRef I
(instanceRef C123)
)
(portRef I3
(instanceRef C295)
)
(portRef I
(instanceRef C299)
)
(portRef I2
(instanceRef C341)
)
(portRef I1
(instanceRef C345)
)
(portRef O
(instanceRef C346)
)
(portRef O
(instanceRef C347)
)
)
)
(net syn648
(joined
(portRef I3
(instanceRef C81)
)
(portRef I1
(instanceRef C89)
)
(portRef I3
(instanceRef C111)
)
(portRef I2
(instanceRef C118)
)
(portRef O
(instanceRef C127)
)
(portRef O
(instanceRef C128)
)
)
)
(net syn850
(joined
(portRef I2
(instanceRef C102)
)
(portRef I
(instanceRef C107)
)
(portRef I1
(instanceRef C109)
)
(portRef I2
(instanceRef C222)
)
(portRef I
(instanceRef C227)
)
(portRef I1
(instanceRef C232)
)
(portRef I2
(instanceRef C279)
)
(portRef I
(instanceRef C284)
)
(portRef I1
(instanceRef C289)
)
(portRef O
(instanceRef C290)
)
(portRef O
(instanceRef C291)
)
)
)
(net syn3354
(joined
(portRef I4
(instanceRef C111)
)
(portRef I1
(instanceRef C117)
)
(portRef O
(instanceRef C119)
)
(portRef O
(instanceRef C120)
)
)
)
(net
(rename Uart_RxUnit_C319 "Uart_RxUnit/C319")
(joined
(portRef I4
(instanceRef C119)
)
(portRef I
(instanceRef C125)
)
(portRef I1
(instanceRef C185)
)
(portRef I0
(instanceRef C189)
)
(portRef O
(instanceRef C190)
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(design UART
(cellRef UART
(libraryRef DESIGNS)
)
(property PART
(string "S10-TQ144-3")
)
)
)
/trunk/impl/Xilinx/out/info.txt
0,0 → 1,4
This is a rough synthezised version of the miniuart in edif netlist.
It has been performed with BRDIVISOR=130.
Thus it can work for a baudrate of 9600bps, assumming that a 5MHz clock is
connected to BR_Clk_I.
/trunk/syn/Xilinx/log/ver1.chp
0,0 → 1,131
 
=========
Chip ver1
=========
 
Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 0 errors, 1 warnings, 6 messages
 
Target Information:
-------------------
Vendor: Xilinx
Family: SPARTAN
Device: S10TQ144
Speed: -4
 
Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0
 
Chip Design Hierarchy:
----------------------
UART: defined in c:\phili\fndtn\miniuart\miniuart.vhd
Counter - Uart_Rxrate: defined in c:\phili\fndtn\miniuart\utils.vhd
Counter - Uart_Txrate: defined in c:\phili\fndtn\miniuart\utils.vhd
TxUnit - Uart_TxUnit: defined in c:\phili\fndtn\miniuart\txunit.vhd
synchroniser - SyncLoad: defined in c:\phili\fndtn\miniuart\utils.vhd
RxUnit - Uart_RxUnit: defined in c:\phili\fndtn\miniuart\rxunit.vhd
 
Primitive reference count:
--------------------------
*ADD_UNS_OP_2_1_2 1
*ADD_UNS_OP_4_1_4 2
*SELECT_OP_2.1_2.1_1 1
*SELECT_OP_2.2_2.1_2 2
*SELECT_OP_3.4_3.1_4 2
*SUB_TC_OP_1_1_1 1
*SUB_TC_OP_2_2_2 1
*SUB_TC_OP_3_3_3 2
AND 209
SEQ 64
 
Clocks:
-------
Required Estimated
Period Rise Fall Freq Freq Signal
(ns) (ns) (ns) (MHz) (MHz)
...............................................................
20 0 10 50.00 -1.00 default
-1 -1 -1 -1000.00 100.00 BR_Clk_I
-1 -1 -1 -1000.00 100.00 LoadA
-1 -1 -1 -1000.00 100.00 RRegL
-1 -1 -1 -1000.00 100.00 WB_CLK_I
 
Timing Groups:
--------------
Name Description
...........................................................................
(I) Input ports
(O) Output ports
(RC,BR_Clk_I) Clocked by rising edge of BR_Clk_I
(RC,LoadA) Clocked by rising edge of LoadA
(RC,RRegL) Clocked by rising edge of RRegL
(RC,WB_CLK_I) Clocked by rising edge of WB_CLK_I
 
Timing Path Groups:
-------------------
Required Estimated
Delay Delay
From To (ns) (ns)
..........................................................................
(I) (O) 20.00 -1.00
(I) (RC,BR_Clk_I) 20.00 -1.00
(I) (RC,WB_CLK_I) 20.00 -1.00
(RC,BR_Clk_I) (O) 20.00 -1.00
(RC,BR_Clk_I) (RC,BR_Clk_I) 20.00 -1.00
(RC,LoadA) (RC,BR_Clk_I) 20.00 -1.00
(RC,RRegL) (O) 20.00 -1.00
(RC,WB_CLK_I) (RC,BR_Clk_I) 20.00 -1.00
 
Input Port Timing:
------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) To-Group
...........................................................................
WB_CLK_I 20.00 -1.00 (RC,BR_Clk_I)
WB_RST_I 20.00 -1.00 (RC,BR_Clk_I)
WB_ADR_I<1> 20.00 -1.00 (RC,BR_Clk_I)
WB_ADR_I<0> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<7> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<6> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<5> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<4> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<3> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<2> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<1> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_I<0> 20.00 -1.00 (RC,BR_Clk_I)
WB_WE_I 20.00 -1.00 (RC,BR_Clk_I)
WB_STB_I 20.00 -1.00 (RC,BR_Clk_I)
BR_Clk_I 20.00 -1.00 (RC,BR_Clk_I)
RxD_PAD_I 20.00 -1.00 (RC,BR_Clk_I)
 
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
...........................................................................
WB_DAT_O<7> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<6> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<5> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<4> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<3> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<2> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<1> 20.00 -1.00 (RC,BR_Clk_I)
WB_DAT_O<0> 20.00 -1.00 (RC,BR_Clk_I)
WB_ACK_O 20.00 -1.00 (RC,BR_Clk_I)
IntTx_O 20.00 -1.00 (RC,BR_Clk_I)
IntRx_O 20.00 -1.00 (RC,BR_Clk_I)
TxD_PAD_O 20.00 -1.00 (RC,BR_Clk_I)
/trunk/syn/Xilinx/log/ver1-optimized.chp
0,0 → 1,140
 
===================
Chip ver1-Optimized
===================
 
Summary Information:
--------------------
Type: Optimized implementation
Source: ver1, up to date
Status: 0 errors, 243 warnings, 0 messages
Export: exported after last optimization
 
Target Information:
-------------------
Vendor: Xilinx
Family: SPARTAN
Device: S10TQ144
Speed: -4
 
Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 64
Number of latches: 0
 
Chip Design Hierarchy:
----------------------
UART: defined in c:\phili\fndtn\miniuart\miniuart.vhd
 
Primitive reference count:
--------------------------
BUFG 4
FDC 9
FDCE 46
FMAP 61
GND 60
HMAP 4
IBUF 6
IFDX 8
INV 3
IPAD 2
OBUF 11
OFDX 1
VCC 1
 
Clocks:
-------
Required Estimated
Period Rise Fall Freq Freq Signal
(ns) (ns) (ns) (MHz) (MHz)
...............................................................
20 0 10 50.00 -1.00 default
-1 -1 -1 -1000.00 99.40 BR_Clk_I_BUFGed
-1 -1 -1 -1000.00 100.00 N295_BUFGed
-1 -1 -1 -1000.00 100.00 N294_BUFGed
-1 -1 -1 -1000.00 52.63 WB_CLK_I_BUFGed
 
Timing Groups:
--------------
Name Description
...........................................................................
(I) Input ports
(O) Output ports
(RC,BR_Clk_I_BUFGed) Clocked by rising edge of BR_Clk_I_BUFGed
(RC,N295_BUFGed) Clocked by rising edge of N295_BUFGed
(RC,N294_BUFGed) Clocked by rising edge of N294_BUFGed
(RC,WB_CLK_I_BUFGed) Clocked by rising edge of WB_CLK_I_BUFGed
 
Timing Path Groups:
-------------------
Required Estimated
Delay Delay
From To (ns) (ns)
..........................................................................
(I) (O) 20.00 13.45
(I) (RC,BR_Clk_I_BUFGed) 20.00 9.20
(I) (RC,WB_CLK_I_BUFGed) 20.00 19.00
(RC,BR_Clk_I_BUFGed) (O) 20.00 13.73
(RC,BR_Clk_I_BUFGed) (RC,BR_Clk_I_BUFGed) 20.00 10.06
(RC,N295_BUFGed) (RC,BR_Clk_I_BUFGed) 20.00 2.89
(RC,N294_BUFGed) (O) 20.00 11.81
(RC,WB_CLK_I_BUFGed) (RC,BR_Clk_I_BUFGed) 20.00 3.54
 
Input Port Timing:
------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) To-Group
...........................................................................
WB_CLK_I 19.90 19.90 (RC,BR_Clk_I_BUFGed)
WB_RST_I 13.93 13.93 (RC,BR_Clk_I_BUFGed)
WB_ADR_I<1> 6.55 6.55 (RC,BR_Clk_I_BUFGed)
WB_ADR_I<0> 6.55 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<7> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<6> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<5> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<4> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<3> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<2> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<1> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_DAT_I<0> 1.00 1.00 (RC,BR_Clk_I_BUFGed)
WB_WE_I 15.47 15.47 (RC,BR_Clk_I_BUFGed)
WB_STB_I 9.15 9.15 (RC,BR_Clk_I_BUFGed)
BR_Clk_I 19.90 19.90 (RC,BR_Clk_I_BUFGed)
RxD_PAD_I 10.80 10.80 (RC,BR_Clk_I_BUFGed)
 
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
...........................................................................
WB_DAT_O<7> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<6> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<5> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<4> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<3> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<2> 20.00 6.55 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<1> 20.00 7.85 (RC,BR_Clk_I_BUFGed)
WB_DAT_O<0> 20.00 6.27 (RC,BR_Clk_I_BUFGed)
WB_ACK_O 20.00 9.15 (RC,BR_Clk_I_BUFGed)
IntTx_O 20.00 7.57 (RC,BR_Clk_I_BUFGed)
IntRx_O 20.00 9.49 (RC,BR_Clk_I_BUFGed)
TxD_PAD_O 20.00 12.07 (RC,BR_Clk_I_BUFGed)
 
Critical Path Timing:
---------------------
Arrival Required
Cell Time Time Fanout
Type (ns) (ns) Count Pin-Name
........................................................................
IFDX 19.00 20.00 10 /ver1-Optimized/TxData_reg<7>/C
IFDX 0.00 1.00 1 /ver1-Optimized/TxData_reg<7>/D
port 0.00 1.00 1 /ver1-Optimized/WB_DAT_I<7>

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