OpenCores
URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/trunk/rtl/vhdl/utils.vhd
7,10 → 7,10
-- (philippe.carton2@libertysurf.fr)
-- Organization:
-- Created : 15/12/2001
-- Last update : 28/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : Foundation logic simulator
-- Synthesizers: Foundation Synopsys
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
45,19 → 45,19
-- one C clock period.
--------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_1164.all;
 
entity synchroniser is
port (
C1 : in Std_Logic; -- Asynchronous signal
C : in Std_Logic; -- Clock
O : out Std_logic); -- Synchronised signal
end entity;
C1 : in std_logic;-- Asynchronous signal
C : in std_logic;-- Clock
O : out std_logic);-- Synchronised signal
end synchroniser;
 
architecture Behaviour of synchroniser is
signal C1A : Std_Logic;
signal C1S : Std_Logic;
signal R : Std_Logic;
signal C1A : std_logic;
signal C1S : std_logic;
signal R : std_logic;
begin
RiseC1A : process(C1,R)
begin
66,12 → 66,12
end if;
if (R = '1') then
C1A <= '0';
end if;
end if;
end process;
 
SyncP : process(C,R)
begin
if Rising_Edge(C) then
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
83,7 → 83,7
end if;
if (R = '1') then
C1S <= '0';
end if;
end if;
end process;
O <= C1S;
end Behaviour;
97,16 → 97,16
-- It can be reseted to 0.
-------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_1164.all;
 
entity Counter is
generic(Count: INTEGER range 0 to 65535); -- Count revolution
port (
Clk : in Std_Logic; -- Clock
Reset : in Std_Logic; -- Reset input
CE : in Std_Logic; -- Chip Enable
O : out Std_Logic); -- Output
end entity;
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
O : out std_logic); -- Output
end Counter;
 
architecture Behaviour of Counter is
begin
115,7 → 115,7
begin
if Reset = '1' then
Cnt := Count - 1;
O <= '0';
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
if Cnt = 0 then
/trunk/rtl/vhdl/miniuart.vhd
2,15 → 2,15
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Uart.vhd
-- File : MiniUart.vhd
-- Author : Philippe CARTON
-- (philippe.carton2@libertysurf.fr)
-- Organization:
-- Created : 15/12/2001
-- Last update : 28/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : Foundation logic simulator
-- Synthesizers: Foundation Synopsys
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
-------------------------------------------------------------------------------
37,67 → 37,67
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor
port (
-- Wishbone signals
WB_CLK_I : in Std_Logic; -- clock
WB_RST_I : in Std_Logic; -- Reset input
WB_ADR_I : in Std_Logic_Vector(1 downto 0); -- Adress bus
WB_DAT_I : in Std_Logic_Vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out Std_Logic_Vector(7 downto 0); -- DataOut Bus
WB_WE_I : in Std_Logic; -- Write Enable
WB_STB_I : in Std_Logic; -- Strobe
WB_ACK_O : out Std_Logic; -- Acknowledge
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out Std_Logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out Std_Logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in Std_Logic; -- Clock used for Transmit/Receive
TxD_PAD_O: out Std_Logic; -- Tx RS232 Line
RxD_PAD_I: in Std_Logic); -- Rx RS232 Line
end entity;
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O: out std_logic; -- Tx RS232 Line
RxD_PAD_I: in std_logic); -- Rx RS232 Line
end UART;
 
-- Architecture for UART for synthesis
architecture Behaviour of UART is
 
component Counter is
component Counter
generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
port (
Clk : in Std_Logic; -- Clock
Reset : in Std_Logic; -- Reset input
CE : in Std_Logic; -- Chip Enable
O : out Std_Logic); -- Output
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
O : out std_logic); -- Output
end component;
 
component RxUnit is
component RxUnit
port (
Clk : in Std_Logic; -- system clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in Std_logic; -- Async Read Received Byte
RxD : in Std_Logic; -- RS-232 data input
RxAv : out Std_Logic; -- Byte available
DataO : out Std_Logic_Vector(7 downto 0)); -- Byte received
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0)); -- Byte received
end component;
 
component TxUnit is
component TxUnit
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadA : in Std_Logic; -- Asynchronous Load
TxD : out Std_Logic; -- RS-232 data output
Busy : out Std_Logic; -- Tx Busy
DataI : in Std_Logic_Vector(7 downto 0)); -- Byte to transmit
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component;
 
signal RxData : Std_Logic_Vector(7 downto 0); -- Last Byte received
signal TxData : Std_Logic_Vector(7 downto 0); -- Last bytes transmitted
signal SReg : Std_Logic_Vector(7 downto 0); -- Status register
signal EnabRx : Std_Logic; -- Enable RX unit
signal EnabTx : Std_Logic; -- Enable TX unit
signal RxAv : Std_Logic; -- Data Received
signal TxBusy : Std_Logic; -- Transmiter Busy
signal ReadA : Std_Logic; -- Async Read receive buffer
signal LoadA : Std_Logic; -- Async Load transmit buffer
signal Sig0 : Std_Logic; -- gnd signal
signal Sig1 : Std_Logic; -- vcc signal
signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
signal SReg : std_logic_vector(7 downto 0); -- Status register
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
signal RxAv : std_logic; -- Data Received
signal TxBusy : std_logic; -- Transmiter Busy
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0 : std_logic; -- gnd signal
signal Sig1 : std_logic; -- vcc signal
begin
sig0 <= '0';
114,11 → 114,12
IntRx_O <= RxAv;
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
SReg(7 downto 2) <= "000000";
-- Implements WishBone data exchange.
-- Clocked on rising edge. Synchronous Reset RST_I
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
variable StatM : Std_Logic_Vector(4 downto 0);
variable StatM : std_logic_vector(4 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
if (WB_RST_I = '1') then
127,7 → 128,7
else
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
TxData <= WB_DAT_I;
LoadA <= '1'; -- Load signal
LoadA <= '1'; -- Load signal
else LoadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
136,10 → 137,10
end if;
end if;
end if;
end process;
end process;
WB_ACK_O <= WB_STB_I;
WB_DAT_O <=
RxData when WB_ADR_I = "00" else -- Read Byte from Rx
SReg when WB_ADR_I = "01" else -- Read Status Reg
X"00";
"00000000";
end Behaviour;
/trunk/rtl/vhdl/Txunit.vhd
7,10 → 7,10
-- (philippe.carton2@libertysurf.fr)
-- Organization:
-- Created : 15/12/2001
-- Last update : 6/05/2002
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : Foundation logic simulator
-- Synthesizers: Foundation Synopsys
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
34,28 → 34,28
 
entity TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadA : in Std_Logic; -- Asynchronous Load
TxD : out Std_Logic; -- RS-232 data output
Busy : out Std_Logic; -- Tx Busy
DataI : in Std_Logic_Vector(7 downto 0)); -- Byte to transmit
end entity;
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
end TxUnit;
 
architecture Behaviour of TxUnit is
 
component synchroniser is
component synchroniser
port (
C1 : in Std_Logic; -- Asynchronous signal
C : in Std_Logic; -- Clock
C1 : in std_logic; -- Asynchronous signal
C : in std_logic; -- Clock
O : out Std_logic);-- Synchronised signal
end component;
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal TBufL : Std_Logic; -- Buffer loaded
signal LoadS : Std_Logic; -- Synchronised load signal
signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer
signal TReg : std_logic_vector(7 downto 0); -- transmit register
signal TBufL : std_logic; -- Buffer loaded
signal LoadS : std_logic; -- Synchronised load signal
 
begin
-- Synchronise Load on Clk
69,8 → 69,8
if Reset = '1' then
TBufL <= '0';
BitPos := 0;
TxD <= '1';
elsif Rising_Edge(Clk) then
TxD <= '1';
elsif Rising_Edge(Clk) then
if LoadS = '1' then
TBuff <= DataI;
TBufL <= '1';
89,7 → 89,7
BitPos := 2;
when others =>
TxD <= TReg(BitPos-2); -- Serialisation of TReg
BitPos := BitPos + 1;
BitPos := BitPos + 1;
end case;
if BitPos = 10 then -- bit8. next is stop bit
BitPos := 0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.