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/trunk/impl/info.txt

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/trunk/impl/Xilinx_xcs10/XILINX.PDF

trunk/impl/Xilinx_xcs10/XILINX.PDF Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/xproj.ini =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xproj.ini (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xproj.ini (revision 19) @@ -0,0 +1,34 @@ +[Current] +Version=ver1 +Revision=rev1 + +[Version] +ver1= + +[time] +ver1=1042179817 + +[ver1.current] +current=rev1 + +[ver1] +rev1= + +[ver1.rev1] +family=SPARTAN +device=XCS10 +package=TQ144 +speed=-4 +state=Implemented +status=OK + +[Template] +ver1.rev1=Foundation EDIF + +[DataFiles] +Constraints=0,"ver1->rev1",1 +FloorPlaner=0,"ver1->rev1",1 +Guide=-1,"None",1 +GuideIdx=1 +FloorIdx=0 + Index: trunk/impl/Xilinx_xcs10/Xilinx/utils.log =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/utils.log (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/utils.log (revision 19) @@ -0,0 +1,2 @@ +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd file started. +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd file finished. Index: trunk/impl/Xilinx_xcs10/Xilinx/utils.vhd =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/utils.vhd (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/utils.vhd (revision 19) @@ -0,0 +1,132 @@ +------------------------------------------------------------------------------- +-- Title : UART +-- Project : UART +------------------------------------------------------------------------------- +-- File : utils.vhd +-- Author : Philippe CARTON +-- (philippe.carton2@libertysurf.fr) +-- Organization: +-- Created : 15/12/2001 +-- Last update : 8/1/2003 +-- Platform : Foundation 3.1i +-- Simulators : ModelSim 5.5b +-- Synthesizers: Xilinx Synthesis +-- Targets : Xilinx Spartan +-- Dependency : IEEE std_logic_1164 +------------------------------------------------------------------------------- +-- Description: VHDL utility file +------------------------------------------------------------------------------- +-- Copyright (c) notice +-- This core adheres to the GNU public license +-- +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : +-- Version : +-- Date : +-- Modifier : name +-- Description : +-- +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------- +-- Revision list +-- Version Author Date Changes +-- +-- 1.0 Philippe CARTON 19 December 2001 New model +-- philippe.carton2@libertysurf.fr +------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Synchroniser: +-- Synchronize an input signal (C1) with an input clock (C). +-- The result is the O signal which is synchronous of C, and persist for +-- one C clock period. +-------------------------------------------------------------------------------- +library IEEE,STD; +use IEEE.std_logic_1164.all; + +entity synchroniser is + port ( + C1 : in std_logic;-- Asynchronous signal + C : in std_logic;-- Clock + O : out std_logic);-- Synchronised signal +end synchroniser; + +architecture Behaviour of synchroniser is + signal C1A : std_logic; + signal C1S : std_logic; + signal R : std_logic; +begin + RiseC1A : process(C1,R) + begin + if Rising_Edge(C1) then + C1A <= '1'; + end if; + if (R = '1') then + C1A <= '0'; + end if; + end process; + + SyncP : process(C,R) + begin + if Rising_Edge(C) then + if (C1A = '1') then + C1S <= '1'; + else C1S <= '0'; + end if; + if (C1S = '1') then + R <= '1'; + else R <= '0'; + end if; + end if; + if (R = '1') then + C1S <= '0'; + end if; + end process; + O <= C1S; +end Behaviour; + +------------------------------------------------------------------------------- +-- Counter +-- This counter is a parametrizable clock divider. +-- The count value is the generic parameter Count. +-- It is CE enabled. (it will count only if CE is high). +-- When it overflow, it will emit a pulse on O. +-- It can be reseted to 0. +------------------------------------------------------------------------------- +library IEEE,STD; +use IEEE.std_logic_1164.all; + +entity Counter is + generic(Count: INTEGER range 0 to 65535); -- Count revolution + port ( + Clk : in std_logic; -- Clock + Reset : in std_logic; -- Reset input + CE : in std_logic; -- Chip Enable + O : out std_logic); -- Output +end Counter; + +architecture Behaviour of Counter is +begin + counter : process(Clk,Reset) + variable Cnt : INTEGER range 0 to Count-1; + begin + if Reset = '1' then + Cnt := Count - 1; + O <= '0'; + elsif Rising_Edge(Clk) then + if CE = '1' then + if Cnt = 0 then + O <= '1'; + Cnt := Count - 1; + else + O <= '0'; + Cnt := Cnt - 1; + end if; + else O <= '0'; + end if; + end if; + end process; +end Behaviour; Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ll =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ll (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ll (revision 19) @@ -0,0 +1,1154 @@ +Revision 3 +; Created by bitgen D.19 at Thu Jan 09 22:24:06 2003 +; Bit lines have the following form: +; +; may be zero or more = pairs +; Block= specifies the latch associated with this memory cell. +; +; Net= specifies the user net associated with this +; memory cell. +; +; COMPARE=[YES | NO] specifies whether or not it is appropriate +; to compare this bit position between a +; "program" and a "readback" bitstream. +; If not present the default is NO. +; +; Ram=: This is used in cases where a CLB function +; Rom=: generator is used as RAM (or ROM). +; will be either 'F', 'G', or 'M', indicating +; that it is part of a single F or G function +; generator used as RAM, or as a single RAM +; (or ROM) built from both F and G. is +; a decimal number. +; +; Info lines have the following form: +; Info = specifies a bit associated with the LCA +; configuration options, and the value of +; that bit. The names of these bits may have +; special meaning to software reading the .ll file. +; +Bit 21 1 140 Block=P76 Latch=I1 +Bit 31 1 130 Block=P78 Latch=I1 +Bit 41 1 120 Block=P80 Latch=I1 +Bit 51 1 110 Block=P83 Latch=I1 +Bit 61 1 100 Block=P85 Latch=I1 +Bit 71 1 90 Block=P87 Latch=I1 +Bit 81 1 80 Block=P89 Latch=I1 +Bit 92 1 69 Block=P93 Latch=I1 +Bit 102 1 59 Block=P95 Latch=I1 +Bit 112 1 49 Block=P97 Latch=I1 +Bit 122 1 39 Block=P99 Latch=I1 +Bit 132 1 29 Block=P102 Latch=I1 +Bit 142 1 19 Block=P104 Latch=I1 +Bit 152 1 9 Block=P106 Latch=I1 +Bit 337 3 146 Block=P75 Latch=OQ +Bit 343 3 140 Block=P76 Latch=I2 +Bit 347 3 136 Block=P77 Latch=OQ +Bit 353 3 130 Block=P78 Latch=I2 +Bit 357 3 126 Block=P79 Latch=OQ +Bit 363 3 120 Block=P80 Latch=I2 +Bit 367 3 116 Block=P82 Latch=OQ +Bit 373 3 110 Block=P83 Latch=I2 +Bit 377 3 106 Block=P84 Latch=OQ +Bit 383 3 100 Block=P85 Latch=I2 +Bit 387 3 96 Block=P86 Latch=OQ +Bit 393 3 90 Block=P87 Latch=I2 +Bit 397 3 86 Block=P88 Latch=OQ +Bit 403 3 80 Block=P89 Latch=I2 +Bit 408 3 75 Block=P92 Latch=OQ +Bit 414 3 69 Block=P93 Latch=I2 +Bit 418 3 65 Block=P94 Latch=OQ +Bit 424 3 59 Block=P95 Latch=I2 +Bit 428 3 55 Block=P96 Latch=OQ +Bit 434 3 49 Block=P97 Latch=I2 +Bit 438 3 45 Block=P98 Latch=OQ +Bit 444 3 39 Block=P99 Latch=I2 +Bit 448 3 35 Block=P101 Latch=OQ +Bit 454 3 29 Block=P102 Latch=I2 +Bit 458 3 25 Block=P103 Latch=OQ +Bit 464 3 19 Block=P104 Latch=I2 +Bit 468 3 15 Block=P105 Latch=OQ +Bit 474 3 9 Block=P106 Latch=I2 +Bit 499 4 145 Block=P75 Latch=I2 +Bit 504 4 140 Block=P76 Latch=OQ +Bit 509 4 135 Block=P77 Latch=I2 +Bit 514 4 130 Block=P78 Latch=OQ +Bit 519 4 125 Block=P79 Latch=I2 +Bit 524 4 120 Block=P80 Latch=OQ +Bit 529 4 115 Block=P82 Latch=I2 +Bit 534 4 110 Block=P83 Latch=OQ +Bit 539 4 105 Block=P84 Latch=I2 +Bit 544 4 100 Block=P85 Latch=OQ +Bit 549 4 95 Block=P86 Latch=I2 +Bit 554 4 90 Block=P87 Latch=OQ +Bit 559 4 85 Block=P88 Latch=I2 +Bit 564 4 80 Block=P89 Latch=OQ +Bit 570 4 74 Block=P92 Latch=I2 +Bit 575 4 69 Block=P93 Latch=OQ +Bit 580 4 64 Block=P94 Latch=I2 +Bit 585 4 59 Block=P95 Latch=OQ +Bit 590 4 54 Block=P96 Latch=I2 +Bit 595 4 49 Block=P97 Latch=OQ +Bit 600 4 44 Block=P98 Latch=I2 +Bit 605 4 39 Block=P99 Latch=OQ +Bit 610 4 34 Block=P101 Latch=I2 +Bit 615 4 29 Block=P102 Latch=OQ +Bit 620 4 24 Block=P103 Latch=I2 +Bit 625 4 19 Block=P104 Latch=OQ +Bit 630 4 14 Block=P105 Latch=I2 +Bit 635 4 9 Block=P106 Latch=OQ +Bit 660 5 145 Block=P75 Latch=I1 +Bit 670 5 135 Block=P77 Latch=I1 +Bit 680 5 125 Block=P79 Latch=I1 +Bit 690 5 115 Block=P82 Latch=I1 +Bit 700 5 105 Block=P84 Latch=I1 +Bit 710 5 95 Block=P86 Latch=I1 +Bit 720 5 85 Block=P88 Latch=I1 +Bit 731 5 74 Block=P92 Latch=I1 +Bit 741 5 64 Block=P94 Latch=I1 +Bit 751 5 54 Block=P96 Latch=I1 +Bit 761 5 44 Block=P98 Latch=I1 +Bit 771 5 34 Block=P101 Latch=I1 +Bit 781 5 24 Block=P103 Latch=I1 +Bit 791 5 14 Block=P105 Latch=I1 +Bit 7102 45 143 Block=CLB_R14C14 Latch=Y +Bit 7112 45 133 Block=CLB_R13C14 Latch=Y +Bit 7122 45 123 Block=CLB_R12C14 Latch=Y +Bit 7132 45 113 Block=CLB_R11C14 Latch=Y +Bit 7142 45 103 Block=CLB_R10C14 Latch=Y +Bit 7152 45 93 Block=CLB_R9C14 Latch=Y +Bit 7162 45 83 Block=CLB_R8C14 Latch=Y +Bit 7173 45 72 Block=CLB_R7C14 Latch=Y +Bit 7183 45 62 Block=CLB_R6C14 Latch=Y +Bit 7193 45 52 Block=CLB_R5C14 Latch=Y +Bit 7203 45 42 Block=CLB_R4C14 Latch=Y +Bit 7213 45 32 Block=CLB_R3C14 Latch=Y +Bit 7223 45 22 Block=CLB_R2C14 Latch=Y +Bit 7233 45 12 Block=CLB_R1C14 Latch=Y +Bit 7906 50 144 Block=CLB_R14C14 Latch=YQ +Bit 7916 50 134 Block=CLB_R13C14 Latch=YQ +Bit 7926 50 124 Block=CLB_R12C14 Latch=YQ +Bit 7936 50 114 Block=CLB_R11C14 Latch=YQ +Bit 7946 50 104 Block=CLB_R10C14 Latch=YQ +Bit 7956 50 94 Block=CLB_R9C14 Latch=YQ +Bit 7966 50 84 Block=CLB_R8C14 Latch=YQ +Bit 7977 50 73 Block=CLB_R7C14 Latch=YQ +Bit 7987 50 63 Block=CLB_R6C14 Latch=YQ +Bit 7997 50 53 Block=CLB_R5C14 Latch=YQ +Bit 8007 50 43 Block=CLB_R4C14 Latch=YQ +Bit 8017 50 33 Block=CLB_R3C14 Latch=YQ +Bit 8027 50 23 Block=CLB_R2C14 Latch=YQ +Bit 8037 50 13 Block=CLB_R1C14 Latch=YQ +Bit 8551 54 143 Block=CLB_R14C14 Latch=XQ +Bit 8561 54 133 Block=CLB_R13C14 Latch=XQ +Bit 8571 54 123 Block=CLB_R12C14 Latch=XQ +Bit 8581 54 113 Block=CLB_R11C14 Latch=XQ +Bit 8591 54 103 Block=CLB_R10C14 Latch=XQ +Bit 8601 54 93 Block=CLB_R9C14 Latch=XQ +Bit 8611 54 83 Block=CLB_R8C14 Latch=XQ +Bit 8622 54 72 Block=CLB_R7C14 Latch=XQ +Bit 8632 54 62 Block=CLB_R6C14 Latch=XQ +Bit 8642 54 52 Block=CLB_R5C14 Latch=XQ +Bit 8652 54 42 Block=CLB_R4C14 Latch=XQ +Bit 8662 54 32 Block=CLB_R3C14 Latch=XQ +Bit 8672 54 22 Block=CLB_R2C14 Latch=XQ +Bit 8682 54 12 Block=CLB_R1C14 Latch=XQ +Bit 8857 56 159 Block=P69 Latch=OQ +Bit 9013 56 3 Block=P112 Latch=OQ +Bit 9018 57 159 Block=P70 Latch=OQ +Bit 9174 57 3 Block=P111 Latch=OQ +Bit 9179 58 159 Block=P70 Latch=I1 +Bit 9194 58 144 Block=CLB_R14C14 Latch=X +Bit 9204 58 134 Block=CLB_R13C14 Latch=X +Bit 9214 58 124 Block=CLB_R12C14 Latch=X +Bit 9224 58 114 Block=CLB_R11C14 Latch=X +Bit 9234 58 104 Block=CLB_R10C14 Latch=X +Bit 9244 58 94 Block=CLB_R9C14 Latch=X +Bit 9254 58 84 Block=CLB_R8C14 Latch=X +Bit 9265 58 73 Block=CLB_R7C14 Latch=X +Bit 9275 58 63 Block=CLB_R6C14 Latch=X +Bit 9285 58 53 Block=CLB_R5C14 Latch=X +Bit 9295 58 43 Block=CLB_R4C14 Latch=X +Bit 9305 58 33 Block=CLB_R3C14 Latch=X +Bit 9315 58 23 Block=CLB_R2C14 Latch=X +Bit 9325 58 13 Block=CLB_R1C14 Latch=X +Bit 9335 58 3 Block=P111 Latch=I1 +Bit 9341 59 158 Block=P70 Latch=I2 +Bit 9495 59 4 Block=P111 Latch=I2 +Bit 9501 60 159 Block=P69 Latch=I2 +Bit 9502 60 158 Block=P69 Latch=I1 +Bit 9656 60 4 Block=P112 Latch=I1 +Bit 9657 60 3 Block=P112 Latch=I2 +Bit 12898 81 143 Block=CLB_R14C13 Latch=Y +Bit 12908 81 133 Block=CLB_R13C13 Latch=Y +Bit 12918 81 123 Block=CLB_R12C13 Latch=Y +Bit 12928 81 113 Block=CLB_R11C13 Latch=Y +Bit 12938 81 103 Block=CLB_R10C13 Latch=Y +Bit 12948 81 93 Block=CLB_R9C13 Latch=Y +Bit 12958 81 83 Block=CLB_R8C13 Latch=Y +Bit 12969 81 72 Block=CLB_R7C13 Latch=Y +Bit 12979 81 62 Block=CLB_R6C13 Latch=Y +Bit 12989 81 52 Block=CLB_R5C13 Latch=Y +Bit 12999 81 42 Block=CLB_R4C13 Latch=Y +Bit 13009 81 32 Block=CLB_R3C13 Latch=Y +Bit 13019 81 22 Block=CLB_R2C13 Latch=Y +Bit 13029 81 12 Block=CLB_R1C13 Latch=Y +Bit 13702 86 144 Block=CLB_R14C13 Latch=YQ +Bit 13712 86 134 Block=CLB_R13C13 Latch=YQ +Bit 13722 86 124 Block=CLB_R12C13 Latch=YQ +Bit 13732 86 114 Block=CLB_R11C13 Latch=YQ +Bit 13742 86 104 Block=CLB_R10C13 Latch=YQ +Bit 13752 86 94 Block=CLB_R9C13 Latch=YQ +Bit 13762 86 84 Block=CLB_R8C13 Latch=YQ +Bit 13773 86 73 Block=CLB_R7C13 Latch=YQ +Bit 13783 86 63 Block=CLB_R6C13 Latch=YQ +Bit 13793 86 53 Block=CLB_R5C13 Latch=YQ +Bit 13803 86 43 Block=CLB_R4C13 Latch=YQ +Bit 13813 86 33 Block=CLB_R3C13 Latch=YQ +Bit 13823 86 23 Block=CLB_R2C13 Latch=YQ +Bit 13833 86 13 Block=CLB_R1C13 Latch=YQ +Bit 14347 90 143 Block=CLB_R14C13 Latch=XQ +Bit 14357 90 133 Block=CLB_R13C13 Latch=XQ +Bit 14367 90 123 Block=CLB_R12C13 Latch=XQ +Bit 14377 90 113 Block=CLB_R11C13 Latch=XQ +Bit 14387 90 103 Block=CLB_R10C13 Latch=XQ +Bit 14397 90 93 Block=CLB_R9C13 Latch=XQ +Bit 14407 90 83 Block=CLB_R8C13 Latch=XQ +Bit 14418 90 72 Block=CLB_R7C13 Latch=XQ +Bit 14428 90 62 Block=CLB_R6C13 Latch=XQ +Bit 14438 90 52 Block=CLB_R5C13 Latch=XQ +Bit 14448 90 42 Block=CLB_R4C13 Latch=XQ +Bit 14458 90 32 Block=CLB_R3C13 Latch=XQ +Bit 14468 90 22 Block=CLB_R2C13 Latch=XQ +Bit 14478 90 12 Block=CLB_R1C13 Latch=XQ +Bit 14653 92 159 Block=P67 Latch=OQ +Bit 14809 92 3 Block=P114 Latch=OQ +Bit 14814 93 159 Block=P68 Latch=OQ +Bit 14970 93 3 Block=P113 Latch=OQ +Bit 14975 94 159 Block=P68 Latch=I1 +Bit 14990 94 144 Block=CLB_R14C13 Latch=X +Bit 15000 94 134 Block=CLB_R13C13 Latch=X +Bit 15010 94 124 Block=CLB_R12C13 Latch=X +Bit 15020 94 114 Block=CLB_R11C13 Latch=X +Bit 15030 94 104 Block=CLB_R10C13 Latch=X +Bit 15040 94 94 Block=CLB_R9C13 Latch=X +Bit 15050 94 84 Block=CLB_R8C13 Latch=X +Bit 15061 94 73 Block=CLB_R7C13 Latch=X +Bit 15071 94 63 Block=CLB_R6C13 Latch=X +Bit 15081 94 53 Block=CLB_R5C13 Latch=X +Bit 15091 94 43 Block=CLB_R4C13 Latch=X +Bit 15101 94 33 Block=CLB_R3C13 Latch=X +Bit 15111 94 23 Block=CLB_R2C13 Latch=X +Bit 15121 94 13 Block=CLB_R1C13 Latch=X +Bit 15131 94 3 Block=P113 Latch=I1 +Bit 15137 95 158 Block=P68 Latch=I2 +Bit 15291 95 4 Block=P113 Latch=I2 +Bit 15297 96 159 Block=P67 Latch=I2 +Bit 15298 96 158 Block=P67 Latch=I1 +Bit 15452 96 4 Block=P114 Latch=I1 +Bit 15453 96 3 Block=P114 Latch=I2 +Bit 18694 117 143 Block=CLB_R14C12 Latch=Y +Bit 18704 117 133 Block=CLB_R13C12 Latch=Y +Bit 18714 117 123 Block=CLB_R12C12 Latch=Y +Bit 18724 117 113 Block=CLB_R11C12 Latch=Y +Bit 18734 117 103 Block=CLB_R10C12 Latch=Y +Bit 18744 117 93 Block=CLB_R9C12 Latch=Y +Bit 18754 117 83 Block=CLB_R8C12 Latch=Y +Bit 18765 117 72 Block=CLB_R7C12 Latch=Y +Bit 18775 117 62 Block=CLB_R6C12 Latch=Y +Bit 18785 117 52 Block=CLB_R5C12 Latch=Y +Bit 18795 117 42 Block=CLB_R4C12 Latch=Y +Bit 18805 117 32 Block=CLB_R3C12 Latch=Y +Bit 18815 117 22 Block=CLB_R2C12 Latch=Y +Bit 18825 117 12 Block=CLB_R1C12 Latch=Y +Bit 19498 122 144 Block=CLB_R14C12 Latch=YQ +Bit 19508 122 134 Block=CLB_R13C12 Latch=YQ +Bit 19518 122 124 Block=CLB_R12C12 Latch=YQ +Bit 19528 122 114 Block=CLB_R11C12 Latch=YQ +Bit 19538 122 104 Block=CLB_R10C12 Latch=YQ +Bit 19548 122 94 Block=CLB_R9C12 Latch=YQ +Bit 19558 122 84 Block=CLB_R8C12 Latch=YQ +Bit 19569 122 73 Block=CLB_R7C12 Latch=YQ +Bit 19579 122 63 Block=CLB_R6C12 Latch=YQ +Bit 19589 122 53 Block=CLB_R5C12 Latch=YQ +Bit 19599 122 43 Block=CLB_R4C12 Latch=YQ +Bit 19609 122 33 Block=CLB_R3C12 Latch=YQ +Bit 19619 122 23 Block=CLB_R2C12 Latch=YQ +Bit 19629 122 13 Block=CLB_R1C12 Latch=YQ +Bit 20143 126 143 Block=CLB_R14C12 Latch=XQ +Bit 20153 126 133 Block=CLB_R13C12 Latch=XQ +Bit 20163 126 123 Block=CLB_R12C12 Latch=XQ +Bit 20173 126 113 Block=CLB_R11C12 Latch=XQ +Bit 20183 126 103 Block=CLB_R10C12 Latch=XQ +Bit 20193 126 93 Block=CLB_R9C12 Latch=XQ +Bit 20203 126 83 Block=CLB_R8C12 Latch=XQ +Bit 20214 126 72 Block=CLB_R7C12 Latch=XQ +Bit 20224 126 62 Block=CLB_R6C12 Latch=XQ +Bit 20234 126 52 Block=CLB_R5C12 Latch=XQ +Bit 20244 126 42 Block=CLB_R4C12 Latch=XQ +Bit 20254 126 32 Block=CLB_R3C12 Latch=XQ +Bit 20264 126 22 Block=CLB_R2C12 Latch=XQ +Bit 20274 126 12 Block=CLB_R1C12 Latch=XQ +Bit 20449 128 159 Block=P65 Latch=OQ +Bit 20605 128 3 Block=P116 Latch=OQ +Bit 20610 129 159 Block=P66 Latch=OQ +Bit 20766 129 3 Block=P115 Latch=OQ +Bit 20771 130 159 Block=P66 Latch=I1 +Bit 20786 130 144 Block=CLB_R14C12 Latch=X +Bit 20796 130 134 Block=CLB_R13C12 Latch=X +Bit 20806 130 124 Block=CLB_R12C12 Latch=X +Bit 20816 130 114 Block=CLB_R11C12 Latch=X +Bit 20826 130 104 Block=CLB_R10C12 Latch=X +Bit 20836 130 94 Block=CLB_R9C12 Latch=X +Bit 20846 130 84 Block=CLB_R8C12 Latch=X +Bit 20857 130 73 Block=CLB_R7C12 Latch=X +Bit 20867 130 63 Block=CLB_R6C12 Latch=X +Bit 20877 130 53 Block=CLB_R5C12 Latch=X +Bit 20887 130 43 Block=CLB_R4C12 Latch=X +Bit 20897 130 33 Block=CLB_R3C12 Latch=X +Bit 20907 130 23 Block=CLB_R2C12 Latch=X +Bit 20917 130 13 Block=CLB_R1C12 Latch=X +Bit 20927 130 3 Block=P115 Latch=I1 +Bit 20933 131 158 Block=P66 Latch=I2 +Bit 21087 131 4 Block=P115 Latch=I2 +Bit 21093 132 159 Block=P65 Latch=I2 +Bit 21094 132 158 Block=P65 Latch=I1 +Bit 21248 132 4 Block=P116 Latch=I1 +Bit 21249 132 3 Block=P116 Latch=I2 +Bit 24490 153 143 Block=CLB_R14C11 Latch=Y +Bit 24500 153 133 Block=CLB_R13C11 Latch=Y +Bit 24510 153 123 Block=CLB_R12C11 Latch=Y +Bit 24520 153 113 Block=CLB_R11C11 Latch=Y +Bit 24530 153 103 Block=CLB_R10C11 Latch=Y +Bit 24540 153 93 Block=CLB_R9C11 Latch=Y +Bit 24550 153 83 Block=CLB_R8C11 Latch=Y +Bit 24561 153 72 Block=CLB_R7C11 Latch=Y +Bit 24571 153 62 Block=CLB_R6C11 Latch=Y +Bit 24581 153 52 Block=CLB_R5C11 Latch=Y +Bit 24591 153 42 Block=CLB_R4C11 Latch=Y +Bit 24601 153 32 Block=CLB_R3C11 Latch=Y +Bit 24611 153 22 Block=CLB_R2C11 Latch=Y +Bit 24621 153 12 Block=CLB_R1C11 Latch=Y +Bit 25294 158 144 Block=CLB_R14C11 Latch=YQ +Bit 25304 158 134 Block=CLB_R13C11 Latch=YQ +Bit 25314 158 124 Block=CLB_R12C11 Latch=YQ +Bit 25324 158 114 Block=CLB_R11C11 Latch=YQ +Bit 25334 158 104 Block=CLB_R10C11 Latch=YQ +Bit 25344 158 94 Block=CLB_R9C11 Latch=YQ Net=Uart_Txrate/Cnt<1> +Bit 25354 158 84 Block=CLB_R8C11 Latch=YQ +Bit 25365 158 73 Block=CLB_R7C11 Latch=YQ +Bit 25375 158 63 Block=CLB_R6C11 Latch=YQ +Bit 25385 158 53 Block=CLB_R5C11 Latch=YQ +Bit 25395 158 43 Block=CLB_R4C11 Latch=YQ +Bit 25405 158 33 Block=CLB_R3C11 Latch=YQ +Bit 25415 158 23 Block=CLB_R2C11 Latch=YQ +Bit 25425 158 13 Block=CLB_R1C11 Latch=YQ +Bit 25939 162 143 Block=CLB_R14C11 Latch=XQ +Bit 25949 162 133 Block=CLB_R13C11 Latch=XQ +Bit 25959 162 123 Block=CLB_R12C11 Latch=XQ +Bit 25969 162 113 Block=CLB_R11C11 Latch=XQ +Bit 25979 162 103 Block=CLB_R10C11 Latch=XQ +Bit 25989 162 93 Block=CLB_R9C11 Latch=XQ Net=Uart_Txrate/Cnt<0> +Bit 25999 162 83 Block=CLB_R8C11 Latch=XQ Net=EnabTx +Bit 26010 162 72 Block=CLB_R7C11 Latch=XQ +Bit 26020 162 62 Block=CLB_R6C11 Latch=XQ +Bit 26030 162 52 Block=CLB_R5C11 Latch=XQ +Bit 26040 162 42 Block=CLB_R4C11 Latch=XQ +Bit 26050 162 32 Block=CLB_R3C11 Latch=XQ +Bit 26060 162 22 Block=CLB_R2C11 Latch=XQ +Bit 26070 162 12 Block=CLB_R1C11 Latch=XQ +Bit 26245 164 159 Block=P62 Latch=OQ +Bit 26401 164 3 Block=P120 Latch=OQ +Bit 26406 165 159 Block=P63 Latch=OQ +Bit 26562 165 3 Block=P119 Latch=OQ +Bit 26567 166 159 Block=P63 Latch=I1 +Bit 26582 166 144 Block=CLB_R14C11 Latch=X +Bit 26592 166 134 Block=CLB_R13C11 Latch=X +Bit 26602 166 124 Block=CLB_R12C11 Latch=X +Bit 26612 166 114 Block=CLB_R11C11 Latch=X +Bit 26622 166 104 Block=CLB_R10C11 Latch=X +Bit 26632 166 94 Block=CLB_R9C11 Latch=X +Bit 26642 166 84 Block=CLB_R8C11 Latch=X +Bit 26653 166 73 Block=CLB_R7C11 Latch=X +Bit 26663 166 63 Block=CLB_R6C11 Latch=X +Bit 26673 166 53 Block=CLB_R5C11 Latch=X +Bit 26683 166 43 Block=CLB_R4C11 Latch=X +Bit 26693 166 33 Block=CLB_R3C11 Latch=X +Bit 26703 166 23 Block=CLB_R2C11 Latch=X +Bit 26713 166 13 Block=CLB_R1C11 Latch=X +Bit 26723 166 3 Block=P119 Latch=I1 +Bit 26729 167 158 Block=P63 Latch=I2 +Bit 26883 167 4 Block=P119 Latch=I2 Net=N_WB_STB_I +Bit 26889 168 159 Block=P62 Latch=I2 +Bit 26890 168 158 Block=P62 Latch=I1 +Bit 27044 168 4 Block=P120 Latch=I1 +Bit 27045 168 3 Block=P120 Latch=I2 +Bit 30286 189 143 Block=CLB_R14C10 Latch=Y Net=C7/N11 +Bit 30296 189 133 Block=CLB_R13C10 Latch=Y +Bit 30306 189 123 Block=CLB_R12C10 Latch=Y +Bit 30316 189 113 Block=CLB_R11C10 Latch=Y +Bit 30326 189 103 Block=CLB_R10C10 Latch=Y +Bit 30336 189 93 Block=CLB_R9C10 Latch=Y +Bit 30346 189 83 Block=CLB_R8C10 Latch=Y +Bit 30357 189 72 Block=CLB_R7C10 Latch=Y +Bit 30367 189 62 Block=CLB_R6C10 Latch=Y +Bit 30377 189 52 Block=CLB_R5C10 Latch=Y +Bit 30387 189 42 Block=CLB_R4C10 Latch=Y +Bit 30397 189 32 Block=CLB_R3C10 Latch=Y +Bit 30407 189 22 Block=CLB_R2C10 Latch=Y +Bit 30417 189 12 Block=CLB_R1C10 Latch=Y +Bit 31090 194 144 Block=CLB_R14C10 Latch=YQ Net=RxData<7> +Bit 31100 194 134 Block=CLB_R13C10 Latch=YQ +Bit 31110 194 124 Block=CLB_R12C10 Latch=YQ +Bit 31120 194 114 Block=CLB_R11C10 Latch=YQ +Bit 31130 194 104 Block=CLB_R10C10 Latch=YQ +Bit 31140 194 94 Block=CLB_R9C10 Latch=YQ +Bit 31150 194 84 Block=CLB_R8C10 Latch=YQ +Bit 31161 194 73 Block=CLB_R7C10 Latch=YQ +Bit 31171 194 63 Block=CLB_R6C10 Latch=YQ +Bit 31181 194 53 Block=CLB_R5C10 Latch=YQ +Bit 31191 194 43 Block=CLB_R4C10 Latch=YQ +Bit 31201 194 33 Block=CLB_R3C10 Latch=YQ +Bit 31211 194 23 Block=CLB_R2C10 Latch=YQ +Bit 31221 194 13 Block=CLB_R1C10 Latch=YQ +Bit 31735 198 143 Block=CLB_R14C10 Latch=XQ Net=RxData<6> +Bit 31745 198 133 Block=CLB_R13C10 Latch=XQ +Bit 31755 198 123 Block=CLB_R12C10 Latch=XQ +Bit 31765 198 113 Block=CLB_R11C10 Latch=XQ +Bit 31775 198 103 Block=CLB_R10C10 Latch=XQ +Bit 31785 198 93 Block=CLB_R9C10 Latch=XQ +Bit 31795 198 83 Block=CLB_R8C10 Latch=XQ +Bit 31806 198 72 Block=CLB_R7C10 Latch=XQ +Bit 31816 198 62 Block=CLB_R6C10 Latch=XQ +Bit 31826 198 52 Block=CLB_R5C10 Latch=XQ +Bit 31836 198 42 Block=CLB_R4C10 Latch=XQ +Bit 31846 198 32 Block=CLB_R3C10 Latch=XQ +Bit 31856 198 22 Block=CLB_R2C10 Latch=XQ +Bit 31866 198 12 Block=CLB_R1C10 Latch=XQ Net=N299 +Bit 32041 200 159 Block=P60 Latch=OQ +Bit 32197 200 3 Block=P122 Latch=OQ +Bit 32202 201 159 Block=P61 Latch=OQ +Bit 32358 201 3 Block=P121 Latch=OQ +Bit 32363 202 159 Block=P61 Latch=I1 +Bit 32378 202 144 Block=CLB_R14C10 Latch=X Net=C7/N29 +Bit 32388 202 134 Block=CLB_R13C10 Latch=X +Bit 32398 202 124 Block=CLB_R12C10 Latch=X +Bit 32408 202 114 Block=CLB_R11C10 Latch=X +Bit 32418 202 104 Block=CLB_R10C10 Latch=X +Bit 32428 202 94 Block=CLB_R9C10 Latch=X +Bit 32438 202 84 Block=CLB_R8C10 Latch=X +Bit 32449 202 73 Block=CLB_R7C10 Latch=X +Bit 32459 202 63 Block=CLB_R6C10 Latch=X +Bit 32469 202 53 Block=CLB_R5C10 Latch=X +Bit 32479 202 43 Block=CLB_R4C10 Latch=X +Bit 32489 202 33 Block=CLB_R3C10 Latch=X +Bit 32499 202 23 Block=CLB_R2C10 Latch=X +Bit 32509 202 13 Block=CLB_R1C10 Latch=X Net=C5/N5 +Bit 32519 202 3 Block=P121 Latch=I1 +Bit 32525 203 158 Block=P61 Latch=I2 +Bit 32679 203 4 Block=P121 Latch=I2 +Bit 32685 204 159 Block=P60 Latch=I2 +Bit 32686 204 158 Block=P60 Latch=I1 +Bit 32840 204 4 Block=P122 Latch=I1 +Bit 32841 204 3 Block=P122 Latch=I2 Net=N_WB_WE_I +Bit 36082 225 143 Block=CLB_R14C9 Latch=Y Net=C7/N4 +Bit 36092 225 133 Block=CLB_R13C9 Latch=Y Net=C7/N17 +Bit 36102 225 123 Block=CLB_R12C9 Latch=Y +Bit 36112 225 113 Block=CLB_R11C9 Latch=Y Net=syn862 +Bit 36122 225 103 Block=CLB_R10C9 Latch=Y +Bit 36132 225 93 Block=CLB_R9C9 Latch=Y +Bit 36142 225 83 Block=CLB_R8C9 Latch=Y +Bit 36153 225 72 Block=CLB_R7C9 Latch=Y +Bit 36163 225 62 Block=CLB_R6C9 Latch=Y +Bit 36173 225 52 Block=CLB_R5C9 Latch=Y +Bit 36183 225 42 Block=CLB_R4C9 Latch=Y +Bit 36193 225 32 Block=CLB_R3C9 Latch=Y +Bit 36203 225 22 Block=CLB_R2C9 Latch=Y +Bit 36213 225 12 Block=CLB_R1C9 Latch=Y +Bit 36886 230 144 Block=CLB_R14C9 Latch=YQ Net=RxData<2> +Bit 36896 230 134 Block=CLB_R13C9 Latch=YQ Net=RxData<5> +Bit 36906 230 124 Block=CLB_R12C9 Latch=YQ Net=Uart_RxUnit/RReg<5> +Bit 36916 230 114 Block=CLB_R11C9 Latch=YQ +Bit 36926 230 104 Block=CLB_R10C9 Latch=YQ +Bit 36936 230 94 Block=CLB_R9C9 Latch=YQ +Bit 36946 230 84 Block=CLB_R8C9 Latch=YQ +Bit 36957 230 73 Block=CLB_R7C9 Latch=YQ +Bit 36967 230 63 Block=CLB_R6C9 Latch=YQ +Bit 36977 230 53 Block=CLB_R5C9 Latch=YQ +Bit 36987 230 43 Block=CLB_R4C9 Latch=YQ +Bit 36997 230 33 Block=CLB_R3C9 Latch=YQ +Bit 37007 230 23 Block=CLB_R2C9 Latch=YQ +Bit 37017 230 13 Block=CLB_R1C9 Latch=YQ +Bit 37531 234 143 Block=CLB_R14C9 Latch=XQ Net=RxData<3> +Bit 37541 234 133 Block=CLB_R13C9 Latch=XQ Net=RxData<4> +Bit 37551 234 123 Block=CLB_R12C9 Latch=XQ Net=Uart_RxUnit/RReg<4> +Bit 37561 234 113 Block=CLB_R11C9 Latch=XQ +Bit 37571 234 103 Block=CLB_R10C9 Latch=XQ +Bit 37581 234 93 Block=CLB_R9C9 Latch=XQ Net=N298 +Bit 37591 234 83 Block=CLB_R8C9 Latch=XQ +Bit 37602 234 72 Block=CLB_R7C9 Latch=XQ +Bit 37612 234 62 Block=CLB_R6C9 Latch=XQ +Bit 37622 234 52 Block=CLB_R5C9 Latch=XQ +Bit 37632 234 42 Block=CLB_R4C9 Latch=XQ +Bit 37642 234 32 Block=CLB_R3C9 Latch=XQ +Bit 37652 234 22 Block=CLB_R2C9 Latch=XQ Net=ReadA +Bit 37662 234 12 Block=CLB_R1C9 Latch=XQ +Bit 37837 236 159 Block=P58 Latch=OQ +Bit 37993 236 3 Block=P124 Latch=OQ +Bit 37998 237 159 Block=P59 Latch=OQ +Bit 38154 237 3 Block=P123 Latch=OQ +Bit 38159 238 159 Block=P59 Latch=I1 +Bit 38174 238 144 Block=CLB_R14C9 Latch=X Net=C7/N35 +Bit 38184 238 134 Block=CLB_R13C9 Latch=X Net=C7/N23 +Bit 38194 238 124 Block=CLB_R12C9 Latch=X +Bit 38204 238 114 Block=CLB_R11C9 Latch=X Net=syn903 +Bit 38214 238 104 Block=CLB_R10C9 Latch=X Net=syn1336 +Bit 38224 238 94 Block=CLB_R9C9 Latch=X +Bit 38234 238 84 Block=CLB_R8C9 Latch=X +Bit 38245 238 73 Block=CLB_R7C9 Latch=X +Bit 38255 238 63 Block=CLB_R6C9 Latch=X +Bit 38265 238 53 Block=CLB_R5C9 Latch=X +Bit 38275 238 43 Block=CLB_R4C9 Latch=X +Bit 38285 238 33 Block=CLB_R3C9 Latch=X +Bit 38295 238 23 Block=CLB_R2C9 Latch=X Net=Uart_RxUnit/n558 +Bit 38305 238 13 Block=CLB_R1C9 Latch=X +Bit 38315 238 3 Block=P123 Latch=I1 +Bit 38321 239 158 Block=P59 Latch=I2 +Bit 38475 239 4 Block=P123 Latch=I2 +Bit 38481 240 159 Block=P58 Latch=I2 +Bit 38482 240 158 Block=P58 Latch=I1 +Bit 38636 240 4 Block=P124 Latch=I1 +Bit 38637 240 3 Block=P124 Latch=I2 Net=N_WB_RST_I +Bit 41878 261 143 Block=CLB_R14C8 Latch=Y +Bit 41888 261 133 Block=CLB_R13C8 Latch=Y +Bit 41898 261 123 Block=CLB_R12C8 Latch=Y +Bit 41908 261 113 Block=CLB_R11C8 Latch=Y Net=syn883 +Bit 41918 261 103 Block=CLB_R10C8 Latch=Y Net=syn854 +Bit 41928 261 93 Block=CLB_R9C8 Latch=Y +Bit 41938 261 83 Block=CLB_R8C8 Latch=Y +Bit 41949 261 72 Block=CLB_R7C8 Latch=Y +Bit 41959 261 62 Block=CLB_R6C8 Latch=Y +Bit 41969 261 52 Block=CLB_R5C8 Latch=Y +Bit 41979 261 42 Block=CLB_R4C8 Latch=Y +Bit 41989 261 32 Block=CLB_R3C8 Latch=Y +Bit 41999 261 22 Block=CLB_R2C8 Latch=Y +Bit 42009 261 12 Block=CLB_R1C8 Latch=Y +Bit 42682 266 144 Block=CLB_R14C8 Latch=YQ Net=Uart_RxUnit/RReg<3> +Bit 42692 266 134 Block=CLB_R13C8 Latch=YQ Net=Uart_RxUnit/RReg<7> +Bit 42702 266 124 Block=CLB_R12C8 Latch=YQ Net=Uart_RxUnit/RReg<1> +Bit 42712 266 114 Block=CLB_R11C8 Latch=YQ +Bit 42722 266 104 Block=CLB_R10C8 Latch=YQ +Bit 42732 266 94 Block=CLB_R9C8 Latch=YQ Net=Uart_RxUnit/BitPos<2> +Bit 42742 266 84 Block=CLB_R8C8 Latch=YQ +Bit 42753 266 73 Block=CLB_R7C8 Latch=YQ +Bit 42763 266 63 Block=CLB_R6C8 Latch=YQ +Bit 42773 266 53 Block=CLB_R5C8 Latch=YQ +Bit 42783 266 43 Block=CLB_R4C8 Latch=YQ +Bit 42793 266 33 Block=CLB_R3C8 Latch=YQ +Bit 42803 266 23 Block=CLB_R2C8 Latch=YQ +Bit 42813 266 13 Block=CLB_R1C8 Latch=YQ +Bit 43327 270 143 Block=CLB_R14C8 Latch=XQ Net=Uart_RxUnit/RReg<2> +Bit 43337 270 133 Block=CLB_R13C8 Latch=XQ Net=Uart_RxUnit/RReg<6> +Bit 43347 270 123 Block=CLB_R12C8 Latch=XQ Net=Uart_RxUnit/RReg<0> +Bit 43357 270 113 Block=CLB_R11C8 Latch=XQ +Bit 43367 270 103 Block=CLB_R10C8 Latch=XQ Net=Uart_RxUnit/BitPos<0> +Bit 43377 270 93 Block=CLB_R9C8 Latch=XQ Net=Uart_RxUnit/BitPos<1> +Bit 43387 270 83 Block=CLB_R8C8 Latch=XQ +Bit 43398 270 72 Block=CLB_R7C8 Latch=XQ +Bit 43408 270 62 Block=CLB_R6C8 Latch=XQ +Bit 43418 270 52 Block=CLB_R5C8 Latch=XQ +Bit 43428 270 42 Block=CLB_R4C8 Latch=XQ +Bit 43438 270 32 Block=CLB_R3C8 Latch=XQ +Bit 43448 270 22 Block=CLB_R2C8 Latch=XQ +Bit 43458 270 12 Block=CLB_R1C8 Latch=XQ +Bit 43633 272 159 Block=P56 Latch=OQ +Bit 43789 272 3 Block=P126 Latch=OQ +Bit 43794 273 159 Block=P57 Latch=OQ +Bit 43950 273 3 Block=P125 Latch=OQ +Bit 43955 274 159 Block=P57 Latch=I1 +Bit 43970 274 144 Block=CLB_R14C8 Latch=X +Bit 43980 274 134 Block=CLB_R13C8 Latch=X +Bit 43990 274 124 Block=CLB_R12C8 Latch=X +Bit 44000 274 114 Block=CLB_R11C8 Latch=X Net=syn893 +Bit 44010 274 104 Block=CLB_R10C8 Latch=X Net=Uart_RxUnit/C315 +Bit 44020 274 94 Block=CLB_R9C8 Latch=X +Bit 44030 274 84 Block=CLB_R8C8 Latch=X +Bit 44041 274 73 Block=CLB_R7C8 Latch=X +Bit 44051 274 63 Block=CLB_R6C8 Latch=X +Bit 44061 274 53 Block=CLB_R5C8 Latch=X +Bit 44071 274 43 Block=CLB_R4C8 Latch=X +Bit 44081 274 33 Block=CLB_R3C8 Latch=X +Bit 44091 274 23 Block=CLB_R2C8 Latch=X +Bit 44101 274 13 Block=CLB_R1C8 Latch=X +Bit 44111 274 3 Block=P125 Latch=I1 +Bit 44117 275 158 Block=P57 Latch=I2 +Bit 44271 275 4 Block=P125 Latch=I2 +Bit 44277 276 159 Block=P56 Latch=I2 +Bit 44278 276 158 Block=P56 Latch=I1 Net=N_RxD_PAD_I +Bit 44432 276 4 Block=P126 Latch=I1 +Bit 44433 276 3 Block=P126 Latch=I2 +Bit 47835 298 143 Block=CLB_R14C7 Latch=Y Net=C7/N45 +Bit 47845 298 133 Block=CLB_R13C7 Latch=Y +Bit 47855 298 123 Block=CLB_R12C7 Latch=Y +Bit 47865 298 113 Block=CLB_R11C7 Latch=Y +Bit 47875 298 103 Block=CLB_R10C7 Latch=Y Net=syn944 +Bit 47885 298 93 Block=CLB_R9C7 Latch=Y Net=Uart_RxUnit/C13/N3 +Bit 47895 298 83 Block=CLB_R8C7 Latch=Y +Bit 47906 298 72 Block=CLB_R7C7 Latch=Y +Bit 47916 298 62 Block=CLB_R6C7 Latch=Y +Bit 47926 298 52 Block=CLB_R5C7 Latch=Y +Bit 47936 298 42 Block=CLB_R4C7 Latch=Y +Bit 47946 298 32 Block=CLB_R3C7 Latch=Y +Bit 47956 298 22 Block=CLB_R2C7 Latch=Y +Bit 47966 298 12 Block=CLB_R1C7 Latch=Y +Bit 48639 303 144 Block=CLB_R14C7 Latch=YQ Net=N_IntRx_O +Bit 48649 303 134 Block=CLB_R13C7 Latch=YQ Net=RxData<1> +Bit 48659 303 124 Block=CLB_R12C7 Latch=YQ +Bit 48669 303 114 Block=CLB_R11C7 Latch=YQ +Bit 48679 303 104 Block=CLB_R10C7 Latch=YQ +Bit 48689 303 94 Block=CLB_R9C7 Latch=YQ +Bit 48699 303 84 Block=CLB_R8C7 Latch=YQ Net=Uart_RxUnit/SampleCnt<1> +Bit 48710 303 73 Block=CLB_R7C7 Latch=YQ +Bit 48720 303 63 Block=CLB_R6C7 Latch=YQ +Bit 48730 303 53 Block=CLB_R5C7 Latch=YQ +Bit 48740 303 43 Block=CLB_R4C7 Latch=YQ +Bit 48750 303 33 Block=CLB_R3C7 Latch=YQ +Bit 48760 303 23 Block=CLB_R2C7 Latch=YQ +Bit 48770 303 13 Block=CLB_R1C7 Latch=YQ +Bit 49284 307 143 Block=CLB_R14C7 Latch=XQ +Bit 49294 307 133 Block=CLB_R13C7 Latch=XQ Net=RxData<0> +Bit 49304 307 123 Block=CLB_R12C7 Latch=XQ +Bit 49314 307 113 Block=CLB_R11C7 Latch=XQ Net=Uart_RxUnit/BitPos<3> +Bit 49324 307 103 Block=CLB_R10C7 Latch=XQ +Bit 49334 307 93 Block=CLB_R9C7 Latch=XQ +Bit 49344 307 83 Block=CLB_R8C7 Latch=XQ Net=Uart_RxUnit/SampleCnt<0> +Bit 49355 307 72 Block=CLB_R7C7 Latch=XQ +Bit 49365 307 62 Block=CLB_R6C7 Latch=XQ +Bit 49375 307 52 Block=CLB_R5C7 Latch=XQ +Bit 49385 307 42 Block=CLB_R4C7 Latch=XQ +Bit 49395 307 32 Block=CLB_R3C7 Latch=XQ +Bit 49405 307 22 Block=CLB_R2C7 Latch=XQ +Bit 49415 307 12 Block=CLB_R1C7 Latch=XQ +Bit 49590 309 159 Block=P52 Latch=OQ +Bit 49746 309 3 Block=P130 Latch=OQ +Bit 49751 310 159 Block=P53 Latch=OQ +Bit 49907 310 3 Block=P129 Latch=OQ +Bit 49912 311 159 Block=P53 Latch=I1 +Bit 49927 311 144 Block=CLB_R14C7 Latch=X Net=C37 +Bit 49937 311 134 Block=CLB_R13C7 Latch=X Net=C7/N52 +Bit 49947 311 124 Block=CLB_R12C7 Latch=X +Bit 49957 311 114 Block=CLB_R11C7 Latch=X Net=syn878 +Bit 49967 311 104 Block=CLB_R10C7 Latch=X Net=syn1466 +Bit 49977 311 94 Block=CLB_R9C7 Latch=X Net=Uart_RxUnit/C15/N19 +Bit 49987 311 84 Block=CLB_R8C7 Latch=X +Bit 49998 311 73 Block=CLB_R7C7 Latch=X +Bit 50008 311 63 Block=CLB_R6C7 Latch=X +Bit 50018 311 53 Block=CLB_R5C7 Latch=X +Bit 50028 311 43 Block=CLB_R4C7 Latch=X +Bit 50038 311 33 Block=CLB_R3C7 Latch=X +Bit 50048 311 23 Block=CLB_R2C7 Latch=X +Bit 50058 311 13 Block=CLB_R1C7 Latch=X +Bit 50068 311 3 Block=P129 Latch=I1 +Bit 50074 312 158 Block=P53 Latch=I2 Net=N_WB_ADR_I<0> +Bit 50228 312 4 Block=P129 Latch=I2 +Bit 50234 313 159 Block=P52 Latch=I2 +Bit 50235 313 158 Block=P52 Latch=I1 Net=N_WB_ADR_I<1> +Bit 50389 313 4 Block=P130 Latch=I1 +Bit 50390 313 3 Block=P130 Latch=I2 Net=TxData<7> +Bit 53631 334 143 Block=CLB_R14C6 Latch=Y +Bit 53641 334 133 Block=CLB_R13C6 Latch=Y +Bit 53651 334 123 Block=CLB_R12C6 Latch=Y +Bit 53661 334 113 Block=CLB_R11C6 Latch=Y +Bit 53671 334 103 Block=CLB_R10C6 Latch=Y +Bit 53681 334 93 Block=CLB_R9C6 Latch=Y +Bit 53691 334 83 Block=CLB_R8C6 Latch=Y Net=Uart_RxUnit/C11/N5 +Bit 53702 334 72 Block=CLB_R7C6 Latch=Y +Bit 53712 334 62 Block=CLB_R6C6 Latch=Y Net=syn755 +Bit 53722 334 52 Block=CLB_R5C6 Latch=Y +Bit 53732 334 42 Block=CLB_R4C6 Latch=Y +Bit 53742 334 32 Block=CLB_R3C6 Latch=Y +Bit 53752 334 22 Block=CLB_R2C6 Latch=Y +Bit 53762 334 12 Block=CLB_R1C6 Latch=Y +Bit 54435 339 144 Block=CLB_R14C6 Latch=YQ +Bit 54445 339 134 Block=CLB_R13C6 Latch=YQ +Bit 54455 339 124 Block=CLB_R12C6 Latch=YQ +Bit 54465 339 114 Block=CLB_R11C6 Latch=YQ +Bit 54475 339 104 Block=CLB_R10C6 Latch=YQ Net=Uart_TxUnit/SyncLoad/C1A +Bit 54485 339 94 Block=CLB_R9C6 Latch=YQ +Bit 54495 339 84 Block=CLB_R8C6 Latch=YQ +Bit 54506 339 73 Block=CLB_R7C6 Latch=YQ Net=Uart_TxUnit/BitPos<3> +Bit 54516 339 63 Block=CLB_R6C6 Latch=YQ Net=Uart_TxUnit/TReg<3> +Bit 54526 339 53 Block=CLB_R5C6 Latch=YQ Net=Uart_TxUnit/TReg<6> +Bit 54536 339 43 Block=CLB_R4C6 Latch=YQ Net=Uart_TxUnit/TBuff<7> +Bit 54546 339 33 Block=CLB_R3C6 Latch=YQ Net=Uart_TxUnit/TBuff<2> +Bit 54556 339 23 Block=CLB_R2C6 Latch=YQ +Bit 54566 339 13 Block=CLB_R1C6 Latch=YQ +Bit 55080 343 143 Block=CLB_R14C6 Latch=XQ +Bit 55090 343 133 Block=CLB_R13C6 Latch=XQ +Bit 55100 343 123 Block=CLB_R12C6 Latch=XQ +Bit 55110 343 113 Block=CLB_R11C6 Latch=XQ +Bit 55120 343 103 Block=CLB_R10C6 Latch=XQ +Bit 55130 343 93 Block=CLB_R9C6 Latch=XQ +Bit 55140 343 83 Block=CLB_R8C6 Latch=XQ +Bit 55151 343 72 Block=CLB_R7C6 Latch=XQ Net=Uart_TxUnit/BitPos<2> +Bit 55161 343 62 Block=CLB_R6C6 Latch=XQ Net=Uart_TxUnit/TReg<2> +Bit 55171 343 52 Block=CLB_R5C6 Latch=XQ Net=Uart_TxUnit/TReg<7> +Bit 55181 343 42 Block=CLB_R4C6 Latch=XQ Net=Uart_TxUnit/TBuff<6> +Bit 55191 343 32 Block=CLB_R3C6 Latch=XQ Net=Uart_TxUnit/TBuff<3> +Bit 55201 343 22 Block=CLB_R2C6 Latch=XQ +Bit 55211 343 12 Block=CLB_R1C6 Latch=XQ +Bit 55386 345 159 Block=P50 Latch=OQ +Bit 55542 345 3 Block=P132 Latch=OQ +Bit 55547 346 159 Block=P51 Latch=OQ +Bit 55703 346 3 Block=P131 Latch=OQ +Bit 55708 347 159 Block=P51 Latch=I1 +Bit 55723 347 144 Block=CLB_R14C6 Latch=X +Bit 55733 347 134 Block=CLB_R13C6 Latch=X +Bit 55743 347 124 Block=CLB_R12C6 Latch=X +Bit 55753 347 114 Block=CLB_R11C6 Latch=X +Bit 55763 347 104 Block=CLB_R10C6 Latch=X +Bit 55773 347 94 Block=CLB_R9C6 Latch=X Net=Uart_RxUnit/C12/N5 +Bit 55783 347 84 Block=CLB_R8C6 Latch=X Net=Uart_RxUnit/C10/N10 +Bit 55794 347 73 Block=CLB_R7C6 Latch=X +Bit 55804 347 63 Block=CLB_R6C6 Latch=X Net=syn1134 +Bit 55814 347 53 Block=CLB_R5C6 Latch=X +Bit 55824 347 43 Block=CLB_R4C6 Latch=X +Bit 55834 347 33 Block=CLB_R3C6 Latch=X +Bit 55844 347 23 Block=CLB_R2C6 Latch=X +Bit 55854 347 13 Block=CLB_R1C6 Latch=X +Bit 55864 347 3 Block=P131 Latch=I1 +Bit 55870 348 158 Block=P51 Latch=I2 +Bit 56024 348 4 Block=P131 Latch=I2 Net=TxData<2> +Bit 56030 349 159 Block=P50 Latch=I2 +Bit 56031 349 158 Block=P50 Latch=I1 +Bit 56185 349 4 Block=P132 Latch=I1 +Bit 56186 349 3 Block=P132 Latch=I2 Net=TxData<3> +Bit 59427 370 143 Block=CLB_R14C5 Latch=Y +Bit 59437 370 133 Block=CLB_R13C5 Latch=Y +Bit 59447 370 123 Block=CLB_R12C5 Latch=Y +Bit 59457 370 113 Block=CLB_R11C5 Latch=Y +Bit 59467 370 103 Block=CLB_R10C5 Latch=Y Net=N296 +Bit 59477 370 93 Block=CLB_R9C5 Latch=Y Net=Uart_TxUnit/C11/N6 +Bit 59487 370 83 Block=CLB_R8C5 Latch=Y Net=Uart_TxUnit/C14/N19 +Bit 59498 370 72 Block=CLB_R7C5 Latch=Y +Bit 59508 370 62 Block=CLB_R6C5 Latch=Y +Bit 59518 370 52 Block=CLB_R5C5 Latch=Y +Bit 59528 370 42 Block=CLB_R4C5 Latch=Y +Bit 59538 370 32 Block=CLB_R3C5 Latch=Y Net=Uart_Rxrate/C64 +Bit 59548 370 22 Block=CLB_R2C5 Latch=Y +Bit 59558 370 12 Block=CLB_R1C5 Latch=Y +Bit 60231 375 144 Block=CLB_R14C5 Latch=YQ +Bit 60241 375 134 Block=CLB_R13C5 Latch=YQ +Bit 60251 375 124 Block=CLB_R12C5 Latch=YQ +Bit 60261 375 114 Block=CLB_R11C5 Latch=YQ +Bit 60271 375 104 Block=CLB_R10C5 Latch=YQ Net=Uart_TxUnit/SyncLoad/R +Bit 60281 375 94 Block=CLB_R9C5 Latch=YQ +Bit 60291 375 84 Block=CLB_R8C5 Latch=YQ +Bit 60302 375 73 Block=CLB_R7C5 Latch=YQ Net=Uart_TxUnit/BitPos<1> +Bit 60312 375 63 Block=CLB_R6C5 Latch=YQ +Bit 60322 375 53 Block=CLB_R5C5 Latch=YQ +Bit 60332 375 43 Block=CLB_R4C5 Latch=YQ Net=Uart_TxUnit/TReg<1> +Bit 60342 375 33 Block=CLB_R3C5 Latch=YQ Net=EnabRx +Bit 60352 375 23 Block=CLB_R2C5 Latch=YQ Net=Uart_Rxrate/Cnt<6> +Bit 60362 375 13 Block=CLB_R1C5 Latch=YQ Net=Uart_Rxrate/Cnt<4> +Bit 60876 379 143 Block=CLB_R14C5 Latch=XQ +Bit 60886 379 133 Block=CLB_R13C5 Latch=XQ +Bit 60896 379 123 Block=CLB_R12C5 Latch=XQ +Bit 60906 379 113 Block=CLB_R11C5 Latch=XQ +Bit 60916 379 103 Block=CLB_R10C5 Latch=XQ Net=Uart_TxUnit/LoadS +Bit 60926 379 93 Block=CLB_R9C5 Latch=XQ +Bit 60936 379 83 Block=CLB_R8C5 Latch=XQ Net=Uart_TxUnit/TBufL +Bit 60947 379 72 Block=CLB_R7C5 Latch=XQ Net=Uart_TxUnit/BitPos<0> +Bit 60957 379 62 Block=CLB_R6C5 Latch=XQ Net=N_TxD_PAD_O +Bit 60967 379 52 Block=CLB_R5C5 Latch=XQ +Bit 60977 379 42 Block=CLB_R4C5 Latch=XQ Net=Uart_TxUnit/TReg<0> +Bit 60987 379 32 Block=CLB_R3C5 Latch=XQ Net=Uart_Rxrate/Cnt<7> +Bit 60997 379 22 Block=CLB_R2C5 Latch=XQ Net=Uart_Rxrate/Cnt<5> +Bit 61007 379 12 Block=CLB_R1C5 Latch=XQ Net=Uart_Rxrate/Cnt<3> +Bit 61182 381 159 Block=P48 Latch=OQ +Bit 61338 381 3 Block=P134 Latch=OQ +Bit 61343 382 159 Block=P49 Latch=OQ +Bit 61499 382 3 Block=P133 Latch=OQ +Bit 61504 383 159 Block=P49 Latch=I1 +Bit 61519 383 144 Block=CLB_R14C5 Latch=X +Bit 61529 383 134 Block=CLB_R13C5 Latch=X +Bit 61539 383 124 Block=CLB_R12C5 Latch=X Net=GLOBAL_LOGIC1_0 +Bit 61549 383 114 Block=CLB_R11C5 Latch=X +Bit 61559 383 104 Block=CLB_R10C5 Latch=X Net=Uart_TxUnit/C8/N5 +Bit 61569 383 94 Block=CLB_R9C5 Latch=X Net=Uart_TxUnit/C9/N5 +Bit 61579 383 84 Block=CLB_R8C5 Latch=X Net=Uart_TxUnit/C10/N6 +Bit 61590 383 73 Block=CLB_R7C5 Latch=X +Bit 61600 383 63 Block=CLB_R6C5 Latch=X +Bit 61610 383 53 Block=CLB_R5C5 Latch=X Net=syn785 +Bit 61620 383 43 Block=CLB_R4C5 Latch=X Net=syn1133 +Bit 61630 383 33 Block=CLB_R3C5 Latch=X +Bit 61640 383 23 Block=CLB_R2C5 Latch=X +Bit 61650 383 13 Block=CLB_R1C5 Latch=X +Bit 61660 383 3 Block=P133 Latch=I1 +Bit 61666 384 158 Block=P49 Latch=I2 +Bit 61820 384 4 Block=P133 Latch=I2 Net=TxData<6> +Bit 61826 385 159 Block=P48 Latch=I2 +Bit 61827 385 158 Block=P48 Latch=I1 +Bit 61981 385 4 Block=P134 Latch=I1 +Bit 61982 385 3 Block=P134 Latch=I2 Net=TxData<0> +Bit 65223 406 143 Block=CLB_R14C4 Latch=Y +Bit 65233 406 133 Block=CLB_R13C4 Latch=Y +Bit 65243 406 123 Block=CLB_R12C4 Latch=Y +Bit 65253 406 113 Block=CLB_R11C4 Latch=Y +Bit 65263 406 103 Block=CLB_R10C4 Latch=Y +Bit 65273 406 93 Block=CLB_R9C4 Latch=Y +Bit 65283 406 83 Block=CLB_R8C4 Latch=Y +Bit 65294 406 72 Block=CLB_R7C4 Latch=Y +Bit 65304 406 62 Block=CLB_R6C4 Latch=Y +Bit 65314 406 52 Block=CLB_R5C4 Latch=Y +Bit 65324 406 42 Block=CLB_R4C4 Latch=Y +Bit 65334 406 32 Block=CLB_R3C4 Latch=Y Net=Uart_Rxrate/C67 +Bit 65344 406 22 Block=CLB_R2C4 Latch=Y +Bit 65354 406 12 Block=CLB_R1C4 Latch=Y +Bit 66027 411 144 Block=CLB_R14C4 Latch=YQ +Bit 66037 411 134 Block=CLB_R13C4 Latch=YQ +Bit 66047 411 124 Block=CLB_R12C4 Latch=YQ +Bit 66057 411 114 Block=CLB_R11C4 Latch=YQ +Bit 66067 411 104 Block=CLB_R10C4 Latch=YQ +Bit 66077 411 94 Block=CLB_R9C4 Latch=YQ +Bit 66087 411 84 Block=CLB_R8C4 Latch=YQ +Bit 66098 411 73 Block=CLB_R7C4 Latch=YQ +Bit 66108 411 63 Block=CLB_R6C4 Latch=YQ Net=Uart_TxUnit/TReg<4> +Bit 66118 411 53 Block=CLB_R5C4 Latch=YQ Net=Uart_TxUnit/TBuff<5> +Bit 66128 411 43 Block=CLB_R4C4 Latch=YQ Net=Uart_TxUnit/TBuff<1> +Bit 66138 411 33 Block=CLB_R3C4 Latch=YQ +Bit 66148 411 23 Block=CLB_R2C4 Latch=YQ Net=Uart_Rxrate/Cnt<0> +Bit 66158 411 13 Block=CLB_R1C4 Latch=YQ Net=Uart_Rxrate/Cnt<2> +Bit 66672 415 143 Block=CLB_R14C4 Latch=XQ +Bit 66682 415 133 Block=CLB_R13C4 Latch=XQ +Bit 66692 415 123 Block=CLB_R12C4 Latch=XQ +Bit 66702 415 113 Block=CLB_R11C4 Latch=XQ +Bit 66712 415 103 Block=CLB_R10C4 Latch=XQ +Bit 66722 415 93 Block=CLB_R9C4 Latch=XQ +Bit 66732 415 83 Block=CLB_R8C4 Latch=XQ +Bit 66743 415 72 Block=CLB_R7C4 Latch=XQ +Bit 66753 415 62 Block=CLB_R6C4 Latch=XQ Net=Uart_TxUnit/TReg<5> +Bit 66763 415 52 Block=CLB_R5C4 Latch=XQ Net=Uart_TxUnit/TBuff<4> +Bit 66773 415 42 Block=CLB_R4C4 Latch=XQ Net=Uart_TxUnit/TBuff<0> +Bit 66783 415 32 Block=CLB_R3C4 Latch=XQ +Bit 66793 415 22 Block=CLB_R2C4 Latch=XQ +Bit 66803 415 12 Block=CLB_R1C4 Latch=XQ Net=Uart_Rxrate/Cnt<1> +Bit 66978 417 159 Block=P46 Latch=OQ +Bit 67134 417 3 Block=P136 Latch=OQ +Bit 67139 418 159 Block=P47 Latch=OQ +Bit 67295 418 3 Block=P135 Latch=OQ +Bit 67300 419 159 Block=P47 Latch=I1 +Bit 67315 419 144 Block=CLB_R14C4 Latch=X +Bit 67325 419 134 Block=CLB_R13C4 Latch=X +Bit 67335 419 124 Block=CLB_R12C4 Latch=X +Bit 67345 419 114 Block=CLB_R11C4 Latch=X +Bit 67355 419 104 Block=CLB_R10C4 Latch=X +Bit 67365 419 94 Block=CLB_R9C4 Latch=X +Bit 67375 419 84 Block=CLB_R8C4 Latch=X +Bit 67386 419 73 Block=CLB_R7C4 Latch=X +Bit 67396 419 63 Block=CLB_R6C4 Latch=X +Bit 67406 419 53 Block=CLB_R5C4 Latch=X +Bit 67416 419 43 Block=CLB_R4C4 Latch=X +Bit 67426 419 33 Block=CLB_R3C4 Latch=X +Bit 67436 419 23 Block=CLB_R2C4 Latch=X +Bit 67446 419 13 Block=CLB_R1C4 Latch=X +Bit 67456 419 3 Block=P135 Latch=I1 +Bit 67462 420 158 Block=P47 Latch=I2 +Bit 67616 420 4 Block=P135 Latch=I2 Net=TxData<5> +Bit 67622 421 159 Block=P46 Latch=I2 +Bit 67623 421 158 Block=P46 Latch=I1 +Bit 67777 421 4 Block=P136 Latch=I1 +Bit 67778 421 3 Block=P136 Latch=I2 Net=TxData<4> +Bit 71019 442 143 Block=CLB_R14C3 Latch=Y +Bit 71029 442 133 Block=CLB_R13C3 Latch=Y +Bit 71039 442 123 Block=CLB_R12C3 Latch=Y +Bit 71049 442 113 Block=CLB_R11C3 Latch=Y Net=GLOBAL_LOGIC1 +Bit 71059 442 103 Block=CLB_R10C3 Latch=Y +Bit 71069 442 93 Block=CLB_R9C3 Latch=Y +Bit 71079 442 83 Block=CLB_R8C3 Latch=Y +Bit 71090 442 72 Block=CLB_R7C3 Latch=Y +Bit 71100 442 62 Block=CLB_R6C3 Latch=Y +Bit 71110 442 52 Block=CLB_R5C3 Latch=Y +Bit 71120 442 42 Block=CLB_R4C3 Latch=Y +Bit 71130 442 32 Block=CLB_R3C3 Latch=Y +Bit 71140 442 22 Block=CLB_R2C3 Latch=Y +Bit 71150 442 12 Block=CLB_R1C3 Latch=Y +Bit 71823 447 144 Block=CLB_R14C3 Latch=YQ +Bit 71833 447 134 Block=CLB_R13C3 Latch=YQ +Bit 71843 447 124 Block=CLB_R12C3 Latch=YQ +Bit 71853 447 114 Block=CLB_R11C3 Latch=YQ +Bit 71863 447 104 Block=CLB_R10C3 Latch=YQ +Bit 71873 447 94 Block=CLB_R9C3 Latch=YQ +Bit 71883 447 84 Block=CLB_R8C3 Latch=YQ +Bit 71894 447 73 Block=CLB_R7C3 Latch=YQ +Bit 71904 447 63 Block=CLB_R6C3 Latch=YQ +Bit 71914 447 53 Block=CLB_R5C3 Latch=YQ +Bit 71924 447 43 Block=CLB_R4C3 Latch=YQ +Bit 71934 447 33 Block=CLB_R3C3 Latch=YQ +Bit 71944 447 23 Block=CLB_R2C3 Latch=YQ +Bit 71954 447 13 Block=CLB_R1C3 Latch=YQ +Bit 72468 451 143 Block=CLB_R14C3 Latch=XQ +Bit 72478 451 133 Block=CLB_R13C3 Latch=XQ +Bit 72488 451 123 Block=CLB_R12C3 Latch=XQ +Bit 72498 451 113 Block=CLB_R11C3 Latch=XQ +Bit 72508 451 103 Block=CLB_R10C3 Latch=XQ +Bit 72518 451 93 Block=CLB_R9C3 Latch=XQ +Bit 72528 451 83 Block=CLB_R8C3 Latch=XQ +Bit 72539 451 72 Block=CLB_R7C3 Latch=XQ +Bit 72549 451 62 Block=CLB_R6C3 Latch=XQ +Bit 72559 451 52 Block=CLB_R5C3 Latch=XQ +Bit 72569 451 42 Block=CLB_R4C3 Latch=XQ +Bit 72579 451 32 Block=CLB_R3C3 Latch=XQ +Bit 72589 451 22 Block=CLB_R2C3 Latch=XQ +Bit 72599 451 12 Block=CLB_R1C3 Latch=XQ +Bit 72774 453 159 Block=P43 Latch=OQ +Bit 72930 453 3 Block=P139 Latch=OQ +Bit 72935 454 159 Block=P44 Latch=OQ +Bit 73091 454 3 Block=P138 Latch=OQ +Bit 73096 455 159 Block=P44 Latch=I1 +Bit 73111 455 144 Block=CLB_R14C3 Latch=X +Bit 73121 455 134 Block=CLB_R13C3 Latch=X +Bit 73131 455 124 Block=CLB_R12C3 Latch=X +Bit 73141 455 114 Block=CLB_R11C3 Latch=X +Bit 73151 455 104 Block=CLB_R10C3 Latch=X +Bit 73161 455 94 Block=CLB_R9C3 Latch=X +Bit 73171 455 84 Block=CLB_R8C3 Latch=X +Bit 73182 455 73 Block=CLB_R7C3 Latch=X +Bit 73192 455 63 Block=CLB_R6C3 Latch=X +Bit 73202 455 53 Block=CLB_R5C3 Latch=X +Bit 73212 455 43 Block=CLB_R4C3 Latch=X +Bit 73222 455 33 Block=CLB_R3C3 Latch=X +Bit 73232 455 23 Block=CLB_R2C3 Latch=X +Bit 73242 455 13 Block=CLB_R1C3 Latch=X +Bit 73252 455 3 Block=P138 Latch=I1 +Bit 73258 456 158 Block=P44 Latch=I2 +Bit 73412 456 4 Block=P138 Latch=I2 Net=TxData<1> +Bit 73418 457 159 Block=P43 Latch=I2 +Bit 73419 457 158 Block=P43 Latch=I1 +Bit 73573 457 4 Block=P139 Latch=I1 +Bit 73574 457 3 Block=P139 Latch=I2 +Bit 76815 478 143 Block=CLB_R14C2 Latch=Y +Bit 76825 478 133 Block=CLB_R13C2 Latch=Y +Bit 76835 478 123 Block=CLB_R12C2 Latch=Y +Bit 76845 478 113 Block=CLB_R11C2 Latch=Y +Bit 76855 478 103 Block=CLB_R10C2 Latch=Y +Bit 76865 478 93 Block=CLB_R9C2 Latch=Y +Bit 76875 478 83 Block=CLB_R8C2 Latch=Y +Bit 76886 478 72 Block=CLB_R7C2 Latch=Y +Bit 76896 478 62 Block=CLB_R6C2 Latch=Y +Bit 76906 478 52 Block=CLB_R5C2 Latch=Y +Bit 76916 478 42 Block=CLB_R4C2 Latch=Y +Bit 76926 478 32 Block=CLB_R3C2 Latch=Y +Bit 76936 478 22 Block=CLB_R2C2 Latch=Y +Bit 76946 478 12 Block=CLB_R1C2 Latch=Y +Bit 77619 483 144 Block=CLB_R14C2 Latch=YQ +Bit 77629 483 134 Block=CLB_R13C2 Latch=YQ +Bit 77639 483 124 Block=CLB_R12C2 Latch=YQ +Bit 77649 483 114 Block=CLB_R11C2 Latch=YQ +Bit 77659 483 104 Block=CLB_R10C2 Latch=YQ +Bit 77669 483 94 Block=CLB_R9C2 Latch=YQ +Bit 77679 483 84 Block=CLB_R8C2 Latch=YQ +Bit 77690 483 73 Block=CLB_R7C2 Latch=YQ +Bit 77700 483 63 Block=CLB_R6C2 Latch=YQ +Bit 77710 483 53 Block=CLB_R5C2 Latch=YQ +Bit 77720 483 43 Block=CLB_R4C2 Latch=YQ +Bit 77730 483 33 Block=CLB_R3C2 Latch=YQ +Bit 77740 483 23 Block=CLB_R2C2 Latch=YQ +Bit 77750 483 13 Block=CLB_R1C2 Latch=YQ +Bit 78264 487 143 Block=CLB_R14C2 Latch=XQ +Bit 78274 487 133 Block=CLB_R13C2 Latch=XQ +Bit 78284 487 123 Block=CLB_R12C2 Latch=XQ +Bit 78294 487 113 Block=CLB_R11C2 Latch=XQ +Bit 78304 487 103 Block=CLB_R10C2 Latch=XQ +Bit 78314 487 93 Block=CLB_R9C2 Latch=XQ +Bit 78324 487 83 Block=CLB_R8C2 Latch=XQ +Bit 78335 487 72 Block=CLB_R7C2 Latch=XQ +Bit 78345 487 62 Block=CLB_R6C2 Latch=XQ +Bit 78355 487 52 Block=CLB_R5C2 Latch=XQ +Bit 78365 487 42 Block=CLB_R4C2 Latch=XQ +Bit 78375 487 32 Block=CLB_R3C2 Latch=XQ +Bit 78385 487 22 Block=CLB_R2C2 Latch=XQ +Bit 78395 487 12 Block=CLB_R1C2 Latch=XQ +Bit 78570 489 159 Block=P41 Latch=OQ +Bit 78726 489 3 Block=P141 Latch=OQ +Bit 78731 490 159 Block=P42 Latch=OQ +Bit 78887 490 3 Block=P140 Latch=OQ +Bit 78892 491 159 Block=P42 Latch=I1 +Bit 78907 491 144 Block=CLB_R14C2 Latch=X +Bit 78917 491 134 Block=CLB_R13C2 Latch=X +Bit 78927 491 124 Block=CLB_R12C2 Latch=X +Bit 78937 491 114 Block=CLB_R11C2 Latch=X +Bit 78947 491 104 Block=CLB_R10C2 Latch=X +Bit 78957 491 94 Block=CLB_R9C2 Latch=X +Bit 78967 491 84 Block=CLB_R8C2 Latch=X +Bit 78978 491 73 Block=CLB_R7C2 Latch=X +Bit 78988 491 63 Block=CLB_R6C2 Latch=X +Bit 78998 491 53 Block=CLB_R5C2 Latch=X +Bit 79008 491 43 Block=CLB_R4C2 Latch=X +Bit 79018 491 33 Block=CLB_R3C2 Latch=X +Bit 79028 491 23 Block=CLB_R2C2 Latch=X +Bit 79038 491 13 Block=CLB_R1C2 Latch=X +Bit 79048 491 3 Block=P140 Latch=I1 +Bit 79054 492 158 Block=P42 Latch=I2 +Bit 79208 492 4 Block=P140 Latch=I2 +Bit 79214 493 159 Block=P41 Latch=I2 +Bit 79215 493 158 Block=P41 Latch=I1 +Bit 79369 493 4 Block=P141 Latch=I1 +Bit 79370 493 3 Block=P141 Latch=I2 +Bit 82611 514 143 Block=CLB_R14C1 Latch=Y +Bit 82621 514 133 Block=CLB_R13C1 Latch=Y +Bit 82631 514 123 Block=CLB_R12C1 Latch=Y +Bit 82641 514 113 Block=CLB_R11C1 Latch=Y +Bit 82651 514 103 Block=CLB_R10C1 Latch=Y +Bit 82661 514 93 Block=CLB_R9C1 Latch=Y +Bit 82671 514 83 Block=CLB_R8C1 Latch=Y +Bit 82682 514 72 Block=CLB_R7C1 Latch=Y +Bit 82692 514 62 Block=CLB_R6C1 Latch=Y +Bit 82702 514 52 Block=CLB_R5C1 Latch=Y +Bit 82712 514 42 Block=CLB_R4C1 Latch=Y +Bit 82722 514 32 Block=CLB_R3C1 Latch=Y +Bit 82732 514 22 Block=CLB_R2C1 Latch=Y +Bit 82742 514 12 Block=CLB_R1C1 Latch=Y +Bit 83415 519 144 Block=CLB_R14C1 Latch=YQ +Bit 83425 519 134 Block=CLB_R13C1 Latch=YQ +Bit 83435 519 124 Block=CLB_R12C1 Latch=YQ +Bit 83445 519 114 Block=CLB_R11C1 Latch=YQ +Bit 83455 519 104 Block=CLB_R10C1 Latch=YQ +Bit 83465 519 94 Block=CLB_R9C1 Latch=YQ +Bit 83475 519 84 Block=CLB_R8C1 Latch=YQ +Bit 83486 519 73 Block=CLB_R7C1 Latch=YQ +Bit 83496 519 63 Block=CLB_R6C1 Latch=YQ +Bit 83506 519 53 Block=CLB_R5C1 Latch=YQ +Bit 83516 519 43 Block=CLB_R4C1 Latch=YQ +Bit 83526 519 33 Block=CLB_R3C1 Latch=YQ +Bit 83536 519 23 Block=CLB_R2C1 Latch=YQ +Bit 83546 519 13 Block=CLB_R1C1 Latch=YQ +Bit 84060 523 143 Block=CLB_R14C1 Latch=XQ +Bit 84070 523 133 Block=CLB_R13C1 Latch=XQ +Bit 84080 523 123 Block=CLB_R12C1 Latch=XQ +Bit 84090 523 113 Block=CLB_R11C1 Latch=XQ +Bit 84100 523 103 Block=CLB_R10C1 Latch=XQ +Bit 84110 523 93 Block=CLB_R9C1 Latch=XQ +Bit 84120 523 83 Block=CLB_R8C1 Latch=XQ +Bit 84131 523 72 Block=CLB_R7C1 Latch=XQ +Bit 84141 523 62 Block=CLB_R6C1 Latch=XQ +Bit 84151 523 52 Block=CLB_R5C1 Latch=XQ +Bit 84161 523 42 Block=CLB_R4C1 Latch=XQ +Bit 84171 523 32 Block=CLB_R3C1 Latch=XQ +Bit 84181 523 22 Block=CLB_R2C1 Latch=XQ +Bit 84191 523 12 Block=CLB_R1C1 Latch=XQ +Bit 84366 525 159 Block=P39 Latch=OQ +Bit 84522 525 3 Block=P143 Latch=OQ +Bit 84527 526 159 Block=P40 Latch=OQ +Bit 84683 526 3 Block=P142 Latch=OQ +Bit 84688 527 159 Block=P40 Latch=I1 +Bit 84703 527 144 Block=CLB_R14C1 Latch=X +Bit 84713 527 134 Block=CLB_R13C1 Latch=X +Bit 84723 527 124 Block=CLB_R12C1 Latch=X +Bit 84733 527 114 Block=CLB_R11C1 Latch=X +Bit 84743 527 104 Block=CLB_R10C1 Latch=X +Bit 84753 527 94 Block=CLB_R9C1 Latch=X +Bit 84763 527 84 Block=CLB_R8C1 Latch=X +Bit 84774 527 73 Block=CLB_R7C1 Latch=X +Bit 84784 527 63 Block=CLB_R6C1 Latch=X +Bit 84794 527 53 Block=CLB_R5C1 Latch=X +Bit 84804 527 43 Block=CLB_R4C1 Latch=X +Bit 84814 527 33 Block=CLB_R3C1 Latch=X +Bit 84824 527 23 Block=CLB_R2C1 Latch=X +Bit 84834 527 13 Block=CLB_R1C1 Latch=X +Bit 84844 527 3 Block=P142 Latch=I1 +Bit 84850 528 158 Block=P40 Latch=I2 +Bit 85004 528 4 Block=P142 Latch=I2 +Bit 85010 529 159 Block=P39 Latch=I2 +Bit 85011 529 158 Block=P39 Latch=I1 +Bit 85165 529 4 Block=P143 Latch=I1 +Bit 85166 529 3 Block=P143 Latch=I2 +Bit 91303 568 145 Block=P33 Latch=I1 +Bit 91313 568 135 Block=P31 Latch=I1 +Bit 91323 568 125 Block=P29 Latch=I1 +Bit 91333 568 115 Block=P26 Latch=I1 +Bit 91343 568 105 Block=P24 Latch=I1 +Bit 91353 568 95 Block=P22 Latch=I1 +Bit 91363 568 85 Block=P20 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Block=UNB104 Latch=OQ +Bit 91565 569 44 Block=P10 Latch=I2 +Bit 91570 569 39 Block=P9 Latch=OQ +Bit 91575 569 34 Block=P7 Latch=I2 +Bit 91580 569 29 Block=P6 Latch=OQ +Bit 91585 569 24 Block=P5 Latch=I2 +Bit 91590 569 19 Block=P4 Latch=OQ +Bit 91595 569 14 Block=P3 Latch=I2 +Bit 91600 569 9 Block=P2 Latch=OQ +Bit 91624 570 146 Block=P33 Latch=OQ +Bit 91630 570 140 Block=P32 Latch=I2 +Bit 91634 570 136 Block=P31 Latch=OQ +Bit 91640 570 130 Block=P30 Latch=I2 +Bit 91644 570 126 Block=P29 Latch=OQ +Bit 91650 570 120 Block=P28 Latch=I2 +Bit 91654 570 116 Block=P26 Latch=OQ +Bit 91660 570 110 Block=P25 Latch=I2 +Bit 91664 570 106 Block=P24 Latch=OQ +Bit 91670 570 100 Block=P23 Latch=I2 +Bit 91674 570 96 Block=P22 Latch=OQ +Bit 91680 570 90 Block=P21 Latch=I2 +Bit 91684 570 86 Block=P20 Latch=OQ +Bit 91690 570 80 Block=P19 Latch=I2 +Bit 91695 570 75 Block=P16 Latch=OQ +Bit 91701 570 69 Block=P15 Latch=I2 +Bit 91705 570 65 Block=P14 Latch=OQ +Bit 91711 570 59 Block=P13 Latch=I2 +Bit 91715 570 55 Block=P12 Latch=OQ +Bit 91721 570 49 Block=UNB104 Latch=I2 +Bit 91725 570 45 Block=P10 Latch=OQ +Bit 91731 570 39 Block=P9 Latch=I2 +Bit 91735 570 35 Block=P7 Latch=OQ +Bit 91741 570 29 Block=P6 Latch=I2 +Bit 91745 570 25 Block=P5 Latch=OQ +Bit 91751 570 19 Block=P4 Latch=I2 +Bit 91755 570 15 Block=P3 Latch=OQ +Bit 91761 570 9 Block=P2 Latch=I2 +Bit 91952 572 140 Block=P32 Latch=I1 +Bit 91962 572 130 Block=P30 Latch=I1 +Bit 91972 572 120 Block=P28 Latch=I1 +Bit 91982 572 110 Block=P25 Latch=I1 +Bit 91992 572 100 Block=P23 Latch=I1 +Bit 92002 572 90 Block=P21 Latch=I1 +Bit 92012 572 80 Block=P19 Latch=I1 +Bit 92023 572 69 Block=P15 Latch=I1 +Bit 92033 572 59 Block=P13 Latch=I1 +Bit 92043 572 49 Block=UNB104 Latch=I1 +Bit 92053 572 39 Block=P9 Latch=I1 +Bit 92063 572 29 Block=P6 Latch=I1 +Bit 92073 572 19 Block=P4 Latch=I1 +Bit 92083 572 9 Block=P2 Latch=I1 +Info ReadCaptureEnabled=1 +Info STARTSEL0=1 Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ucf =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ucf (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.ucf (revision 19) @@ -0,0 +1,301 @@ +############################################## +# BASIC UCF SYNTAX EXAMPLES V2.1.6 # +############################################## +# +# The "#" symbol is a comment character. To use this sample file, find the +# specification necessary, remove the comment character (#) from the beginning +# of the line, and modify the line (if necessary) to fit your design. +# +# TIMING SPECIFICATIONS +# +# Timing specifications can be applied to the entire device (global) or to +# specific groups in your design (called "time groups'). The time groups are +# declared in two basic ways. +# +# Method 1: Based on a net name, where 'my_net' is a net that touches all the +# logic to be grouped in to 'logic_grp'. Example: +#NET my_net TNM_NET = logic_grp ; +# +# Method 2: Group using the key word 'TIMEGRP' and declare using the names of +# logic in your design. Example: +#TIMEGRP group_name = FFS ("U1/*"); +# creates a group called 'group_name' for all flip-flops within +# the hierarchical block called U1. Wildcards are valid. +# +# Grouping is very important because it lets you tell the software which parts +# of a design run at which speeds. For the majority of the designs with only +# one clock, use simple global constraints. +# +# The type of grouping constraint you use can vary depending on the synthesis +# tools you are using. Foundation Express does better with Method 2. +# +# +############################################################ +# Internal to the device clock speed specifications - Tsys # +############################################################ +# +# data _________ /^^^^^\ _________ out +# ----------| D Q |-----{ LOGIC } -----| D Q |------ +# | | \vvvvv/ | | +# ---|> CLK | ---|> CLK | +# clock | --------- | --------- +# ------------------------------------ +# +# --------------- +# Single Clock +# --------------- +# +# ---------------- +# PERIOD TIME-SPEC +# ---------------- +# The PERIOD spec. covers all timing paths that start or end at a +# register, latch, or synchronous RAM which are clocked by the reference +# net (excluding pad destinations). Also covered is the setup +# requirement of the synchronous element relative to other elements +# (ex. flip flops, pads, etc...). +# NOTE: The default unit for time is nanoseconds. +# +#NET clock PERIOD = 50ns ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +# FROM:TO style timespecs can be used to constrain paths between time +# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined +# time groups used to specify all elements of each type in a design. +#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS +#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS +#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge +#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge +#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge +# +# --------------- +# Multiple Clocks +# --------------- +# Requires a combination of the 'Period' and 'FROM:TO' type time specifications +#NET clock1 TNM_NET = clk1_grp ; +#NET clock2 TNM_NET = clk2_grp ; +# +#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ; +#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ; +#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ; +#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ; +# +# +############################################################ +# CLOCK TO OUT specifications - Tco # +############################################################ +# +# from _________ /^^^^^\ --------\ +# ----------| D Q |-----{ LOGIC } -----| Pad > +# PLD | | \vvvvv/ --------/ +# ---|> CLK | +# clock | --------- +# -------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically include clock buffer/routing delay in your +# clock-to-out timing specifications, use OFFSET constraints . +# For an output where the maximum clock-to-out (Tco) is 25 ns: +# +#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns; +# Note that FROM: FFS : TO: PADS constraints start the delay analysis +# at the flip flop itself, and not the clock input pin. The recommended +# method to create a clock-to-out constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Flip-Flop speed specifications - Tsu # +############################################################ +# +# ------\ /^^^^^\ _________ into PLD +# |pad >-------{ LOGIC } -----| D Q |------ +# ------/ \vvvvv/ | | +# ---|> CLK | +# clock | --------- +# ---------------------------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically account for clock delay in your input setup timing +# specifications, use OFFSET constraints. +# For an input where the maximum setup time is 25 ns: +#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns; +# Note that FROM: PADS : TO: FFS constraints do not take into account any +# delay for the clock path. The recommended method to create an input +# setup time constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Pad speed specifications - Tpd # +############################################################ +# +# ------\ /^^^^^\ -------\ +# |pad >-------{ LOGIC } -----| pad > +# ------/ \vvvvv/ -------/ +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns; +# +# +############################################################ +# Other timing specifications # +############################################################ +# +# ------------- +# TIMING IGNORE +# ------------- +# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The +# "*" character is a wild card, which can be used for bus names. A "?" +# character can be used to wild-card one character. +# Ignore timing of net reset_n: +#NET : reset_n : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem: +#NET : mux_mem/data_reg* : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC +# named TS01 only: +#NET : mux_mem/data_reg* : TIG = TS01 ; +# +# Ignore data1_sig and data2_sig nets: +#NET : data?_sig : TIG ; +# +# --------------- +# PATH EXCEPTIONS +# --------------- +# If your design has outputs that can be slower than others, you can +# create specific timespecs similar to this example for output nets +# named out_data(7:0) and irq_n: +#TIMEGRP slow_outs = PADS(out_data* : irq_n) ; +#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ; +#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ; +#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ; +# +# If you have multi-cycle FF to FF paths, you can create a time group +# using either the TIMEGRP or TNM statements. +# +# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip +# flop Q output nets. Most synthesizers do assign predictable instance +# names to flip flops, however. +# +# TIMEGRP example: +#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* : +#inst_path/ff_q_output_net2*); +# +# TNM attached to instance example: +#INST inst_path/ff_instance_name1_reg* TNM = slowffs ; +#INST inst_path/ff_instance_name2_reg* TNM = slowffs ; +# +# If a FF clock-enable is used on all flip flops of a multi-cycle path, +# you can attach TNM to the clock enable net. NOTE: TNM attached to a +# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the +# net. +#NET ff_clock_enable_net TNM = slowffs ; +# +# Example of using "slowffs" timegroup, in a FROM:TO timespec, with +# either of the three timegroup methods shown above: +#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ; +# +# Constrain the skew or delay associate with a net. +#NET any_net_name MAXSKEW = 7 ; +#NET any_net_name MAXDELAY = 20 ns; +# +# +# Constraint priority in your .ucf file is as follows: +# +# highest 1. Timing Ignore (TIG) +# 2. FROM : THRU : TO specs +# 3. FROM : TO specs +# lowest 4. PERIOD specs +# +# See the on-line "Library Reference Guide" document for +# additional timespec features and more information. +# +# +############################################################ +# # +# LOCATION and ATTRIBUTE SPECIFICATIONS # +# # +############################################################ +# Pin and CLB location locking constraints # +############################################################ +# +# ----------------------- +# Assign an IO pin number +# ----------------------- +#INST io_buf_instance_name LOC = P110 ; +#NET io_net_name LOC = P111 ; +# +# ----------------------- +# Assign a signal to a range of I/O pins +# ----------------------- +#NET "signal_name" LOC=P32, P33, P34; +# +# ----------------------- +# Place a logic element(called a BEL) in a specific CLB location. +# BEL = FF, LUT, RAM, etc... +# ----------------------- +#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ; +# +# ----------------------- +# Place CLB in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1* LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Prohibit IO pin P26 or CLBR5C3 from being used: +# ----------------------- +#CONFIG PROHIBIT = P26 ; +#CONFIG PROHIBIT = CLB_R5C3 ; +# Config Prohibit is very important for forcing the software to not use critical +# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG +# Pins require a special pad so they will not be available to this constraint +# +# ----------------------- +# Assign an OBUF to be FAST or SLOW: +# ----------------------- +#INST obuf_instance_name FAST ; +#INST obuf_instance_name SLOW ; +# +# ----------------------- +# FPGAs only: IOB input Flip-flop delay specification +# ----------------------- +# Declare an IOB input FF delay (default = MAXDELAY). +# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed +# into an IOB by the "map -pr i" option. +#INST input_ff_instance_name MEDDELAY ; +#INST input_ff_instance_name NODELAY ; +# +# ----------------------- +# Assign Global Clock Buffers Lower Left Right Side +# ----------------------- +# INST gbuf1 LOC=SSW +# +# # Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.bit =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.bit (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.bit (revision 19)

trunk/impl/Xilinx_xcs10/Xilinx/xilinx.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.prj =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.prj (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.prj (revision 19) @@ -0,0 +1,10 @@ +Created by PCM: 1/9/103 +Empty design C:\PHILI\MINIUART\IMPL\XILINX~2\XILINX\xilinx.EDF created: 1/9/103 [22.21.5]. +Document c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd added: 1/9/103 [22.21.24]. +Document c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd added: 1/9/103 [22.21.24]. +Document c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd added: 1/9/103 [22.21.24]. +Document c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd added: 1/9/103 [22.21.24]. +Implementation ver1 updated: 1/9/103 [22.21.57]. +Entity UART, non optimized chip, file c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd.Implementation ver1 updated: 1/9/103 [22.22.1]. +Entity UART, optimized chip ver1-Optimized, file c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd.Implementation ver1 updated: 1/9/103 [22.22.2]. +Entity UART, optimized chip ver1-Optimized, file c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd. \ No newline at end of file Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.FIG =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.FIG =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.FIG (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.FIG (revision 19)

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trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.INI Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.MOD =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.MOD =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.MOD (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.MOD (revision 19)

trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.MOD Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.VIS =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.VIS =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.VIS (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.VIS (revision 19)

trunk/impl/Xilinx_xcs10/Xilinx/lib/XILINX.VIS Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/express.ini =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/express.ini (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/express.ini (revision 19) @@ -0,0 +1,25 @@ +[Modules] +55415254=c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd +5278556e6974=c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd +5478556e6974=c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd +73796e6368726f6e69736572=c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd +436f756e746572=c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd + +[c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd] +55415254= + +[files] +c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd= +c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd= +c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd= +c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd= + +[c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd] +5278556e6974= + +[c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd] +5478556e6974= + +[c:\phili\miniuart\impl\xilinx~2\xilinx\utils.vhd] +73796e6368726f6e69736572= +436f756e746572= Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.alb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.alb =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.alb (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.alb (revision 19)

trunk/impl/Xilinx_xcs10/Xilinx/xilinx.alb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/impl/Xilinx_xcs10/Xilinx/miniuart.log =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/miniuart.log (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/miniuart.log (revision 19) @@ -0,0 +1,2 @@ +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd file started. +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\miniuart.vhd file finished. Index: trunk/impl/Xilinx_xcs10/Xilinx/miniuart.vhd =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/miniuart.vhd (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/miniuart.vhd (revision 19) @@ -0,0 +1,146 @@ +------------------------------------------------------------------------------- +-- Title : UART +-- Project : UART +------------------------------------------------------------------------------- +-- File : MiniUart.vhd +-- Author : Philippe CARTON +-- (philippe.carton2@libertysurf.fr) +-- Organization: +-- Created : 15/12/2001 +-- Last update : 8/1/2003 +-- Platform : Foundation 3.1i +-- Simulators : ModelSim 5.5b +-- Synthesizers: Xilinx Synthesis +-- Targets : Xilinx Spartan +-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd +------------------------------------------------------------------------------- +-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC. +-- Wishbone compatable. +------------------------------------------------------------------------------- +-- Copyright (c) notice +-- This core adheres to the GNU public license +-- +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : +-- Version : +-- Date : +-- Modifier : name +-- Description : +-- +------------------------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + +entity UART is + generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor + port ( +-- Wishbone signals + WB_CLK_I : in std_logic; -- clock + WB_RST_I : in std_logic; -- Reset input + WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus + WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus + WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus + WB_WE_I : in std_logic; -- Write Enable + WB_STB_I : in std_logic; -- Strobe + WB_ACK_O : out std_logic; -- Acknowledge +-- process signals + IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte + IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received + BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive + TxD_PAD_O: out std_logic; -- Tx RS232 Line + RxD_PAD_I: in std_logic); -- Rx RS232 Line +end UART; + +-- Architecture for UART for synthesis +architecture Behaviour of UART is + + component Counter + generic(COUNT: INTEGER range 0 to 65535); -- Count revolution + port ( + Clk : in std_logic; -- Clock + Reset : in std_logic; -- Reset input + CE : in std_logic; -- Chip Enable + O : out std_logic); -- Output + end component; + + component RxUnit + port ( + Clk : in std_logic; -- system clock signal + Reset : in std_logic; -- Reset input + Enable : in std_logic; -- Enable input + ReadA : in Std_logic; -- Async Read Received Byte + RxD : in std_logic; -- RS-232 data input + RxAv : out std_logic; -- Byte available + DataO : out std_logic_vector(7 downto 0)); -- Byte received + end component; + + component TxUnit + port ( + Clk : in std_logic; -- Clock signal + Reset : in std_logic; -- Reset input + Enable : in std_logic; -- Enable input + LoadA : in std_logic; -- Asynchronous Load + TxD : out std_logic; -- RS-232 data output + Busy : out std_logic; -- Tx Busy + DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit + end component; + + signal RxData : std_logic_vector(7 downto 0); -- Last Byte received + signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted + signal SReg : std_logic_vector(7 downto 0); -- Status register + signal EnabRx : std_logic; -- Enable RX unit + signal EnabTx : std_logic; -- Enable TX unit + signal RxAv : std_logic; -- Data Received + signal TxBusy : std_logic; -- Transmiter Busy + signal ReadA : std_logic; -- Async Read receive buffer + signal LoadA : std_logic; -- Async Load transmit buffer + signal Sig0 : std_logic; -- gnd signal + signal Sig1 : std_logic; -- vcc signal + + begin + sig0 <= '0'; + sig1 <= '1'; + Uart_Rxrate : Counter -- Baud Rate adjust + generic map (COUNT => BRDIVISOR) + port map (BR_CLK_I, sig0, sig1, EnabRx); + Uart_Txrate : Counter -- 4 Divider for Tx + generic map (COUNT => 4) + port map (BR_CLK_I, Sig0, EnabRx, EnabTx); + Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData); + Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData); + IntTx_O <= not TxBusy; + IntRx_O <= RxAv; + SReg(0) <= not TxBusy; + SReg(1) <= RxAv; + SReg(7 downto 2) <= "000000"; + + -- Implements WishBone data exchange. + -- Clocked on rising edge. Synchronous Reset RST_I + WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I) + variable StatM : std_logic_vector(4 downto 0); + begin + if Rising_Edge(WB_CLK_I) then + if (WB_RST_I = '1') then + ReadA <= '0'; + LoadA <= '0'; + else + if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx + TxData <= WB_DAT_I; + LoadA <= '1'; -- Load signal + else LoadA <= '0'; + end if; + if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx + ReadA <= '1'; -- Read signal + else ReadA <= '0'; + end if; + end if; + end if; + end process; + WB_ACK_O <= WB_STB_I; + WB_DAT_O <= + RxData when WB_ADR_I = "00" else -- Read Byte from Rx + SReg when WB_ADR_I = "01" else -- Read Status Reg + "00000000"; +end Behaviour; Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx.EDF =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx.EDF (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx.EDF (revision 19) @@ -0,0 +1,16942 @@ +(edif UART + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap + (keywordLevel 0) + ) + (status + (written + (timeStamp 2003 1 9 21 23 35) + (program "UNKNOWN" + (version "3.4.0.5124") + ) + (author "Test") + ) + ) + (external SPARTAN + (edifLevel 0) + (technology + (numberDefinition) + ) + (cell AND2 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I1 + (direction INPUT) + ) + (port I0 + (direction INPUT) + ) + ) + ) + ) + (cell AND3 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I2 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I0 + (direction INPUT) + ) + ) + ) + ) + (cell AND4 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I3 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I0 + (direction INPUT) + ) + ) + ) + ) + (cell BUF + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell BUFG + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell CY4 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port COUT + (direction OUTPUT) + ) + (port COUT0 + (direction OUTPUT) + ) + (port CIN + (direction INPUT) + ) + (port A0 + (direction INPUT) + ) + (port A1 + (direction INPUT) + ) + (port B0 + (direction INPUT) + ) + (port B1 + (direction INPUT) + ) + (port ADD + (direction INPUT) + ) + (port C0 + (direction INPUT) + ) + (port C1 + (direction INPUT) + ) + (port C2 + (direction INPUT) + ) + (port C3 + (direction INPUT) + ) + (port C4 + (direction INPUT) + ) + (port C5 + (direction INPUT) + ) + (port C6 + (direction INPUT) + ) + (port C7 + (direction INPUT) + ) + ) + ) + ) + (cell CY4_25 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port C7 + (direction OUTPUT) + ) + (port C6 + (direction OUTPUT) + ) + (port C5 + (direction OUTPUT) + ) + (port C4 + (direction OUTPUT) + ) + (port C3 + (direction OUTPUT) + ) + (port C2 + (direction OUTPUT) + ) + (port C1 + (direction OUTPUT) + ) + (port C0 + (direction OUTPUT) + ) + ) + ) + ) + (cell CY4_27 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port C7 + (direction OUTPUT) + ) + (port C6 + (direction OUTPUT) + ) + (port C5 + (direction OUTPUT) + ) + (port C4 + (direction OUTPUT) + ) + (port C3 + (direction OUTPUT) + ) + (port C2 + (direction OUTPUT) + ) + (port C1 + (direction OUTPUT) + ) + (port C0 + (direction OUTPUT) + ) + ) + ) + ) + (cell CY4_42 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port C7 + (direction OUTPUT) + ) + (port C6 + (direction OUTPUT) + ) + (port C5 + (direction OUTPUT) + ) + (port C4 + (direction OUTPUT) + ) + (port C3 + (direction OUTPUT) + ) + (port C2 + (direction OUTPUT) + ) + (port C1 + (direction OUTPUT) + ) + (port C0 + (direction OUTPUT) + ) + ) + ) + ) + (cell FDC + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port Q + (direction OUTPUT) + ) + (port D + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port CLR + (direction INPUT) + ) + ) + ) + ) + (cell FDCE + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port Q + (direction OUTPUT) + ) + (port D + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port CLR + (direction INPUT) + ) + ) + ) + ) + (cell FDPE + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port Q + (direction OUTPUT) + ) + (port D + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port PRE + (direction INPUT) + ) + ) + ) + ) + (cell GND + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell IFDX + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port Q + (direction OUTPUT) + ) + (port D + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell IPAD + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port IPAD + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell FMAP + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction INPUT) + ) + ) + ) + ) + (cell HMAP + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction INPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell XOR2 + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I1 + (direction INPUT) + ) + (port I0 + (direction INPUT) + ) + ) + ) + ) + ) + (library DESIGNS + (edifLevel 0) + (technology + (numberDefinition) + ) + (cell UART + (cellType GENERIC) + (view Netlist_representation + (viewType NETLIST) + (interface + (port WB_CLK_I + (direction INPUT) + ) + (port WB_RST_I + (direction INPUT) + ) + (port + (rename WB_ADR_I_1 "WB_ADR_I<1>") + (direction INPUT) + ) + (port + (rename WB_ADR_I_0 "WB_ADR_I<0>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_7 "WB_DAT_I<7>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_6 "WB_DAT_I<6>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_5 "WB_DAT_I<5>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_4 "WB_DAT_I<4>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_3 "WB_DAT_I<3>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_2 "WB_DAT_I<2>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_1 "WB_DAT_I<1>") + (direction INPUT) + ) + (port + (rename WB_DAT_I_0 "WB_DAT_I<0>") + (direction INPUT) + ) + (port + (rename WB_DAT_O_7 "WB_DAT_O<7>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_6 "WB_DAT_O<6>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_5 "WB_DAT_O<5>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_4 "WB_DAT_O<4>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_3 "WB_DAT_O<3>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_2 "WB_DAT_O<2>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_1 "WB_DAT_O<1>") + (direction OUTPUT) + ) + (port + (rename WB_DAT_O_0 "WB_DAT_O<0>") + (direction OUTPUT) + ) + (port WB_WE_I + (direction INPUT) + ) + (port WB_STB_I + (direction INPUT) + ) + (port WB_ACK_O + (direction OUTPUT) + ) + (port IntTx_O + (direction OUTPUT) + ) + (port IntRx_O + (direction OUTPUT) + ) + (port BR_Clk_I + (direction INPUT) + ) + (port TxD_PAD_O + (direction OUTPUT) + ) + (port RxD_PAD_I + (direction INPUT) + ) + ) + (contents + (instance + (rename Uart_Rxrate_C126_C0_C1 "Uart_Rxrate/C126/C0/C1") + (viewRef Netlist_representation + (cellRef CY4 + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_0") + ) + (property RLOC + (string "R0C0") + ) + ) + (instance + (rename Uart_Rxrate_C126_C0_C2 "Uart_Rxrate/C126/C0/C2") + (viewRef Netlist_representation + (cellRef CY4_27 + (libraryRef SPARTAN) + ) + ) + (property CYMODE + (string "DEC-G-0") + ) + ) + (instance + (rename Uart_Rxrate_C126_C1_C2 "Uart_Rxrate/C126/C1/C2") + (viewRef Netlist_representation + (cellRef CY4 + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_1") + ) + (property RLOC + (string "R0C0") + ) + ) + (instance + (rename Uart_Rxrate_C126_C1_C3 "Uart_Rxrate/C126/C1/C3") + (viewRef Netlist_representation + (cellRef CY4_25 + (libraryRef SPARTAN) + ) + ) + (property CYMODE + (string "DEC-FG-CI") + ) + ) + (instance + (rename Uart_Rxrate_C126_C2_C2 "Uart_Rxrate/C126/C2/C2") + (viewRef Netlist_representation + (cellRef CY4 + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_2") + ) + (property RLOC + (string "R0C0") + ) + ) + (instance + (rename Uart_Rxrate_C126_C2_C3 "Uart_Rxrate/C126/C2/C3") + (viewRef Netlist_representation + (cellRef CY4_25 + (libraryRef SPARTAN) + ) + ) + (property CYMODE + (string "DEC-FG-CI") + ) + ) + (instance + (rename Uart_Rxrate_C126_C3_C2 "Uart_Rxrate/C126/C3/C2") + (viewRef Netlist_representation + (cellRef CY4 + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_3") + ) + (property RLOC + (string "R0C0") + ) + ) + (instance + (rename Uart_Rxrate_C126_C3_C3 "Uart_Rxrate/C126/C3/C3") + (viewRef Netlist_representation + (cellRef CY4_25 + (libraryRef SPARTAN) + ) + ) + (property CYMODE + (string "DEC-FG-CI") + ) + ) + (instance ReadA_reg + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance LoadA_reg + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_0 "Uart_Rxrate/Cnt_reg<0>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_0") + ) + (property RLOC + (string "R0C0.FFY") + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_4 "Uart_Rxrate/Cnt_reg<4>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_O_reg "Uart_Rxrate/O_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_6 "Uart_Rxrate/Cnt_reg<6>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_2 "Uart_Rxrate/Cnt_reg<2>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_3 "Uart_Rxrate/Cnt_reg<3>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_7 "Uart_Rxrate/Cnt_reg<7>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_5 "Uart_Rxrate/Cnt_reg<5>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Rxrate_Cnt_reg_1 "Uart_Rxrate/Cnt_reg<1>") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Txrate_O_reg "Uart_Txrate/O_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Txrate_Cnt_reg_1 "Uart_Txrate/Cnt_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_Txrate_Cnt_reg_0 "Uart_Txrate/Cnt_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TxD_reg "Uart_TxUnit/TxD_reg") + (viewRef Netlist_representation + (cellRef FDPE + (libraryRef SPARTAN) + ) + ) + (property INIT + (string "S") + ) + ) + (instance + (rename Uart_TxUnit_TBufL_reg "Uart_TxUnit/TBufL_reg") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_0 "Uart_TxUnit/TReg_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_1 "Uart_TxUnit/TReg_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_2 "Uart_TxUnit/TReg_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_3 "Uart_TxUnit/TReg_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_4 "Uart_TxUnit/TReg_reg<4>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_5 "Uart_TxUnit/TReg_reg<5>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_6 "Uart_TxUnit/TReg_reg<6>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TReg_reg_7 "Uart_TxUnit/TReg_reg<7>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_0 "Uart_TxUnit/TBuff_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_1 "Uart_TxUnit/TBuff_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_2 "Uart_TxUnit/TBuff_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_3 "Uart_TxUnit/TBuff_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_4 "Uart_TxUnit/TBuff_reg<4>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_5 "Uart_TxUnit/TBuff_reg<5>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_6 "Uart_TxUnit/TBuff_reg<6>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_TBuff_reg_7 "Uart_TxUnit/TBuff_reg<7>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_BitPos_reg_3 "Uart_TxUnit/BitPos_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_BitPos_reg_2 "Uart_TxUnit/BitPos_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_BitPos_reg_1 "Uart_TxUnit/BitPos_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_BitPos_reg_0 "Uart_TxUnit/BitPos_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RRegL_reg "Uart_RxUnit/RRegL_reg") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RxAv_reg "Uart_RxUnit/RxAv_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_0 "Uart_RxUnit/RReg_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_1 "Uart_RxUnit/RReg_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_2 "Uart_RxUnit/RReg_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_3 "Uart_RxUnit/RReg_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_4 "Uart_RxUnit/RReg_reg<4>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_5 "Uart_RxUnit/RReg_reg<5>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_6 "Uart_RxUnit/RReg_reg<6>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_RReg_reg_7 "Uart_RxUnit/RReg_reg<7>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_0 "Uart_RxUnit/DataO_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_1 "Uart_RxUnit/DataO_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_2 "Uart_RxUnit/DataO_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_3 "Uart_RxUnit/DataO_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_4 "Uart_RxUnit/DataO_reg<4>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_5 "Uart_RxUnit/DataO_reg<5>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_6 "Uart_RxUnit/DataO_reg<6>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_DataO_reg_7 "Uart_RxUnit/DataO_reg<7>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_SampleCnt_reg_1 "Uart_RxUnit/SampleCnt_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_SampleCnt_reg_0 "Uart_RxUnit/SampleCnt_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_BitPos_reg_3 "Uart_RxUnit/BitPos_reg<3>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_BitPos_reg_2 "Uart_RxUnit/BitPos_reg<2>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_BitPos_reg_1 "Uart_RxUnit/BitPos_reg<1>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_RxUnit_BitPos_reg_0 "Uart_RxUnit/BitPos_reg<0>") + (viewRef Netlist_representation + (cellRef FDCE + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_SyncLoad_C1S_reg "Uart_TxUnit/SyncLoad/C1S_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_SyncLoad_R_reg "Uart_TxUnit/SyncLoad/R_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename Uart_TxUnit_SyncLoad_C1A_reg "Uart_TxUnit/SyncLoad/C1A_reg") + (viewRef Netlist_representation + (cellRef FDC + (libraryRef SPARTAN) + ) + ) + ) + (instance C467 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C468 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C469 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_7 "TxData_reg<7>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_6 "TxData_reg<6>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_5 "TxData_reg<5>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_4 "TxData_reg<4>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_3 "TxData_reg<3>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_2 "TxData_reg<2>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_1 "TxData_reg<1>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance + (rename TxData_reg_0 "TxData_reg<0>") + (viewRef Netlist_representation + (cellRef IFDX + (libraryRef SPARTAN) + ) + ) + ) + (instance C502 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C503 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C504 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C505 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C506 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C507 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C508 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C509 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C510 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C511 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C512 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C513 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C514 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C516 + (viewRef Netlist_representation + (cellRef OBUF + (libraryRef SPARTAN) + ) + ) + (property SLOW + (string "") + ) + ) + (instance C517 + (viewRef Netlist_representation + (cellRef IBUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C594 + (viewRef Netlist_representation + (cellRef BUFG + (libraryRef SPARTAN) + ) + ) + ) + (instance C595 + (viewRef Netlist_representation + (cellRef IPAD + (libraryRef SPARTAN) + ) + ) + ) + (instance C596 + (viewRef Netlist_representation + (cellRef BUFG + (libraryRef SPARTAN) + ) + ) + ) + (instance C597 + (viewRef Netlist_representation + (cellRef IPAD + (libraryRef SPARTAN) + ) + ) + ) + (instance C598 + (viewRef Netlist_representation + (cellRef BUFG + (libraryRef SPARTAN) + ) + ) + ) + (instance C599 + (viewRef Netlist_representation + (cellRef BUFG + (libraryRef SPARTAN) + ) + ) + ) + (instance C600 + (viewRef Netlist_representation + (cellRef CY4 + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "UART_5") + ) + (property RLOC + (string "R0C0") + ) + ) + (instance C601 + (viewRef Netlist_representation + (cellRef CY4_42 + (libraryRef SPARTAN) + ) + ) + (property CYMODE + (string "EXAMINE-CI") + ) + ) + (instance C602 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C603 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C667 + (viewRef Netlist_representation + (cellRef VCC + (libraryRef SPARTAN) + ) + ) + ) + (instance C668 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C669 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C670 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C671 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C672 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C673 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C674 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C675 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C676 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C677 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C678 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C679 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C680 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C681 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C682 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C683 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C684 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C685 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C686 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C687 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C688 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C689 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C690 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C691 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C692 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C693 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C694 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C695 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C696 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C697 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C698 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C699 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C700 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C701 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C702 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C703 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C704 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C705 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C706 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C707 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C708 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C709 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C710 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C711 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C712 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C713 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C714 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C715 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C716 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C717 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C718 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C719 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C720 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C721 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C722 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C723 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C724 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C725 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C726 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C727 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C728 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C729 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C730 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C731 + (viewRef Netlist_representation + (cellRef GND + (libraryRef SPARTAN) + ) + ) + ) + (instance C0 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_0") + ) + (property RLOC + (string "R0C0.G") + ) + ) + (instance C1 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C2 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C3 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C4 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C5 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C6 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C7 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C8 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C9 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C10 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C11 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C12 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C13 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C14 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C15 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_1") + ) + (property RLOC + (string "R0C0.F") + ) + ) + (instance C16 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C17 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C18 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C19 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C20 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C21 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C22 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C23 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C24 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_1") + ) + (property RLOC + (string "R0C0.G") + ) + ) + (instance C25 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C26 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C27 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C28 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C29 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C30 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C31 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C32 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C33 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_2") + ) + (property RLOC + (string "R0C0.F") + ) + ) + (instance C34 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C35 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C36 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C37 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C38 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C39 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C40 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C41 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C42 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_2") + ) + (property RLOC + (string "R0C0.G") + ) + ) + (instance C43 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C44 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C45 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C46 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C47 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C48 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C49 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C50 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C51 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_3") + ) + (property RLOC + (string "R0C0.F") + ) + ) + (instance C52 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C53 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C54 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C55 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C56 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C57 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C58 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C59 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C60 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + (property HU_SET + (string "dec_rpl_8_33_3") + ) + (property RLOC + (string "R0C0.G") + ) + ) + (instance C61 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C62 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C63 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C64 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C65 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C66 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C67 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C68 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C69 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C70 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C71 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C72 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C73 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C74 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C75 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C76 + (viewRef Netlist_representation + (cellRef XOR2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C77 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C78 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C79 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C80 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C81 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C82 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C83 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C84 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C85 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C86 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C87 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C88 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C89 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C90 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C91 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C92 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C93 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C94 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C95 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C96 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C97 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C98 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C99 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C100 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C101 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C102 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C103 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C104 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C105 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C106 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C107 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C108 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C109 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C110 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C111 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C112 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C113 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C114 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C115 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C116 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C117 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C118 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C119 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C120 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C121 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C122 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C123 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C124 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C125 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C126 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C127 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C128 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C129 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C130 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C131 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C132 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C133 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C134 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C135 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C136 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C137 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C138 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C139 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C140 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C141 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C142 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C143 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C144 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C145 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C146 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C147 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C148 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C149 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C150 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C151 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C152 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C153 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C154 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C155 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C156 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C157 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C158 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C159 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C160 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C161 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C162 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C163 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C164 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C165 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C166 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C167 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C168 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C169 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C170 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C171 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C172 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C173 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C174 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C175 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C176 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C177 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C178 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C179 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C180 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C181 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C182 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C183 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C184 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C185 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C186 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C187 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C188 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C189 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C190 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C191 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C192 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C193 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C194 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C195 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C196 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C197 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C198 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C199 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C200 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C201 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C202 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C206 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C207 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C208 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C209 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C210 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C211 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C212 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C213 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C214 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C215 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C216 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C217 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C218 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C219 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C220 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C221 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C222 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C223 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C224 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C225 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C226 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C227 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C228 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C229 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C230 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C231 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C232 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C233 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C234 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C235 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C236 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C237 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C238 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C239 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C240 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C241 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C242 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C243 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C244 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C245 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C246 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C247 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C248 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C249 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C250 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C251 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C252 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C253 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C254 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C255 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C256 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C257 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C258 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C259 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C260 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C261 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C262 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C263 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C264 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C265 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C266 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C267 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C268 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C269 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C270 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C271 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C272 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C273 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C274 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C275 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C276 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C277 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C278 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C279 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C280 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C281 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C282 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C283 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C284 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C285 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C286 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C287 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C288 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C289 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C290 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C291 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C292 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C293 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C294 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C295 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C296 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C297 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C298 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C299 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C300 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C301 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C302 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C303 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C304 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C305 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C306 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C307 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C308 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C309 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C310 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C311 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C312 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C313 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C314 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C315 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C316 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C317 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C318 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C319 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C320 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C321 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C322 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C323 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C324 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C325 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C326 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C327 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C328 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C329 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C330 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C331 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C332 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C333 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C334 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C335 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C336 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C337 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C338 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C339 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C340 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C341 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C342 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C343 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C344 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C345 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C346 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C347 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C348 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C349 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C350 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C351 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C352 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C353 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C354 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C355 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C356 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C357 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C358 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C359 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C360 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C361 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C362 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C363 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C364 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C365 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C366 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C367 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C368 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C369 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C370 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C371 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C372 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C373 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C374 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C375 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C376 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C377 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C378 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C379 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C380 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C381 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C382 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C383 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C384 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C385 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C386 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C387 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C388 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C389 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C390 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C391 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C392 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C393 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C394 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C395 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C396 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C397 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C398 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C399 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C400 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C401 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C402 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C403 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C404 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C405 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C406 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C407 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C408 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C409 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C410 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C411 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C412 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C413 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C414 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C415 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C416 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C417 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C418 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C419 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C420 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C421 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C422 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C423 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C424 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C425 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C426 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C427 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C428 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C429 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C430 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C431 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C432 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C433 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C434 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C435 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C436 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C437 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C438 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C439 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C440 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C441 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C442 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C443 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C444 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C445 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C446 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C447 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C448 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C449 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C450 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C451 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C452 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C453 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C454 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C455 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C456 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C457 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C458 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C459 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C460 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C461 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C462 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C463 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C464 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C465 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C466 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C470 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C471 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C472 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C473 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C474 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C475 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C476 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C477 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C478 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C479 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C480 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C481 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C482 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C483 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C484 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C485 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C486 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C487 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C488 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C489 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C490 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C491 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C492 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C493 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C494 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C495 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C496 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C497 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C498 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C499 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C500 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C501 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C515 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C518 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C519 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C520 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C521 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C522 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C523 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C524 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C525 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C526 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C527 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C528 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C529 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C530 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C531 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C532 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C533 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C534 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C535 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C536 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C537 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C538 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C539 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C540 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C541 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C542 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C543 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C544 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C545 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C546 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C547 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C548 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C549 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C550 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C551 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C552 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C553 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C554 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C555 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C556 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C557 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C558 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C559 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C560 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C561 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C562 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C563 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C564 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C565 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C566 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C567 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C568 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C569 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C570 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C571 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C572 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C573 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C574 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C575 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C576 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C577 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C581 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C586 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C593 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C604 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C605 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C606 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C607 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C608 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C609 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C610 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C611 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C612 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C613 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C614 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C615 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C616 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C617 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C618 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C619 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C620 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C621 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C622 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C623 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C624 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C625 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C626 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C627 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C628 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C629 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C630 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C631 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C632 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C633 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C634 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C635 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C636 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C637 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C638 + (viewRef Netlist_representation + (cellRef AND3 + (libraryRef SPARTAN) + ) + ) + ) + (instance C639 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C640 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C641 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C642 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C643 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C644 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C645 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C646 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C647 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C648 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C649 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C650 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C651 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C652 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C653 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C654 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C655 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C656 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C657 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C658 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C659 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C660 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C661 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C662 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C663 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C664 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C665 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C666 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C732 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C733 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C734 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C735 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C736 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C737 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C738 + (viewRef Netlist_representation + (cellRef HMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C739 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C740 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C741 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C742 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C743 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C744 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C745 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C746 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C747 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C748 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C749 + (viewRef Netlist_representation + (cellRef AND2 + (libraryRef SPARTAN) + ) + ) + ) + (instance C750 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C751 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C752 + (viewRef Netlist_representation + (cellRef FMAP + (libraryRef SPARTAN) + ) + ) + ) + (instance C753 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C754 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C755 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C756 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C757 + (viewRef Netlist_representation + (cellRef INV + (libraryRef SPARTAN) + ) + ) + ) + (instance C758 + (viewRef Netlist_representation + (cellRef AND4 + (libraryRef SPARTAN) + ) + ) + ) + (instance C759 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C760 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C761 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (instance C762 + (viewRef Netlist_representation + (cellRef BUF + (libraryRef SPARTAN) + ) + ) + ) + (net WB_CLK_I_BUFGed + (joined + (portRef C + (instanceRef ReadA_reg) + ) + (portRef C + (instanceRef LoadA_reg) + ) + (portRef C + (instanceRef TxData_reg_7) + ) + (portRef C + (instanceRef TxData_reg_6) + ) + (portRef C + (instanceRef TxData_reg_5) + ) + (portRef C + (instanceRef TxData_reg_4) + ) + (portRef C + (instanceRef TxData_reg_3) + ) + (portRef C + (instanceRef TxData_reg_2) + ) + (portRef C + (instanceRef TxData_reg_1) + ) + (portRef C + (instanceRef TxData_reg_0) + ) + (portRef O + (instanceRef C596) + ) + ) + ) + (net N_WB_RST_I + (joined + (portRef PRE + (instanceRef Uart_TxUnit_TxD_reg) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBufL_reg) + ) + (portRef CLR + (instanceRef Uart_TxUnit_BitPos_reg_3) + ) + (portRef CLR + (instanceRef Uart_TxUnit_BitPos_reg_2) + ) + (portRef CLR + (instanceRef Uart_TxUnit_BitPos_reg_1) + ) + (portRef CLR + (instanceRef Uart_TxUnit_BitPos_reg_0) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RRegL_reg) + ) + (portRef CLR + (instanceRef Uart_RxUnit_BitPos_reg_3) + ) + (portRef CLR + (instanceRef Uart_RxUnit_BitPos_reg_2) + ) + (portRef CLR + (instanceRef Uart_RxUnit_BitPos_reg_1) + ) + (portRef CLR + (instanceRef Uart_RxUnit_BitPos_reg_0) + ) + (portRef O + (instanceRef C467) + ) + (portRef I1 + (instanceRef C217) + ) + (portRef I + (instanceRef C220) + ) + (portRef I1 + (instanceRef C241) + ) + (portRef I + (instanceRef C244) + ) + (portRef I1 + (instanceRef C369) + ) + (portRef I + (instanceRef C372) + ) + (portRef I1 + (instanceRef C402) + ) + (portRef I + (instanceRef C407) + ) + (portRef I1 + (instanceRef C480) + ) + (portRef I + (instanceRef C483) + ) + (portRef I1 + (instanceRef C486) + ) + (portRef I + (instanceRef C489) + ) + (portRef I3 + (instanceRef C646) + ) + (portRef I + (instanceRef C649) + ) + (portRef I3 + (instanceRef C652) + ) + (portRef I + (instanceRef C656) + ) + ) + ) + (net + (rename N_WB_ADR_I_1 "N_WB_ADR_I<1>") + (joined + (portRef O + (instanceRef C468) + ) + (portRef I1 + (instanceRef C81) + ) + (portRef I + (instanceRef C85) + ) + (portRef I + (instanceRef C87) + ) + (portRef I1 + (instanceRef C98) + ) + (portRef I + (instanceRef C102) + ) + (portRef I + (instanceRef C104) + ) + (portRef I1 + (instanceRef C659) + ) + (portRef I + (instanceRef C662) + ) + ) + ) + (net + (rename N_WB_ADR_I_0 "N_WB_ADR_I<0>") + (joined + (portRef O + (instanceRef C469) + ) + (portRef I2 + (instanceRef C81) + ) + (portRef I + (instanceRef C86) + ) + (portRef I1 + (instanceRef C90) + ) + (portRef I2 + (instanceRef C98) + ) + (portRef I + (instanceRef C103) + ) + (portRef I1 + (instanceRef C107) + ) + (portRef I2 + (instanceRef C659) + ) + (portRef I + (instanceRef C663) + ) + ) + ) + (net + (rename WB_DAT_I_7 "WB_DAT_I<7>") + (joined + (portRef WB_DAT_I_7) + (portRef D + (instanceRef TxData_reg_7) + ) + ) + ) + (net + (rename WB_DAT_I_6 "WB_DAT_I<6>") + (joined + (portRef WB_DAT_I_6) + (portRef D + (instanceRef TxData_reg_6) + ) + ) + ) + (net + (rename WB_DAT_I_5 "WB_DAT_I<5>") + (joined + (portRef WB_DAT_I_5) + (portRef D + (instanceRef TxData_reg_5) + ) + ) + ) + (net + (rename WB_DAT_I_4 "WB_DAT_I<4>") + (joined + (portRef WB_DAT_I_4) + (portRef D + (instanceRef TxData_reg_4) + ) + ) + ) + (net + (rename WB_DAT_I_3 "WB_DAT_I<3>") + (joined + (portRef WB_DAT_I_3) + (portRef D + (instanceRef TxData_reg_3) + ) + ) + ) + (net + (rename WB_DAT_I_2 "WB_DAT_I<2>") + (joined + (portRef WB_DAT_I_2) + (portRef D + (instanceRef TxData_reg_2) + ) + ) + ) + (net + (rename WB_DAT_I_1 "WB_DAT_I<1>") + (joined + (portRef WB_DAT_I_1) + (portRef D + (instanceRef TxData_reg_1) + ) + ) + ) + (net + (rename WB_DAT_I_0 "WB_DAT_I<0>") + (joined + (portRef WB_DAT_I_0) + (portRef D + (instanceRef TxData_reg_0) + ) + ) + ) + (net N_WB_WE_I + (joined + (portRef O + (instanceRef C510) + ) + (portRef I2 + (instanceRef C646) + ) + (portRef I1 + (instanceRef C651) + ) + (portRef I2 + (instanceRef C652) + ) + (portRef I + (instanceRef C655) + ) + ) + ) + (net N_WB_STB_I + (joined + (portRef O + (instanceRef C511) + ) + (portRef I + (instanceRef C512) + ) + (portRef I1 + (instanceRef C646) + ) + (portRef I0 + (instanceRef C651) + ) + (portRef I1 + (instanceRef C652) + ) + (portRef I0 + (instanceRef C658) + ) + ) + ) + (net N_IntRx_O + (joined + (portRef Q + (instanceRef Uart_RxUnit_RxAv_reg) + ) + (portRef I + (instanceRef C514) + ) + (portRef I4 + (instanceRef C98) + ) + (portRef I2 + (instanceRef C107) + ) + ) + ) + (net BR_Clk_I_BUFGed + (joined + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_0) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_4) + ) + (portRef C + (instanceRef Uart_Rxrate_O_reg) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_6) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_2) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_3) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_7) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_5) + ) + (portRef C + (instanceRef Uart_Rxrate_Cnt_reg_1) + ) + (portRef C + (instanceRef Uart_Txrate_O_reg) + ) + (portRef C + (instanceRef Uart_Txrate_Cnt_reg_1) + ) + (portRef C + (instanceRef Uart_Txrate_Cnt_reg_0) + ) + (portRef C + (instanceRef Uart_TxUnit_TxD_reg) + ) + (portRef C + (instanceRef Uart_TxUnit_TBufL_reg) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_0) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_1) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_2) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_3) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_4) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_5) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_6) + ) + (portRef C + (instanceRef Uart_TxUnit_TReg_reg_7) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_0) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_1) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_2) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_3) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_4) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_5) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_6) + ) + (portRef C + (instanceRef Uart_TxUnit_TBuff_reg_7) + ) + (portRef C + (instanceRef Uart_TxUnit_BitPos_reg_3) + ) + (portRef C + (instanceRef Uart_TxUnit_BitPos_reg_2) + ) + (portRef C + (instanceRef Uart_TxUnit_BitPos_reg_1) + ) + (portRef C + (instanceRef Uart_TxUnit_BitPos_reg_0) + ) + (portRef C + (instanceRef Uart_RxUnit_RRegL_reg) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_0) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_1) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_2) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_3) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_4) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_5) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_6) + ) + (portRef C + (instanceRef Uart_RxUnit_RReg_reg_7) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_0) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_1) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_2) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_3) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_4) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_5) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_6) + ) + (portRef C + (instanceRef Uart_RxUnit_DataO_reg_7) + ) + (portRef C + (instanceRef Uart_RxUnit_SampleCnt_reg_1) + ) + (portRef C + (instanceRef Uart_RxUnit_SampleCnt_reg_0) + ) + (portRef C + (instanceRef Uart_RxUnit_BitPos_reg_3) + ) + (portRef C + (instanceRef Uart_RxUnit_BitPos_reg_2) + ) + (portRef C + (instanceRef Uart_RxUnit_BitPos_reg_1) + ) + (portRef C + (instanceRef Uart_RxUnit_BitPos_reg_0) + ) + (portRef C + (instanceRef Uart_TxUnit_SyncLoad_C1S_reg) + ) + (portRef C + (instanceRef Uart_TxUnit_SyncLoad_R_reg) + ) + (portRef O + (instanceRef C594) + ) + ) + ) + (net N_TxD_PAD_O + (joined + (portRef Q + (instanceRef Uart_TxUnit_TxD_reg) + ) + (portRef I + (instanceRef C516) + ) + ) + ) + (net N_RxD_PAD_I + (joined + (portRef O + (instanceRef C517) + ) + (portRef I1 + (instanceRef C182) + ) + (portRef I + (instanceRef C186) + ) + (portRef I1 + (instanceRef C234) + ) + (portRef I + (instanceRef C237) + ) + (portRef I1 + (instanceRef C254) + ) + (portRef I0 + (instanceRef C264) + ) + (portRef I1 + (instanceRef C265) + ) + (portRef I0 + (instanceRef C275) + ) + (portRef I1 + (instanceRef C276) + ) + (portRef I0 + (instanceRef C286) + ) + (portRef I1 + (instanceRef C287) + ) + (portRef I0 + (instanceRef C297) + ) + (portRef I1 + (instanceRef C298) + ) + (portRef I0 + (instanceRef C308) + ) + (portRef I1 + (instanceRef C315) + ) + (portRef I0 + (instanceRef C325) + ) + (portRef I1 + (instanceRef C333) + ) + (portRef I0 + (instanceRef C343) + ) + (portRef I1 + (instanceRef C376) + ) + (portRef I0 + (instanceRef C386) + ) + ) + ) + (net EnabRx + (joined + (portRef Q + (instanceRef Uart_Rxrate_O_reg) + ) + (portRef CE + (instanceRef Uart_Txrate_Cnt_reg_1) + ) + (portRef CE + (instanceRef Uart_Txrate_Cnt_reg_0) + ) + (portRef I1 + (instanceRef C169) + ) + (portRef I0 + (instanceRef C173) + ) + (portRef I2 + (instanceRef C217) + ) + (portRef I1 + (instanceRef C222) + ) + (portRef I2 + (instanceRef C241) + ) + (portRef I1 + (instanceRef C246) + ) + (portRef I2 + (instanceRef C369) + ) + (portRef I1 + (instanceRef C375) + ) + (portRef I1 + (instanceRef C409) + ) + (portRef I0 + (instanceRef C413) + ) + (portRef I3 + (instanceRef C632) + ) + (portRef I2 + (instanceRef C638) + ) + ) + ) + (net + (rename RxData_0 "RxData<0>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_0) + ) + (portRef I3 + (instanceRef C81) + ) + (portRef I2 + (instanceRef C89) + ) + ) + ) + (net + (rename RxData_1 "RxData<1>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_1) + ) + (portRef I3 + (instanceRef C98) + ) + (portRef I2 + (instanceRef C106) + ) + ) + ) + (net + (rename RxData_2 "RxData<2>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_2) + ) + (portRef I2 + (instanceRef C108) + ) + (portRef I1 + (instanceRef C112) + ) + ) + ) + (net + (rename RxData_3 "RxData<3>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_3) + ) + (portRef I2 + (instanceRef C113) + ) + (portRef I1 + (instanceRef C117) + ) + ) + ) + (net + (rename RxData_4 "RxData<4>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_4) + ) + (portRef I2 + (instanceRef C118) + ) + (portRef I1 + (instanceRef C122) + ) + ) + ) + (net + (rename RxData_5 "RxData<5>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_5) + ) + (portRef I2 + (instanceRef C123) + ) + (portRef I1 + (instanceRef C127) + ) + ) + ) + (net + (rename RxData_6 "RxData<6>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_6) + ) + (portRef I2 + (instanceRef C128) + ) + (portRef I1 + (instanceRef C132) + ) + ) + ) + (net + (rename RxData_7 "RxData<7>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_DataO_reg_7) + ) + (portRef I2 + (instanceRef C133) + ) + (portRef I1 + (instanceRef C137) + ) + ) + ) + (net EnabTx + (joined + (portRef Q + (instanceRef Uart_Txrate_O_reg) + ) + (portRef CE + (instanceRef Uart_TxUnit_TxD_reg) + ) + (portRef I2 + (instanceRef C452) + ) + (portRef I1 + (instanceRef C459) + ) + (portRef I0 + (instanceRef C460) + ) + (portRef I0 + (instanceRef C461) + ) + (portRef I2 + (instanceRef C501) + ) + (portRef I + (instanceRef C522) + ) + ) + ) + (net N299_BUFGed + (joined + (portRef C + (instanceRef Uart_TxUnit_SyncLoad_C1A_reg) + ) + (portRef O + (instanceRef C599) + ) + ) + ) + (net + (rename TxData_7 "TxData<7>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_7) + ) + (portRef Q + (instanceRef TxData_reg_7) + ) + ) + ) + (net + (rename TxData_6 "TxData<6>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_6) + ) + (portRef Q + (instanceRef TxData_reg_6) + ) + ) + ) + (net + (rename TxData_5 "TxData<5>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_5) + ) + (portRef Q + (instanceRef TxData_reg_5) + ) + ) + ) + (net + (rename TxData_4 "TxData<4>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_4) + ) + (portRef Q + (instanceRef TxData_reg_4) + ) + ) + ) + (net + (rename TxData_3 "TxData<3>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_3) + ) + (portRef Q + (instanceRef TxData_reg_3) + ) + ) + ) + (net + (rename TxData_2 "TxData<2>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_2) + ) + (portRef Q + (instanceRef TxData_reg_2) + ) + ) + ) + (net + (rename TxData_1 "TxData<1>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_1) + ) + (portRef Q + (instanceRef TxData_reg_1) + ) + ) + ) + (net + (rename TxData_0 "TxData<0>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBuff_reg_0) + ) + (portRef Q + (instanceRef TxData_reg_0) + ) + ) + ) + (net ReadA + (joined + (portRef Q + (instanceRef ReadA_reg) + ) + (portRef I2 + (instanceRef C402) + ) + (portRef I + (instanceRef C408) + ) + ) + ) + (net + (rename C3_N5 "C3/N5") + (joined + (portRef D + (instanceRef ReadA_reg) + ) + (portRef O + (instanceRef C652) + ) + (portRef O + (instanceRef C653) + ) + ) + ) + (net + (rename C5_N5 "C5/N5") + (joined + (portRef D + (instanceRef LoadA_reg) + ) + (portRef CE + (instanceRef TxData_reg_7) + ) + (portRef CE + (instanceRef TxData_reg_6) + ) + (portRef CE + (instanceRef TxData_reg_5) + ) + (portRef CE + (instanceRef TxData_reg_4) + ) + (portRef CE + (instanceRef TxData_reg_3) + ) + (portRef CE + (instanceRef TxData_reg_2) + ) + (portRef CE + (instanceRef TxData_reg_1) + ) + (portRef CE + (instanceRef TxData_reg_0) + ) + (portRef O + (instanceRef C646) + ) + (portRef O + (instanceRef C647) + ) + ) + ) + (net + (rename C7_N4 "C7/N4") + (joined + (portRef I + (instanceRef C502) + ) + (portRef O + (instanceRef C133) + ) + (portRef O + (instanceRef C134) + ) + ) + ) + (net + (rename C7_N11 "C7/N11") + (joined + (portRef I + (instanceRef C503) + ) + (portRef O + (instanceRef C128) + ) + (portRef O + (instanceRef C129) + ) + ) + ) + (net + (rename C7_N17 "C7/N17") + (joined + (portRef I + (instanceRef C504) + ) + (portRef O + (instanceRef C123) + ) + (portRef O + (instanceRef C124) + ) + ) + ) + (net + (rename C7_N23 "C7/N23") + (joined + (portRef I + (instanceRef C505) + ) + (portRef O + (instanceRef C118) + ) + (portRef O + (instanceRef C119) + ) + ) + ) + (net + (rename C7_N29 "C7/N29") + (joined + (portRef I + (instanceRef C506) + ) + (portRef O + (instanceRef C113) + ) + (portRef O + (instanceRef C114) + ) + ) + ) + (net + (rename C7_N35 "C7/N35") + (joined + (portRef I + (instanceRef C507) + ) + (portRef O + (instanceRef C108) + ) + (portRef O + (instanceRef C109) + ) + ) + ) + (net + (rename C7_N45 "C7/N45") + (joined + (portRef I + (instanceRef C508) + ) + (portRef O + (instanceRef C98) + ) + (portRef O + (instanceRef C99) + ) + ) + ) + (net + (rename C7_N52 "C7/N52") + (joined + (portRef I + (instanceRef C509) + ) + (portRef O + (instanceRef C81) + ) + (portRef O + (instanceRef C82) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_0 "Uart_Rxrate/Cnt<0>") + (joined + (portRef A1 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_0) + ) + (portRef I1 + (instanceRef C0) + ) + (portRef I4 + (instanceRef C0) + ) + (portRef I + (instanceRef C1) + ) + (portRef I + (instanceRef C5) + ) + (portRef I4 + (instanceRef C15) + ) + (portRef I + (instanceRef C23) + ) + (portRef I3 + (instanceRef C24) + ) + (portRef I + (instanceRef C32) + ) + (portRef I4 + (instanceRef C33) + ) + (portRef I + (instanceRef C41) + ) + (portRef I3 + (instanceRef C42) + ) + (portRef I + (instanceRef C50) + ) + (portRef I4 + (instanceRef C51) + ) + (portRef I + (instanceRef C59) + ) + (portRef I3 + (instanceRef C60) + ) + (portRef I + (instanceRef C68) + ) + (portRef I4 + (instanceRef C69) + ) + (portRef I + (instanceRef C80) + ) + (portRef I1 + (instanceRef C639) + ) + (portRef I + (instanceRef C642) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_4 "Uart_Rxrate/Cnt<4>") + (joined + (portRef A1 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_4) + ) + (portRef I4 + (instanceRef C42) + ) + (portRef I1 + (instanceRef C47) + ) + (portRef I3 + (instanceRef C752) + ) + (portRef I + (instanceRef C761) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_6 "Uart_Rxrate/Cnt<6>") + (joined + (portRef A1 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_6) + ) + (portRef I4 + (instanceRef C60) + ) + (portRef I1 + (instanceRef C65) + ) + (portRef I2 + (instanceRef C745) + ) + (portRef I + (instanceRef C751) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_2 "Uart_Rxrate/Cnt<2>") + (joined + (portRef A1 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_2) + ) + (portRef I4 + (instanceRef C24) + ) + (portRef I1 + (instanceRef C29) + ) + (portRef I1 + (instanceRef C752) + ) + (portRef I + (instanceRef C759) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_3 "Uart_Rxrate/Cnt<3>") + (joined + (portRef A0 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_3) + ) + (portRef I1 + (instanceRef C33) + ) + (portRef I0 + (instanceRef C38) + ) + (portRef I2 + (instanceRef C752) + ) + (portRef I + (instanceRef C760) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_7 "Uart_Rxrate/Cnt<7>") + (joined + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_7) + ) + (portRef I1 + (instanceRef C69) + ) + (portRef I0 + (instanceRef C76) + ) + (portRef I1 + (instanceRef C745) + ) + (portRef I + (instanceRef C750) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_5 "Uart_Rxrate/Cnt<5>") + (joined + (portRef A0 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_5) + ) + (portRef I1 + (instanceRef C51) + ) + (portRef I0 + (instanceRef C56) + ) + (portRef I4 + (instanceRef C752) + ) + (portRef I + (instanceRef C762) + ) + ) + ) + (net + (rename Uart_Rxrate_Cnt_1 "Uart_Rxrate/Cnt<1>") + (joined + (portRef A0 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef Q + (instanceRef Uart_Rxrate_Cnt_reg_1) + ) + (portRef I2 + (instanceRef C0) + ) + (portRef I + (instanceRef C8) + ) + (portRef I1 + (instanceRef C15) + ) + (portRef I0 + (instanceRef C20) + ) + (portRef I1 + (instanceRef C666) + ) + (portRef I + (instanceRef C736) + ) + ) + ) + (net + (rename Uart_Rxrate_C64 "Uart_Rxrate/C64") + (joined + (portRef I2 + (instanceRef C15) + ) + (portRef I + (instanceRef C19) + ) + (portRef I1 + (instanceRef C24) + ) + (portRef I + (instanceRef C28) + ) + (portRef I2 + (instanceRef C33) + ) + (portRef I + (instanceRef C37) + ) + (portRef I1 + (instanceRef C42) + ) + (portRef I + (instanceRef C46) + ) + (portRef I2 + (instanceRef C51) + ) + (portRef I + (instanceRef C55) + ) + (portRef I1 + (instanceRef C60) + ) + (portRef I + (instanceRef C64) + ) + (portRef I2 + (instanceRef C69) + ) + (portRef I + (instanceRef C75) + ) + (portRef I2 + (instanceRef C639) + ) + (portRef I + (instanceRef C643) + ) + (portRef O + (instanceRef C666) + ) + (portRef O + (instanceRef C732) + ) + ) + ) + (net + (rename Uart_Rxrate_C67 "Uart_Rxrate/C67") + (joined + (portRef I3 + (instanceRef C0) + ) + (portRef I + (instanceRef C9) + ) + (portRef I2 + (instanceRef C666) + ) + (portRef I + (instanceRef C737) + ) + (portRef O + (instanceRef C738) + ) + (portRef O + (instanceRef C739) + ) + ) + ) + (net + (rename Uart_Txrate_C0_N3 "Uart_Txrate/C0/N3") + (joined + (portRef D + (instanceRef Uart_Txrate_O_reg) + ) + (portRef O + (instanceRef C632) + ) + (portRef O + (instanceRef C633) + ) + ) + ) + (net + (rename Uart_Txrate_Cnt_1 "Uart_Txrate/Cnt<1>") + (joined + (portRef Q + (instanceRef Uart_Txrate_Cnt_reg_1) + ) + (portRef I1 + (instanceRef C623) + ) + (portRef I + (instanceRef C627) + ) + (portRef I0 + (instanceRef C630) + ) + (portRef I1 + (instanceRef C632) + ) + (portRef I + (instanceRef C635) + ) + ) + ) + (net + (rename Uart_Txrate_Cnt_0 "Uart_Txrate/Cnt<0>") + (joined + (portRef Q + (instanceRef Uart_Txrate_Cnt_reg_0) + ) + (portRef I + (instanceRef C603) + ) + (portRef I2 + (instanceRef C623) + ) + (portRef I + (instanceRef C628) + ) + (portRef I1 + (instanceRef C630) + ) + (portRef I2 + (instanceRef C632) + ) + (portRef I + (instanceRef C636) + ) + ) + ) + (net + (rename Uart_TxUnit_LoadS "Uart_TxUnit/LoadS") + (joined + (portRef Q + (instanceRef Uart_TxUnit_SyncLoad_C1S_reg) + ) + (portRef D + (instanceRef Uart_TxUnit_SyncLoad_R_reg) + ) + (portRef I1 + (instanceRef C91) + ) + (portRef I + (instanceRef C94) + ) + (portRef I2 + (instanceRef C480) + ) + (portRef I1 + (instanceRef C485) + ) + (portRef I1 + (instanceRef C493) + ) + (portRef I + (instanceRef C499) + ) + ) + ) + (net + (rename Uart_TxUnit_TBufL "Uart_TxUnit/TBufL") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TBufL_reg) + ) + (portRef I2 + (instanceRef C91) + ) + (portRef I + (instanceRef C95) + ) + (portRef I3 + (instanceRef C452) + ) + (portRef I1 + (instanceRef C460) + ) + (portRef I3 + (instanceRef C501) + ) + (portRef I + (instanceRef C523) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_7 "Uart_TxUnit/TReg<7>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_7) + ) + (portRef I4 + (instanceRef C547) + ) + (portRef I1 + (instanceRef C556) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_6 "Uart_TxUnit/TReg<6>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_6) + ) + (portRef I3 + (instanceRef C615) + ) + (portRef I1 + (instanceRef C622) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_5 "Uart_TxUnit/TReg<5>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_5) + ) + (portRef I4 + (instanceRef C557) + ) + (portRef I1 + (instanceRef C567) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_4 "Uart_TxUnit/TReg<4>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_4) + ) + (portRef I4 + (instanceRef C607) + ) + (portRef I2 + (instanceRef C614) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_3 "Uart_TxUnit/TReg<3>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_3) + ) + (portRef I3 + (instanceRef C547) + ) + (portRef I1 + (instanceRef C555) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_2 "Uart_TxUnit/TReg<2>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_2) + ) + (portRef I2 + (instanceRef C615) + ) + (portRef I1 + (instanceRef C621) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_1 "Uart_TxUnit/TReg<1>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_1) + ) + (portRef I3 + (instanceRef C557) + ) + (portRef I1 + (instanceRef C566) + ) + ) + ) + (net + (rename Uart_TxUnit_TReg_0 "Uart_TxUnit/TReg<0>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_TReg_reg_0) + ) + (portRef I3 + (instanceRef C607) + ) + (portRef I2 + (instanceRef C613) + ) + ) + ) + (net + (rename Uart_TxUnit_BitPos_3 "Uart_TxUnit/BitPos<3>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_BitPos_reg_3) + ) + (portRef I3 + (instanceRef C427) + ) + (portRef I + (instanceRef C434) + ) + (portRef I3 + (instanceRef C462) + ) + (portRef I + (instanceRef C474) + ) + (portRef I1 + (instanceRef C476) + ) + (portRef I1 + (instanceRef C477) + ) + (portRef I1 + (instanceRef C478) + ) + (portRef I3 + (instanceRef C568) + ) + (portRef I + (instanceRef C573) + ) + ) + ) + (net + (rename Uart_TxUnit_BitPos_2 "Uart_TxUnit/BitPos<2>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_BitPos_reg_2) + ) + (portRef I4 + (instanceRef C427) + ) + (portRef I2 + (instanceRef C439) + ) + (portRef I2 + (instanceRef C440) + ) + (portRef I + (instanceRef C447) + ) + (portRef I0 + (instanceRef C449) + ) + (portRef I1 + (instanceRef C450) + ) + (portRef I4 + (instanceRef C462) + ) + (portRef I + (instanceRef C473) + ) + (portRef I2 + (instanceRef C477) + ) + (portRef I3 + (instanceRef C479) + ) + (portRef I2 + (instanceRef C547) + ) + (portRef I + (instanceRef C552) + ) + (portRef I0 + (instanceRef C555) + ) + (portRef I2 + (instanceRef C557) + ) + (portRef I + (instanceRef C563) + ) + (portRef I0 + (instanceRef C567) + ) + (portRef I2 + (instanceRef C568) + ) + (portRef I + (instanceRef C572) + ) + (portRef I2 + (instanceRef C607) + ) + (portRef I + (instanceRef C611) + ) + (portRef I1 + (instanceRef C614) + ) + (portRef I1 + (instanceRef C615) + ) + (portRef I + (instanceRef C619) + ) + (portRef I0 + (instanceRef C621) + ) + ) + ) + (net + (rename Uart_TxUnit_BitPos_1 "Uart_TxUnit/BitPos<1>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_BitPos_reg_1) + ) + (portRef I2 + (instanceRef C427) + ) + (portRef I + (instanceRef C433) + ) + (portRef I + (instanceRef C435) + ) + (portRef I1 + (instanceRef C437) + ) + (portRef I1 + (instanceRef C440) + ) + (portRef I + (instanceRef C446) + ) + (portRef I0 + (instanceRef C451) + ) + (portRef I2 + (instanceRef C462) + ) + (portRef I + (instanceRef C472) + ) + (portRef I0 + (instanceRef C478) + ) + (portRef I1 + (instanceRef C479) + ) + (portRef I1 + (instanceRef C547) + ) + (portRef I + (instanceRef C554) + ) + (portRef I1 + (instanceRef C557) + ) + (portRef I + (instanceRef C562) + ) + (portRef I1 + (instanceRef C568) + ) + (portRef I + (instanceRef C571) + ) + (portRef I1 + (instanceRef C576) + ) + (portRef I + (instanceRef C593) + ) + (portRef I1 + (instanceRef C607) + ) + (portRef I0 + (instanceRef C613) + ) + (portRef I0 + (instanceRef C614) + ) + ) + ) + (net + (rename Uart_TxUnit_BitPos_0 "Uart_TxUnit/BitPos<0>") + (joined + (portRef Q + (instanceRef Uart_TxUnit_BitPos_reg_0) + ) + (portRef I + (instanceRef C602) + ) + (portRef I1 + (instanceRef C427) + ) + (portRef I + (instanceRef C432) + ) + (portRef I0 + (instanceRef C438) + ) + (portRef I0 + (instanceRef C439) + ) + (portRef I3 + (instanceRef C440) + ) + (portRef I + (instanceRef C445) + ) + (portRef I2 + (instanceRef C451) + ) + (portRef I1 + (instanceRef C452) + ) + (portRef I0 + (instanceRef C459) + ) + (portRef I1 + (instanceRef C462) + ) + (portRef I + (instanceRef C471) + ) + (portRef I0 + (instanceRef C479) + ) + (portRef I1 + (instanceRef C501) + ) + (portRef I + (instanceRef C526) + ) + (portRef I1 + (instanceRef C530) + ) + (portRef I + (instanceRef C534) + ) + (portRef I1 + (instanceRef C538) + ) + (portRef I + (instanceRef C542) + ) + (portRef I0 + (instanceRef C546) + ) + ) + ) + (net + (rename Uart_TxUnit_C17_N9 "Uart_TxUnit/C17/N9") + (joined + (portRef D + (instanceRef Uart_TxUnit_TxD_reg) + ) + (portRef O + (instanceRef C530) + ) + (portRef O + (instanceRef C531) + ) + ) + ) + (net + (rename Uart_TxUnit_C11_N6 "Uart_TxUnit/C11/N6") + (joined + (portRef CE + (instanceRef Uart_TxUnit_TBufL_reg) + ) + (portRef O + (instanceRef C493) + ) + (portRef O + (instanceRef C494) + ) + ) + ) + (net + (rename Uart_TxUnit_C10_N6 "Uart_TxUnit/C10/N6") + (joined + (portRef D + (instanceRef Uart_TxUnit_TBufL_reg) + ) + (portRef I2 + (instanceRef C486) + ) + (portRef I + (instanceRef C490) + ) + (portRef I2 + (instanceRef C493) + ) + (portRef I + (instanceRef C497) + ) + (portRef O + (instanceRef C501) + ) + (portRef O + (instanceRef C515) + ) + ) + ) + (net + (rename Uart_TxUnit_C9_N5 "Uart_TxUnit/C9/N5") + (joined + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_0) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_1) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_2) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_3) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_4) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_5) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_6) + ) + (portRef CE + (instanceRef Uart_TxUnit_TReg_reg_7) + ) + (portRef O + (instanceRef C486) + ) + (portRef O + (instanceRef C487) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_0 "Uart_TxUnit/TBuff<0>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_0) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_0) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_1 "Uart_TxUnit/TBuff<1>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_1) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_1) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_2 "Uart_TxUnit/TBuff<2>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_2) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_2) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_3 "Uart_TxUnit/TBuff<3>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_3) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_3) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_4 "Uart_TxUnit/TBuff<4>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_4) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_4) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_5 "Uart_TxUnit/TBuff<5>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_5) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_5) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_6 "Uart_TxUnit/TBuff<6>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_6) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_6) + ) + ) + ) + (net + (rename Uart_TxUnit_TBuff_7 "Uart_TxUnit/TBuff<7>") + (joined + (portRef D + (instanceRef Uart_TxUnit_TReg_reg_7) + ) + (portRef Q + (instanceRef Uart_TxUnit_TBuff_reg_7) + ) + ) + ) + (net + (rename Uart_TxUnit_C8_N5 "Uart_TxUnit/C8/N5") + (joined + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_0) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_1) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_2) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_3) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_4) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_5) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_6) + ) + (portRef CE + (instanceRef Uart_TxUnit_TBuff_reg_7) + ) + (portRef O + (instanceRef C480) + ) + (portRef O + (instanceRef C481) + ) + ) + ) + (net + (rename Uart_TxUnit_C14_N19 "Uart_TxUnit/C14/N19") + (joined + (portRef CE + (instanceRef Uart_TxUnit_BitPos_reg_3) + ) + (portRef CE + (instanceRef Uart_TxUnit_BitPos_reg_2) + ) + (portRef CE + (instanceRef Uart_TxUnit_BitPos_reg_1) + ) + (portRef CE + (instanceRef Uart_TxUnit_BitPos_reg_0) + ) + (portRef O + (instanceRef C452) + ) + (portRef O + (instanceRef C453) + ) + ) + ) + (net + (rename Uart_TxUnit_C4_N5 "Uart_TxUnit/C4/N5") + (joined + (portRef D + (instanceRef Uart_TxUnit_BitPos_reg_3) + ) + (portRef O + (instanceRef C462) + ) + (portRef O + (instanceRef C463) + ) + ) + ) + (net + (rename Uart_TxUnit_C4_N10 "Uart_TxUnit/C4/N10") + (joined + (portRef D + (instanceRef Uart_TxUnit_BitPos_reg_2) + ) + (portRef O + (instanceRef C440) + ) + (portRef O + (instanceRef C441) + ) + ) + ) + (net + (rename Uart_TxUnit_C4_N15 "Uart_TxUnit/C4/N15") + (joined + (portRef D + (instanceRef Uart_TxUnit_BitPos_reg_1) + ) + (portRef O + (instanceRef C427) + ) + (portRef O + (instanceRef C428) + ) + ) + ) + (net + (rename Uart_TxUnit_C4_N20 "Uart_TxUnit/C4/N20") + (joined + (portRef D + (instanceRef Uart_TxUnit_BitPos_reg_0) + ) + (portRef O + (instanceRef C602) + ) + ) + ) + (net + (rename Uart_RxUnit_SampleCnt_1 "Uart_RxUnit/SampleCnt<1>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_SampleCnt_reg_1) + ) + (portRef I2 + (instanceRef C174) + ) + (portRef I1 + (instanceRef C181) + ) + (portRef I3 + (instanceRef C223) + ) + (portRef I + (instanceRef C228) + ) + (portRef I2 + (instanceRef C233) + ) + (portRef I3 + (instanceRef C369) + ) + (portRef I + (instanceRef C373) + ) + ) + ) + (net + (rename Uart_RxUnit_SampleCnt_0 "Uart_RxUnit/SampleCnt<0>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_SampleCnt_reg_0) + ) + (portRef I3 + (instanceRef C174) + ) + (portRef I2 + (instanceRef C181) + ) + (portRef I1 + (instanceRef C209) + ) + (portRef I + (instanceRef C213) + ) + (portRef I1 + (instanceRef C223) + ) + (portRef I + (instanceRef C229) + ) + (portRef I0 + (instanceRef C232) + ) + (portRef I4 + (instanceRef C369) + ) + (portRef I3 + (instanceRef C375) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_7 "Uart_RxUnit/RReg<7>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_7) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_7) + ) + (portRef I4 + (instanceRef C254) + ) + (portRef I1 + (instanceRef C262) + ) + (portRef I1 + (instanceRef C263) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_7 "Uart_RxUnit/larray420<7>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_7) + ) + (portRef O + (instanceRef C254) + ) + (portRef O + (instanceRef C255) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_6 "Uart_RxUnit/RReg<6>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_6) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_6) + ) + (portRef I4 + (instanceRef C265) + ) + (portRef I1 + (instanceRef C273) + ) + (portRef I1 + (instanceRef C274) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_6 "Uart_RxUnit/larray420<6>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_6) + ) + (portRef O + (instanceRef C265) + ) + (portRef O + (instanceRef C266) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_5 "Uart_RxUnit/RReg<5>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_5) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_5) + ) + (portRef I4 + (instanceRef C276) + ) + (portRef I1 + (instanceRef C284) + ) + (portRef I1 + (instanceRef C285) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_5 "Uart_RxUnit/larray420<5>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_5) + ) + (portRef O + (instanceRef C276) + ) + (portRef O + (instanceRef C277) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_4 "Uart_RxUnit/RReg<4>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_4) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_4) + ) + (portRef I4 + (instanceRef C287) + ) + (portRef I1 + (instanceRef C295) + ) + (portRef I1 + (instanceRef C296) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_4 "Uart_RxUnit/larray420<4>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_4) + ) + (portRef O + (instanceRef C287) + ) + (portRef O + (instanceRef C288) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_3 "Uart_RxUnit/RReg<3>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_3) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_3) + ) + (portRef I4 + (instanceRef C298) + ) + (portRef I1 + (instanceRef C306) + ) + (portRef I1 + (instanceRef C307) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_3 "Uart_RxUnit/larray420<3>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_3) + ) + (portRef O + (instanceRef C298) + ) + (portRef O + (instanceRef C299) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_2 "Uart_RxUnit/RReg<2>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_2) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_2) + ) + (portRef I4 + (instanceRef C315) + ) + (portRef I1 + (instanceRef C323) + ) + (portRef I1 + (instanceRef C324) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_2 "Uart_RxUnit/larray420<2>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_2) + ) + (portRef O + (instanceRef C315) + ) + (portRef O + (instanceRef C316) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_1 "Uart_RxUnit/RReg<1>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_1) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_1) + ) + (portRef I4 + (instanceRef C333) + ) + (portRef I1 + (instanceRef C341) + ) + (portRef I1 + (instanceRef C342) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_1 "Uart_RxUnit/larray420<1>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_1) + ) + (portRef O + (instanceRef C333) + ) + (portRef O + (instanceRef C334) + ) + ) + ) + (net + (rename Uart_RxUnit_RReg_0 "Uart_RxUnit/RReg<0>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_RReg_reg_0) + ) + (portRef D + (instanceRef Uart_RxUnit_DataO_reg_0) + ) + (portRef I4 + (instanceRef C376) + ) + (portRef I1 + (instanceRef C384) + ) + (portRef I1 + (instanceRef C385) + ) + ) + ) + (net + (rename Uart_RxUnit_larray420_0 "Uart_RxUnit/larray420<0>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RReg_reg_0) + ) + (portRef O + (instanceRef C376) + ) + (portRef O + (instanceRef C377) + ) + ) + ) + (net N298_BUFGed + (joined + (portRef C + (instanceRef Uart_RxUnit_RxAv_reg) + ) + (portRef O + (instanceRef C598) + ) + ) + ) + (net + (rename Uart_RxUnit_C13_N3 "Uart_RxUnit/C13/N3") + (joined + (portRef CE + (instanceRef Uart_RxUnit_RRegL_reg) + ) + (portRef O + (instanceRef C409) + ) + (portRef O + (instanceRef C410) + ) + ) + ) + (net + (rename Uart_RxUnit_BitPos_3 "Uart_RxUnit/BitPos<3>") + (joined + (portRef D + (instanceRef Uart_RxUnit_RRegL_reg) + ) + (portRef Q + (instanceRef Uart_RxUnit_BitPos_reg_3) + ) + (portRef I1 + (instanceRef C191) + ) + (portRef I + (instanceRef C200) + ) + (portRef I0 + (instanceRef C202) + ) + (portRef I0 + (instanceRef C206) + ) + (portRef I0 + (instanceRef C207) + ) + (portRef I1 + (instanceRef C247) + ) + (portRef I0 + (instanceRef C253) + ) + (portRef I3 + (instanceRef C361) + ) + (portRef I + (instanceRef C366) + ) + (portRef I3 + (instanceRef C414) + ) + (portRef I + (instanceRef C422) + ) + (portRef I2 + (instanceRef C425) + ) + ) + ) + (net + (rename Uart_RxUnit_n558 "Uart_RxUnit/n558") + (joined + (portRef CLR + (instanceRef Uart_RxUnit_RxAv_reg) + ) + (portRef O + (instanceRef C402) + ) + (portRef O + (instanceRef C403) + ) + ) + ) + (net + (rename Uart_RxUnit_C12_N5 "Uart_RxUnit/C12/N5") + (joined + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_0) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_1) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_2) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_3) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_4) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_5) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_6) + ) + (portRef CE + (instanceRef Uart_RxUnit_RReg_reg_7) + ) + (portRef O + (instanceRef C349) + ) + (portRef O + (instanceRef C350) + ) + ) + ) + (net + (rename Uart_RxUnit_C11_N5 "Uart_RxUnit/C11/N5") + (joined + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_0) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_1) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_2) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_3) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_4) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_5) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_6) + ) + (portRef CE + (instanceRef Uart_RxUnit_DataO_reg_7) + ) + (portRef O + (instanceRef C241) + ) + (portRef O + (instanceRef C242) + ) + ) + ) + (net + (rename Uart_RxUnit_C10_N10 "Uart_RxUnit/C10/N10") + (joined + (portRef CE + (instanceRef Uart_RxUnit_SampleCnt_reg_1) + ) + (portRef CE + (instanceRef Uart_RxUnit_SampleCnt_reg_0) + ) + (portRef O + (instanceRef C217) + ) + (portRef O + (instanceRef C218) + ) + ) + ) + (net + (rename Uart_RxUnit_C15_N19 "Uart_RxUnit/C15/N19") + (joined + (portRef CE + (instanceRef Uart_RxUnit_BitPos_reg_3) + ) + (portRef CE + (instanceRef Uart_RxUnit_BitPos_reg_2) + ) + (portRef CE + (instanceRef Uart_RxUnit_BitPos_reg_1) + ) + (portRef CE + (instanceRef Uart_RxUnit_BitPos_reg_0) + ) + (portRef O + (instanceRef C169) + ) + (portRef O + (instanceRef C170) + ) + ) + ) + (net + (rename Uart_RxUnit_BitPos_2 "Uart_RxUnit/BitPos<2>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_BitPos_reg_2) + ) + (portRef I1 + (instanceRef C160) + ) + (portRef I + (instanceRef C164) + ) + (portRef I0 + (instanceRef C168) + ) + (portRef I4 + (instanceRef C191) + ) + (portRef I + (instanceRef C199) + ) + (portRef I2 + (instanceRef C206) + ) + (portRef I3 + (instanceRef C208) + ) + (portRef I4 + (instanceRef C247) + ) + (portRef I + (instanceRef C251) + ) + (portRef I2 + (instanceRef C361) + ) + (portRef I + (instanceRef C365) + ) + (portRef I2 + (instanceRef C387) + ) + (portRef I + (instanceRef C392) + ) + (portRef I1 + (instanceRef C394) + ) + (portRef I4 + (instanceRef C414) + ) + (portRef I + (instanceRef C419) + ) + (portRef I + (instanceRef C423) + ) + ) + ) + (net + (rename Uart_RxUnit_BitPos_1 "Uart_RxUnit/BitPos<1>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_BitPos_reg_1) + ) + (portRef I2 + (instanceRef C138) + ) + (portRef I + (instanceRef C143) + ) + (portRef I2 + (instanceRef C149) + ) + (portRef I + (instanceRef C155) + ) + (portRef I1 + (instanceRef C158) + ) + (portRef I3 + (instanceRef C191) + ) + (portRef I + (instanceRef C197) + ) + (portRef I2 + (instanceRef C208) + ) + (portRef I3 + (instanceRef C247) + ) + (portRef I2 + (instanceRef C253) + ) + (portRef I2 + (instanceRef C309) + ) + (portRef I + (instanceRef C312) + ) + (portRef I2 + (instanceRef C326) + ) + (portRef I + (instanceRef C330) + ) + (portRef I2 + (instanceRef C344) + ) + (portRef I1 + (instanceRef C348) + ) + (portRef I1 + (instanceRef C361) + ) + (portRef I + (instanceRef C364) + ) + (portRef I1 + (instanceRef C387) + ) + (portRef I + (instanceRef C391) + ) + (portRef I0 + (instanceRef C395) + ) + (portRef I2 + (instanceRef C396) + ) + (portRef I1 + (instanceRef C401) + ) + (portRef I2 + (instanceRef C414) + ) + (portRef I + (instanceRef C421) + ) + (portRef I1 + (instanceRef C425) + ) + ) + ) + (net + (rename Uart_RxUnit_BitPos_0 "Uart_RxUnit/BitPos<0>") + (joined + (portRef Q + (instanceRef Uart_RxUnit_BitPos_reg_0) + ) + (portRef I1 + (instanceRef C138) + ) + (portRef I + (instanceRef C142) + ) + (portRef I + (instanceRef C144) + ) + (portRef I1 + (instanceRef C149) + ) + (portRef I + (instanceRef C153) + ) + (portRef I0 + (instanceRef C159) + ) + (portRef I3 + (instanceRef C182) + ) + (portRef I + (instanceRef C187) + ) + (portRef I2 + (instanceRef C191) + ) + (portRef I + (instanceRef C198) + ) + (portRef I1 + (instanceRef C207) + ) + (portRef I1 + (instanceRef C208) + ) + (portRef I2 + (instanceRef C247) + ) + (portRef I + (instanceRef C250) + ) + (portRef I1 + (instanceRef C309) + ) + (portRef I0 + (instanceRef C314) + ) + (portRef I1 + (instanceRef C326) + ) + (portRef I + (instanceRef C329) + ) + (portRef I1 + (instanceRef C344) + ) + (portRef I0 + (instanceRef C348) + ) + (portRef I1 + (instanceRef C396) + ) + (portRef I + (instanceRef C399) + ) + (portRef I1 + (instanceRef C414) + ) + (portRef I + (instanceRef C418) + ) + (portRef I + (instanceRef C420) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_N2 "Uart_Rxrate/C126/N2") + (joined + (portRef COUT + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef CIN + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef I3 + (instanceRef C15) + ) + (portRef I1 + (instanceRef C20) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_N7 "Uart_Rxrate/C126/N7") + (joined + (portRef COUT + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef CIN + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef I3 + (instanceRef C33) + ) + (portRef I1 + (instanceRef C38) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_N12 "Uart_Rxrate/C126/N12") + (joined + (portRef COUT + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef CIN + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef I3 + (instanceRef C51) + ) + (portRef I1 + (instanceRef C56) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_N17 "Uart_Rxrate/C126/N17") + (joined + (portRef COUT + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef CIN + (instanceRef C600) + ) + (portRef I3 + (instanceRef C69) + ) + (portRef I1 + (instanceRef C76) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N6 "Uart_Rxrate/C127/N6") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_0) + ) + (portRef O + (instanceRef C0) + ) + (portRef O + (instanceRef C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N11 "Uart_Rxrate/C127/N11") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_1) + ) + (portRef O + (instanceRef C15) + ) + (portRef O + (instanceRef C21) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N16 "Uart_Rxrate/C127/N16") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_2) + ) + (portRef O + (instanceRef C24) + ) + (portRef O + (instanceRef C30) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N21 "Uart_Rxrate/C127/N21") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_3) + ) + (portRef O + (instanceRef C33) + ) + (portRef O + (instanceRef C39) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N26 "Uart_Rxrate/C127/N26") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_4) + ) + (portRef O + (instanceRef C42) + ) + (portRef O + (instanceRef C48) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N31 "Uart_Rxrate/C127/N31") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_5) + ) + (portRef O + (instanceRef C51) + ) + (portRef O + (instanceRef C57) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N36 "Uart_Rxrate/C127/N36") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_6) + ) + (portRef O + (instanceRef C60) + ) + (portRef O + (instanceRef C66) + ) + ) + ) + (net + (rename Uart_Rxrate_C127_N42 "Uart_Rxrate/C127/N42") + (joined + (portRef D + (instanceRef Uart_Rxrate_Cnt_reg_7) + ) + (portRef O + (instanceRef C69) + ) + (portRef O + (instanceRef C71) + ) + ) + ) + (net + (rename Uart_Txrate_C59_N6 "Uart_Txrate/C59/N6") + (joined + (portRef D + (instanceRef Uart_Txrate_Cnt_reg_0) + ) + (portRef O + (instanceRef C603) + ) + ) + ) + (net + (rename Uart_Txrate_C59_N11 "Uart_Txrate/C59/N11") + (joined + (portRef D + (instanceRef Uart_Txrate_Cnt_reg_1) + ) + (portRef O + (instanceRef C623) + ) + (portRef O + (instanceRef C624) + ) + ) + ) + (net + (rename Uart_TxUnit_SyncLoad_R "Uart_TxUnit/SyncLoad/R") + (joined + (portRef CLR + (instanceRef Uart_TxUnit_SyncLoad_C1S_reg) + ) + (portRef Q + (instanceRef Uart_TxUnit_SyncLoad_R_reg) + ) + (portRef CLR + (instanceRef Uart_TxUnit_SyncLoad_C1A_reg) + ) + ) + ) + (net + (rename Uart_TxUnit_SyncLoad_C1A "Uart_TxUnit/SyncLoad/C1A") + (joined + (portRef D + (instanceRef Uart_TxUnit_SyncLoad_C1S_reg) + ) + (portRef Q + (instanceRef Uart_TxUnit_SyncLoad_C1A_reg) + ) + ) + ) + (net + (rename Uart_RxUnit_C286_N9 "Uart_RxUnit/C286/N9") + (joined + (portRef D + (instanceRef Uart_RxUnit_BitPos_reg_0) + ) + (portRef O + (instanceRef C138) + ) + (portRef O + (instanceRef C139) + ) + ) + ) + (net + (rename Uart_RxUnit_C286_N14 "Uart_RxUnit/C286/N14") + (joined + (portRef D + (instanceRef Uart_RxUnit_BitPos_reg_1) + ) + (portRef O + (instanceRef C149) + ) + (portRef O + (instanceRef C150) + ) + ) + ) + (net + (rename Uart_RxUnit_C286_N20 "Uart_RxUnit/C286/N20") + (joined + (portRef D + (instanceRef Uart_RxUnit_BitPos_reg_2) + ) + (portRef O + (instanceRef C160) + ) + (portRef O + (instanceRef C161) + ) + ) + ) + (net + (rename Uart_RxUnit_C286_N26 "Uart_RxUnit/C286/N26") + (joined + (portRef D + (instanceRef Uart_RxUnit_BitPos_reg_3) + ) + (portRef O + (instanceRef C191) + ) + (portRef O + (instanceRef C192) + ) + ) + ) + (net + (rename Uart_RxUnit_C287_N5 "Uart_RxUnit/C287/N5") + (joined + (portRef D + (instanceRef Uart_RxUnit_SampleCnt_reg_0) + ) + (portRef O + (instanceRef C209) + ) + (portRef O + (instanceRef C210) + ) + ) + ) + (net + (rename Uart_RxUnit_C287_N10 "Uart_RxUnit/C287/N10") + (joined + (portRef D + (instanceRef Uart_RxUnit_SampleCnt_reg_1) + ) + (portRef O + (instanceRef C223) + ) + (portRef O + (instanceRef C224) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N0 "Uart_Rxrate/C126/C0/N0") + (joined + (portRef C0 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C0 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N1 "Uart_Rxrate/C126/C0/N1") + (joined + (portRef C1 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C1 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N2 "Uart_Rxrate/C126/C0/N2") + (joined + (portRef C2 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C2 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N3 "Uart_Rxrate/C126/C0/N3") + (joined + (portRef C3 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C3 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N4 "Uart_Rxrate/C126/C0/N4") + (joined + (portRef C4 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C4 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N5 "Uart_Rxrate/C126/C0/N5") + (joined + (portRef C5 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C5 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N6 "Uart_Rxrate/C126/C0/N6") + (joined + (portRef C6 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C6 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C0_N7 "Uart_Rxrate/C126/C0/N7") + (joined + (portRef C7 + (instanceRef Uart_Rxrate_C126_C0_C1) + ) + (portRef C7 + (instanceRef Uart_Rxrate_C126_C0_C2) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_cout0_net "Uart_Rxrate/C126/C1/cout0_net") + (joined + (portRef COUT0 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef I2 + (instanceRef C24) + ) + (portRef I0 + (instanceRef C29) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N0 "Uart_Rxrate/C126/C1/N0") + (joined + (portRef C0 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C0 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N1 "Uart_Rxrate/C126/C1/N1") + (joined + (portRef C1 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C1 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N2 "Uart_Rxrate/C126/C1/N2") + (joined + (portRef C2 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C2 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N3 "Uart_Rxrate/C126/C1/N3") + (joined + (portRef C3 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C3 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N4 "Uart_Rxrate/C126/C1/N4") + (joined + (portRef C4 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C4 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N5 "Uart_Rxrate/C126/C1/N5") + (joined + (portRef C5 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C5 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N6 "Uart_Rxrate/C126/C1/N6") + (joined + (portRef C6 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C6 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C1_N7 "Uart_Rxrate/C126/C1/N7") + (joined + (portRef C7 + (instanceRef Uart_Rxrate_C126_C1_C2) + ) + (portRef C7 + (instanceRef Uart_Rxrate_C126_C1_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_cout0_net "Uart_Rxrate/C126/C2/cout0_net") + (joined + (portRef COUT0 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef I2 + (instanceRef C42) + ) + (portRef I0 + (instanceRef C47) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N0 "Uart_Rxrate/C126/C2/N0") + (joined + (portRef C0 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C0 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N1 "Uart_Rxrate/C126/C2/N1") + (joined + (portRef C1 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C1 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N2 "Uart_Rxrate/C126/C2/N2") + (joined + (portRef C2 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C2 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N3 "Uart_Rxrate/C126/C2/N3") + (joined + (portRef C3 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C3 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N4 "Uart_Rxrate/C126/C2/N4") + (joined + (portRef C4 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C4 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N5 "Uart_Rxrate/C126/C2/N5") + (joined + (portRef C5 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C5 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N6 "Uart_Rxrate/C126/C2/N6") + (joined + (portRef C6 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C6 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C2_N7 "Uart_Rxrate/C126/C2/N7") + (joined + (portRef C7 + (instanceRef Uart_Rxrate_C126_C2_C2) + ) + (portRef C7 + (instanceRef Uart_Rxrate_C126_C2_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_cout0_net "Uart_Rxrate/C126/C3/cout0_net") + (joined + (portRef COUT0 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef I2 + (instanceRef C60) + ) + (portRef I0 + (instanceRef C65) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N0 "Uart_Rxrate/C126/C3/N0") + (joined + (portRef C0 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C0 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N1 "Uart_Rxrate/C126/C3/N1") + (joined + (portRef C1 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C1 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N2 "Uart_Rxrate/C126/C3/N2") + (joined + (portRef C2 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C2 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N3 "Uart_Rxrate/C126/C3/N3") + (joined + (portRef C3 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C3 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N4 "Uart_Rxrate/C126/C3/N4") + (joined + (portRef C4 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C4 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N5 "Uart_Rxrate/C126/C3/N5") + (joined + (portRef C5 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C5 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N6 "Uart_Rxrate/C126/C3/N6") + (joined + (portRef C6 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C6 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net + (rename Uart_Rxrate_C126_C3_N7 "Uart_Rxrate/C126/C3/N7") + (joined + (portRef C7 + (instanceRef Uart_Rxrate_C126_C3_C2) + ) + (portRef C7 + (instanceRef Uart_Rxrate_C126_C3_C3) + ) + ) + ) + (net N193 + (joined + (portRef D + (instanceRef Uart_RxUnit_RxAv_reg) + ) + (portRef D + (instanceRef Uart_TxUnit_SyncLoad_C1A_reg) + ) + (portRef P + (instanceRef C667) + ) + ) + ) + (net N197 + (joined + (portRef CLR + (instanceRef ReadA_reg) + ) + (portRef CLR + (instanceRef LoadA_reg) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_0) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_4) + ) + (portRef CLR + (instanceRef Uart_Rxrate_O_reg) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_6) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_2) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_3) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_7) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_5) + ) + (portRef CLR + (instanceRef Uart_Rxrate_Cnt_reg_1) + ) + (portRef CLR + (instanceRef Uart_Txrate_O_reg) + ) + (portRef CLR + (instanceRef Uart_Txrate_Cnt_reg_1) + ) + (portRef CLR + (instanceRef Uart_Txrate_Cnt_reg_0) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_0) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_1) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_2) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_3) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_4) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_5) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_6) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TReg_reg_7) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_0) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_1) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_2) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_3) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_4) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_5) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_6) + ) + (portRef CLR + (instanceRef Uart_TxUnit_TBuff_reg_7) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_0) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_1) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_2) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_3) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_4) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_5) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_6) + ) + (portRef CLR + (instanceRef Uart_RxUnit_RReg_reg_7) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_0) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_1) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_2) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_3) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_4) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_5) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_6) + ) + (portRef CLR + (instanceRef Uart_RxUnit_DataO_reg_7) + ) + (portRef CLR + (instanceRef Uart_RxUnit_SampleCnt_reg_1) + ) + (portRef CLR + (instanceRef Uart_RxUnit_SampleCnt_reg_0) + ) + (portRef CLR + (instanceRef Uart_TxUnit_SyncLoad_R_reg) + ) + (portRef G + (instanceRef C668) + ) + ) + ) + (net WB_CLK_I + (joined + (portRef WB_CLK_I) + (portRef I + (instanceRef C596) + ) + (portRef IPAD + (instanceRef C597) + ) + ) + ) + (net WB_RST_I + (joined + (portRef WB_RST_I) + (portRef I + (instanceRef C467) + ) + ) + ) + (net + (rename WB_ADR_I_1 "WB_ADR_I<1>") + (joined + (portRef WB_ADR_I_1) + (portRef I + (instanceRef C468) + ) + ) + ) + (net + (rename WB_ADR_I_0 "WB_ADR_I<0>") + (joined + (portRef WB_ADR_I_0) + (portRef I + (instanceRef C469) + ) + ) + ) + (net + (rename WB_DAT_O_7 "WB_DAT_O<7>") + (joined + (portRef WB_DAT_O_7) + (portRef O + (instanceRef C502) + ) + ) + ) + (net + (rename WB_DAT_O_6 "WB_DAT_O<6>") + (joined + (portRef WB_DAT_O_6) + (portRef O + (instanceRef C503) + ) + ) + ) + (net + (rename WB_DAT_O_5 "WB_DAT_O<5>") + (joined + (portRef WB_DAT_O_5) + (portRef O + (instanceRef C504) + ) + ) + ) + (net + (rename WB_DAT_O_4 "WB_DAT_O<4>") + (joined + (portRef WB_DAT_O_4) + (portRef O + (instanceRef C505) + ) + ) + ) + (net + (rename WB_DAT_O_3 "WB_DAT_O<3>") + (joined + (portRef WB_DAT_O_3) + (portRef O + (instanceRef C506) + ) + ) + ) + (net + (rename WB_DAT_O_2 "WB_DAT_O<2>") + (joined + (portRef WB_DAT_O_2) + (portRef O + (instanceRef C507) + ) + ) + ) + (net + (rename WB_DAT_O_1 "WB_DAT_O<1>") + (joined + (portRef WB_DAT_O_1) + (portRef O + (instanceRef C508) + ) + ) + ) + (net + (rename WB_DAT_O_0 "WB_DAT_O<0>") + (joined + (portRef WB_DAT_O_0) + (portRef O + (instanceRef C509) + ) + ) + ) + (net WB_WE_I + (joined + (portRef WB_WE_I) + (portRef I + (instanceRef C510) + ) + ) + ) + (net WB_STB_I + (joined + (portRef WB_STB_I) + (portRef I + (instanceRef C511) + ) + ) + ) + (net WB_ACK_O + (joined + (portRef WB_ACK_O) + (portRef O + (instanceRef C512) + ) + ) + ) + (net IntTx_O + (joined + (portRef IntTx_O) + (portRef O + (instanceRef C513) + ) + ) + ) + (net IntRx_O + (joined + (portRef IntRx_O) + (portRef O + (instanceRef C514) + ) + ) + ) + (net BR_Clk_I + (joined + (portRef BR_Clk_I) + (portRef I + (instanceRef C594) + ) + (portRef IPAD + (instanceRef C595) + ) + ) + ) + (net TxD_PAD_O + (joined + (portRef TxD_PAD_O) + (portRef O + (instanceRef C516) + ) + ) + ) + (net RxD_PAD_I + (joined + (portRef RxD_PAD_I) + (portRef I + (instanceRef C517) + ) + ) + ) + (net N295 + (joined + (portRef D + (instanceRef Uart_Rxrate_O_reg) + ) + (portRef O + (instanceRef C639) + ) + (portRef O + (instanceRef C640) + ) + ) + ) + (net N296 + (joined + (portRef I + (instanceRef C513) + ) + (portRef I4 + (instanceRef C81) + ) + (portRef I2 + (instanceRef C90) + ) + (portRef O + (instanceRef C91) + ) + (portRef O + (instanceRef C92) + ) + ) + ) + (net C37 + (joined + (portRef I1 + (instanceRef C108) + ) + (portRef I0 + (instanceRef C112) + ) + (portRef I1 + (instanceRef C113) + ) + (portRef I0 + (instanceRef C117) + ) + (portRef I1 + (instanceRef C118) + ) + (portRef I0 + (instanceRef C122) + ) + (portRef I1 + (instanceRef C123) + ) + (portRef I0 + (instanceRef C127) + ) + (portRef I1 + (instanceRef C128) + ) + (portRef I0 + (instanceRef C132) + ) + (portRef I1 + (instanceRef C133) + ) + (portRef I0 + (instanceRef C137) + ) + (portRef I4 + (instanceRef C646) + ) + (portRef I3 + (instanceRef C651) + ) + (portRef I4 + (instanceRef C652) + ) + (portRef I3 + (instanceRef C658) + ) + (portRef O + (instanceRef C659) + ) + (portRef O + (instanceRef C660) + ) + ) + ) + (net syn854 + (joined + (portRef I3 + (instanceRef C138) + ) + (portRef I + (instanceRef C145) + ) + (portRef I3 + (instanceRef C149) + ) + (portRef I + (instanceRef C154) + ) + (portRef I + (instanceRef C156) + ) + (portRef I1 + (instanceRef C174) + ) + (portRef I + (instanceRef C178) + ) + (portRef I3 + (instanceRef C234) + ) + (portRef I2 + (instanceRef C240) + ) + (portRef I1 + (instanceRef C354) + ) + (portRef I + (instanceRef C357) + ) + (portRef I2 + (instanceRef C409) + ) + (portRef I1 + (instanceRef C413) + ) + (portRef O + (instanceRef C414) + ) + (portRef O + (instanceRef C415) + ) + ) + ) + (net syn883 + (joined + (portRef I2 + (instanceRef C160) + ) + (portRef I + (instanceRef C165) + ) + (portRef I1 + (instanceRef C167) + ) + (portRef I2 + (instanceRef C276) + ) + (portRef I + (instanceRef C281) + ) + (portRef I1 + (instanceRef C286) + ) + (portRef I2 + (instanceRef C333) + ) + (portRef I + (instanceRef C338) + ) + (portRef I1 + (instanceRef C343) + ) + (portRef O + (instanceRef C344) + ) + (portRef O + (instanceRef C345) + ) + ) + ) + (net syn1635 + (joined + (portRef I2 + (instanceRef C169) + ) + (portRef I1 + (instanceRef C173) + ) + (portRef O + (instanceRef C174) + ) + (portRef O + (instanceRef C175) + ) + ) + ) + (net syn1466 + (joined + (portRef I4 + (instanceRef C174) + ) + (portRef I + (instanceRef C180) + ) + (portRef O + (instanceRef C182) + ) + (portRef O + (instanceRef C183) + ) + ) + ) + (net + (rename Uart_RxUnit_C315 "Uart_RxUnit/C315") + (joined + (portRef I2 + (instanceRef C182) + ) + (portRef I + (instanceRef C189) + ) + (portRef I2 + (instanceRef C234) + ) + (portRef I + (instanceRef C238) + ) + (portRef I3 + (instanceRef C241) + ) + (portRef I2 + (instanceRef C246) + ) + (portRef O + (instanceRef C247) + ) + (portRef O + (instanceRef C248) + ) + ) + ) + (net syn878 + (joined + (portRef I4 + (instanceRef C182) + ) + (portRef I2 + (instanceRef C190) + ) + (portRef I2 + (instanceRef C354) + ) + (portRef I + (instanceRef C358) + ) + (portRef O + (instanceRef C361) + ) + (portRef O + (instanceRef C362) + ) + ) + ) + (net syn944 + (joined + (portRef I2 + (instanceRef C209) + ) + (portRef I + (instanceRef C216) + ) + (portRef I2 + (instanceRef C223) + ) + (portRef I + (instanceRef C227) + ) + (portRef I + (instanceRef C230) + ) + (portRef O + (instanceRef C234) + ) + (portRef O + (instanceRef C235) + ) + ) + ) + (net syn903 + (joined + (portRef I2 + (instanceRef C254) + ) + (portRef I + (instanceRef C259) + ) + (portRef I1 + (instanceRef C264) + ) + (portRef I2 + (instanceRef C298) + ) + (portRef I + (instanceRef C303) + ) + (portRef I1 + (instanceRef C308) + ) + (portRef O + (instanceRef C309) + ) + (portRef O + (instanceRef C310) + ) + ) + ) + (net syn1336 + (joined + (portRef I3 + (instanceRef C254) + ) + (portRef I + (instanceRef C260) + ) + (portRef I0 + (instanceRef C263) + ) + (portRef I3 + (instanceRef C265) + ) + (portRef I + (instanceRef C271) + ) + (portRef I0 + (instanceRef C274) + ) + (portRef I3 + (instanceRef C276) + ) + (portRef I + (instanceRef C282) + ) + (portRef I0 + (instanceRef C285) + ) + (portRef I3 + (instanceRef C287) + ) + (portRef I + (instanceRef C293) + ) + (portRef I0 + (instanceRef C296) + ) + (portRef I3 + (instanceRef C298) + ) + (portRef I + (instanceRef C304) + ) + (portRef I2 + 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+------------------------------------------------------------------------------- +-- Title : UART +-- Project : UART +------------------------------------------------------------------------------- +-- File : Rxunit.vhd +-- Author : Philippe CARTON +-- (philippe.carton2@libertysurf.fr) +-- Organization: +-- Created : 15/12/2001 +-- Last update : 8/1/2003 +-- Platform : Foundation 3.1i +-- Simulators : ModelSim 5.5b +-- Synthesizers: Xilinx Synthesis +-- Targets : Xilinx Spartan +-- Dependency : IEEE std_logic_1164 +------------------------------------------------------------------------------- +-- Description: RxUnit is a serial to parallel unit Receiver. +------------------------------------------------------------------------------- +-- Copyright (c) notice +-- This core adheres to the GNU public license +-- +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : +-- Version : +-- Date : +-- Modifier : name +-- Description : +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + +entity RxUnit is + port ( + Clk : in std_logic; -- system clock signal + Reset : in std_logic; -- Reset input + Enable : in std_logic; -- Enable input + ReadA : in Std_logic; -- Async Read Received Byte + RxD : in std_logic; -- RS-232 data input + RxAv : out std_logic; -- Byte available + DataO : out std_logic_vector(7 downto 0)); -- Byte received +end RxUnit; + +architecture Behaviour of RxUnit is + signal RReg : std_logic_vector(7 downto 0); -- receive register + signal RRegL : std_logic; -- Byte received +begin + -- RxAv process + RxAvProc : process(RRegL,Reset,ReadA) + begin + if ReadA = '1' or Reset = '1' then + RxAv <= '0'; -- Negate RxAv when RReg read + elsif Rising_Edge(RRegL) then + RxAv <= '1'; -- Assert RxAv when RReg written + end if; + end process; + + -- Rx Process + RxProc : process(Clk,Reset,Enable,RxD,RReg) + variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame + variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit + begin + if Reset = '1' then -- Reset + RRegL <= '0'; + BitPos := 0; + elsif Rising_Edge(Clk) then + if Enable = '1' then + case BitPos is + when 0 => -- idle + RRegL <= '0'; + if RxD = '0' then -- Start Bit + SampleCnt := 0; + BitPos := 1; + end if; + when 10 => -- Stop Bit + BitPos := 0; -- next is idle + RRegL <= '1'; -- Indicate byte received + DataO <= RReg; -- Store received byte + when others => + if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1 + RReg(BitPos-2) <= RxD; -- Deserialisation + end if; + if SampleCnt = 3 then -- Increment BitPos on 3 + BitPos := BitPos + 1; + end if; + end case; + if SampleCnt = 3 then + SampleCnt := 0; + else + sampleCnt := SampleCnt + 1; + end if; + + end if; + end if; + end process; +end Behaviour; Index: trunk/impl/Xilinx_xcs10/Xilinx/rxunit.log =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/rxunit.log (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/rxunit.log (revision 19) @@ -0,0 +1,2 @@ +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd file started. +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\rxunit.vhd file finished. Index: trunk/impl/Xilinx_xcs10/Xilinx/txunit.log =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/txunit.log (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/txunit.log (revision 19) @@ -0,0 +1,2 @@ +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd file started. +Analyze of c:\phili\miniuart\impl\xilinx~2\xilinx\txunit.vhd file finished. Index: trunk/impl/Xilinx_xcs10/Xilinx/Txunit.vhd =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/Txunit.vhd (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/Txunit.vhd (revision 19) @@ -0,0 +1,100 @@ +------------------------------------------------------------------------------- +-- Title : UART +-- Project : UART +------------------------------------------------------------------------------- +-- File : Txunit.vhd +-- Author : Philippe CARTON +-- (philippe.carton2@libertysurf.fr) +-- Organization: +-- Created : 15/12/2001 +-- Last update : 8/1/2003 +-- Platform : Foundation 3.1i +-- Simulators : ModelSim 5.5b +-- Synthesizers: Xilinx Synthesis +-- Targets : Xilinx Spartan +-- Dependency : IEEE std_logic_1164 +------------------------------------------------------------------------------- +-- Description: Txunit is a parallel to serial unit transmitter. +------------------------------------------------------------------------------- +-- Copyright (c) notice +-- This core adheres to the GNU public license +-- +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : +-- Version : +-- Date : +-- Modifier : name +-- Description : +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +entity TxUnit is + port ( + Clk : in std_logic; -- Clock signal + Reset : in std_logic; -- Reset input + Enable : in std_logic; -- Enable input + LoadA : in std_logic; -- Asynchronous Load + TxD : out std_logic; -- RS-232 data output + Busy : out std_logic; -- Tx Busy + DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit +end TxUnit; + +architecture Behaviour of TxUnit is + + component synchroniser + port ( + C1 : in std_logic; -- Asynchronous signal + C : in std_logic; -- Clock + O : out Std_logic);-- Synchronised signal + end component; + + signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer + signal TReg : std_logic_vector(7 downto 0); -- transmit register + signal TBufL : std_logic; -- Buffer loaded + signal LoadS : std_logic; -- Synchronised load signal + +begin + -- Synchronise Load on Clk + SyncLoad : Synchroniser port map (LoadA, Clk, LoadS); + Busy <= LoadS or TBufL; + + -- Tx process + TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL) + variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame + begin + if Reset = '1' then + TBufL <= '0'; + BitPos := 0; + TxD <= '1'; + elsif Rising_Edge(Clk) then + if LoadS = '1' then + TBuff <= DataI; + TBufL <= '1'; + end if; + if Enable = '1' then + case BitPos is + when 0 => -- idle or stop bit + TxD <= '1'; + if TBufL = '1' then -- start transmit. next is start bit + TReg <= TBuff; + TBufL <= '0'; + BitPos := 1; + end if; + when 1 => -- Start bit + TxD <= '0'; + BitPos := 2; + when others => + TxD <= TReg(BitPos-2); -- Serialisation of TReg + BitPos := BitPos + 1; + end case; + if BitPos = 10 then -- bit8. next is stop bit + BitPos := 0; + end if; + end if; + end if; + end process; +end Behaviour; Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx/xilinx.exp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/impl/Xilinx_xcs10/Xilinx/xilinx/xilinx.exp =================================================================== --- trunk/impl/Xilinx_xcs10/Xilinx/xilinx/xilinx.exp (nonexistent) +++ trunk/impl/Xilinx_xcs10/Xilinx/xilinx/xilinx.exp (revision 19)

trunk/impl/Xilinx_xcs10/Xilinx/xilinx/xilinx.exp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: branches/avendor/sim/Foundation sim/TESTRx.CMD =================================================================== --- branches/avendor/sim/Foundation sim/TESTRx.CMD (nonexistent) +++ branches/avendor/sim/Foundation sim/TESTRx.CMD (revision 19) @@ -0,0 +1,54 @@ +| Script file for testing the receiver +| for multi frames + +| Initial settings +delete_waveforms +restart +stepsize 50nS + +| Watched Signals and Vectors +watch WB_CLK_I | Wishbone clock +watch WB_RST_I +watch WB_WE_I +watch WB_STB_I +watch WB_ACK_O +vector ADR WB_ADR_I[1:0] +vector DI WB_DAT_I[7:0] +vector DO WB_DAT_O[7:0] +watch RxD_PAD_I | RS232 Rx Line +watch IntRx_O | Emit Buffer is empty +watch BR_Clk_I +watch EnabRx + +| Stimulators Assignment +| 1/Read SReg +| 2/Read Byte Rx +| 3/Read SReg +| 4/Read Byte Rx +clock WB_CLK_I 1 0 | BR_CLK_I=10MHz +wfm WB_RST_I @1nS=L 100nS=H 100nS=L +wfm WB_STB_I @1nS=L + + @190.001uS=H 100nS=L + + @200.001uS=H 100nS=L + + @210.001uS=H 100nS=L + + @355.501uS=H 100nS=L +wfm WB_WE_I @1nS=L + + @190.001uS=L + + @200.001uS=L + + @210.001uS=L + + @355.501uS=L +wfm ADR @1nS=L + + @190.001uS=1\H 100nS=Z + + @200.001uS=0\H 100nS=Z + + @210.001uS=1\H 100nS=Z + + @355.501uS=0\H 100nS=Z + +wfm BR_Clk_I @0nS=L (1uS=H 1uS=L)*8000 | BR_Clk_I=500kHz +| BRDIVISOR=1. Baudrate=500000/1/4=125kHz (Bit period=8uS) +| Below is a generation of 50 same frames, coding 40h. +wfm RxD_PAD_I @0nS=H + + 102.7uS=H (8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=H 8uS=L 8uS=H)*50 8uS=H + +| Perform Simulation +sim 4000uS +

branches/avendor/sim/Foundation sim/TESTRx.CMD Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property