URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 128 to Rev 127
- ↔ Reverse comparison
Rev 128 → Rev 127
/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v
4,15 → 4,18
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`include "timescale.v" |
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module minsoc_bench( |
clock, |
reset, |
eth_tx_clk, |
eth_rx_clk |
); |
module minsoc_bench(); |
|
input clock, reset, eth_tx_clk, eth_rx_clk; |
`ifdef POSITIVE_RESET |
localparam RESET_LEVEL = 1'b1; |
`elsif NEGATIVE_RESET |
localparam RESET_LEVEL = 1'b0; |
`else |
localparam RESET_LEVEL = 1'b1; |
`endif |
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reg clock, reset; |
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//Debug interface |
wire dbg_tms_i; |
wire dbg_tck_i; |
35,9 → 38,11
reg eth_col; |
reg eth_crs; |
wire eth_trst; |
reg eth_tx_clk; |
wire eth_tx_en; |
wire eth_tx_er; |
wire [3:0] eth_txd; |
reg eth_rx_clk; |
reg eth_rx_dv; |
reg eth_rx_er; |
reg [3:0] eth_rxd; |
73,6 → 78,8
reg load_file; |
|
initial begin |
reset = ~RESET_LEVEL; |
clock = 1'b0; |
design_ready = 1'b0; |
uart_echo = 1'b1; |
|
87,6 → 94,9
eth_crs = 1'b0; |
eth_fds_mdint = 1'b1; |
eth_rx_er = 1'b0; |
|
eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
eth_rxd = 4'h0; |
eth_rx_dv = 1'b0; |
|
128,6 → 138,12
$display("%d Bytes loaded from %d ...", initialize , firmware_size); |
`endif |
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// Reset controller |
repeat (2) @ (negedge clock); |
reset = RESET_LEVEL; |
repeat (16) @ (negedge clock); |
reset = ~RESET_LEVEL; |
|
`ifdef START_UP |
// Pass firmware over spi to or1k_startup |
ptr = 0; |
276,7 → 292,7
uart_echo = 1'b1; |
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if ( hello == "Hello World." ) |
$display("UART firmware test completed, behaving correctly."); |
$display("UART firmware test completed, behaving correclty."); |
else |
$display("UART firmware test completed, failed."); |
end |
299,6 → 315,13
endtask |
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// |
// Regular clocking and output |
// |
always begin |
#((`CLK_PERIOD)/2) clock <= ~clock; |
end |
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`ifdef VCD_OUTPUT |
initial begin |
$dumpfile("../results/minsoc_wave.vcd"); |
573,6 → 596,15
endtask |
//~CRC32 |
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//Generate tx and rx clocks |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; |
end |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; |
end |
//~Generate tx and rx clocks |
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`endif // !ETHERNET |
//~MAC_DATA |
|
886,5 → 918,7
end |
endtask |
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endmodule |
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/minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
1,6 → 1,5
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog) |
PROJECT_SRC=(minsoc_bench_defines.v |
minsoc_bench_clock.v |
minsoc_bench.v |
minsoc_memory_model.v |
dbg_comm_vpi.v |