URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 141 to Rev 140
- ↔ Reverse comparison
Rev 141 → Rev 140
/minsoc/trunk/utils/setup/minsoc-setup.sh
File deleted
minsoc/trunk/utils/setup/minsoc-setup.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/utils/setup/configure.sh
===================================================================
--- minsoc/trunk/utils/setup/configure.sh (revision 141)
+++ minsoc/trunk/utils/setup/configure.sh (nonexistent)
@@ -1,39 +0,0 @@
-. ${SCRIPT_DIR}/beautify.sh
-
-#Configuring MinSoC
-cecho "\nConfiguring MinSoC"
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std"
-execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure"
-execcmd "cd ${DIR_TO_INSTALL}"
-
-
-#Configuring Advanced Debug System to work with MinSoC
-cecho "\nConfiguring Advanced Debug System to work with MinSoC"
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog"
-execcmd "Turning off Advanced Debug System's JSP" "sed 's%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%' adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v"
-
-#Compiling and moving adv_jtag_bridge debug modules for simulation
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus"
-execcmd "Compiling VPI interface to connect GDB with simulation" "make"
-execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi"
-
-#Patching OpenRISC Release 1 with Advanced Debug System patch for Watchpoints
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/or1200/rtl/verilog"
-cecho "Patching OpenRISC for watchpoint support"
-#patch -p0 < ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Patches/OR1200v1/or1200v1_hwbkpt.patch
-patch -p0 < ${SCRIPT_DIR}/or1200v1_hwbkpt.patch
-
-
-#Precompiling firmwares
-cecho "\nPrecompiling delivered firmwares";
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/utils"
-execcmd "Make utils" "make"
-
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/support"
-execcmd "Make support tools" "make"
-
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/drivers"
-execcmd "Make drivers" "make"
-
-execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/uart"
-execcmd "Make UART" "make"
Index: minsoc/trunk/utils/setup/minsoc-install.sh
===================================================================
--- minsoc/trunk/utils/setup/minsoc-install.sh (revision 141)
+++ minsoc/trunk/utils/setup/minsoc-install.sh (revision 140)
@@ -1,17 +1,34 @@
#!/bin/bash
-# Author: Constantinos Xanthopoulos & Raul Fajardo
+# Author: Constantinos Xanthopoulos
# This script install MinSOC tree
# under a specific directory.
# ===== CONFIGURATIONS =====
# ==========================
-MINSOC_SVN_URL=http://opencores.org/ocsvn/minsoc/minsoc/trunk
-export SCRIPT_DIR="$( cd -P "$( dirname "$0" )" && pwd )"
-export DIR_TO_INSTALL=`pwd`
+# Where should I put the dir. minsoc?
+# ex. /home/conx/Thesis/
+DIR_TO_INSTALL=`pwd`
+
+# This variable should be set to trunk
+# or to stable.
+VERSION=""
+
+# This variable should take one of
+# the following values depending
+# to your system: linux, cygwin, freebsd
+ENV=""
+
+# !!! DO NOT EDIT BELLOW THIS LINE !!!
+# ===================================
+
+# ===== SCRIPT ======
+# ===================
+
+
# Debug ?
export DEBUG=0;
-. ${SCRIPT_DIR}/beautify.sh
+. beautify.sh
function testtool
{
@@ -85,12 +102,7 @@
if [ ! -d ${DIR_TO_INSTALL} ]
then
- cecho "Directory ${DIR_TO_INSTALL} doesn't exist."
- execcmd "Creating directory ${DIR_TO_INSTALL}" "mkdir -p ${DIR_TO_INSTALL}"
- if [ $? -ne 0 ]
- then
- errormsg "Connot create ${DIR_TO_INSTALL}";
- fi
+ errormsg "Directory doesn't exist. Please create it";
fi;
@@ -105,7 +117,7 @@
cecho "\nDownloading packages"
cd ${DIR_TO_INSTALL}
cecho "Download MinSoC"
-svn co -q ${MINSOC_SVN_URL} minsoc #user need to input password, execcmd omits command output and should be this way
+svn co -q http://opencores.org/ocsvn/minsoc/minsoc/trunk/ minsoc #user need to input password, execcmd omits command output and should be this way
execcmd "cd ${DIR_TO_INSTALL}/download"
if [ "$ENV" == "Cygwin" ]
then
@@ -181,7 +193,7 @@
execcmd "cd build"
execcmd "../configure --target=or32-elf --disable-werror --prefix=$DIR_TO_INSTALL/tools"
execcmd "Compiling GDB" "make"
-make install 1>>${SCRIPT_DIR}/progress.log 2>>${SCRIPT_DIR}/error.log #avoid Fedora failing due to missing Makeinfo
+make install 1>>${DIR_TO_INSTALL}/progress.log 2>>${DIR_TO_INSTALL}/error.log #avoid Fedora failing due to missing Makeinfo
PATH=$PATH:${DIR_TO_INSTALL}/tools/bin
@@ -232,10 +244,39 @@
execcmd "make install"
-#Configuring MinSoC, Advanced Debug System and patching OpenRISC
-bash ${SCRIPT_DIR}/configure.sh
+#Configuring MinSoC
+cecho "\nConfiguring MinSoC"
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std"
+execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure"
+execcmd "cd ${DIR_TO_INSTALL}"
+#Configuring Advanced Debug System to work with MinSoC
+cecho "\nConfiguring Advanced Debug System to work with MinSoC"
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog"
+sed "s%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%" adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v
+
+#Compiling and moving adv_jtag_bridge debug modules for simulation
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus"
+execcmd "make"
+execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi"
+
+
+#Precompiling firmwares
+cecho "\nPrecompiling delivered firmwares";
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/utils"
+execcmd "Make utils" "make"
+
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/support"
+execcmd "Make support tools" "make"
+
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/drivers"
+execcmd "Make drivers" "make"
+
+execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/uart"
+execcmd "Make UART" "make"
+
+
#Setting-up new variables
cecho "\nSystem configurations"
execcmd "Adding MinSoC tools to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/tools/bin\" >> /home/$(whoami)/.bashrc;";
/minsoc/trunk/utils/setup/beautify.sh
5,19 → 5,19
function cecho |
{ |
echo -e "\033[1m\033[33m$1\033[0m" |
echo -e "\033[1m\033[33m$1\033[0m" >> ${SCRIPT_DIR}/progress.log |
echo -e "\033[1m\033[33m$1\033[0m" >> ${DIR_TO_INSTALL}/progress.log |
} |
|
function cnecho |
{ |
echo -e -n "\033[0m\033[33m$1\033[0m" |
echo -e -n "\033[0m\033[33m$1\033[0m" >> ${SCRIPT_DIR}/progress.log |
echo -e -n "\033[0m\033[33m$1\033[0m" >> ${DIR_TO_INSTALL}/progress.log |
} |
|
function errormsg |
{ |
echo -e "\033[1m\033[31mError: $1\033[0m\n"; |
echo -e "\033[1m\033[31mError: $1\033[0m\n" >> ${SCRIPT_DIR}/error.log |
echo -e "\033[1m\033[31mError: $1\033[0m\n" >> ${DIR_TO_INSTALL}/error.log |
exit 1; |
} |
|
24,7 → 24,7
function _execcmd |
{ |
# Print Message |
echo -e "\033[35m$1...\033[0m\n" >> ${SCRIPT_DIR}/progress.log |
echo -e "\033[35m$1...\033[0m\n" >> ${DIR_TO_INSTALL}/progress.log |
if [ -n "$1" ] |
then |
echo -e -n "\033[35m$1...\033[0m" |
32,7 → 32,7
# Execute command |
if [ $DEBUG -ne 1 ]; |
then |
eval $2 1>>${SCRIPT_DIR}/progress.log 2>>${SCRIPT_DIR}/error.log; |
eval $2 1>>${DIR_TO_INSTALL}/progress.log 2>>${DIR_TO_INSTALL}/error.log; |
fi; |
# Check Execution |
if [ $? -eq 0 ] |
40,7 → 40,7
if [ -n "$1" ] |
then |
echo -e "\033[32mcomplete\033[0m"; |
echo -e "\033[32mcomplete\033[0m" >> ${SCRIPT_DIR}/progress.log |
echo -e "\033[32mcomplete\033[0m" >> ${DIR_TO_INSTALL}/progress.log |
fi |
else |
errormsg "Command: $2 Description: $1"; |
minsoc/trunk/utils/setup/required-cygwin-tools.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: minsoc/trunk/prj/scripts/altvprj.sh
===================================================================
--- minsoc/trunk/prj/scripts/altvprj.sh (revision 141)
+++ minsoc/trunk/prj/scripts/altvprj.sh (nonexistent)
@@ -1,64 +0,0 @@
-#!/bin/bash
-
-#system workings
-MINSOC_DIR=`pwd`/..
-
-PROJECT=$1
-OUTPUT=$2
-
-ENV=`uname -o`
-
-function adaptpath
-{
- if [ "$ENV" == "Cygwin" ]
- then
- local cygpath=`cygpath -w $1`
- local result=`echo $cygpath | sed 's/\\\\/\\//g'`
- echo "$result"
- else
- echo "$1"
- fi
-}
-
-if [ ! -f $PROJECT ]
-then
- echo "Unexistent project file."
- exit 1
-fi
-
-if [ -z "$OUTPUT" ]
-then
- echo "Second argument should be the destintion file for the file and directory inclusions."
- exit 1
-fi
-echo -n "" > $OUTPUT
-
-source $PROJECT
-
-for dir in "${PROJECT_DIR[@]}"
-do
- adapted_dir=`adaptpath $MINSOC_DIR/$dir`
- echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT
-done
-
-for file in "${PROJECT_SRC[@]}"
-do
- FOUND=0
-
- for dir in "${PROJECT_DIR[@]}"
- do
- if [ -f $MINSOC_DIR/$dir/$file ]
- then
- adapted_file=`adaptpath $MINSOC_DIR/$dir/$file`
- echo "set_global_assignment -name VERILOG_FILE $adapted_file" >> $OUTPUT
- FOUND=1
- break
- fi
- done
-
- if [ $FOUND != 1 ]
- then
- echo "FILE NOT FOUND: $file"
- exit 1
- fi
-done
minsoc/trunk/prj/scripts/altvprj.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/prj/scripts/altvhdprj.sh
===================================================================
--- minsoc/trunk/prj/scripts/altvhdprj.sh (revision 141)
+++ minsoc/trunk/prj/scripts/altvhdprj.sh (nonexistent)
@@ -1,64 +0,0 @@
-#!/bin/bash
-
-#system workings
-MINSOC_DIR=`pwd`/..
-
-PROJECT=$1
-OUTPUT=$2
-
-ENV=`uname -o`
-
-function adaptpath
-{
- if [ "$ENV" == "Cygwin" ]
- then
- local cygpath=`cygpath -w $1`
- local result=`echo $cygpath | sed 's/\\\\/\\//g'`
- echo "$result"
- else
- echo "$1"
- fi
-}
-
-if [ ! -f $PROJECT ]
-then
- echo "Unexistent project file."
- exit 1
-fi
-
-if [ -z "$OUTPUT" ]
-then
- echo "Second argument should be the destintion file for the file and directory inclusions."
- exit 1
-fi
-echo -n "" > $OUTPUT
-
-source $PROJECT
-
-for dir in "${PROJECT_DIR[@]}"
-do
- adapted_dir=`adaptpath $MINSOC_DIR/$dir`
- echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT
-done
-
-for file in "${PROJECT_SRC[@]}"
-do
- FOUND=0
-
- for dir in "${PROJECT_DIR[@]}"
- do
- if [ -f $MINSOC_DIR/$dir/$file ]
- then
- adapted_file=`adaptpath $MINSOC_DIR/$dir/$file`
- echo "set_global_assignment -name VHDL_FILE $adapted_file" >> $OUTPUT
- FOUND=1
- break
- fi
- done
-
- if [ $FOUND != 1 ]
- then
- echo "FILE NOT FOUND: $file"
- exit 1
- fi
-done
minsoc/trunk/prj/scripts/altvhdprj.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/prj/scripts/simvhdl.sh
===================================================================
--- minsoc/trunk/prj/scripts/simvhdl.sh (revision 141)
+++ minsoc/trunk/prj/scripts/simvhdl.sh (revision 140)
@@ -52,7 +52,7 @@
if [ $FOUND != 1 ]
then
- echo "FILE NOT FOUND: $file"
+ echo "FILE NOT FOUND"
exit 1
fi
done
/minsoc/trunk/prj/scripts/xilinxprj.sh
54,7 → 54,7
|
if [ $FOUND != 1 ] |
then |
echo "FILE NOT FOUND: $file" |
echo "FILE NOT FOUND" |
exit 1 |
fi |
done |
/minsoc/trunk/prj/scripts/simverilog.sh
58,7 → 58,7
|
if [ $FOUND != 1 ] |
then |
echo "FILE NOT FOUND: $file" |
echo "FILE NOT FOUND" |
exit 1 |
fi |
done |
/minsoc/trunk/prj/scripts/altprj.sh
0,0 → 1,70
#!/bin/bash |
|
#system workings |
MINSOC_DIR=`pwd`/.. |
|
PROJECT=$1 |
OUTPUT=$2 |
|
ENV=`uname -o` |
|
function adaptpath |
{ |
if [ "$ENV" == "Cygwin" ] |
then |
local cygpath=`cygpath -w $1` |
local result=`echo $cygpath | sed 's/\\\\/\\//g'` |
echo "$result" |
else |
echo "$1" |
fi |
} |
|
if [ ! -f $PROJECT ] |
then |
echo "Unexistent project file." |
exit 1 |
fi |
|
if [ -z "$OUTPUT" ] |
then |
echo "Second argument should be the destintion file for the file and directory inclusions." |
exit 1 |
fi |
echo -n "" > $OUTPUT |
|
source $PROJECT |
|
for dir in "${PROJECT_DIR[@]}" |
do |
adapted_dir=`adaptpath $MINSOC_DIR/$dir` |
echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT |
done |
|
for file in "${PROJECT_SRC[@]}" |
do |
FOUND=0 |
|
for dir in "${PROJECT_DIR[@]}" |
do |
if [ -f $MINSOC_DIR/$dir/$file ] |
then |
adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` |
is_vhdl=`ls $MINSOC_DIR/$dir/$file | grep vhd` |
if [ -z $is_vhdl ] |
then |
echo "set_global_assignment -name VERILOG_FILE $adapted_file" >> $OUTPUT |
else |
echo "set_global_assignment -name VHDL_FILE $adapted_file" >> $OUTPUT |
fi |
FOUND=1 |
break |
fi |
done |
|
if [ $FOUND != 1 ] |
then |
echo "FILE NOT FOUND" |
exit 1 |
fi |
done |
minsoc/trunk/prj/scripts/altprj.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: minsoc/trunk/prj/Makefile
===================================================================
--- minsoc/trunk/prj/Makefile (revision 141)
+++ minsoc/trunk/prj/Makefile (revision 140)
@@ -11,19 +11,15 @@
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
-
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
+ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
-ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS))))
-ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS))))
+all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
-all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES)
-
clean:
- rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.vprj $(ALTERA_DIR)/*.vhdprj
+ rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
-
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
@@ -36,14 +32,9 @@
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
+$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
+ bash $(SCRIPTS_DIR)/altprj.sh $^ $@
-$(ALTERA_DIR)/%.vprj: $(SRC_DIR)/%.prj
- bash $(SCRIPTS_DIR)/altvprj.sh $^ $@
-
-$(ALTERA_DIR)/%.vhdprj: $(SRC_DIR)/%.prj
- bash $(SCRIPTS_DIR)/altvhdprj.sh $^ $@
-
-
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
/minsoc/trunk/prj/src/ethmac.prj
23,5 → 23,4
eth_fifo.v |
eth_receivecontrol.v |
eth_transmitcontrol.v |
eth_txcounters.v |
xilinx_dist_ram_16x32.v) |
eth_txcounters.v) |
/minsoc/trunk/syn/xilinx/setup.bat
9,5 → 9,4
) ELSE ( |
echo %xilinx_settings% could not be found. |
set /p exit=Press ENTER to close this window... |
) |
|
) |
minsoc/trunk/syn/xilinx/setup.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/backend/spartan3a_dsp_kit/configure
===================================================================
--- minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 141)
+++ minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 140)
@@ -34,7 +34,7 @@
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
- exit 1
+ exit 1
fi
echo ""
@@ -47,33 +47,15 @@
echo ""
echo ""
-echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
-echo "__________________________________________________________________________"
-echo ""
-for file in "${BOARD_FILES[@]}"
-do
- if [ $file != NONE ]
- then
- echo "Copying $file, to backend directory..."
- cp $BOARD_DIR/$file $BACKEND_DIR
- fi
-done
-echo ""
-echo ""
-
echo "Generating project files for simulation and synthesis..."
-echo "__________________________________________________________________________"
-echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
+echo "__________________________________________________________________________"
echo ""
-echo ""
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
- echo ""
- echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
@@ -97,8 +79,21 @@
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
- echo ""
- echo ""
fi
+echo ""
+echo ""
-echo "Configuration done."
+
+echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
+echo "__________________________________________________________________________"
+echo ""
+for file in "${BOARD_FILES[@]}"
+do
+ if [ $file != NONE ]
+ then
+ echo "Copying $file, to backend directory..."
+ cp $BOARD_DIR/$file $BACKEND_DIR
+ fi
+done
+echo ""
+echo ""
/minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|
`define FREQ_NUM_FOR_NS 100000000 |
`define FREQ_NUM_FOR_NS 1000000000 |
|
`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,6 → 24,3
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
|
`define TEST_UART |
//`define TEST_ETHERNET |
/minsoc/trunk/backend/std/configure
47,33 → 47,15
echo "" |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
|
echo "Generating project files for simulation and synthesis..." |
echo "__________________________________________________________________________" |
echo "" |
make -C $MINSOC_DIR/prj |
echo "Generation complete." |
echo "__________________________________________________________________________" |
echo "" |
echo "" |
|
if [ $CONSTRAINT_FILE == 'NONE' ] |
then |
echo "Skipping synthesis preparation. Standard implementation can only be simulated." |
echo "" |
echo "" |
else |
echo "Device part for files under $SYNSRC_DIR will be patched and stored " |
echo "temporarily." |
97,8 → 79,21
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE |
rm TMPFILE |
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat |
echo "" |
echo "" |
fi |
echo "" |
echo "" |
|
echo "Configuration done." |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
/minsoc/trunk/backend/std/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|
`define FREQ_NUM_FOR_NS 100000000 |
`define FREQ_NUM_FOR_NS 1000000000 |
|
`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,6 → 24,3
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
|
`define TEST_UART |
//`define TEST_ETHERNET |
/minsoc/trunk/backend/altera_3c25_board/configure
17,7 → 17,7
|
PROJECT_FILE=minsoc_top.qsf |
|
SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj) |
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj altera_virtual_jtag.prj) |
MAKEFILE=Makefile |
|
FIND_PART='DEVICE_PART' |
52,31 → 52,15
echo "" |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
|
echo "Generating project files for simulation and synthesis..." |
echo "__________________________________________________________________________" |
echo "" |
make -C $MINSOC_DIR/prj |
echo "Generation complete." |
echo "__________________________________________________________________________" |
echo "" |
echo "" |
|
if [ $CONSTRAINT_FILE == 'NONE' ] |
then |
echo "Skipping synthesis preparation. Standard implementation can only be simulated." |
echo "" |
echo "" |
else |
echo "Device part and family for files under $SYNSRC_DIR will patched and stored " |
echo "temporarily." |
104,9 → 88,21
echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..." |
cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE |
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat |
echo "For synthesis help go to $SYN_DIR and type \"make\"." |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "Configuration done." |
echo "For synthesis help go to $SYN_DIR and type \"make\"." |
fi |
|
echo "Configuration done." |
/minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|
`define FREQ_NUM_FOR_NS 100000000 |
`define FREQ_NUM_FOR_NS 1000000000 |
|
`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,6 → 24,3
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
|
`define TEST_UART |
//`define TEST_ETHERNET |
/minsoc/trunk/backend/spartan3e_starter_kit/configure
42,7 → 42,8
#NON STANDARD SCRIPT PART |
echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." |
echo "__________________________________________________________________________" |
echo "${BOARD} requires another configuration for or1200." |
echo "Spartan3E Starter Kit requires another configuration for or1200_r3." |
echo "or1200_r1 should work fine, roll back this for minsoc release-1.0." |
|
echo "" |
echo "Copying or1200_defines.v, to or1200 implementation directory..." |
64,33 → 65,15
echo "" |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
|
echo "Generating project files for simulation and synthesis..." |
echo "__________________________________________________________________________" |
echo "" |
make -C $MINSOC_DIR/prj |
echo "Generation complete." |
echo "__________________________________________________________________________" |
echo "" |
echo "" |
|
if [ $CONSTRAINT_FILE == 'NONE' ] |
then |
echo "Skipping synthesis preparation. Standard implementation can only be simulated." |
echo "" |
echo "" |
else |
echo "Device part for files under $SYNSRC_DIR will be patched and stored " |
echo "temporarily." |
114,8 → 97,21
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE |
rm TMPFILE |
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat |
echo "" |
echo "" |
fi |
echo "" |
echo "" |
|
echo "Configuration done." |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
/minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|
`define FREQ_NUM_FOR_NS 100000000 |
`define FREQ_NUM_FOR_NS 1000000000 |
|
`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,6 → 24,3
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
|
`define TEST_UART |
//`define TEST_ETHERNET |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
42,7 → 42,9
#NON STANDARD SCRIPT PART |
echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." |
echo "__________________________________________________________________________" |
echo "${BOARD} requires another configuration for or1200." |
echo "Ethernet on Spartan3E Starter Kit requires another configuration for or1200." |
echo "For minsoc release-1.0 or1200_r1 will be used." |
echo "This will need or1200_defines.v of or1200_r1 with same configuration." |
|
echo "" |
echo "Copying or1200_defines.v, to or1200 implementation directory..." |
64,33 → 66,15
echo "" |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
|
echo "Generating project files for simulation and synthesis..." |
echo "__________________________________________________________________________" |
echo "" |
make -C $MINSOC_DIR/prj |
echo "Generation complete." |
echo "__________________________________________________________________________" |
echo "" |
echo "" |
|
if [ $CONSTRAINT_FILE == 'NONE' ] |
then |
echo "Skipping synthesis preparation. Standard implementation can only be simulated." |
echo "" |
echo "" |
else |
echo "Device part for files under $SYNSRC_DIR will be patched and stored " |
echo "temporarily." |
114,8 → 98,21
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE |
rm TMPFILE |
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat |
echo "" |
echo "" |
fi |
echo "" |
echo "" |
|
echo "Configuration done." |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "" |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|
`define FREQ_NUM_FOR_NS 100000000 |
`define FREQ_NUM_FOR_NS 1000000000 |
|
`define FREQ 10000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,6 → 24,3
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
|
`define TEST_UART |
//`define TEST_ETHERNET |
/minsoc/trunk/sim/run/run_bench
1,13 → 1,2
#!/bin/bash |
|
set -o errexit |
set -o nounset |
set -o pipefail |
set -o posix # Make command substitution subshells inherit the errexit option. |
# Otherwise, the 'command' in this example will not fail for non-zero exit codes: echo "$(command)" |
|
# A word count should always deliver the number of bytes in the hex file, |
# regardless of the number of hex bytes per line. |
FIRMWARE_SIZE_IN_BYTES="$(wc -w <"$1")" |
|
vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name="$1" +firmware_size="$FIRMWARE_SIZE_IN_BYTES" |
#!/bin/sh |
vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name=$1 |
minsoc/trunk/sim/modelsim/compile_design.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/sim/modelsim/run_sim.bat
===================================================================
--- minsoc/trunk/sim/modelsim/run_sim.bat (revision 141)
+++ minsoc/trunk/sim/modelsim/run_sim.bat (revision 140)
@@ -1,13 +1,8 @@
@echo off
-set /p target_firmware=Input the target firmware hex file along with its path. Ex: "..\..\sw\uart\uart.hex":
-
-for /f "tokens=*" %%i in ('find /c /v "NOTTHISSTRING" %target_firmware%') do set line_output=%%i
-for /f "tokens=1,2 delims=:" %%a in ("%line_output%") do set firmware_size=%%b
-set firmware_size=%firmware_size: =%
-
+set /p target_firmware=Input the target firmware hex file along with its path. Ex: "..\..\sw\uart\uart-nocache.hex":
if EXIST %target_firmware% (
-vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.dll +file_name=%target_firmware% +firmware_size=%firmware_size%
+vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.dll +file_name=%target_firmware%
) else (
echo %target_firmware% could not be found.
set /p exit=Press ENTER to close this window...
-)
+)
\ No newline at end of file
minsoc/trunk/sim/modelsim/run_sim.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/sim/modelsim/prepare_modelsim.bat
===================================================================
--- minsoc/trunk/sim/modelsim/prepare_modelsim.bat (revision 141)
+++ minsoc/trunk/sim/modelsim/prepare_modelsim.bat (revision 140)
@@ -2,4 +2,4 @@
vlib minsoc
vmap minsoc ./minsoc
echo Finished...
-set /p exit=Press ENTER to close this window...
+set /p exit=Press ENTER to close this window...
\ No newline at end of file
minsoc/trunk/sim/modelsim/prepare_modelsim.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc/trunk/sim/modelsim/run_sim.sh
===================================================================
--- minsoc/trunk/sim/modelsim/run_sim.sh (revision 141)
+++ minsoc/trunk/sim/modelsim/run_sim.sh (revision 140)
@@ -1,13 +1,3 @@
#!/bin/bash
-set -o errexit
-set -o nounset
-set -o pipefail
-set -o posix # Make command substitution subshells inherit the errexit option.
- # Otherwise, the 'command' in this example will not fail for non-zero exit codes: echo "$(command)"
-
-# A word count should always deliver the number of bytes in the hex file,
-# regardless of the number of hex bytes per line.
-FIRMWARE_SIZE_IN_BYTES="$(wc -w <"$1")"
-
-vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1 +firmware_size="$FIRMWARE_SIZE_IN_BYTES"
+vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1
/minsoc/trunk/sw/utils/bin2hex.c
43,9 → 43,6
// Generates basic ASCII hex output to stdout from binary file input |
// Compile and run the program with no options for usage. |
// |
// Modified by R. Diez in 2011 so that, when using option -size_word, |
// padding zeroes are eventually appended, so that the length of |
// the resulting file matches the length written in the header. |
|
#include <stdio.h> |
#include <stdlib.h> |
67,18 → 64,16
int filename_index=1; |
int bytes_per_line=1; |
int bytes_per_line_index=2; |
unsigned int padding_size = 0; |
unsigned int image_size; |
|
if(argc < 3) { |
fprintf(stderr,"\n\tInsufficient options.\n"); |
fprintf(stderr,"\tPlease specify, in this order: a binary file to\n"); |
fprintf(stderr,"\tconvert and the number of bytes of data to output\n"); |
fprintf(stderr,"\tconvert and the number of bytes of data to putput\n"); |
fprintf(stderr,"\tper line.\n"); |
fprintf(stderr,"\tOptionally specify the option -size_word to output\n"); |
fprintf(stderr,"\tOptionally specify the option -size_word to output,\n"); |
fprintf(stderr,"\tthe size of the image in the first 4 bytes. This is\n"); |
fprintf(stderr,"\tused by some of the new OR1k bootloaders. Note that\n"); |
fprintf(stderr,"\tpadding zeroes will be appended so that the image size\n"); |
fprintf(stderr,"\tis a multiple of 4.\n\n"); |
fprintf(stderr,"\tused by some of the new OR1k bootloaders.\n\n"); |
exit(1); |
} |
|
110,8 → 105,6
|
if (write_size_word) |
{ |
unsigned int image_size; |
|
// or1200 startup method of determining size of boot image we're copying by reading out |
// the very first word in flash is used. Determine the length of this file |
fseek(fd, 0, SEEK_END); |
119,8 → 112,8
fseek(fd,0,SEEK_SET); |
|
// Now we should have the size of the file in bytes. Let's ensure it's a word multiple |
padding_size = ( 4 - (image_size % 4) ) % 4; |
image_size += padding_size; |
image_size+=3; |
image_size &= 0xfffffffc; |
|
// Sanity check on image size |
if (image_size < 8){ |
155,15 → 148,5
} |
} |
|
unsigned j; |
for ( j = 0; j < padding_size; ++j ) { |
// printf("Adding one padding byte.\n"); |
printf("%.2x", 0); |
if (++i == bytes_per_line) { |
printf("\n"); |
i = 0; |
} |
} |
|
return 0; |
} |
/minsoc/trunk/bench/verilog/minsoc_bench.v
53,14 → 53,6
// |
// TASKS registers to communicate with interfaces |
// |
reg design_ready; |
reg uart_echo; |
`ifdef UART |
reg [40*8-1:0] line; |
reg [12*8-1:0] hello; |
reg new_line; |
reg new_char; |
`endif |
`ifdef ETHERNET |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) |
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536) |
73,21 → 65,14
// Testbench mechanics |
// |
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0]; |
integer initialize, ptr; |
integer initialize, final, ptr; |
reg [8*64:0] file_name; |
integer firmware_size; // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters. |
integer firmware_size_in_header; |
reg load_file; |
|
initial begin |
reset = ~RESET_LEVEL; |
clock = 1'b0; |
eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
|
design_ready = 1'b0; |
uart_echo = 1'b1; |
|
`ifndef NO_CLOCK_DIVISION |
minsoc_top_0.clk_adjust.clk_int = 1'b0; |
minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000; |
99,6 → 84,9
eth_crs = 1'b0; |
eth_fds_mdint = 1'b1; |
eth_rx_er = 1'b0; |
|
eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
eth_rxd = 4'h0; |
eth_rx_dv = 1'b0; |
|
117,37 → 105,18
//get firmware hex file from command line input |
if ( load_file ) begin |
if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin |
$display("ERROR: Please specify the name of the firmware file to load on start-up."); |
$display("ERROR: please specify an input file to start."); |
$finish; |
end |
|
// We are passing the firmware size separately as a command-line argument in order |
// to avoid this kind of Icarus Verilog warnings: |
// WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005. |
// WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767]. |
// Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is, |
// Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone |
// it's not easy to read the firmware file header without getting such warnings. |
if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin |
$display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file."); |
$finish; |
end |
|
$readmemh(file_name, program_mem, 0, firmware_size - 1); |
|
firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] }; |
|
if ( firmware_size != firmware_size_in_header ) begin |
$display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?"); |
$finish; |
end |
|
$readmemh(file_name, program_mem); |
// First word comprehends size of program |
final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] }; |
end |
|
`ifdef INITIALIZE_MEMORY_MODEL |
// Initialize memory with firmware |
initialize = 0; |
while ( initialize < firmware_size ) begin |
while ( initialize < final ) begin |
minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize]; |
minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1]; |
minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2]; |
156,7 → 125,7
end |
$display("Memory model initialized with firmware:"); |
$display("%s", file_name); |
$display("%d Bytes loaded from %d ...", initialize , firmware_size); |
$display("%d Bytes loaded from %d ...", initialize , final); |
`endif |
|
// Reset controller |
174,7 → 143,7
send_spi(program_mem[ptr]); |
send_spi(program_mem[ptr]); |
//~read dummy |
while ( ptr < firmware_size ) begin |
while ( ptr < final ) begin |
send_spi(program_mem[ptr]); |
ptr = ptr + 1; |
end |
187,41 → 156,32
// |
// Testbench START |
// |
design_ready = 1'b1; |
$display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards."); |
|
fork |
begin |
`ifdef UART |
|
`ifdef ETHERNET |
`ifdef TEST_ETHERNET |
$display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)..."); |
$display("Ethernet firmware encloses UART firmware, testing UART firmware first..."); |
test_uart(); |
test_eth(); |
$display("Stopping simulation."); |
$finish; |
`endif |
`endif |
|
`ifdef TEST_UART |
$display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)..."); |
test_uart(); |
$display("Stopping simulation."); |
$finish; |
`endif |
|
`endif |
end |
begin |
`ifdef ETHERNET |
`ifdef TEST_ETHERNET |
`ifdef ETHERNET |
get_mac(); |
|
if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 ) |
$display("Ethernet firmware started correctly."); |
$display("eth-nocache firmware started."); |
`endif |
`endif |
end |
begin |
#2000000; |
`ifdef UART |
uart_send(8'h41); //Character A |
`endif |
`ifdef ETHERNET |
eth_tx_data[ETH_HDR+0] = 8'hBA; |
eth_tx_data[ETH_HDR+1] = 8'h87; |
eth_tx_data[ETH_HDR+2] = 8'hAA; |
eth_tx_data[ETH_HDR+3] = 8'hBB; |
eth_tx_data[ETH_HDR+4] = 8'hCC; |
eth_tx_data[ETH_HDR+5] = 8'hDD; |
|
send_mac(6); |
`endif |
end |
join |
|
end |
294,53 → 254,6
|
|
// |
// Firmware testers |
// |
`ifdef UART |
task test_uart(); |
begin |
@ (posedge new_line); |
$display("UART data received."); |
hello = line[12*8-1:0]; |
//sending character A to UART, B expected |
$display("Testing UART interrupt..."); |
uart_echo = 1'b0; |
uart_send(8'h41); //Character A |
@ (posedge new_char); |
if ( line[7:0] == "B" ) |
$display("UART interrupt working."); |
else |
$display("UART interrupt failed."); |
uart_echo = 1'b1; |
|
if ( hello == "Hello World." ) |
$display("UART firmware test completed, behaving correctly."); |
else |
$display("UART firmware test completed, failed."); |
end |
endtask |
`endif |
|
`ifdef ETHERNET |
task test_eth(); |
begin |
eth_tx_data[ETH_HDR+0] = 8'hBA; |
eth_tx_data[ETH_HDR+1] = 8'h87; |
eth_tx_data[ETH_HDR+2] = 8'hAA; |
eth_tx_data[ETH_HDR+3] = 8'hBB; |
eth_tx_data[ETH_HDR+4] = 8'hCC; |
eth_tx_data[ETH_HDR+5] = 8'hDD; |
|
$display("Sending an Ethernet package to the system and waiting for the data to be output through UART..."); |
send_mac(6); |
repeat(3+40) @ (posedge new_line); |
$display("Ethernet test completed."); |
end |
endtask |
`endif |
|
|
// |
// Regular clocking and output |
// |
always begin |
383,13 → 296,13
integer i; |
begin |
uart_srx = 1'b0; |
#UART_TX_WAIT; |
#UART_TX_WAIT; |
for ( i = 0; i < 8 ; i = i + 1 ) begin |
uart_srx = data[i]; |
#UART_TX_WAIT; |
#UART_TX_WAIT; |
end |
uart_srx = 1'b0; |
#UART_TX_WAIT; |
#UART_TX_WAIT; |
uart_srx = 1'b1; |
end |
endtask |
396,53 → 309,36
|
//UART Monitor (prints uart output on the terminal) |
// Something to trigger the task |
initial |
begin |
new_line = 1'b0; |
new_char = 1'b0; |
end |
always @(posedge clock) |
uart_decoder; |
|
always @ (posedge clock) |
if ( design_ready ) |
uart_decoder; |
|
task uart_decoder; |
integer i; |
reg [7:0] tx_byte; |
begin |
new_char = 1'b0; |
// Wait for start bit |
while (uart_stx == 1'b1) |
@(uart_stx); |
|
#(UART_TX_WAIT + (UART_TX_WAIT/2)); |
// Wait for start bit |
while (uart_stx == 1'b1) |
@(uart_stx); |
|
for ( i = 0; i < 8 ; i = i + 1 ) begin |
tx_byte[i] = uart_stx; |
#UART_TX_WAIT; |
end |
#(UART_TX_WAIT+(UART_TX_WAIT/2)); |
|
//Check for stop bit |
if (uart_stx == 1'b0) begin |
//$display("* WARNING: user stop bit not received when expected at time %d__", $time); |
// Wait for return to idle |
while (uart_stx == 1'b0) |
@(uart_stx); |
//$display("* USER UART returned to idle at time %d",$time); |
end |
// display the char |
new_char = 1'b1; |
if ( uart_echo ) |
$write("%c", tx_byte); |
if ( new_line ) |
line = ""; |
if ( tx_byte == "\n" ) |
new_line = 1'b1; |
else begin |
line = { line[39*8-1:0], tx_byte}; |
new_line = 1'b0; |
end |
end |
for ( i = 0; i < 8 ; i = i + 1 ) begin |
tx_byte[i] = uart_stx; |
#UART_TX_WAIT; |
end |
|
//Check for stop bit |
if (uart_stx == 1'b0) begin |
//$display("* WARNING: user stop bit not received when expected at time %d__", $time); |
// Wait for return to idle |
while (uart_stx == 1'b0) |
@(uart_stx); |
//$display("* USER UART returned to idle at time %d",$time); |
end |
// display the char |
$write("%c", tx_byte); |
end |
endtask |
//~UART Monitor |
`endif // !UART |
540,7 → 436,7
reg [7:0] eth_tx_data_data_out; // data for reading from RX memory |
begin |
@(posedge eth_rx_clk); |
eth_rx_dv = 1; |
#1 eth_rx_dv = 1; |
|
// set initial rx memory address |
eth_tx_data_addr_in = start_addr; |
548,8 → 444,8
// send preamble |
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1) |
begin |
eth_rxd = preamble_data[3:0]; |
preamble_data = preamble_data >> 4; |
#1 eth_rxd = preamble_data[3:0]; |
#1 preamble_data = preamble_data >> 4; |
@(posedge eth_rx_clk); |
end |
|
556,8 → 452,8
// send SFD |
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1) |
begin |
eth_rxd = sfd_data[3:0]; |
sfd_data = sfd_data >> 4; |
#1 eth_rxd = sfd_data[3:0]; |
#1 sfd_data = sfd_data >> 4; |
@(posedge eth_rx_clk); |
end |
|
564,12 → 460,15
// send packet's addresses, type/length, data and FCS |
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1) |
begin |
#1; |
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]]; |
eth_rxd = eth_tx_data_data_out[3:0]; |
@(posedge eth_rx_clk); |
#1; |
eth_rxd = eth_tx_data_data_out[7:4]; |
eth_tx_data_addr_in = eth_tx_data_addr_in + 1; |
@(posedge eth_rx_clk); |
#1; |
end |
if (plus_drible_nibble) |
begin |
578,7 → 477,7
@(posedge eth_rx_clk); |
end |
|
eth_rx_dv = 0; |
#1 eth_rx_dv = 0; |
@(posedge eth_rx_clk); |
|
end |
621,9 → 520,6
endtask |
//~CRC32 |
|
`endif // !ETHERNET |
//~MAC_DATA |
|
//Generate tx and rx clocks |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; |
633,8 → 529,11
end |
//~Generate tx and rx clocks |
|
`endif // !ETHERNET |
//~MAC_DATA |
|
|
|
// |
// TASK to initialize instantiated FPGA dual and two port memory to 0 |
// |
943,5 → 842,7
end |
endtask |
|
|
|
endmodule |
|
minsoc/trunk/bench/verilog/minsoc_bench.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: minsoc/trunk
===================================================================
--- minsoc/trunk (revision 141)
+++ minsoc/trunk (revision 140)
minsoc/trunk
Property changes :
Deleted: svn:mergeinfo
## -0,1 +0,0 ##
Reverse-merged /minsoc/branches/rc-1.0:r109-140