OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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Rev 63 → Rev 62

/minsoc/trunk/syn/buildSupport/uart_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/eth_top.prj File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/adbg_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/eth_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/or1200_top.prj File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/or1200_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/minsoc_top.prj File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/minsoc_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst File deleted \ No newline at end of file
/minsoc/trunk/syn/buildSupport/adbg_top.prj File deleted \ No newline at end of file
minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc/trunk/syn/blackboxes/uart_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/uart_top.v (revision 63) +++ minsoc/trunk/syn/blackboxes/uart_top.v (nonexistent) @@ -1,58 +0,0 @@ - - -`include "uart_defines.v" - -module uart_top ( - wb_clk_i, - - // Wishbone signals - wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, - int_o, // interrupt request - - // UART signals - // serial input/output - stx_pad_o, srx_pad_i, - - // modem signals - rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i -`ifdef UART_HAS_BAUDRATE_OUTPUT - , baud_o -`endif - ); - -parameter uart_data_width = `UART_DATA_WIDTH; -parameter uart_addr_width = `UART_ADDR_WIDTH; - -input wb_clk_i; - -// WISHBONE interface -input wb_rst_i; -input [uart_addr_width-1:0] wb_adr_i; -input [uart_data_width-1:0] wb_dat_i; -output [uart_data_width-1:0] wb_dat_o; -input wb_we_i; -input wb_stb_i; -input wb_cyc_i; -input [3:0] wb_sel_i; -output wb_ack_o; -output int_o; - -// UART signals -input srx_pad_i; -output stx_pad_o; -output rts_pad_o; -input cts_pad_i; -output dtr_pad_o; -input dsr_pad_i; -input ri_pad_i; -input dcd_pad_i; - -// optional baudrate output -`ifdef UART_HAS_BAUDRATE_OUTPUT -output baud_o; -`endif - - -endmodule - - Index: minsoc/trunk/syn/blackboxes/adbg_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/adbg_top.v (revision 63) +++ minsoc/trunk/syn/blackboxes/adbg_top.v (nonexistent) @@ -1,180 +0,0 @@ - - -`include "adbg_defines.v" - -module adbg_top( - // JTAG signals - tck_i, - tdi_i, - tdo_o, - rst_i, - - - // TAP states - shift_dr_i, - pause_dr_i, - update_dr_i, - capture_dr_i, - - // Instructions - debug_select_i - - - `ifdef DBG_WISHBONE_SUPPORTED - // WISHBONE common signals - , - wb_clk_i, - wb_rst_i, - - // WISHBONE master interface - wb_adr_o, - wb_dat_o, - wb_dat_i, - wb_cyc_o, - wb_stb_o, - wb_sel_o, - wb_we_o, - wb_ack_i, - wb_cab_o, - wb_err_i, - wb_cti_o, - wb_bte_o - `endif - - `ifdef DBG_CPU0_SUPPORTED - // CPU signals - , - cpu0_clk_i, - cpu0_addr_o, - cpu0_data_i, - cpu0_data_o, - cpu0_bp_i, - cpu0_stall_o, - cpu0_stb_o, - cpu0_we_o, - cpu0_ack_i, - cpu0_rst_o - `endif - - `ifdef DBG_CPU1_SUPPORTED - // CPU signals - , - cpu1_clk_i, - cpu1_addr_o, - cpu1_data_i, - cpu1_data_o, - cpu1_bp_i, - cpu1_stall_o, - cpu1_stb_o, - cpu1_we_o, - cpu1_ack_i, - cpu1_rst_o - `endif - - `ifdef DBG_JSP_SUPPORTED - , - `ifndef DBG_WISHBONE_SUPPORTED - wb_clk_i, - wb_rst_i, - `endif - - // WISHBONE target interface - wb_jsp_adr_i, - wb_jsp_dat_o, - wb_jsp_dat_i, - wb_jsp_cyc_i, - wb_jsp_stb_i, - wb_jsp_sel_i, - wb_jsp_we_i, - wb_jsp_ack_o, - wb_jsp_cab_i, - wb_jsp_err_o, - wb_jsp_cti_i, - wb_jsp_bte_i, - int_o - `endif - - ); - - - // JTAG signals - input tck_i; - input tdi_i; - output tdo_o; - input rst_i; - - // TAP states - input shift_dr_i; - input pause_dr_i; - input update_dr_i; - input capture_dr_i; - - // Module select from TAP - input debug_select_i; - -`ifdef DBG_WISHBONE_SUPPORTED - input wb_clk_i; - input wb_rst_i; - output [31:0] wb_adr_o; - output [31:0] wb_dat_o; - input [31:0] wb_dat_i; - output wb_cyc_o; - output wb_stb_o; - output [3:0] wb_sel_o; - output wb_we_o; - input wb_ack_i; - output wb_cab_o; - input wb_err_i; - output [2:0] wb_cti_o; - output [1:0] wb_bte_o; -`endif - -`ifdef DBG_CPU0_SUPPORTED - // CPU signals - input cpu0_clk_i; - output [31:0] cpu0_addr_o; - input [31:0] cpu0_data_i; - output [31:0] cpu0_data_o; - input cpu0_bp_i; - output cpu0_stall_o; - output cpu0_stb_o; - output cpu0_we_o; - input cpu0_ack_i; - output cpu0_rst_o; -`endif - -`ifdef DBG_CPU1_SUPPORTED - input cpu1_clk_i; - output [31:0] cpu1_addr_o; - input [31:0] cpu1_data_i; - output [31:0] cpu1_data_o; - input cpu1_bp_i; - output cpu1_stall_o; - output cpu1_stb_o; - output cpu1_we_o; - input cpu1_ack_i; - output cpu1_rst_o; -`endif - -`ifdef DBG_JSP_SUPPORTED - `ifndef DBG_WISHBONE_SUPPORTED - input wb_clk_i; - input wb_rst_i; - `endif - input [31:0] wb_jsp_adr_i; - output [31:0] wb_jsp_dat_o; - input [31:0] wb_jsp_dat_i; - input wb_jsp_cyc_i; - input wb_jsp_stb_i; - input [3:0] wb_jsp_sel_i; - input wb_jsp_we_i; - output wb_jsp_ack_o; - input wb_jsp_cab_i; - output wb_jsp_err_o; - input [2:0] wb_jsp_cti_i; - input [1:0] wb_jsp_bte_i; - output int_o; -`endif - - -endmodule Index: minsoc/trunk/syn/blackboxes/eth_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/eth_top.v (revision 63) +++ minsoc/trunk/syn/blackboxes/eth_top.v (nonexistent) @@ -1,113 +0,0 @@ - - -`include "eth_defines.v" - -module eth_top -( - // WISHBONE common - wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, - - // WISHBONE slave - wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, - - // WISHBONE master - m_wb_adr_o, m_wb_sel_o, m_wb_we_o, - m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, - m_wb_stb_o, m_wb_ack_i, m_wb_err_i, - -`ifdef ETH_WISHBONE_B3 - m_wb_cti_o, m_wb_bte_o, -`endif - - //TX - mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, - - //RX - mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, - - // MIIM - mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, - - int_o - - // Bist -`ifdef ETH_BIST - , - // debug chain signals - mbist_si_i, // bist scan serial in - mbist_so_o, // bist scan serial out - mbist_ctrl_i // bist chain shift control -`endif - -); - - -parameter Tp = 1; - - -// WISHBONE common -input wb_clk_i; // WISHBONE clock -input wb_rst_i; // WISHBONE reset -input [31:0] wb_dat_i; // WISHBONE data input -output [31:0] wb_dat_o; // WISHBONE data output -output wb_err_o; // WISHBONE error output - -// WISHBONE slave -input [11:2] wb_adr_i; // WISHBONE address input -input [3:0] wb_sel_i; // WISHBONE byte select input -input wb_we_i; // WISHBONE write enable input -input wb_cyc_i; // WISHBONE cycle input -input wb_stb_i; // WISHBONE strobe input -output wb_ack_o; // WISHBONE acknowledge output - -// WISHBONE master -output [31:0] m_wb_adr_o; -output [3:0] m_wb_sel_o; -output m_wb_we_o; -input [31:0] m_wb_dat_i; -output [31:0] m_wb_dat_o; -output m_wb_cyc_o; -output m_wb_stb_o; -input m_wb_ack_i; -input m_wb_err_i; - -wire [29:0] m_wb_adr_tmp; - -`ifdef ETH_WISHBONE_B3 -output [2:0] m_wb_cti_o; // Cycle Type Identifier -output [1:0] m_wb_bte_o; // Burst Type Extension -`endif - -// Tx -input mtx_clk_pad_i; // Transmit clock (from PHY) -output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) -output mtxen_pad_o; // Transmit enable (to PHY) -output mtxerr_pad_o; // Transmit error (to PHY) - -// Rx -input mrx_clk_pad_i; // Receive clock (from PHY) -input [3:0] mrxd_pad_i; // Receive nibble (from PHY) -input mrxdv_pad_i; // Receive data valid (from PHY) -input mrxerr_pad_i; // Receive data error (from PHY) - -// Common Tx and Rx -input mcoll_pad_i; // Collision (from PHY) -input mcrs_pad_i; // Carrier sense (from PHY) - -// MII Management interface -input md_pad_i; // MII data input (from I/O cell) -output mdc_pad_o; // MII Management data clock (to PHY) -output md_pad_o; // MII data output (to I/O cell) -output md_padoe_o; // MII data output enable (to I/O cell) - -output int_o; // Interrupt output - -// Bist -`ifdef ETH_BIST -input mbist_si_i; // bist scan serial in -output mbist_so_o; // bist scan serial out -input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control -`endif - - -endmodule Index: minsoc/trunk/syn/blackboxes/or1200_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/or1200_top.v (revision 63) +++ minsoc/trunk/syn/blackboxes/or1200_top.v (nonexistent) @@ -1,152 +0,0 @@ - - -`include "or1200_defines.v" - -module or1200_top( - // System - clk_i, rst_i, pic_ints_i, clmode_i, - - // Instruction WISHBONE INTERFACE - iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, - iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, -`ifdef OR1200_WB_CAB - iwb_cab_o, -`endif -`ifdef OR1200_WB_B3 - iwb_cti_o, iwb_bte_o, -`endif - // Data WISHBONE INTERFACE - dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, - dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, -`ifdef OR1200_WB_CAB - dwb_cab_o, -`endif -`ifdef OR1200_WB_B3 - dwb_cti_o, dwb_bte_o, -`endif - - // External Debug Interface - dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, - dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, - -`ifdef OR1200_BIST - // RAM BIST - mbist_si_i, mbist_so_o, mbist_ctrl_i, -`endif - // Power Management - pm_cpustall_i, - pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, - pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o - -,sig_tick - -); - -parameter dw = `OR1200_OPERAND_WIDTH; -parameter aw = `OR1200_OPERAND_WIDTH; -parameter ppic_ints = `OR1200_PIC_INTS; - -// -// I/O -// - -// -// System -// -input clk_i; -input rst_i; -input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 -input [ppic_ints-1:0] pic_ints_i; - -// -// Instruction WISHBONE interface -// -input iwb_clk_i; // clock input -input iwb_rst_i; // reset input -input iwb_ack_i; // normal termination -input iwb_err_i; // termination w/ error -input iwb_rty_i; // termination w/ retry -input [dw-1:0] iwb_dat_i; // input data bus -output iwb_cyc_o; // cycle valid output -output [aw-1:0] iwb_adr_o; // address bus outputs -output iwb_stb_o; // strobe output -output iwb_we_o; // indicates write transfer -output [3:0] iwb_sel_o; // byte select outputs -output [dw-1:0] iwb_dat_o; // output data bus -`ifdef OR1200_WB_CAB -output iwb_cab_o; // indicates consecutive address burst -`endif -`ifdef OR1200_WB_B3 -output [2:0] iwb_cti_o; // cycle type identifier -output [1:0] iwb_bte_o; // burst type extension -`endif - -// -// Data WISHBONE interface -// -input dwb_clk_i; // clock input -input dwb_rst_i; // reset input -input dwb_ack_i; // normal termination -input dwb_err_i; // termination w/ error -input dwb_rty_i; // termination w/ retry -input [dw-1:0] dwb_dat_i; // input data bus -output dwb_cyc_o; // cycle valid output -output [aw-1:0] dwb_adr_o; // address bus outputs -output dwb_stb_o; // strobe output -output dwb_we_o; // indicates write transfer -output [3:0] dwb_sel_o; // byte select outputs -output [dw-1:0] dwb_dat_o; // output data bus -`ifdef OR1200_WB_CAB -output dwb_cab_o; // indicates consecutive address burst -`endif -`ifdef OR1200_WB_B3 -output [2:0] dwb_cti_o; // cycle type identifier -output [1:0] dwb_bte_o; // burst type extension -`endif - -// -// External Debug Interface -// -input dbg_stall_i; // External Stall Input -input dbg_ewt_i; // External Watchpoint Trigger Input -output [3:0] dbg_lss_o; // External Load/Store Unit Status -output [1:0] dbg_is_o; // External Insn Fetch Status -output [10:0] dbg_wp_o; // Watchpoints Outputs -output dbg_bp_o; // Breakpoint Output -input dbg_stb_i; // External Address/Data Strobe -input dbg_we_i; // External Write Enable -input [aw-1:0] dbg_adr_i; // External Address Input -input [dw-1:0] dbg_dat_i; // External Data Input -output [dw-1:0] dbg_dat_o; // External Data Output -output dbg_ack_o; // External Data Acknowledge (not WB compatible) - -`ifdef OR1200_BIST -// -// RAM BIST -// -input mbist_si_i; -input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; -output mbist_so_o; -`endif - -// -// Power Management -// -input pm_cpustall_i; -output [3:0] pm_clksd_o; -output pm_dc_gate_o; -output pm_ic_gate_o; -output pm_dmmu_gate_o; -output pm_immu_gate_o; -output pm_tt_gate_o; -output pm_cpu_gate_o; -output pm_wakeup_o; -output pm_lvolt_o; - -// -// CPU and TT -// -output sig_tick; // jb - - -endmodule Index: minsoc/trunk/syn/Makefile =================================================================== --- minsoc/trunk/syn/Makefile (revision 63) +++ minsoc/trunk/syn/Makefile (nonexistent) @@ -1,133 +0,0 @@ -ROOT = /home/rfajardo/ongoing/or1k/risc_raul -MINSOC = $(ROOT)/minsoc -MINSOC_RTL = $(MINSOC)/rtl/verilog -MINSOC_STARTUP_RTL = $(MINSOC_RTL)/minsoc_startup -UART_RTL = $(MINSOC_RTL)/uart16550/rtl/verilog -ADV_DEBUG_ROOT = $(MINSOC_RTL)/adv_debug_sys/Hardware -DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog -OR1200_RTL = $(MINSOC_RTL)/or1200/rtl/verilog -ETH_RTL = $(MINSOC_RTL)/ethmac/rtl/verilog - -help: - @echo " all: Synthesize and implement the SoC, then generate a bit stream" - @echo " soc: Synthesize the SoC" - @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" - @echo " map: Express the SoC netlist in the target hardware" - @echo " par: Place the target hardware, then route the wires" - @echo " bitgen: Generate a programming file for the target FPGA" - @echo " clean: Delete all superfluous files generated by Xilinx tools" - @echo " distclean: Delete all generated files" - @echo " or1200: Synthesize the OR1200 processor" - @echo " debug: Synthesize the debug interface" - @echo " uart: Synthesize the UART" - @echo " eth: Synthesize the ethernet controller" - @echo " startup: Synthesize the modules to automatically start-up the firmware on power on" - -all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit -soc: minsoc_top.ngc -translate: minsoc.ngd -map: minsoc.ncd -par: minsoc_par.ncd -bitgen: minsoc.bit - -distclean: - rm -rf _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} -clean: - rm -rf _xmsgs xst *.{xst,xrpt,srp,lso,log} - -minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc - mkdir xst - xst -ifn "buildSupport/minsoc_top.xst" - rm -f minsoc_top_xst.xrpt - rm -f minsoc_top.srp - rm -f minsoc_top.lso - rm -rf _xmsgs - rm -rf xst - -startup: minsoc_startup_top.ngc -minsoc_startup_top.ngc: $(MINSOC_STARTUP_RTL)/*.v buildSupport/minsoc_startup_top.xst buildSupport/minsoc_startup_top.prj - mkdir xst - xst -ifn "buildSupport/minsoc_startup_top.xst" - rm -f minsoc_startup_top_xst.xrpt - rm -f minsoc_startup_top.srp - rm -f minsoc_startup_top.lso - rm -rf _xmsgs - rm -rf xst - -uart: uart_top.ngc -uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj - mkdir xst - xst -ifn "buildSupport/uart_top.xst" - rm -f uart_top_xst.xrpt - rm -f uart_top.srp - rm -f uart_top.lso - rm -rf _xmsgs - rm -rf xst - -eth: eth_top.ngc -eth_top.ngc: $(ETH_RTL)/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj - mkdir xst - xst -ifn "buildSupport/eth_top.xst" - rm -f eth_top_xst.xrpt - rm -f eth_top.srp - rm -f eth_top.lso - rm -rf _xmsgs - rm -rf xst - -debug: adbg_top.ngc -adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj - mkdir xst - xst -ifn "buildSupport/adbg_top.xst" - rm -f adbg_top_xst.xrpt - rm -f adbg_top.srp - rm -f adbg_top.lso - rm -rf _xmsgs - rm -rf xst - -or1200: or1200_top.ngc -or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj - mkdir xst - xst -ifn "buildSupport/or1200_top.xst" - rm -f or1200_top_xst.xrpt - rm -f or1200_top.srp - rm -f or1200_top.lso - rm -rf _xmsgs - rm -rf xst - -minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc - ngdbuild -p xc3sd1800a-4-fg676 -uc $(MINSOC)/backend/spartan3a_dsp_kit.ucf -aul minsoc_top.ngc minsoc.ngd - rm -rf netlist.lst - rm -rf minsoc.bld - rm -rf minsoc*.xrpt - rm -rf xlnx_auto_0_xdb - rm -rf _xmsgs - -minsoc.ncd : minsoc.ngd - map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd - rm -rf minsoc.map - rm -rf minsoc.mrp - rm -rf minsoc.ngm - rm -rf minsoc.pcf - rm -rf minsoc.psr - rm -rf minsoc*.xml - rm -rf minsoc_top*.xrpt - rm -rf _xmsgs - -minsoc_par.ncd: minsoc.ncd - par -ol high -w -xe n minsoc.ncd minsoc_par.ncd - rm -rf minsoc_par.pad - rm -rf minsoc_par.par - rm -rf minsoc_par.ptwx - rm -rf minsoc_par.unroutes - rm -rf minsoc_par.xpi - rm -rf minsoc_par_pad* - rm -rf minsoc_top*.xrpt - rm -rf _xmsgs - -minsoc.bit: minsoc_par.ncd - bitgen -d -w minsoc_par.ncd minsoc.bit - rm -rf minsoc.bgn - rm -rf *.xwbt - rm -rf *.xml - rm -rf *.log - rm -rf _xmsgs Index: minsoc/trunk/syn/doc/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: minsoc/trunk/syn/doc/guideTop.pdf =================================================================== --- minsoc/trunk/syn/doc/guideTop.pdf (revision 63) +++ minsoc/trunk/syn/doc/guideTop.pdf (nonexistent)
minsoc/trunk/syn/doc/guideTop.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: minsoc/trunk/rtl/verilog/altera_pll.v =================================================================== --- minsoc/trunk/rtl/verilog/altera_pll.v (revision 63) +++ minsoc/trunk/rtl/verilog/altera_pll.v (revision 62) @@ -58,7 +58,6 @@ wire sub_wire2 = inclk0; wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; -`ifdef ALTERA_FPGA altpll altpll_component ( .inclk (sub_wire3), .clk (sub_wire0), @@ -152,7 +151,5 @@ altpll_component.port_extclk2 = "PORT_UNUSED", altpll_component.port_extclk3 = "PORT_UNUSED", altpll_component.width_clock = 5; -`endif - endmodule
/minsoc/trunk/rtl/verilog/minsoc_defines.v
81,8 → 81,8
//
// Reset polarity
//
//`define NEGATIVE_RESET //rstn
`define POSITIVE_RESET //rst
`define NEGATIVE_RESET //rstn
//`define POSITIVE_RESET //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
/minsoc/trunk/backend/spartan3a_dsp_kit.ucf
1,72 → 1,72
###########################
##
## Global signals
##
###########################
##
## Global signals
##
net "clk" loc = "f13"; #125MHz clock
net "reset" loc = "j17"; #SW5
###########################
 
###########################
##
## JTAG
##
net "reset" loc = "j17"; #SW5
###########################
 
###########################
##
## JTAG
##
#net "jtag_tms" loc = "aa23"; #SAM D0
#net "jtag_tdi" loc = "u20"; #SAM D2
#net "jtag_tdo" loc = "aa25"; #SAM D4
#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6
#net "jtag_gnd" loc = "y23"; #SAM D8
#net "jtag_vref" loc = "t20"; #SAM D10
###########################
 
#############################
##
## SPI Flash External Memory
##
#NET "spi_flash_mosi" LOC = "ab15";
#NET "spi_flash_miso" LOC = "af24";
#NET "spi_flash_sclk" LOC = "ae24";
#NET "spi_flash_ss(1)" LOC = "ac25";
#NET "spi_flash_ss(0)" LOC = "aa7";
###########################
 
###########################
##
## UART
##
net "uart_stx" loc = "p22";
net "uart_srx" loc = "n21";
###########################
 
###########################
##
## ETH
##
#NET "eth_txd(3)" LOC = "b1";
#NET "eth_txd(2)" LOC = "b2";
#NET "eth_txd(1)" LOC = "j9";
#NET "eth_txd(0)" LOC = "j8";
#
#NET "eth_tx_en" LOC = "d3";
#NET "eth_tx_clk" LOC = "p2";
#NET "eth_tx_er" LOC = "e4";
#
#NET "eth_rxd(3)" LOC = "d2";
#NET "eth_rxd(2)" LOC = "g5";
#NET "eth_rxd(1)" LOC = "g2";
#NET "eth_rxd(0)" LOC = "c2";
#
#NET "eth_rx_er" LOC = "j3";
#NET "eth_rx_dv" LOC = "d1";
#
#NET "eth_rx_clk" LOC = "p1";
#
#NET "eth_mdio" LOC = "f5" | PULLUP;
#NET "eth_crs" LOC = "g1";
#NET "eth_col" LOC = "y3";
#NET "eth_mdc" LOC = "f4";
#
#NET "eth_trste" LOC = "g4";
#
#NET "eth_fds_mdint" LOC = "j1";
###########################
 
#net "jtag_vref" loc = "t20"; #SAM D10
###########################
 
#############################
##
## SPI Flash External Memory
##
#NET "spi_flash_mosi" LOC = "ab15";
#NET "spi_flash_miso" LOC = "af24";
#NET "spi_flash_sclk" LOC = "ae24";
#NET "spi_flash_ss(1)" LOC = "ac25";
#NET "spi_flash_ss(0)" LOC = "aa7";
###########################
 
###########################
##
## UART
##
net "uart_stx" loc = "p22";
net "uart_srx" loc = "n21";
###########################
 
###########################
##
## ETH
##
NET "eth_txd(3)" LOC = "b1";
NET "eth_txd(2)" LOC = "b2";
NET "eth_txd(1)" LOC = "j9";
NET "eth_txd(0)" LOC = "j8";
 
NET "eth_tx_en" LOC = "d3";
NET "eth_tx_clk" LOC = "p2";
NET "eth_tx_er" LOC = "e4";
 
NET "eth_rxd(3)" LOC = "d2";
NET "eth_rxd(2)" LOC = "g5";
NET "eth_rxd(1)" LOC = "g2";
NET "eth_rxd(0)" LOC = "c2";
 
NET "eth_rx_er" LOC = "j3";
NET "eth_rx_dv" LOC = "d1";
 
NET "eth_rx_clk" LOC = "p1";
 
NET "eth_mdio" LOC = "f5" | PULLUP;
NET "eth_crs" LOC = "g1";
NET "eth_col" LOC = "y3";
NET "eth_mdc" LOC = "f4";
 
NET "eth_trste" LOC = "g4";
 
NET "eth_fds_mdint" LOC = "j1";
###########################
 

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