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Rev 85 → Rev 84

/minsoc/trunk/prj/scripts/xilinxxst.sh File deleted
minsoc/trunk/prj/scripts/xilinxxst.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc/trunk/prj/scripts/simprj.sh =================================================================== --- minsoc/trunk/prj/scripts/simprj.sh (revision 85) +++ minsoc/trunk/prj/scripts/simprj.sh (nonexistent) @@ -1,46 +0,0 @@ -#!/bin/bash - -#system workings -MINSOC_DIR=`pwd`/.. - -PROJECT=$1 -OUTPUT=$2 - -if [ ! -f $PROJECT ] -then - echo "Unexistent project file." - exit 1 -fi - -if [ -z "$OUTPUT" ] -then - echo "Second argument should be the destintion file for the file and directory inclusions." - exit 1 -fi - -source $PROJECT - -for dir in "${PROJECT_DIR[@]}" -do - echo "+incdir+$MINSOC_DIR/$dir" >> $OUTPUT -done - -for file in "${PROJECT_SRC[@]}" -do - FOUND=0 - - for dir in "${PROJECT_DIR[@]}" - do - if [ -f $MINSOC_DIR/$dir/$file ] - then - echo "$MINSOC_DIR/$dir/$file" >> $OUTPUT - FOUND=1 - fi - done - - if [ $FOUND != 1 ] - then - echo "FILE NOT FOUND" - exit 1 - fi -done
minsoc/trunk/prj/scripts/simprj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc/trunk/prj/scripts/xilinxprj.sh =================================================================== --- minsoc/trunk/prj/scripts/xilinxprj.sh (revision 85) +++ minsoc/trunk/prj/scripts/xilinxprj.sh (nonexistent) @@ -1,54 +0,0 @@ -#!/bin/bash - -#system workings -MINSOC_DIR=`pwd`/.. - -PROJECT=$1 -SRC_OUTPUT=$2 -TOP_MODULE=$3 - -if [ ! -f $PROJECT ] -then - echo "Unexistent project file." - exit 1 -fi - -if [ -z "$SRC_OUTPUT" ] -then - echo "Third argument should be the destintion file for the source inclusions." - exit 1 -fi - -source $PROJECT - -for file in "${PROJECT_SRC[@]}" -do - FOUND=0 - - for dir in "${PROJECT_DIR[@]}" - do - if [ -f $MINSOC_DIR/$dir/$file ] - then - echo -n '`include "' >> $SRC_OUTPUT - echo -n "$MINSOC_DIR/$dir/$file" >> $SRC_OUTPUT - echo '"' >> $SRC_OUTPUT - FOUND=1 - fi - done - - if [ $FOUND != 1 ] - then - echo "FILE NOT FOUND" - exit 1 - fi -done - -if [ -n "$TOP_MODULE" ] -then - for file in src/blackboxes/*.v - do - echo -n '`include "' >> $SRC_OUTPUT - echo -n "`pwd`/$file" >> $SRC_OUTPUT - echo '"' >> $SRC_OUTPUT - done -fi
minsoc/trunk/prj/scripts/xilinxprj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc/trunk/prj/src/adbg_top.prj =================================================================== --- minsoc/trunk/prj/src/adbg_top.prj (revision 85) +++ minsoc/trunk/prj/src/adbg_top.prj (nonexistent) @@ -1,11 +0,0 @@ -PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog -PROJECT_SRC=(adbg_wb_biu.v -adbg_wb_module.v -adbg_or1k_module.v -adbg_wb_defines.v -adbg_defines.v -adbg_crc32.v -adbg_or1k_biu.v -adbg_or1k_defines.v -adbg_or1k_status_reg.v -adbg_top.v) Index: minsoc/trunk/prj/src/ethmac.prj =================================================================== --- minsoc/trunk/prj/src/ethmac.prj (revision 85) +++ minsoc/trunk/prj/src/ethmac.prj (nonexistent) @@ -1,26 +0,0 @@ -PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog -PROJECT_SRC=(eth_cop.v -eth_registers.v -eth_rxethmac.v -eth_miim.v -ethmac.v -eth_rxaddrcheck.v -eth_outputcontrol.v -eth_rxstatem.v -eth_txethmac.v -eth_wishbone.v -eth_maccontrol.v -eth_txstatem.v -ethmac_defines.v -eth_spram_256x32.v -eth_shiftreg.v -eth_clockgen.v -eth_crc.v -eth_rxcounters.v -eth_macstatus.v -eth_random.v -eth_register.v -eth_fifo.v -eth_receivecontrol.v -eth_transmitcontrol.v -eth_txcounters.v) Index: minsoc/trunk/prj/src/blackboxes/uart_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/uart_top.v (revision 85) +++ minsoc/trunk/prj/src/blackboxes/uart_top.v (nonexistent) @@ -1,58 +0,0 @@ - - -`include "uart_defines.v" - -module uart_top ( - wb_clk_i, - - // Wishbone signals - wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, - int_o, // interrupt request - - // UART signals - // serial input/output - stx_pad_o, srx_pad_i, - - // modem signals - rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i -`ifdef UART_HAS_BAUDRATE_OUTPUT - , baud_o -`endif - ); - -parameter uart_data_width = `UART_DATA_WIDTH; -parameter uart_addr_width = `UART_ADDR_WIDTH; - -input wb_clk_i; - -// WISHBONE interface -input wb_rst_i; -input [uart_addr_width-1:0] wb_adr_i; -input [uart_data_width-1:0] wb_dat_i; -output [uart_data_width-1:0] wb_dat_o; -input wb_we_i; -input wb_stb_i; -input wb_cyc_i; -input [3:0] wb_sel_i; -output wb_ack_o; -output int_o; - -// UART signals -input srx_pad_i; -output stx_pad_o; -output rts_pad_o; -input cts_pad_i; -output dtr_pad_o; -input dsr_pad_i; -input ri_pad_i; -input dcd_pad_i; - -// optional baudrate output -`ifdef UART_HAS_BAUDRATE_OUTPUT -output baud_o; -`endif - - -endmodule - - Index: minsoc/trunk/prj/src/blackboxes/adbg_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/adbg_top.v (revision 85) +++ minsoc/trunk/prj/src/blackboxes/adbg_top.v (nonexistent) @@ -1,180 +0,0 @@ - - -`include "adbg_defines.v" - -module adbg_top( - // JTAG signals - tck_i, - tdi_i, - tdo_o, - rst_i, - - - // TAP states - shift_dr_i, - pause_dr_i, - update_dr_i, - capture_dr_i, - - // Instructions - debug_select_i - - - `ifdef DBG_WISHBONE_SUPPORTED - // WISHBONE common signals - , - wb_clk_i, - wb_rst_i, - - // WISHBONE master interface - wb_adr_o, - wb_dat_o, - wb_dat_i, - wb_cyc_o, - wb_stb_o, - wb_sel_o, - wb_we_o, - wb_ack_i, - wb_cab_o, - wb_err_i, - wb_cti_o, - wb_bte_o - `endif - - `ifdef DBG_CPU0_SUPPORTED - // CPU signals - , - cpu0_clk_i, - cpu0_addr_o, - cpu0_data_i, - cpu0_data_o, - cpu0_bp_i, - cpu0_stall_o, - cpu0_stb_o, - cpu0_we_o, - cpu0_ack_i, - cpu0_rst_o - `endif - - `ifdef DBG_CPU1_SUPPORTED - // CPU signals - , - cpu1_clk_i, - cpu1_addr_o, - cpu1_data_i, - cpu1_data_o, - cpu1_bp_i, - cpu1_stall_o, - cpu1_stb_o, - cpu1_we_o, - cpu1_ack_i, - cpu1_rst_o - `endif - - `ifdef DBG_JSP_SUPPORTED - , - `ifndef DBG_WISHBONE_SUPPORTED - wb_clk_i, - wb_rst_i, - `endif - - // WISHBONE target interface - wb_jsp_adr_i, - wb_jsp_dat_o, - wb_jsp_dat_i, - wb_jsp_cyc_i, - wb_jsp_stb_i, - wb_jsp_sel_i, - wb_jsp_we_i, - wb_jsp_ack_o, - wb_jsp_cab_i, - wb_jsp_err_o, - wb_jsp_cti_i, - wb_jsp_bte_i, - int_o - `endif - - ); - - - // JTAG signals - input tck_i; - input tdi_i; - output tdo_o; - input rst_i; - - // TAP states - input shift_dr_i; - input pause_dr_i; - input update_dr_i; - input capture_dr_i; - - // Module select from TAP - input debug_select_i; - -`ifdef DBG_WISHBONE_SUPPORTED - input wb_clk_i; - input wb_rst_i; - output [31:0] wb_adr_o; - output [31:0] wb_dat_o; - input [31:0] wb_dat_i; - output wb_cyc_o; - output wb_stb_o; - output [3:0] wb_sel_o; - output wb_we_o; - input wb_ack_i; - output wb_cab_o; - input wb_err_i; - output [2:0] wb_cti_o; - output [1:0] wb_bte_o; -`endif - -`ifdef DBG_CPU0_SUPPORTED - // CPU signals - input cpu0_clk_i; - output [31:0] cpu0_addr_o; - input [31:0] cpu0_data_i; - output [31:0] cpu0_data_o; - input cpu0_bp_i; - output cpu0_stall_o; - output cpu0_stb_o; - output cpu0_we_o; - input cpu0_ack_i; - output cpu0_rst_o; -`endif - -`ifdef DBG_CPU1_SUPPORTED - input cpu1_clk_i; - output [31:0] cpu1_addr_o; - input [31:0] cpu1_data_i; - output [31:0] cpu1_data_o; - input cpu1_bp_i; - output cpu1_stall_o; - output cpu1_stb_o; - output cpu1_we_o; - input cpu1_ack_i; - output cpu1_rst_o; -`endif - -`ifdef DBG_JSP_SUPPORTED - `ifndef DBG_WISHBONE_SUPPORTED - input wb_clk_i; - input wb_rst_i; - `endif - input [31:0] wb_jsp_adr_i; - output [31:0] wb_jsp_dat_o; - input [31:0] wb_jsp_dat_i; - input wb_jsp_cyc_i; - input wb_jsp_stb_i; - input [3:0] wb_jsp_sel_i; - input wb_jsp_we_i; - output wb_jsp_ack_o; - input wb_jsp_cab_i; - output wb_jsp_err_o; - input [2:0] wb_jsp_cti_i; - input [1:0] wb_jsp_bte_i; - output int_o; -`endif - - -endmodule Index: minsoc/trunk/prj/src/blackboxes/ethmac.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/ethmac.v (revision 85) +++ minsoc/trunk/prj/src/blackboxes/ethmac.v (nonexistent) @@ -1,113 +0,0 @@ - - -`include "ethmac_defines.v" - -module ethmac -( - // WISHBONE common - wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, - - // WISHBONE slave - wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, - - // WISHBONE master - m_wb_adr_o, m_wb_sel_o, m_wb_we_o, - m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, - m_wb_stb_o, m_wb_ack_i, m_wb_err_i, - -`ifdef ETH_WISHBONE_B3 - m_wb_cti_o, m_wb_bte_o, -`endif - - //TX - mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, - - //RX - mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, - - // MIIM - mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, - - int_o - - // Bist -`ifdef ETH_BIST - , - // debug chain signals - mbist_si_i, // bist scan serial in - mbist_so_o, // bist scan serial out - mbist_ctrl_i // bist chain shift control -`endif - -); - - -parameter Tp = 1; - - -// WISHBONE common -input wb_clk_i; // WISHBONE clock -input wb_rst_i; // WISHBONE reset -input [31:0] wb_dat_i; // WISHBONE data input -output [31:0] wb_dat_o; // WISHBONE data output -output wb_err_o; // WISHBONE error output - -// WISHBONE slave -input [11:2] wb_adr_i; // WISHBONE address input -input [3:0] wb_sel_i; // WISHBONE byte select input -input wb_we_i; // WISHBONE write enable input -input wb_cyc_i; // WISHBONE cycle input -input wb_stb_i; // WISHBONE strobe input -output wb_ack_o; // WISHBONE acknowledge output - -// WISHBONE master -output [31:0] m_wb_adr_o; -output [3:0] m_wb_sel_o; -output m_wb_we_o; -input [31:0] m_wb_dat_i; -output [31:0] m_wb_dat_o; -output m_wb_cyc_o; -output m_wb_stb_o; -input m_wb_ack_i; -input m_wb_err_i; - -wire [29:0] m_wb_adr_tmp; - -`ifdef ETH_WISHBONE_B3 -output [2:0] m_wb_cti_o; // Cycle Type Identifier -output [1:0] m_wb_bte_o; // Burst Type Extension -`endif - -// Tx -input mtx_clk_pad_i; // Transmit clock (from PHY) -output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) -output mtxen_pad_o; // Transmit enable (to PHY) -output mtxerr_pad_o; // Transmit error (to PHY) - -// Rx -input mrx_clk_pad_i; // Receive clock (from PHY) -input [3:0] mrxd_pad_i; // Receive nibble (from PHY) -input mrxdv_pad_i; // Receive data valid (from PHY) -input mrxerr_pad_i; // Receive data error (from PHY) - -// Common Tx and Rx -input mcoll_pad_i; // Collision (from PHY) -input mcrs_pad_i; // Carrier sense (from PHY) - -// MII Management interface -input md_pad_i; // MII data input (from I/O cell) -output mdc_pad_o; // MII Management data clock (to PHY) -output md_pad_o; // MII data output (to I/O cell) -output md_padoe_o; // MII data output enable (to I/O cell) - -output int_o; // Interrupt output - -// Bist -`ifdef ETH_BIST -input mbist_si_i; // bist scan serial in -output mbist_so_o; // bist scan serial out -input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control -`endif - - -endmodule Index: minsoc/trunk/prj/src/blackboxes/or1200_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/or1200_top.v (revision 85) +++ minsoc/trunk/prj/src/blackboxes/or1200_top.v (nonexistent) @@ -1,152 +0,0 @@ - - -`include "or1200_defines.v" - -module or1200_top( - // System - clk_i, rst_i, pic_ints_i, clmode_i, - - // Instruction WISHBONE INTERFACE - iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, - iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, -`ifdef OR1200_WB_CAB - iwb_cab_o, -`endif -`ifdef OR1200_WB_B3 - iwb_cti_o, iwb_bte_o, -`endif - // Data WISHBONE INTERFACE - dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, - dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, -`ifdef OR1200_WB_CAB - dwb_cab_o, -`endif -`ifdef OR1200_WB_B3 - dwb_cti_o, dwb_bte_o, -`endif - - // External Debug Interface - dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, - dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, - -`ifdef OR1200_BIST - // RAM BIST - mbist_si_i, mbist_so_o, mbist_ctrl_i, -`endif - // Power Management - pm_cpustall_i, - pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, - pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o - -,sig_tick - -); - -parameter dw = `OR1200_OPERAND_WIDTH; -parameter aw = `OR1200_OPERAND_WIDTH; -parameter ppic_ints = `OR1200_PIC_INTS; - -// -// I/O -// - -// -// System -// -input clk_i; -input rst_i; -input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 -input [ppic_ints-1:0] pic_ints_i; - -// -// Instruction WISHBONE interface -// -input iwb_clk_i; // clock input -input iwb_rst_i; // reset input -input iwb_ack_i; // normal termination -input iwb_err_i; // termination w/ error -input iwb_rty_i; // termination w/ retry -input [dw-1:0] iwb_dat_i; // input data bus -output iwb_cyc_o; // cycle valid output -output [aw-1:0] iwb_adr_o; // address bus outputs -output iwb_stb_o; // strobe output -output iwb_we_o; // indicates write transfer -output [3:0] iwb_sel_o; // byte select outputs -output [dw-1:0] iwb_dat_o; // output data bus -`ifdef OR1200_WB_CAB -output iwb_cab_o; // indicates consecutive address burst -`endif -`ifdef OR1200_WB_B3 -output [2:0] iwb_cti_o; // cycle type identifier -output [1:0] iwb_bte_o; // burst type extension -`endif - -// -// Data WISHBONE interface -// -input dwb_clk_i; // clock input -input dwb_rst_i; // reset input -input dwb_ack_i; // normal termination -input dwb_err_i; // termination w/ error -input dwb_rty_i; // termination w/ retry -input [dw-1:0] dwb_dat_i; // input data bus -output dwb_cyc_o; // cycle valid output -output [aw-1:0] dwb_adr_o; // address bus outputs -output dwb_stb_o; // strobe output -output dwb_we_o; // indicates write transfer -output [3:0] dwb_sel_o; // byte select outputs -output [dw-1:0] dwb_dat_o; // output data bus -`ifdef OR1200_WB_CAB -output dwb_cab_o; // indicates consecutive address burst -`endif -`ifdef OR1200_WB_B3 -output [2:0] dwb_cti_o; // cycle type identifier -output [1:0] dwb_bte_o; // burst type extension -`endif - -// -// External Debug Interface -// -input dbg_stall_i; // External Stall Input -input dbg_ewt_i; // External Watchpoint Trigger Input -output [3:0] dbg_lss_o; // External Load/Store Unit Status -output [1:0] dbg_is_o; // External Insn Fetch Status -output [10:0] dbg_wp_o; // Watchpoints Outputs -output dbg_bp_o; // Breakpoint Output -input dbg_stb_i; // External Address/Data Strobe -input dbg_we_i; // External Write Enable -input [aw-1:0] dbg_adr_i; // External Address Input -input [dw-1:0] dbg_dat_i; // External Data Input -output [dw-1:0] dbg_dat_o; // External Data Output -output dbg_ack_o; // External Data Acknowledge (not WB compatible) - -`ifdef OR1200_BIST -// -// RAM BIST -// -input mbist_si_i; -input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; -output mbist_so_o; -`endif - -// -// Power Management -// -input pm_cpustall_i; -output [3:0] pm_clksd_o; -output pm_dc_gate_o; -output pm_ic_gate_o; -output pm_dmmu_gate_o; -output pm_immu_gate_o; -output pm_tt_gate_o; -output pm_cpu_gate_o; -output pm_wakeup_o; -output pm_lvolt_o; - -// -// CPU and TT -// -output sig_tick; // jb - - -endmodule Index: minsoc/trunk/prj/src/or1200_top.prj =================================================================== --- minsoc/trunk/prj/src/or1200_top.prj (revision 85) +++ minsoc/trunk/prj/src/or1200_top.prj (nonexistent) @@ -1,64 +0,0 @@ -PROJECT_DIR=rtl/verilog/or1200/rtl/verilog -PROJECT_SRC=(or1200_spram_512x20.v -or1200_spram_64x24.v -or1200_du.v -or1200_spram_2048x32_bw.v -or1200_rf.v -or1200_alu.v -or1200_dmmu_top.v -or1200_lsu.v -or1200_spram_1024x32.v -or1200_dc_top.v -or1200_cpu.v -or1200_gmultp2_32x32.v -or1200_immu_top.v -or1200_dpram_256x32.v -or1200_tt.v -or1200_iwb_biu.v -or1200_rfram_generic.v -or1200_dc_tag.v -or1200_spram_2048x8.v -or1200_immu_tlb.v -or1200_ic_tag.v -or1200_spram_64x14.v -or1200_spram_32x24.v -or1200_dpram_32x32.v -or1200_xcv_ram32x8d.v -or1200_spram_1024x8.v -or1200_mem2reg.v -or1200_pm.v -or1200_spram_256x21.v -or1200_operandmuxes.v -or1200_pic.v -or1200_cfgr.v -or1200_if.v -or1200_qmem_top.v -or1200_genpc.v -or1200_defines.v -or1200_wbmux.v -or1200_ic_ram.v -or1200_dmmu_tlb.v -or1200_sb_fifo.v -or1200_sprs.v -or1200_tpram_32x32.v -or1200_ctrl.v -or1200_sb.v -or1200_mult_mac.v -or1200_ic_fsm.v -or1200_amultp2_32x32.v -or1200_reg2mem.v -or1200_spram_2048x32.v -or1200_except.v -or1200_top.v -or1200_ic_top.v -or1200_dc_ram.v -or1200_spram_1024x32_bw.v -or1200_freeze.v -or1200_spram_128x32.v -or1200_dc_fsm.v -or1200_wb_biu.v -or1200_spram_64x22.v -or1200_fpu.v -or1200_spram.v -or1200_spram_32_bw.v -or1200_dpram.v) Index: minsoc/trunk/prj/src/jtag_top.prj =================================================================== --- minsoc/trunk/prj/src/jtag_top.prj (revision 85) +++ minsoc/trunk/prj/src/jtag_top.prj (nonexistent) @@ -1,3 +0,0 @@ -PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog -PROJECT_SRC=(tap_top.v -tap_defines.v) Index: minsoc/trunk/prj/src/minsoc_top.prj =================================================================== --- minsoc/trunk/prj/src/minsoc_top.prj (revision 85) +++ minsoc/trunk/prj/src/minsoc_top.prj (nonexistent) @@ -1,18 +0,0 @@ -PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup) -PROJECT_SRC=(minsoc_defines.v -minsoc_bench_defines.v -minsoc_bench.v -minsoc_memory_model.v -dbg_comm_vpi.v -fpga_memory_primitives.v -timescale.v -minsoc_top.v -spi_top.v -spi_defines.v -spi_shift.v -spi_clgen.v -OR1K_startup_generic.v -minsoc_tc_top.v -minsoc_onchip_ram.v -minsoc_clock_manager.v -minsoc_onchip_ram_top.v) Index: minsoc/trunk/prj/src/uart_top.prj =================================================================== --- minsoc/trunk/prj/src/uart_top.prj (revision 85) +++ minsoc/trunk/prj/src/uart_top.prj (nonexistent) @@ -1,12 +0,0 @@ -PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog -PROJECT_SRC=(uart_top.v -uart_sync_flops.v -uart_transmitter.v -uart_debug_if.v -uart_wb.v -uart_receiver.v -uart_tfifo.v -uart_regs.v -uart_rfifo.v -uart_defines.v -raminfr.v) Index: minsoc/trunk/prj/sim/uart_top.src =================================================================== --- minsoc/trunk/prj/sim/uart_top.src (revision 85) +++ minsoc/trunk/prj/sim/uart_top.src (nonexistent) @@ -1,12 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v Index: minsoc/trunk/prj/sim/adbg_top.src =================================================================== --- minsoc/trunk/prj/sim/adbg_top.src (revision 85) +++ minsoc/trunk/prj/sim/adbg_top.src (nonexistent) @@ -1,11 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v Index: minsoc/trunk/prj/sim/ethmac.src =================================================================== --- minsoc/trunk/prj/sim/ethmac.src (revision 85) +++ minsoc/trunk/prj/sim/ethmac.src (nonexistent) @@ -1,26 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v Index: minsoc/trunk/prj/sim/or1200_top.src =================================================================== --- minsoc/trunk/prj/sim/or1200_top.src (revision 85) +++ minsoc/trunk/prj/sim/or1200_top.src (nonexistent) @@ -1,64 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v Index: minsoc/trunk/prj/sim/jtag_top.src =================================================================== --- minsoc/trunk/prj/sim/jtag_top.src (revision 85) +++ minsoc/trunk/prj/sim/jtag_top.src (nonexistent) @@ -1,3 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v Index: minsoc/trunk/prj/sim/minsoc.src =================================================================== --- minsoc/trunk/prj/sim/minsoc.src (revision 85) +++ minsoc/trunk/prj/sim/minsoc.src (nonexistent) @@ -1,139 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../backend -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup -/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v -/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v -/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v -/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v -/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v -/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v Index: minsoc/trunk/prj/sim/minsoc_top.src =================================================================== --- minsoc/trunk/prj/sim/minsoc_top.src (revision 85) +++ minsoc/trunk/prj/sim/minsoc_top.src (nonexistent) @@ -1,23 +0,0 @@ -+incdir+/home/raul/or1k/minsoc/prj/../backend -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi -+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog -+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup -/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v -/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v -/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v -/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v -/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v -/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v -/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v Index: minsoc/trunk/prj/xilinx/ethmac.prj =================================================================== --- minsoc/trunk/prj/xilinx/ethmac.prj (revision 85) +++ minsoc/trunk/prj/xilinx/ethmac.prj (nonexistent) @@ -1,25 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v" Index: minsoc/trunk/prj/xilinx/adbg_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/adbg_top.xst (revision 85) +++ minsoc/trunk/prj/xilinx/adbg_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" } --ifn /home/raul/or1k/minsoc/prj/../prj/adbg_top.prj --ifmt Verilog --ofn adbg_top --ofmt NGC --p DEVICE_PART --top adbg_top --opt_mode Speed --opt_level 1 --iobuf no Index: minsoc/trunk/prj/xilinx/ethmac.xst =================================================================== --- minsoc/trunk/prj/xilinx/ethmac.xst (revision 85) +++ minsoc/trunk/prj/xilinx/ethmac.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" } --ifn /home/raul/or1k/minsoc/prj/../prj/ethmac.prj --ifmt Verilog --ofn ethmac --ofmt NGC --p DEVICE_PART --top ethmac --opt_mode Speed --opt_level 1 --iobuf no Index: minsoc/trunk/prj/xilinx/or1200_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/or1200_top.prj (revision 85) +++ minsoc/trunk/prj/xilinx/or1200_top.prj (nonexistent) @@ -1,63 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v" Index: minsoc/trunk/prj/xilinx/jtag_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/jtag_top.prj (revision 85) +++ minsoc/trunk/prj/xilinx/jtag_top.prj (nonexistent) @@ -1,2 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v" Index: minsoc/trunk/prj/xilinx/or1200_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/or1200_top.xst (revision 85) +++ minsoc/trunk/prj/xilinx/or1200_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" } --ifn /home/raul/or1k/minsoc/prj/../prj/or1200_top.prj --ifmt Verilog --ofn or1200_top --ofmt NGC --p DEVICE_PART --top or1200_top --opt_mode Speed --opt_level 1 --iobuf no Index: minsoc/trunk/prj/xilinx/minsoc_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/minsoc_top.prj (revision 85) +++ minsoc/trunk/prj/xilinx/minsoc_top.prj (nonexistent) @@ -1,21 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v" -`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v" -`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v" -`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v" -`include "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v" -`include "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" -`include "/home/raul/or1k/minsoc/prj/src/blackboxes/adbg_top.v" -`include "/home/raul/or1k/minsoc/prj/src/blackboxes/ethmac.v" -`include "/home/raul/or1k/minsoc/prj/src/blackboxes/or1200_top.v" -`include "/home/raul/or1k/minsoc/prj/src/blackboxes/uart_top.v" Index: minsoc/trunk/prj/xilinx/jtag_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/jtag_top.xst (revision 85) +++ minsoc/trunk/prj/xilinx/jtag_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog" } --ifn /home/raul/or1k/minsoc/prj/../prj/jtag_top.prj --ifmt Verilog --ofn jtag_top --ofmt NGC --p DEVICE_PART --top jtag_top --opt_mode Speed --opt_level 1 --iobuf no Index: minsoc/trunk/prj/xilinx/uart_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/uart_top.prj (revision 85) +++ minsoc/trunk/prj/xilinx/uart_top.prj (nonexistent) @@ -1,11 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v" Index: minsoc/trunk/prj/xilinx/minsoc_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/minsoc_top.xst (revision 85) +++ minsoc/trunk/prj/xilinx/minsoc_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" } --ifn /home/raul/or1k/minsoc/prj/../prj/minsoc_top.prj --ifmt Verilog --ofn minsoc_top --ofmt NGC --p DEVICE_PART --top minsoc_top --opt_mode Speed --opt_level 1 --iobuf yes Index: minsoc/trunk/prj/xilinx/adbg_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/adbg_top.prj (revision 85) +++ minsoc/trunk/prj/xilinx/adbg_top.prj (nonexistent) @@ -1,10 +0,0 @@ -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v" -`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v" Index: minsoc/trunk/prj/xilinx/uart_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/uart_top.xst (revision 85) +++ minsoc/trunk/prj/xilinx/uart_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir ./xst -run --vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" } --ifn /home/raul/or1k/minsoc/prj/../prj/uart_top.prj --ifmt Verilog --ofn uart_top --ofmt NGC --p DEVICE_PART --top uart_top --opt_mode Speed --opt_level 1 --iobuf no Index: minsoc/trunk/prj/Makefile =================================================================== --- minsoc/trunk/prj/Makefile (revision 85) +++ minsoc/trunk/prj/Makefile (nonexistent) @@ -1,36 +0,0 @@ -PROJECTS = minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj - -SRC_DIR = src -SCRIPTS_DIR = scripts - -SIMULATION_DIR = sim -XILINX_DIR = xilinx -ALTERA_DIR = altera - -SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS)))) -XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) -XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) - -all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) - -clean: - rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst - -$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj - bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule - -$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj - bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule - -$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj - bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $* - -$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj - bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ - -$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES) - cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src - -$(SIMULATION_DIR)/%.src: $(SRC_DIR)/%.prj - bash $(SCRIPTS_DIR)/simprj.sh $^ $@ - Index: minsoc/trunk/syn/xilinx/Makefile =================================================================== --- minsoc/trunk/syn/xilinx/Makefile (revision 85) +++ minsoc/trunk/syn/xilinx/Makefile (nonexistent) @@ -1,83 +0,0 @@ -MINSOC = ../ -MINSOC_DEFINES = ${MINSOC}/backend -MINSOC_RTL = ${MINSOC}/rtl/verilog -MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup -UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog -ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware -DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog -OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog -ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog -BUILD_SUPPORT = $(MINSOC)/syn/buildSupport - -help: - @echo " all: Synthesize and implement the SoC, then generate a bit stream" - @echo "" - @echo " soc: Synthesize the SoC" - @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" - @echo " map: Express the SoC netlist in the target hardware" - @echo " par: Place the target hardware, then route the wires" - @echo " bitgen: Generate a programming file for the target FPGA" - @echo "" - @echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" - @echo " or1200: Synthesize the OR1200 processor" - @echo " debug: Synthesize the debug interface" - @echo " uart: Synthesize the UART" - @echo " eth: Synthesize the Ethernet controller" - @echo "" - @echo " clean: Delete all superfluous files generated by Xilinx tools" - @echo " distclean: Delete all generated files" - -all: minsoc.bit -soc: minsoc_top.ngc -translate: minsoc.ngd -map: minsoc.ncd -par: minsoc_par.ncd -bitgen: minsoc.bit -modules: or1200 debug uart eth -MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc - -prepare: - rm -rf xst - mkdir xst -clean: - rm -rf _xmsgs xst xlnx_auto_0_xdb - rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html -distclean: - rm -rf *.ngc *.ncd *.ngd *.bit - make clean - -minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(BUILD_SUPPORT)/minsoc_top.prj - make prepare - xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst" - -uart: uart_top.ngc -uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(BUILD_SUPPORT)/uart_top.prj - make prepare - xst -ifn "$(BUILD_SUPPORT)/uart_top.xst" - -eth: ethmac.ngc -ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(BUILD_SUPPORT)/ethmac.prj - make prepare - xst -ifn "$(BUILD_SUPPORT)/ethmac.xst" - -debug: adbg_top.ngc -adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(BUILD_SUPPORT)/adbg_top.prj - make prepare - xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst" - -or1200: or1200_top.ngc -or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(BUILD_SUPPORT)/or1200_top.prj - make prepare - xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst" - -minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) - ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd - -minsoc.ncd: minsoc.ngd - map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd - -minsoc_par.ncd: minsoc.ncd - par -ol high -w -xe n minsoc.ncd minsoc_par.ncd - -minsoc.bit: minsoc_par.ncd - bitgen -d -w minsoc_par.ncd minsoc.bit Index: minsoc/trunk/syn/blackboxes/eth_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/eth_top.v (nonexistent) +++ minsoc/trunk/syn/blackboxes/eth_top.v (revision 84) @@ -0,0 +1,113 @@ + + +`include "ethmac_defines.v" + +module ethmac +( + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, + + //RX + mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, + + // MIIM + mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, + + int_o + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +); + + +parameter Tp = 1; + + +// WISHBONE common +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [31:0] wb_dat_i; // WISHBONE data input +output [31:0] wb_dat_o; // WISHBONE data output +output wb_err_o; // WISHBONE error output + +// WISHBONE slave +input [11:2] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input +output wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +input m_wb_err_i; + +wire [29:0] m_wb_adr_tmp; + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +`endif + +// Tx +input mtx_clk_pad_i; // Transmit clock (from PHY) +output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) +output mtxen_pad_o; // Transmit enable (to PHY) +output mtxerr_pad_o; // Transmit error (to PHY) + +// Rx +input mrx_clk_pad_i; // Receive clock (from PHY) +input [3:0] mrxd_pad_i; // Receive nibble (from PHY) +input mrxdv_pad_i; // Receive data valid (from PHY) +input mrxerr_pad_i; // Receive data error (from PHY) + +// Common Tx and Rx +input mcoll_pad_i; // Collision (from PHY) +input mcrs_pad_i; // Carrier sense (from PHY) + +// MII Management interface +input md_pad_i; // MII data input (from I/O cell) +output mdc_pad_o; // MII Management data clock (to PHY) +output md_pad_o; // MII data output (to I/O cell) +output md_padoe_o; // MII data output enable (to I/O cell) + +output int_o; // Interrupt output + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + + +endmodule Index: minsoc/trunk/syn/blackboxes/uart_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/uart_top.v (nonexistent) +++ minsoc/trunk/syn/blackboxes/uart_top.v (revision 84) @@ -0,0 +1,58 @@ + + +`include "uart_defines.v" + +module uart_top ( + wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + ); + +parameter uart_data_width = `UART_DATA_WIDTH; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input wb_clk_i; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_adr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +// optional baudrate output +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + + +endmodule + + Index: minsoc/trunk/syn/blackboxes/adbg_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/adbg_top.v (nonexistent) +++ minsoc/trunk/syn/blackboxes/adbg_top.v (revision 84) @@ -0,0 +1,180 @@ + + +`include "adbg_defines.v" + +module adbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + capture_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + wb_rst_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + `ifdef DBG_JSP_SUPPORTED + , + `ifndef DBG_WISHBONE_SUPPORTED + wb_clk_i, + wb_rst_i, + `endif + + // WISHBONE target interface + wb_jsp_adr_i, + wb_jsp_dat_o, + wb_jsp_dat_i, + wb_jsp_cyc_i, + wb_jsp_stb_i, + wb_jsp_sel_i, + wb_jsp_we_i, + wb_jsp_ack_o, + wb_jsp_cab_i, + wb_jsp_err_o, + wb_jsp_cti_i, + wb_jsp_bte_i, + int_o + `endif + + ); + + + // JTAG signals + input tck_i; + input tdi_i; + output tdo_o; + input rst_i; + + // TAP states + input shift_dr_i; + input pause_dr_i; + input update_dr_i; + input capture_dr_i; + + // Module select from TAP + input debug_select_i; + +`ifdef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; +`endif + +`ifdef DBG_CPU0_SUPPORTED + // CPU signals + input cpu0_clk_i; + output [31:0] cpu0_addr_o; + input [31:0] cpu0_data_i; + output [31:0] cpu0_data_o; + input cpu0_bp_i; + output cpu0_stall_o; + output cpu0_stb_o; + output cpu0_we_o; + input cpu0_ack_i; + output cpu0_rst_o; +`endif + +`ifdef DBG_CPU1_SUPPORTED + input cpu1_clk_i; + output [31:0] cpu1_addr_o; + input [31:0] cpu1_data_i; + output [31:0] cpu1_data_o; + input cpu1_bp_i; + output cpu1_stall_o; + output cpu1_stb_o; + output cpu1_we_o; + input cpu1_ack_i; + output cpu1_rst_o; +`endif + +`ifdef DBG_JSP_SUPPORTED + `ifndef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + `endif + input [31:0] wb_jsp_adr_i; + output [31:0] wb_jsp_dat_o; + input [31:0] wb_jsp_dat_i; + input wb_jsp_cyc_i; + input wb_jsp_stb_i; + input [3:0] wb_jsp_sel_i; + input wb_jsp_we_i; + output wb_jsp_ack_o; + input wb_jsp_cab_i; + output wb_jsp_err_o; + input [2:0] wb_jsp_cti_i; + input [1:0] wb_jsp_bte_i; + output int_o; +`endif + + +endmodule Index: minsoc/trunk/syn/blackboxes/or1200_top.v =================================================================== --- minsoc/trunk/syn/blackboxes/or1200_top.v (nonexistent) +++ minsoc/trunk/syn/blackboxes/or1200_top.v (revision 84) @@ -0,0 +1,152 @@ + + +`include "or1200_defines.v" + +module or1200_top( + // System + clk_i, rst_i, pic_ints_i, clmode_i, + + // Instruction WISHBONE INTERFACE + iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, + iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, +`ifdef OR1200_WB_CAB + iwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + iwb_cti_o, iwb_bte_o, +`endif + // Data WISHBONE INTERFACE + dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, + dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, +`ifdef OR1200_WB_CAB + dwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + dwb_cti_o, dwb_bte_o, +`endif + + // External Debug Interface + dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, + dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, + +`ifdef OR1200_BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Power Management + pm_cpustall_i, + pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, + pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o + +,sig_tick + +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; +parameter ppic_ints = `OR1200_PIC_INTS; + +// +// I/O +// + +// +// System +// +input clk_i; +input rst_i; +input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 +input [ppic_ints-1:0] pic_ints_i; + +// +// Instruction WISHBONE interface +// +input iwb_clk_i; // clock input +input iwb_rst_i; // reset input +input iwb_ack_i; // normal termination +input iwb_err_i; // termination w/ error +input iwb_rty_i; // termination w/ retry +input [dw-1:0] iwb_dat_i; // input data bus +output iwb_cyc_o; // cycle valid output +output [aw-1:0] iwb_adr_o; // address bus outputs +output iwb_stb_o; // strobe output +output iwb_we_o; // indicates write transfer +output [3:0] iwb_sel_o; // byte select outputs +output [dw-1:0] iwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output iwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] iwb_cti_o; // cycle type identifier +output [1:0] iwb_bte_o; // burst type extension +`endif + +// +// Data WISHBONE interface +// +input dwb_clk_i; // clock input +input dwb_rst_i; // reset input +input dwb_ack_i; // normal termination +input dwb_err_i; // termination w/ error +input dwb_rty_i; // termination w/ retry +input [dw-1:0] dwb_dat_i; // input data bus +output dwb_cyc_o; // cycle valid output +output [aw-1:0] dwb_adr_o; // address bus outputs +output dwb_stb_o; // strobe output +output dwb_we_o; // indicates write transfer +output [3:0] dwb_sel_o; // byte select outputs +output [dw-1:0] dwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output dwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] dwb_cti_o; // cycle type identifier +output [1:0] dwb_bte_o; // burst type extension +`endif + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +input dbg_stb_i; // External Address/Data Strobe +input dbg_we_i; // External Write Enable +input [aw-1:0] dbg_adr_i; // External Address Input +input [dw-1:0] dbg_dat_i; // External Data Input +output [dw-1:0] dbg_dat_o; // External Data Output +output dbg_ack_o; // External Data Acknowledge (not WB compatible) + +`ifdef OR1200_BIST +// +// RAM BIST +// +input mbist_si_i; +input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Power Management +// +input pm_cpustall_i; +output [3:0] pm_clksd_o; +output pm_dc_gate_o; +output pm_ic_gate_o; +output pm_dmmu_gate_o; +output pm_immu_gate_o; +output pm_tt_gate_o; +output pm_cpu_gate_o; +output pm_wakeup_o; +output pm_lvolt_o; + +// +// CPU and TT +// +output sig_tick; // jb + + +endmodule Index: minsoc/trunk/syn/src/Makefile =================================================================== --- minsoc/trunk/syn/src/Makefile (nonexistent) +++ minsoc/trunk/syn/src/Makefile (revision 84) @@ -0,0 +1,82 @@ +MINSOC = ../ +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo "" + @echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" + @echo " or1200: Synthesize the OR1200 processor" + @echo " debug: Synthesize the debug interface" + @echo " uart: Synthesize the UART" + @echo " eth: Synthesize the Ethernet controller" + @echo "" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + +all: minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit +modules: or1200 debug uart eth +MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc eth_top.ngc + +prepare: + rm -rf xst + mkdir xst +clean: + rm -rf _xmsgs xst xlnx_auto_0_xdb + rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html +distclean: + rm -rf *.ngc *.ncd *.ngd *.bit + make clean + +minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v buildSupport/minsoc_top.xst buildSupport/minsoc_top.prj + make prepare + xst -ifn "buildSupport/minsoc_top.xst" + +uart: uart_top.ngc +uart_top.ngc: ${UART_RTL}/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + make prepare + xst -ifn "buildSupport/uart_top.xst" + +eth: eth_top.ngc +eth_top.ngc: ${ETH_RTL}/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj + make prepare + xst -ifn "buildSupport/eth_top.xst" + +debug: adbg_top.ngc +adbg_top.ngc: ${DEBUG_RTL}/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + make prepare + xst -ifn "buildSupport/adbg_top.xst" + +or1200: or1200_top.ngc +or1200_top.ngc: ${OR1200_RTL}/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + make prepare + xst -ifn "buildSupport/or1200_top.xst" + +minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) + ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd + +minsoc.ncd: minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + +minsoc_par.ncd: minsoc.ncd + par -ol high -w -xe n minsoc.ncd minsoc_par.ncd + +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit Index: minsoc/trunk/syn/src/eth_top.xst =================================================================== --- minsoc/trunk/syn/src/eth_top.xst (nonexistent) +++ minsoc/trunk/syn/src/eth_top.xst (revision 84) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"} +-ifn ./buildSupport/eth_top.prj +-ifmt Verilog +-ofn eth_top +-ofmt NGC +-p DEVICE_PART +-top eth_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: minsoc/trunk/syn/src/or1200_top.xst =================================================================== --- minsoc/trunk/syn/src/or1200_top.xst (nonexistent) +++ minsoc/trunk/syn/src/or1200_top.xst (revision 84) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"} +-ifn ./buildSupport/or1200_top.prj +-ifmt Verilog +-ofn or1200_top +-ofmt NGC +-p DEVICE_PART +-top or1200_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: minsoc/trunk/syn/src/minsoc_top.xst =================================================================== --- minsoc/trunk/syn/src/minsoc_top.xst (nonexistent) +++ minsoc/trunk/syn/src/minsoc_top.xst (revision 84) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../backend" "../rtl/verilog/" "../rtl/verilog/minsoc_startup" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"} +-ifn ./buildSupport/minsoc_top.prj +-ifmt Verilog +-ofn minsoc_top +-ofmt NGC +-p DEVICE_PART +-top minsoc_top +-opt_mode Speed +-opt_level 1 +-iobuf yes \ No newline at end of file Index: minsoc/trunk/syn/src/uart_top.xst =================================================================== --- minsoc/trunk/syn/src/uart_top.xst (nonexistent) +++ minsoc/trunk/syn/src/uart_top.xst (revision 84) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"} +-ifn ./buildSupport/uart_top.prj +-ifmt Verilog +-ofn uart_top +-ofmt NGC +-p DEVICE_PART +-top uart_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: minsoc/trunk/syn/src/adbg_top.xst =================================================================== --- minsoc/trunk/syn/src/adbg_top.xst (nonexistent) +++ minsoc/trunk/syn/src/adbg_top.xst (revision 84) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"} +-ifn ./buildSupport/adbg_top.prj +-ifmt Verilog +-ofn adbg_top +-ofmt NGC +-p DEVICE_PART +-top adbg_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: minsoc/trunk/syn/buildSupport/minsoc_top.prj =================================================================== --- minsoc/trunk/syn/buildSupport/minsoc_top.prj (nonexistent) +++ minsoc/trunk/syn/buildSupport/minsoc_top.prj (revision 84) @@ -0,0 +1,18 @@ +`include "../backend/minsoc_defines.v" +`include "../rtl/verilog/minsoc_xilinx_internal_jtag.v" +`include "../rtl/verilog/minsoc_clock_manager.v" +`include "../rtl/verilog/altera_pll.v" +`include "../rtl/verilog/minsoc_tc_top.v" +`include "../rtl/verilog/minsoc_onchip_ram_top.v" +`include "../rtl/verilog/minsoc_top.v" +`include "../rtl/verilog/minsoc_onchip_ram.v" +`include "../rtl/verilog/xilinx_dcm.v" +`include "../rtl/verilog/minsoc_startup/spi_shift.v" +`include "../rtl/verilog/minsoc_startup/spi_clgen.v" +`include "../rtl/verilog/minsoc_startup/spi_top.v" +`include "../rtl/verilog/minsoc_startup/spi_defines.v" +`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" +`include "./blackboxes/adbg_top.v" +`include "./blackboxes/eth_top.v" +`include "./blackboxes/uart_top.v" +`include "./blackboxes/or1200_top.v" \ No newline at end of file Index: minsoc/trunk/syn/buildSupport/or1200_top.prj =================================================================== --- minsoc/trunk/syn/buildSupport/or1200_top.prj (nonexistent) +++ minsoc/trunk/syn/buildSupport/or1200_top.prj (revision 84) @@ -0,0 +1,77 @@ +`include "../rtl/verilog/or1200/rtl/verilog/or1200_tt.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_div.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_du.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_div.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_pic.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_defines.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_rf.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_fcmp.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_except.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_sb.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_mul.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_pm.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_alu.v" +`include "../rtl/verilog/or1200/rtl/verilog/timescale.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_arith.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_mul.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_if.v" +`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_addsub.v" \ No newline at end of file Index: minsoc/trunk/syn/buildSupport/uart_top.prj =================================================================== --- minsoc/trunk/syn/buildSupport/uart_top.prj (nonexistent) +++ minsoc/trunk/syn/buildSupport/uart_top.prj (revision 84) @@ -0,0 +1,12 @@ +`include "../rtl/verilog/uart16550/rtl/verilog/uart_wb.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_regs.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_defines.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v" +`include "../rtl/verilog/uart16550/rtl/verilog/raminfr.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v" +`include "../rtl/verilog/uart16550/rtl/verilog/timescale.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v" +`include "../rtl/verilog/uart16550/rtl/verilog/uart_top.v" Index: minsoc/trunk/syn/buildSupport/adbg_top.prj =================================================================== --- minsoc/trunk/syn/buildSupport/adbg_top.prj (nonexistent) +++ minsoc/trunk/syn/buildSupport/adbg_top.prj (revision 84) @@ -0,0 +1,15 @@ +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncreg.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v" +`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncflop.v" \ No newline at end of file Index: minsoc/trunk/syn/buildSupport/eth_top.prj =================================================================== --- minsoc/trunk/syn/buildSupport/eth_top.prj (nonexistent) +++ minsoc/trunk/syn/buildSupport/eth_top.prj (revision 84) @@ -0,0 +1,27 @@ +`include "../rtl/verilog/ethmac/rtl/verilog/eth_miim.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_crc.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_register.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_random.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_top.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_registers.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_cop.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_defines.v" +`include "../rtl/verilog/ethmac/rtl/verilog/timescale.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v" +`include "../rtl/verilog/ethmac/rtl/verilog/xilinx_dist_ram_16x32.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v" +`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v" \ No newline at end of file Index: minsoc/trunk/backend/spartan3a_dsp_kit/configure =================================================================== --- minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 85) +++ minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 84) @@ -10,12 +10,10 @@ MINSOC_DIR=`pwd`/../.. BACKEND_DIR=$MINSOC_DIR/backend SYN_DIR=$MINSOC_DIR/syn -SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSRC_DIR=$SYN_DIR/src SYNSUPPORT_DIR=$SYN_DIR/buildSupport -MAKEFILE_DIR=$SYN_DIR/xilinx -SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) -MAKEFILE=Makefile +SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile) FIND_PART='DEVICE_PART' FIND_CONSTRAINT='CONSTRAINT_FILE' @@ -28,12 +26,9 @@ then echo "" echo " !!!WARNING!!!" - echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "This script cannot be run out of a board directory inside minsoc/backend," echo "because it relies on the directory structure of the minsoc system." echo "" - echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." - echo "Its name must be minsoc only." - echo "" exit 1 fi @@ -64,12 +59,8 @@ rm TMPFILE done - echo "Updating Makefile file..." - echo "Copying Makefile to synthesis directory..." - echo "" - sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE - sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE - rm TMPFILE + echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..." + mv $SYNSUPPORT_DIR/Makefile $SYN_DIR fi echo "" echo ""
/minsoc/trunk/backend/std/configure
10,10 → 10,10
MINSOC_DIR=`pwd`/../..
BACKEND_DIR=$MINSOC_DIR/backend
SYN_DIR=$MINSOC_DIR/syn
SYNSRC_DIR=$SYN_DIR/xilinx
SYNSRC_DIR=$SYN_DIR/src
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
 
SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
 
FIND_PART='DEVICE_PART'
FIND_CONSTRAINT='CONSTRAINT_FILE'
26,12 → 26,10
then
echo ""
echo " !!!WARNING!!!"
echo "This script cannot be run if not in a board directory inside minsoc/backend,"
echo "This script cannot be run out of a board directory inside minsoc/backend,"
echo "because it relies on the directory structure of the minsoc system."
echo ""
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
fi
 
echo ""
/minsoc/trunk/backend/spartan3e_starter_kit/configure
12,12 → 12,10
MINSOC_DIR=`pwd`/../..
BACKEND_DIR=$MINSOC_DIR/backend
SYN_DIR=$MINSOC_DIR/syn
SYNSRC_DIR=$MINSOC_DIR/prj/xilinx
SYNSRC_DIR=$SYN_DIR/src
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
MAKEFILE_DIR=$SYN_DIR/xilinx
 
SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst)
MAKEFILE=Makefile
SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
 
FIND_PART='DEVICE_PART'
FIND_CONSTRAINT='CONSTRAINT_FILE'
30,12 → 28,10
then
echo ""
echo " !!!WARNING!!!"
echo "This script cannot be run if not in a board directory inside minsoc/backend,"
echo "This script cannot be run out of a board directory inside minsoc/backend,"
echo "because it relies on the directory structure of the minsoc system."
echo ""
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
fi
 
#NON STANDARD SCRIPT PART
81,12 → 77,8
rm TMPFILE
done
 
echo "Updating Makefile file..."
echo "Copying Makefile to synthesis directory..."
echo ""
sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..."
mv $SYNSUPPORT_DIR/Makefile $SYN_DIR
fi
echo ""
echo ""
/minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
12,12 → 12,10
MINSOC_DIR=`pwd`/../..
BACKEND_DIR=$MINSOC_DIR/backend
SYN_DIR=$MINSOC_DIR/syn
SYNSRC_DIR=$MINSOC_DIR/prj/xilinx
SYNSRC_DIR=$SYN_DIR/src
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
MAKEFILE_DIR=$SYN_DIR/xilinx
 
SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst)
MAKEFILE=Makefile
SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
 
FIND_PART='DEVICE_PART'
FIND_CONSTRAINT='CONSTRAINT_FILE'
30,12 → 28,10
then
echo ""
echo " !!!WARNING!!!"
echo "This script cannot be run if not in a board directory inside minsoc/backend,"
echo "This script cannot be run out of a board directory inside minsoc/backend,"
echo "because it relies on the directory structure of the minsoc system."
echo ""
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
fi
 
#NON STANDARD SCRIPT PART
82,12 → 78,8
rm TMPFILE
done
 
echo "Updating Makefile file..."
echo "Copying Makefile to synthesis directory..."
echo ""
sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..."
mv $SYNSUPPORT_DIR/Makefile $SYN_DIR
fi
echo ""
echo ""
/minsoc/trunk/sim/bin/minsoc_verilog_files.txt
0,0 → 1,140
+incdir+../../backend
+incdir+../../bench/verilog
+incdir+../../bench/verilog/vpi
+incdir+../../bench/verilog/sim_lib
+incdir+../../rtl/verilog
+incdir+../../rtl/verilog/minsoc_startup
+incdir+../../rtl/verilog/or1200/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
+incdir+../../rtl/verilog/uart16550/rtl/verilog
+incdir+../../rtl/verilog/ethmac/rtl/verilog
../../backend/minsoc_defines.v
../../backend/minsoc_bench_defines.v
../../bench/verilog/minsoc_bench.v
../../bench/verilog/minsoc_memory_model.v
../../bench/verilog/vpi/dbg_comm_vpi.v
../../bench/verilog/sim_lib/fpga_memory_primitives.v
../../rtl/verilog/timescale.v
../../rtl/verilog/minsoc_top.v
../../rtl/verilog/minsoc_startup/spi_top.v
../../rtl/verilog/minsoc_startup/spi_defines.v
../../rtl/verilog/minsoc_startup/spi_shift.v
../../rtl/verilog/minsoc_startup/spi_clgen.v
../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
../../rtl/verilog/minsoc_tc_top.v
../../rtl/verilog/minsoc_onchip_ram.v
../../rtl/verilog/minsoc_clock_manager.v
../../rtl/verilog/minsoc_onchip_ram_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
../../rtl/verilog/ethmac/rtl/verilog/ethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
minsoc/trunk/sim/bin/minsoc_verilog_files.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/sim/modelsim/compile_design.bat =================================================================== --- minsoc/trunk/sim/modelsim/compile_design.bat (revision 85) +++ minsoc/trunk/sim/modelsim/compile_design.bat (revision 84) @@ -1,4 +1,4 @@ @echo off -vlog -incr -work minsoc -f ../../prj/sim/minsoc.src +vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt echo Finished... -set /p exit=Press ENTER to close this window... +set /p exit=Press ENTER to close this window... \ No newline at end of file Index: minsoc/trunk/sim/modelsim/compile_design.sh =================================================================== --- minsoc/trunk/sim/modelsim/compile_design.sh (revision 85) +++ minsoc/trunk/sim/modelsim/compile_design.sh (revision 84) @@ -1,3 +1,3 @@ #!/bin/bash -vlog -incr -work minsoc -f ../../prj/sim/minsoc.src +vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt \ No newline at end of file
/minsoc/trunk/sim/run/generate_bench
1,2 → 1,2
#!/bin/sh
iverilog -c ../../prj/sim/minsoc.src -o minsoc_bench
iverilog -c ../bin/minsoc_verilog_files.txt -o minsoc_bench

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