URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/branches/rc-1.0
- from Rev 127 to Rev 128
- ↔ Reverse comparison
Rev 127 → Rev 128
/bench/verilog/minsoc_bench_clock.v
0,0 → 1,54
`include "minsoc_bench_defines.v" |
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`include "timescale.v" |
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module minsoc_verilog_bench(); |
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`ifdef POSITIVE_RESET |
localparam RESET_LEVEL = 1'b1; |
`elsif NEGATIVE_RESET |
localparam RESET_LEVEL = 1'b0; |
`else |
localparam RESET_LEVEL = 1'b1; |
`endif |
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reg clock, reset, eth_tx_clk, eth_rx_clk; |
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minsoc_bench minsoc_bench_0( |
.clock(clock), |
.reset(reset), |
.eth_tx_clk(eth_tx_clk), |
.eth_rx_clk(eth_rx_clk) |
); |
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initial begin |
reset = ~RESET_LEVEL; |
clock = 1'b0; |
eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
// Reset controller |
repeat (2) @ (negedge clock); |
reset = RESET_LEVEL; |
repeat (16) @ (negedge clock); |
reset = ~RESET_LEVEL; |
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end |
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// |
// Regular clocking and output |
// |
always begin |
#((`CLK_PERIOD)/2) clock <= ~clock; |
end |
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//Generate tx and rx clocks |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; |
end |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; |
end |
//~Generate tx and rx clocks |
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endmodule |
/bench/verilog/minsoc_bench.v
4,18 → 4,15
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`include "timescale.v" |
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module minsoc_bench(); |
module minsoc_bench( |
clock, |
reset, |
eth_tx_clk, |
eth_rx_clk |
); |
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`ifdef POSITIVE_RESET |
localparam RESET_LEVEL = 1'b1; |
`elsif NEGATIVE_RESET |
localparam RESET_LEVEL = 1'b0; |
`else |
localparam RESET_LEVEL = 1'b1; |
`endif |
input clock, reset, eth_tx_clk, eth_rx_clk; |
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reg clock, reset; |
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//Debug interface |
wire dbg_tms_i; |
wire dbg_tck_i; |
38,11 → 35,9
reg eth_col; |
reg eth_crs; |
wire eth_trst; |
reg eth_tx_clk; |
wire eth_tx_en; |
wire eth_tx_er; |
wire [3:0] eth_txd; |
reg eth_rx_clk; |
reg eth_rx_dv; |
reg eth_rx_er; |
reg [3:0] eth_rxd; |
78,8 → 73,6
reg load_file; |
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initial begin |
reset = ~RESET_LEVEL; |
clock = 1'b0; |
design_ready = 1'b0; |
uart_echo = 1'b1; |
|
94,9 → 87,6
eth_crs = 1'b0; |
eth_fds_mdint = 1'b1; |
eth_rx_er = 1'b0; |
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eth_tx_clk = 1'b0; |
eth_rx_clk = 1'b0; |
eth_rxd = 4'h0; |
eth_rx_dv = 1'b0; |
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138,12 → 128,6
$display("%d Bytes loaded from %d ...", initialize , firmware_size); |
`endif |
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// Reset controller |
repeat (2) @ (negedge clock); |
reset = RESET_LEVEL; |
repeat (16) @ (negedge clock); |
reset = ~RESET_LEVEL; |
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`ifdef START_UP |
// Pass firmware over spi to or1k_startup |
ptr = 0; |
292,7 → 276,7
uart_echo = 1'b1; |
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if ( hello == "Hello World." ) |
$display("UART firmware test completed, behaving correclty."); |
$display("UART firmware test completed, behaving correctly."); |
else |
$display("UART firmware test completed, failed."); |
end |
315,13 → 299,6
endtask |
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// |
// Regular clocking and output |
// |
always begin |
#((`CLK_PERIOD)/2) clock <= ~clock; |
end |
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`ifdef VCD_OUTPUT |
initial begin |
$dumpfile("../results/minsoc_wave.vcd"); |
596,15 → 573,6
endtask |
//~CRC32 |
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//Generate tx and rx clocks |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; |
end |
always begin |
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; |
end |
//~Generate tx and rx clocks |
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`endif // !ETHERNET |
//~MAC_DATA |
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918,7 → 886,5
end |
endtask |
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endmodule |
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/prj/src/minsoc_bench.prj
1,5 → 1,6
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog) |
PROJECT_SRC=(minsoc_bench_defines.v |
minsoc_bench_clock.v |
minsoc_bench.v |
minsoc_memory_model.v |
dbg_comm_vpi.v |