Subversion Repositories minsoc

/release-0.9/utils/contributions/setup/conxshlib.sh

/release-0.9/utils/contributions/setup/cable-install.sh

release-0.9/utils/contributions/setup/cable-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/utils/contributions/setup/minsoc-install.sh =================================================================== --- release-0.9/utils/contributions/setup/minsoc-install.sh (nonexistent) +++ release-0.9/utils/contributions/setup/minsoc-install.sh (revision 42) @@ -0,0 +1,74 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing cable drivers for the impact to work +# under Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where should I put the dir. minsoc? +# ex. /home/conx/Thesis/ +DIR_TO_INSTALL="" + + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +cd $DIR_TO_INSTALL + +if [ ! -f "minsoc.tar.gz" ]; +then + execcmd "Download minsoc" "wget http://xanthopoulos.info/pub/minsoc.tar.gz" +fi + +if [ -d "minsoc" ] +then + rm minsoc -rf +fi + +execcmd "Un-tar minsoc" "tar xf minsoc.tar.gz" + +cecho "I will now start to compile everything that's needed"; + +cd minsoc/sw/utils + +execcmd "Make utils" "make" + +cd ../support + +execcmd "Make support tools" "make" + +cd ../drivers + +execcmd "Make drivers" "make" + +cd ../gpio + +execcmd "Make GPIO" "make" + +cd ../uart + +execcmd "Make UART" "make" + +cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge + +cecho "Installing FTDI headers! You will be asked to give root pass" + +execcmd "Install FTDI headers" "su -c \"aptitude install libftdi-dev\""; + +execcmd "Make adv_jtag_bridge" "make" + +cecho "Installation Finised"

release-0.9/utils/contributions/setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/utils/contributions/setup/README =================================================================== --- release-0.9/utils/contributions/setup/README (nonexistent) +++ release-0.9/utils/contributions/setup/README (revision 42) @@ -0,0 +1,24 @@ +===== STEPS ===== + +A. Install Cable Drivers: + - Edit the cable-install.sh file and set the variable ISE_PATH to the directory + where you have installed ISE (that directory must contain a directory ISE_DS). + - Run the script: ./cable-install.sh + - When finished type lsusb and you should get a line similar to + "Bus 001 Device 005: ID 03fd:0008 Xilinx, Inc." where the ID + should be as shown (03fd:0008). + - You should be able to run IMPACT and see the devices in the JTAG chain. + +B. Install GNU Toolchain for OR: + - Edit the toolchain-install.sh file and set the variables DIR_TO_INSTALL and + KERNEL_ARCH as explained in the file. + - Run the script: ./toolchain-install.sh + - When finished you should be able to run or32-elf-gdb in a new terminal. + +C. Install minsoc: + - Edit the minsoc-install.sh file and the variable DIR_TO_INSTALL. + - Run the script: ./minsoc-install.sh + - When finished you should have a working copy of minsoc project in the + specified directory. + +Hope it works! Index: release-0.9/utils/contributions/setup/toolchain-install.sh =================================================================== --- release-0.9/utils/contributions/setup/toolchain-install.sh (nonexistent) +++ release-0.9/utils/contributions/setup/toolchain-install.sh (revision 42) @@ -0,0 +1,51 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing OR GNU Toolchain. +# Only tested in Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where will I put the binaries? +# ex. /opt/openrisc/bin +DIR_TO_INSTALL=""; + +# Debian's kernel architecture {32,64} +# ex. KERNEL_ARCH="32" +KERNEL_ARCH="" + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +execcmd "Change permissions" "chmod 777 $DIR_TO_INSTALL"; + +cd $DIR_TO_INSTALL; + +if [ $KERNEL_ARCH == "32" ]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86.tar.bz2"; +elif [ $KERNEL_ARCH == "64"]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2"; +else + errormsg "Not a correct architecture. Check Configurations"; +fi + +execcmd "Un-tar" "tar xf *bz2"; + +execcmd "Adding toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;"; + +cecho "Install completed"

release-0.9/utils/contributions/setup/toolchain-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/utils/contributions/.directory =================================================================== --- release-0.9/utils/contributions/.directory (nonexistent) +++ release-0.9/utils/contributions/.directory (revision 42) @@ -0,0 +1,4 @@ +[Dolphin] +Timestamp=2011,3,1,12,36,19 +Version=2 +ViewMode=1 Index: release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v =================================================================== --- release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (nonexistent) +++ release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (revision 42) @@ -0,0 +1,310 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file + //if no initalization file used, give a name of "UNUSED" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +`ifdef ALTERA_FPGA //only for altera memory initialization + +//2^adr_width x 32bit single-port ram. +altsyncram altsyncram_component ( + .wren_a (we), + .clock0 (wb_clk_i), + .byteena_a (be_i), + .address_a (wb_adr_i[adr_width+1:2]), + .data_a (wb_dat_i), + .q_a (wb_dat_o), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = `mem_init_file, + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.numwords_a = (1<>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate +`endif + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: release-0.9/utils/contributions/initialized_onchip_ram/bin2init.py =================================================================== --- release-0.9/utils/contributions/initialized_onchip_ram/bin2init.py (nonexistent) +++ release-0.9/utils/contributions/initialized_onchip_ram/bin2init.py (revision 42) @@ -0,0 +1,212 @@ +""" +***************************************************************************** + * + H E A D E R I N F O R M A T I O N * + * +***************************************************************************** +Project Name : SysPy (System Python) + http://cgi.di.uoa.gr/~evlog/syspy.html + +File Name : bin2init.py + +Created by : Evangelos Logaras + + +***************************************************************************** + * + C O P Y R I G H T N O T I C E * + * +***************************************************************************** + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +***************************************************************************** + * + D E S C R I P T I O N * + * +***************************************************************************** + + Generates block_ram.init file from binary images. Binary images are first converted in hex files + using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script. + + Currently init file is generated for Xilinx's RAMB16_S9 BRAMs + + Usage: python bin2init.py (Python 2.6) +""" + +import commands +import sys + + +# Python's variable declarations +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +mem_arr = [] +block_ram_num = 4 +block0 = [] +block1 = [] +block2 = [] +block3 = [] +block_ram = [block3, block2, block1, block0] +init_arr = [] +mem_size2 = 8192 +mem_count = 0 +bram_count = -1 +init_count = -1 +hex_count = 0 +zero_pad = '' +filename = '' +#---------------------------------------------------------------------------------------------------------------------------------- + +# Exceptions' class +#---------------------------------------------------------------------------------------------------------------------------------- +class MyExceptions(Exception): + def __init__(self, value): + self.value = value + def __str__(self): + return repr(self.value) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Raising exception if a *.bin file is not provided as an argument +#---------------------------------------------------------------------------------------------------------------------------------- +filename = sys.argv[len(sys.argv) - 1] + +if (filename.find(".bin") == -1): + raise MyExceptions("*.bin file required") +#---------------------------------------------------------------------------------------------------------------------------------- + +i = filename.find(".bin") + +filename = filename[:i] + +# Deleting old *.hex and *.bin files +#---------------------------------------------------------------------------------------------------------------------------------- +commands.getoutput("rm " + filename + ".hex") +commands.getoutput("rm " + filename + ".init") +#---------------------------------------------------------------------------------------------------------------------------------- + +## Calling bin2hex executable to convert *.bin file to *.hex +commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex") + +# Opening the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile = open(filename + ".hex", 'r') +initFile = open(filename + ".init", 'w') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading the *.hex file and appending its contents to mem_arr[] +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +hex_count = 0 +while(y): + hex_count = hex_count + 1 + if (hex_count == 127): + mem_arr.append("00000000") + + y = hexFile.readline() + mem_arr.append(y) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading mem_arr[] and creating the contents of BRAMs +#---------------------------------------------------------------------------------------------------------------------------------- +for i in range(len(mem_arr)): + bram_count = bram_count + 1 + if (bram_count < 32): + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + elif (bram_count >= 32): + bram_count = 0 + + init_count = init_count + 1 + + if (init_count >= 64): + init_count = 0 + mem_count = mem_count + 1 + + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + + for j in range((block_ram_num - 1), -1, -1): + if (j == (block_ram_num - 1)): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + else: + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + + block_ram[0] = [] + block_ram[1] = [] + block_ram[2] = [] + block_ram[3] = [] + + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + +if (bram_count != -1): + init_count = init_count + 1 + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + if (init_count == 0): + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + else: + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + + for j in range((block_ram_num - 1), -1, -1): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + init_arr.append(zero_pad) + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + +init_arr.append(';') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Writing BRAMs contetns to *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +i = init_arr[0].find(";/n") + +init_arr[0] = init_arr[0][i + 2:] + +for i in range(len(init_arr)): + initFile.write(init_arr[i]) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Closing the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile.close() +initFile.close() +#---------------------------------------------------------------------------------------------------------------------------------- Index: release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v =================================================================== --- release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (nonexistent) +++ release-0.9/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (revision 42) @@ -0,0 +1,312 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 +/* minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); +*/ + RAMB16_S9 block_ram_0( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[7:0]), + .DIP(1'b0), + .EN(be_i[0]), + .WE(we & bank[i]), + .DO(int_dat_o[i][7:0]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); +*/ + RAMB16_S9 block_ram_1( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[15:8]), + .DIP(1'b0), + .EN(be_i[1]), + .WE(we & bank[i]), + .DO(int_dat_o[i][15:8]), + .DOP() + ); +/* + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); +*/ + RAMB16_S9 block_ram_2( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[23:16]), + .DIP(1'b0), + .EN(be_i[2]), + .WE(we & bank[i]), + .DO(int_dat_o[i][23:16]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); +*/ + RAMB16_S9 block_ram_3( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[31:24]), + .DIP(1'b0), + .EN(be_i[3]), + .WE(we & bank[i]), + .DO(int_dat_o[i][31:24]), + .DOP() + ); + + end +endgenerate + +`ifdef BLOCK_RAM_INIT +`include "block_ram.init" +`endif + +endmodule + +module mux21(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: release-0.9/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== --- release-0.9/utils/contributions/synthesis_makefile/guideTop.pdf (nonexistent) +++ release-0.9/utils/contributions/synthesis_makefile/guideTop.pdf (revision 42)

release-0.9/utils/contributions/synthesis_makefile/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/utils/contributions/synthesis_makefile/Makefile =================================================================== --- release-0.9/utils/contributions/synthesis_makefile/Makefile (nonexistent) +++ release-0.9/utils/contributions/synthesis_makefile/Makefile (revision 42) @@ -0,0 +1,107 @@ +ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +UART_RTL = $(ROOT)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog +OR1200_RTL = $(ROOT)/or1200/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " uart: Synthesize the UART" + @echo " debug: Synthesize the debug interface" + @echo " xilDebug: Synthesize the Xilinx JTAG user interface" + @echo " or1200: Synthesize the OR1200 processor" +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst +xilDebug: xilinx_internal_jtag.ngc +xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj + xst -ifn "buildSupport/xilinx_internal_jtag.xst" + rm -f xilinx_internal_jtag_xst.xrpt + rm -f xilinx_internal_jtag.srp + rm -f xilinx_internal_jtag.lso + rm -rf _xmsgs + rm -rf xst +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc_par.ncd: minsoc.ncd + par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs Index: release-0.9/utils/contributions/assembly_new_toolchain/reset.S =================================================================== --- release-0.9/utils/contributions/assembly_new_toolchain/reset.S (nonexistent) +++ release-0.9/utils/contributions/assembly_new_toolchain/reset.S (revision 42) @@ -0,0 +1,113 @@ +/* Support file for c based tests */ +#include "spr_defs.h" +#include "board.h" +#include "mc.h" + + .section .stack + .space STACK_SIZE +_stack: + + .section .reset, "ax" + + .org 0x100 +_reset_vector: + l.nop + l.nop + l.addi r2,r0,0x0 + l.addi r3,r0,0x0 + l.addi r4,r0,0x0 + l.addi r5,r0,0x0 + l.addi r6,r0,0x0 + l.addi r7,r0,0x0 + l.addi r8,r0,0x0 + l.addi r9,r0,0x0 + l.addi r10,r0,0x0 + l.addi r11,r0,0x0 + l.addi r12,r0,0x0 + l.addi r13,r0,0x0 + l.addi r14,r0,0x0 + l.addi r15,r0,0x0 + l.addi r16,r0,0x0 + l.addi r17,r0,0x0 + l.addi r18,r0,0x0 + l.addi r19,r0,0x0 + l.addi r20,r0,0x0 + l.addi r21,r0,0x0 + l.addi r22,r0,0x0 + l.addi r23,r0,0x0 + l.addi r24,r0,0x0 + l.addi r25,r0,0x0 + l.addi r26,r0,0x0 + l.addi r27,r0,0x0 + l.addi r28,r0,0x0 + l.addi r29,r0,0x0 + l.addi r30,r0,0x0 + l.addi r31,r0,0x0 + +/* + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,MC_BA_MASK + l.addi r5,r0,0x00 + l.sw 0(r3),r5 + */ + l.movhi r3,hi(_start) + l.ori r3,r3,lo(_start) + l.jr r3 + l.nop + + .section .text + +_start: + +.if IC | DC + /* Flush IC and/or DC */ + l.addi r10,r0,0 + l.addi r11,r0,0 + l.addi r12,r0,0 +.if IC + l.addi r11,r0,IC_SIZE +.endif +.if DC + l.addi r12,r0,DC_SIZE +.endif + l.sfleu r12,r11 + l.bf loop + l.nop + l.add r11,r0,r12 +loop: +.if IC + l.mtspr r0,r10,SPR_ICBIR +.endif +.if DC + l.mtspr r0,r10,SPR_DCBIR +.endif + l.sfne r10,r11 + l.bf loop + l.addi r10,r10,16 + + /* Enable IC and/or DC */ + l.addi r10,r0,(SPR_SR_SM) +.if IC + l.ori r10,r10,(SPR_SR_ICE) +.endif +.if DC + l.ori r10,r10,(SPR_SR_DCE) +.endif + l.mtspr r0,r10,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop +.endif + + /* Set stack pointer */ + l.movhi r1,hi(_stack) + l.ori r1,r1,lo(_stack) + + /* Jump to main */ + l.movhi r2,hi(reset) + l.ori r2,r2,lo(reset) + l.jr r2 + l.nop + Index: release-0.9/utils/contributions/assembly_new_toolchain/except.S =================================================================== --- release-0.9/utils/contributions/assembly_new_toolchain/except.S (nonexistent) +++ release-0.9/utils/contributions/assembly_new_toolchain/except.S (revision 42) @@ -0,0 +1,276 @@ +#include "spr_defs.h" + +// Linked from 0x200, so subtract 0x200 from each .org +.section .vectors, "ax" + +/* +.org 0x100 + +_reset: + l.nop + l.j _reset_except + l.nop +*/ +.org 0x000 + +_except_200: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j buserr_except + l.nop + +.org 0x100 + +_except_300: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j dpf_except + l.nop + +.org 0x200 + +_except_400: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j ipf_except + l.nop + +.org 0x300 + +_except_500: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j tick_except + l.nop + +.org 0x400 + +_except_600: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j align_except + l.nop + +.org 0x500 + +_except_700: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j illegal_except + l.nop + +.org 0x600 + +_except_800: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j ext_except //jmp to C interrupt handler (returns later to end_except) + l.nop + + +.org 0x700 + +_except_900: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j dtlbmiss_except + l.nop + +.org 0x800 + +_except_a00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j itlbmiss_except + l.nop + +.org 0x900 + +_except_b00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j range_except + l.nop + +.org 0xa00 + +_except_c00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j syscall_except + l.nop + +.org 0xb00 + +_except_d00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j res1_except + l.nop + +.org 0xc00 + +_except_e00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j trap_except + l.nop + +.org 0xd00 + +_except_f00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j res2_except + l.nop + +store_regs: //save registers r3-r31 (except r9) to stack + l.sw 0x00(r1),r3 + l.sw 0x04(r1),r4 + l.sw 0x08(r1),r5 + l.sw 0x0c(r1),r6 + l.sw 0x10(r1),r7 + l.sw 0x14(r1),r8 + l.sw 0x1c(r1),r10 + l.sw 0x20(r1),r11 + l.sw 0x24(r1),r12 + l.sw 0x28(r1),r13 + l.sw 0x2c(r1),r14 + l.sw 0x30(r1),r15 + l.sw 0x34(r1),r16 + l.sw 0x38(r1),r17 + l.sw 0x3c(r1),r18 + l.sw 0x40(r1),r19 + l.sw 0x44(r1),r20 + l.sw 0x48(r1),r21 + l.sw 0x4c(r1),r22 + l.sw 0x50(r1),r23 + l.sw 0x54(r1),r24 + l.sw 0x58(r1),r25 + l.sw 0x5c(r1),r26 + l.sw 0x60(r1),r27 + l.sw 0x64(r1),r28 + l.sw 0x68(r1),r29 + l.sw 0x6c(r1),r30 + l.sw 0x70(r1),r31 + l.jr r9 + l.nop + +end_except: //load back registers from stack r3-r31 + l.lwz r3,0x00(r1) + l.lwz r4,0x04(r1) + l.lwz r5,0x08(r1) + l.lwz r6,0x0c(r1) + l.lwz r7,0x10(r1) + l.lwz r8,0x14(r1) + l.lwz r9,0x18(r1) + l.lwz r10,0x1c(r1) + l.lwz r11,0x20(r1) + l.lwz r12,0x24(r1) + l.lwz r13,0x28(r1) + l.lwz r14,0x2c(r1) + l.lwz r15,0x30(r1) + l.lwz r16,0x34(r1) + l.lwz r17,0x38(r1) + l.lwz r18,0x3c(r1) + l.lwz r19,0x40(r1) + l.lwz r20,0x44(r1) + l.lwz r21,0x48(r1) + l.lwz r22,0x4c(r1) + l.lwz r23,0x50(r1) + l.lwz r24,0x54(r1) + l.lwz r25,0x58(r1) + l.lwz r26,0x5c(r1) + l.lwz r27,0x60(r1) + l.lwz r28,0x64(r1) + l.lwz r29,0x68(r1) + l.lwz r30,0x6c(r1) + l.lwz r31,0x70(r1) + l.addi r1,r1,116 //free stack places + l.rfe //recover SR register and prior PC (jumps back to program) + l.nop + Index: release-0.9/utils/contributions/minsoc_tc_top_B3.v =================================================================== --- release-0.9/utils/contributions/minsoc_tc_top_B3.v (nonexistent) +++ release-0.9/utils/contributions/minsoc_tc_top_B3.v (revision 42) @@ -0,0 +1,1883 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i, + t8_wb_cti_o, + t8_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; +output [2:0] t8_wb_cti_o; +output [1:0] t8_wb_bte_o; + + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; +wire [2:0] z_wb_cti_i; +wire [1:0] z_wb_bte_i; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i), + .t0_wb_cti_o(t0_wb_cti_o), + .t0_wb_bte_o(t0_wb_bte_o) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t), + .t0_wb_cti_o(z_wb_cti_i), + .t0_wb_bte_o(z_wb_bte_i) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + .i0_wb_cti_i(z_wb_cti_i), + .i0_wb_bte_i(z_wb_bte_i), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + .t0_wb_cti_o(t1_wb_cti_o), + .t0_wb_bte_o(t1_wb_bte_o), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + .t1_wb_cti_o(t2_wb_cti_o), + .t1_wb_bte_o(t2_wb_bte_o), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + .t2_wb_cti_o(t3_wb_cti_o), + .t2_wb_bte_o(t3_wb_bte_o), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + .t3_wb_cti_o(t4_wb_cti_o), + .t3_wb_bte_o(t4_wb_bte_o), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + .t4_wb_cti_o(t5_wb_cti_o), + .t4_wb_bte_o(t5_wb_bte_o), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + .t5_wb_cti_o(t6_wb_cti_o), + .t5_wb_bte_o(t6_wb_bte_o), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + .t6_wb_cti_o(t7_wb_cti_o), + .t6_wb_bte_o(t7_wb_bte_o), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i), + .t7_wb_cti_o(t8_wb_cti_o), + .t7_wb_bte_o(t8_wb_bte_o), + + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, +t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, +t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, +t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, +t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, +t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, +t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, +t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, +t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule Index: release-0.9/utils/contributions/eth_transf_linux/eth1_mac_recv.c =================================================================== --- release-0.9/utils/contributions/eth_transf_linux/eth1_mac_recv.c (nonexistent) +++ release-0.9/utils/contributions/eth_transf_linux/eth1_mac_recv.c (revision 42) @@ -0,0 +1,118 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; +// MacAddress localMac = {0xD3, 0x36, 0x41, 0xC0, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + //create packet socket from type sock_dgram where headers are automatically thrown out + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + //bind to interface goten from ioctl SIOCGIFHWADDR directive (otherwise all packets are recved) + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll from; + int fromlen; + + fromlen = sizeof(from); + + for (;;) + { + iRet = recvfrom(socket_id, buf, 256, 0, &from, &fromlen); + if ( iRet == -1 ) + { + perror("recvfrom"); + exit(1); + } + else + { + printf("Received %d bytes of data.\n", iRet); + printf("This is the received data:\n"); + for ( i = 0; i < iRet; i++) + printf("Byte %d: %X\n", i, (int)buf[i]); + printf("End of transmission!\n"); + } + } + + return 0; +} + Index: release-0.9/utils/contributions/eth_transf_linux/eth1_mac_snd.c =================================================================== --- release-0.9/utils/contributions/eth_transf_linux/eth1_mac_snd.c (nonexistent) +++ release-0.9/utils/contributions/eth_transf_linux/eth1_mac_snd.c (revision 42) @@ -0,0 +1,139 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; + MacAddress extMac = {0x55, 0x47, 0x34, 0x22, 0x88, 0x92}; +// MacAddress extMac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll addr_to; + int addr_toLen; + + addr_toLen = sizeof(addr_to); + + memset(&addr_to, '0', sizeof(addr_to) ); + + addr_to.sll_family = AF_PACKET; + addr_to.sll_ifindex = if_index; + addr_to.sll_halen = 6; + memcpy( &(addr_to.sll_addr), extMac, MAC_ADDR_LEN ); + + for (i=0; i<256 ; i++ ) + buf[i] = 0; + + //first 2 bytes are gathered with length and are ignored + buf[0] = 0xAA; + buf[1] = 0xAA; + //now it gets to fpga: send opcode 0xBA8 + buf[2] = 0xBA; + buf[3] = 0x87; + //opcode sent + buf[4] = 0xAA; + buf[5] = 0xAA; + buf[6] = 0xAA; + buf[7] = 0xAA; + buf[8] = 0xAA; + buf[9] = 0xAA; + buf[10] = 0xAA; + buf[11] = 0xAA; + +// for (;;) +// { + iRet = sendto(socket_id, buf, 46, 0, (struct sockaddr *) &addr_to, addr_toLen); + if ( iRet == -1 ) + { + perror("sendto"); + exit(1); + } + else + { +// printf("%s\n", buf); + printf("Data sent!\nExiting...\n"); + } +// } + + return 0; +} + Index: release-0.9/utils/contributions/gpio/rtl/gpio_defines.v =================================================================== --- release-0.9/utils/contributions/gpio/rtl/gpio_defines.v (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/gpio_defines.v (revision 42) @@ -0,0 +1,326 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE GPIO Definitions //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// GPIO IP Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.7 2003/12/01 17:10:44 simons +// ifndef directive is not supported by all tools. +// +// Revision 1.6 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.2 2003/10/02 18:54:35 simons +// GPIO signals muxed with other peripherals, higland_board fixed. +// +// Revision 1.1.1.1 2003/06/24 09:09:23 simons +// This files were moved here from toplevel folder. +// +// Revision 1.1.1.1 2003/06/11 18:51:13 simons +// Initial import. +// +// Revision 1.5 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.4 2002/05/06 18:25:31 lampret +// negedge flops are enabled by default. +// +// Revision 1.3 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.2 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.3 2001/07/15 00:21:10 lampret +// Registers can be omitted and will have certain default values +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Number of GPIO I/O signals +// +// This is the most important parameter of the GPIO IP core. It defines how many +// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are +// required, use several instances of GPIO IP core. +// +// Default is 16. +// +`define GPIO_IOS 31 + +//depending on number of GPIO_IOS, define this... +// for example: if there is 26 GPIO_IOS, define GPIO_LINES26 +// + +`define GPIO_LINES31 + +// +// Undefine this one if you don't want to remove GPIO block from your design +// but you also don't need it. When it is undefined, all GPIO ports still +// remain valid and the core can be synthesized however internally there is +// no GPIO funationality. +// +// Defined by default (duhh !). +// +`define GPIO_IMPLEMENTED + +// +// Define to register all WISHBONE outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_WB_OUTPUTS + +// +// Define to register all GPIO pad outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_IO_OUTPUTS + +// +// Implement aux feature. If this define is not defined also aux_i port and +// RGPIO_AUX register will be removed +// +// Defined by default. +// +//`define GPIO_AUX_IMPLEMENT + +// +// If this is not defined clk_pad_i will be removed. Input lines will be lached on +// positive edge of system clock +// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect. +// +// Defined by default. +// +//`define GPIO_CLKPAD + +// +// Define to avoid using negative edge clock flip-flops for external clock +// (caused by NEC register. Instead an inverted external clock with +// positive edge clock flip-flops will be used. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_NEGEDGE_FLOPS + +// +// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock +// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on +// clock signal, enable the following define. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_CLKPAD_LOGIC + + +// +// synchronization defines +// +// Two synchronization flops to input lineis added. +// system clock synchronization. +// +`define GPIO_SYNC_IN_WB + +// +// Add synchronization flops to external clock input line. Gpio will have just one clock domain, +// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower +// as systam clock. +// +`define GPIO_SYNC_CLK_WB + +// +// Add synchronization to input pads. synchronization to external clock. +// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined. +// +//`define GPIO_SYNC_IN_CLK + +// +// Add synchronization flops between system clock and external clock. +// Only possible if external clock is enabled and clock synchroization is disabled. +// +//`define GPIO_SYNC_IN_CLK_WB + + + +// +// Undefine if you don't need to read GPIO registers except for RGPIO_IN register. +// When it is undefined all reads of GPIO registers return RGPIO_IN register. This +// is usually useful if you want really small area (for example when implemented in +// FPGA). +// +// To follow GPIO IP core specification document this one must be defined. Also to +// successfully run the test bench it must be defined. By default it is defined. +// +`define GPIO_READREGS + +// +// Full WISHBONE address decoding +// +// It is is undefined, partial WISHBONE address decoding is performed. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define GPIO_FULL_DECODE + +// +// Strict 32-bit WISHBONE access +// +// If this one is defined, all WISHBONE accesses must be 32-bit. If it is +// not defined, err_o is asserted whenever 8- or 16-bit access is made. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +//`define GPIO_STRICT_32BIT_ACCESS +// +`ifdef GPIO_STRICT_32BIT_ACCESS +`else +// added by gorand : +// if GPIO_STRICT_32BIT_ACCESS is not defined, +// depending on number of gpio I/O lines, the following are defined : +// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined, +// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined, +// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined, +// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined, + +`define GPIO_WB_BYTES4 +//`define GPIO_WB_BYTES3 +//`define GPIO_WB_BYTES2 +//`define GPIO_WB_BYTES1 + +`endif + +// +// WISHBONE address bits used for full decoding of GPIO registers. +// +`define GPIO_ADDRHH 7 +`define GPIO_ADDRHL 6 +`define GPIO_ADDRLH 1 +`define GPIO_ADDRLL 0 + +// +// Bits of WISHBONE address used for partial decoding of GPIO registers. +// +// Default 5:2. +// +`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 + +// +// Addresses of GPIO registers +// +// To comply with GPIO IP core specification document they must go from +// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT, +// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL +// +// If particular register is not needed, it's address definition can be omitted +// and the register will not be implemented. Instead a fixed default value will +// be used. +// +`define GPIO_RGPIO_IN 4'h0 // Address 0x00 +`define GPIO_RGPIO_OUT 4'h1 // Address 0x04 +`define GPIO_RGPIO_OE 4'h2 // Address 0x08 +`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c +`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10 + +`ifdef GPIO_AUX_IMPLEMENT +`define GPIO_RGPIO_AUX 4'h5 // Address 0x14 +`endif // GPIO_AUX_IMPLEMENT + +`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18 +`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c + +`ifdef GPIO_CLKPAD +`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20 +`define GPIO_RGPIO_NEC 4'h9 // Address 0x24 +`endif // GPIO_CLKPAD + +// +// Default values for unimplemented GPIO registers +// +`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0 + + +// +// RGPIO_CTRL bits +// +// To comply with the GPIO IP core specification document they must go from +// bit 0 to bit 1 in the following order: INTE, INT +// +`define GPIO_RGPIO_CTRL_INTE 0 +`define GPIO_RGPIO_CTRL_INTS 1 + + Index: release-0.9/utils/contributions/gpio/rtl/gpio_top.v =================================================================== --- release-0.9/utils/contributions/gpio/rtl/gpio_top.v (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/gpio_top.v (revision 42) @@ -0,0 +1,1135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE General-Purpose I/O //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// Implementation of GPIO IP core according to //// +//// GPIO IP core specification document. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.17 2004/05/05 08:21:00 andreje +// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec +// +// Revision 1.16 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.15 2003/11/10 23:21:22 gorand +// bug fixed. all tests passed. +// +// Revision 1.14 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.13 2002/11/18 22:35:18 lampret +// Bug fix. Interrupts were also asserted when condition was not met. +// +// Revision 1.12 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.11 2002/03/13 20:56:28 lampret +// Removed zero padding as per Avi Shamli suggestion. +// +// Revision 1.10 2002/03/13 20:47:57 lampret +// Ports changed per Ran Aviram suggestions. +// +// Revision 1.9 2002/03/09 03:43:27 lampret +// Interrupt is asserted only when an input changes (code patch by Jacob Gorban) +// +// Revision 1.8 2002/01/14 19:06:28 lampret +// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. +// +// Revision 1.7 2001/12/25 17:21:21 lampret +// Fixed two typos. +// +// Revision 1.6 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.5 2001/12/12 20:35:53 lampret +// Fixing style. +// +// Revision 1.4 2001/12/12 07:12:58 lampret +// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) +// +// Revision 1.3 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.2 2001/10/31 02:26:51 lampret +// Fixed wb_err_o. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "gpio_defines.v" + +module gpio_top( + // WISHBONE Interface + wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, + wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, + +`ifdef GPIO_AUX_IMPLEMENT + // Auxiliary inputs interface + aux_i, +`endif // GPIO_AUX_IMPLEMENT + + // External GPIO Interface + ext_pad_i, ext_pad_o, ext_padoe_o +`ifdef GPIO_CLKPAD + , clk_pad_i +`endif +); + +parameter dw = 32; +parameter aw = `GPIO_ADDRHH+1; +parameter gw = `GPIO_IOS; +// +// WISHBONE Interface +// +input wb_clk_i; // Clock +input wb_rst_i; // Reset +input wb_cyc_i; // cycle valid input +input [aw-1:0] wb_adr_i; // address bus inputs +input [dw-1:0] wb_dat_i; // input data bus +input [3:0] wb_sel_i; // byte select inputs +input wb_we_i; // indicates write transfer +input wb_stb_i; // strobe input +output [dw-1:0] wb_dat_o; // output data bus +output wb_ack_o; // normal termination +output wb_err_o; // termination w/ error +output wb_inta_o; // Interrupt request output + +`ifdef GPIO_AUX_IMPLEMENT +// Auxiliary Inputs Interface +input [gw-1:0] aux_i; // Auxiliary inputs +`endif // GPIO_AUX_IMPLEMENT + +// +// External GPIO Interface +// +input [gw-1:0] ext_pad_i; // GPIO Inputs +`ifdef GPIO_CLKPAD +input clk_pad_i; // GPIO Eclk +`endif // GPIO_CLKPAD +output [gw-1:0] ext_pad_o; // GPIO Outputs +output [gw-1:0] ext_padoe_o; // GPIO output drivers enables + +`ifdef GPIO_IMPLEMENTED + +// +// GPIO Input Register (or no register) +// +`ifdef GPIO_RGPIO_IN +reg [gw-1:0] rgpio_in; // RGPIO_IN register +`else +wire [gw-1:0] rgpio_in; // No register +`endif + +// +// GPIO Output Register (or no register) +// +`ifdef GPIO_RGPIO_OUT +reg [gw-1:0] rgpio_out; // RGPIO_OUT register +`else +wire [gw-1:0] rgpio_out; // No register +`endif + +// +// GPIO Output Driver Enable Register (or no register) +// +`ifdef GPIO_RGPIO_OE +reg [gw-1:0] rgpio_oe; // RGPIO_OE register +`else +wire [gw-1:0] rgpio_oe; // No register +`endif + +// +// GPIO Interrupt Enable Register (or no register) +// +`ifdef GPIO_RGPIO_INTE +reg [gw-1:0] rgpio_inte; // RGPIO_INTE register +`else +wire [gw-1:0] rgpio_inte; // No register +`endif + +// +// GPIO Positive edge Triggered Register (or no register) +// +`ifdef GPIO_RGPIO_PTRIG +reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register +`else +wire [gw-1:0] rgpio_ptrig; // No register +`endif + +// +// GPIO Auxiliary select Register (or no register) +// +`ifdef GPIO_RGPIO_AUX +reg [gw-1:0] rgpio_aux; // RGPIO_AUX register +`else +wire [gw-1:0] rgpio_aux; // No register +`endif + +// +// GPIO Control Register (or no register) +// +`ifdef GPIO_RGPIO_CTRL +reg [1:0] rgpio_ctrl; // RGPIO_CTRL register +`else +wire [1:0] rgpio_ctrl; // No register +`endif + +// +// GPIO Interrupt Status Register (or no register) +// +`ifdef GPIO_RGPIO_INTS +reg [gw-1:0] rgpio_ints; // RGPIO_INTS register +`else +wire [gw-1:0] rgpio_ints; // No register +`endif + +// +// GPIO Enable Clock Register (or no register) +// +`ifdef GPIO_RGPIO_ECLK +reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register +`else +wire [gw-1:0] rgpio_eclk; // No register +`endif + +// +// GPIO Active Negative Edge Register (or no register) +// +`ifdef GPIO_RGPIO_NEC +reg [gw-1:0] rgpio_nec; // RGPIO_NEC register +`else +wire [gw-1:0] rgpio_nec; // No register +`endif + + +// +// Synchronization flops for input signals +// +`ifdef GPIO_SYNC_IN_WB +reg [gw-1:0] sync , + ext_pad_s ; +`else +wire [gw-1:0] ext_pad_s ; +`endif + + + +// +// Internal wires & regs +// +wire rgpio_out_sel; // RGPIO_OUT select +wire rgpio_oe_sel; // RGPIO_OE select +wire rgpio_inte_sel; // RGPIO_INTE select +wire rgpio_ptrig_sel;// RGPIO_PTRIG select +wire rgpio_aux_sel; // RGPIO_AUX select +wire rgpio_ctrl_sel; // RGPIO_CTRL select +wire rgpio_ints_sel; // RGPIO_INTS select +wire rgpio_eclk_sel ; +wire rgpio_nec_sel ; +wire full_decoding; // Full address decoding qualification +wire [gw-1:0] in_muxed; // Muxed inputs +wire wb_ack; // WB Acknowledge +wire wb_err; // WB Error +wire wb_inta; // WB Interrupt +reg [dw-1:0] wb_dat; // WB Data out +`ifdef GPIO_REGISTERED_WB_OUTPUTS +reg wb_ack_o; // WB Acknowledge +reg wb_err_o; // WB Error +reg wb_inta_o; // WB Interrupt +reg [dw-1:0] wb_dat_o; // WB Data out +`endif +wire [gw-1:0] out_pad; // GPIO Outputs +`ifdef GPIO_REGISTERED_IO_OUTPUTS +reg [gw-1:0] ext_pad_o; // GPIO Outputs +`endif +`ifdef GPIO_CLKPAD +wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock +wire [gw-1:0] pext_clk; // External clock for posedge flops +reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs +`ifdef GPIO_NO_NEGEDGE_FLOPS +`ifdef GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif // GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif +`endif // GPIO_CLKPAD + + +// +// All WISHBONE transfer terminations are successful except when: +// a) full address decoding is enabled and address doesn't match +// any of the GPIO registers +// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero +// + +// +// WB Acknowledge +// +assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o; + +// +// Optional registration of WB Ack +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_ack_o <= #1 1'b0; + else + wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ; +`else +assign wb_ack_o = wb_ack; +`endif + +// +// WB Error +// +`ifdef GPIO_FULL_DECODE +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); +`else +assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding; +`endif +`else +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); +`else +assign wb_err = 1'b0; +`endif +`endif + +// +// Optional registration of WB error +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_err_o <= #1 1'b0; + else + wb_err_o <= #1 wb_err & ~wb_err_o; +`else +assign wb_err_o = wb_err; +`endif + +// +// Full address decoder +// +`ifdef GPIO_FULL_DECODE +assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & + (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}}); +`else +assign full_decoding = 1'b1; +`endif + +// +// GPIO registers address decoder +// +`ifdef GPIO_RGPIO_OUT +assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding; +`endif +`ifdef GPIO_RGPIO_OE +assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTE +assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_PTRIG +assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding; +`endif +`ifdef GPIO_RGPIO_AUX +assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding; +`endif +`ifdef GPIO_RGPIO_CTRL +assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTS +assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; +`endif +`ifdef GPIO_RGPIO_ECLK +assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding; +`endif +`ifdef GPIO_RGPIO_NEC +assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding; +`endif + + +// +// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit +// +`ifdef GPIO_RGPIO_CTRL +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ctrl <= #1 2'b0; + else if (rgpio_ctrl_sel && wb_we_i) + rgpio_ctrl <= #1 wb_dat_i[1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; +`else +assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1 +`endif + +// +// Write to RGPIO_OUT +// +`ifdef GPIO_RGPIO_OUT +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_out <= #1 {gw{1'b0}}; + else if (rgpio_out_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_out <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0 +`endif + +// +// Write to RGPIO_OE. +// +`ifdef GPIO_RGPIO_OE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_oe <= #1 {gw{1'b0}}; + else if (rgpio_oe_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_oe <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_oe = `GPIO_DEF_RGPIO_OE; // RGPIO_OE = 0x0 +`endif + +// +// Write to RGPIO_INTE +// +`ifdef GPIO_RGPIO_INTE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_inte <= #1 {gw{1'b0}}; + else if (rgpio_inte_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_inte <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_inte = `GPIO_DEF_RGPIO_INTE; // RGPIO_INTE = 0x0 +`endif + +// +// Write to RGPIO_PTRIG +// +`ifdef GPIO_RGPIO_PTRIG +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ptrig <= #1 {gw{1'b0}}; + else if (rgpio_ptrig_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_ptrig <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG; // RGPIO_PTRIG = 0x0 +`endif + +// +// Write to RGPIO_AUX +// +`ifdef GPIO_RGPIO_AUX +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_aux <= #1 {gw{1'b0}}; + else if (rgpio_aux_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_aux <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0 +`endif + + +// +// Write to RGPIO_ECLK +// +`ifdef GPIO_RGPIO_ECLK +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_eclk <= #1 {gw{1'b0}}; + else if (rgpio_eclk_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_eclk <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK; // RGPIO_ECLK = 0x0 +`endif + + + +// +// Write to RGPIO_NEC +// +`ifdef GPIO_RGPIO_NEC +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_nec <= #1 {gw{1'b0}}; + else if (rgpio_nec_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_nec <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0 +`endif + +// +// synchronize inputs to systam clock +// +`ifdef GPIO_SYNC_IN_WB +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync <= #1 {gw{1'b0}} ; + ext_pad_s <= #1 {gw{1'b0}} ; + end else begin + sync <= #1 ext_pad_i ; + ext_pad_s <= #1 sync ; + end +`else +assign ext_pad_s = ext_pad_i; +`endif // GPIO_SYNC_IN_WB + +// +// Latch into RGPIO_IN +// +`ifdef GPIO_RGPIO_IN +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_in <= #1 {gw{1'b0}}; + else + rgpio_in <= #1 in_muxed; +`else +assign rgpio_in = in_muxed; +`endif + +`ifdef GPIO_CLKPAD + +`ifdef GPIO_SYNC_CLK_WB +// +// external clock enabled +// synchronized to system clock +// (one clock domain) +// + +reg sync_clk, + clk_s , + clk_r ; +wire pedge , + nedge ; +wire [gw-1:0] pedge_vec , + nedge_vec ; +wire [gw-1:0] in_lach ; + +assign pedge = clk_s & !clk_r ; +assign nedge = !clk_s & clk_r ; +assign pedge_vec = {gw{pedge}} ; +assign nedge_vec = {gw{nedge}} ; + +assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ; +assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync_clk <= #1 1'b0 ; + clk_s <= #1 1'b0 ; + clk_r <= #1 1'b0 ; + end else begin + sync_clk <= #1 clk_pad_i ; + clk_s <= #1 sync_clk ; + clk_r <= #1 clk_s ; + end + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 extc_in ; + end + +assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ; + +`else +// +// external clock enabled +// not synchronized to system clock +// (two clock domains) +// + +`ifdef GPIO_SYNC_IN_CLK_WB + +reg [gw-1:0] syn_extc , + extc_s ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_extc <= #1 {gw{1'b0}}; + extc_s <= #1 {gw{1'b0}}; + end else begin + syn_extc <= #1 extc_in ; + extc_s <= #1 syn_extc; + end + +`else + +wire [gw-1:0] extc_s ; +assign extc_s = syn_extc ; + +`endif // GPIO_SYNC_IN_CLK_WB + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_pclk , + ext_pad_spc ; + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_pclk <= #1 {gw{1'b0}} ; + ext_pad_spc <= #1 {gw{1'b0}} ; + end else begin + syn_pclk <= #1 ext_pad_i ; + ext_pad_spc <= #1 syn_pclk ; + end + +`else + +wire [gw-1:0] ext_pad_spc ; +assign ext_pad_spc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 ext_pad_spc ; + end + + +`ifdef GPIO_NO_NEGEDGE_FLOPS + +`ifdef GPIO_NO_CLKPAD_LOGIC + +assign extc_in = pextc_sampled; + +`else + +wire clk_n; +assign clk_n = !clk_pad_i; + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_CLKPAD_LOGIC + + +`else + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(negedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(negedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_NEGEDGE_FLOPS + +assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ; + + +`endif // GPIO_SYNC_CLK_WB + + +`else + +assign in_muxed = ext_pad_s ; + +`endif // GPIO_CLKPAD + + + +// +// Mux all registers when doing a read of GPIO registers +// +always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or + rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec) + case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case +`ifdef GPIO_READREGS + `ifdef GPIO_RGPIO_OUT + `GPIO_RGPIO_OUT: begin + wb_dat[dw-1:0] = rgpio_out; + end + `endif + `ifdef GPIO_RGPIO_OE + `GPIO_RGPIO_OE: begin + wb_dat[dw-1:0] = rgpio_oe; + end + `endif + `ifdef GPIO_RGPIO_INTE + `GPIO_RGPIO_INTE: begin + wb_dat[dw-1:0] = rgpio_inte; + end + `endif + `ifdef GPIO_RGPIO_PTRIG + `GPIO_RGPIO_PTRIG: begin + wb_dat[dw-1:0] = rgpio_ptrig; + end + `endif + `ifdef GPIO_RGPIO_NEC + `GPIO_RGPIO_NEC: begin + wb_dat[dw-1:0] = rgpio_nec; + end + `endif + `ifdef GPIO_RGPIO_ECLK + `GPIO_RGPIO_ECLK: begin + wb_dat[dw-1:0] = rgpio_eclk; + end + `endif + `ifdef GPIO_RGPIO_AUX + `GPIO_RGPIO_AUX: begin + wb_dat[dw-1:0] = rgpio_aux; + end + `endif + `ifdef GPIO_RGPIO_CTRL + `GPIO_RGPIO_CTRL: begin + wb_dat[1:0] = rgpio_ctrl; + wb_dat[dw-1:2] = {dw-2{1'b0}}; + end + `endif +`endif + `ifdef GPIO_RGPIO_INTS + `GPIO_RGPIO_INTS: begin + wb_dat[dw-1:0] = rgpio_ints; + end + `endif + default: begin + wb_dat[dw-1:0] = rgpio_in; + end + endcase + +// +// WB data output +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 {dw{1'b0}}; + else + wb_dat_o <= #1 wb_dat; +`else +assign wb_dat_o = wb_dat; +`endif + +// +// RGPIO_INTS +// +`ifdef GPIO_RGPIO_INTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ints <= #1 {gw{1'b0}}; + else if (rgpio_ints_sel && wb_we_i) + rgpio_ints <= #1 wb_dat_i[gw-1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`else +assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`endif + +// +// Generate interrupt request +// +assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0; + +// +// Optional registration of WB interrupt +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 wb_inta; +`else +assign wb_inta_o = wb_inta; +`endif // GPIO_REGISTERED_WB_OUTPUTS + +// +// Output enables are RGPIO_OE bits +// +assign ext_padoe_o = rgpio_oe; + +// +// Generate GPIO outputs +// +`ifdef GPIO_AUX_IMPLEMENT +assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux; +`else +assign out_pad = rgpio_out ; +`endif // GPIO_AUX_IMPLEMENT + +// +// Optional registration of GPIO outputs +// +`ifdef GPIO_REGISTERED_IO_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ext_pad_o <= #1 {gw{1'b0}}; + else + ext_pad_o <= #1 out_pad; +`else +assign ext_pad_o = out_pad; +`endif // GPIO_REGISTERED_IO_OUTPUTS + + +`else + +// +// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL +// is cleared and WISHBONE transfers complete with errors +// +assign wb_inta_o = 1'b0; +assign wb_ack_o = 1'b0; +assign wb_err_o = wb_cyc_i & wb_stb_i; +assign ext_padoe_o = {gw{1'b1}}; +assign ext_pad_o = {gw{1'b0}}; + +// +// Read GPIO registers +// +assign wb_dat_o = {dw{1'b0}}; + +`endif // GPIO_IMPLEMENTED + +endmodule + Index: release-0.9/utils/contributions/gpio/rtl/minsoc_top.ucf =================================================================== --- release-0.9/utils/contributions/gpio/rtl/minsoc_top.ucf (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/minsoc_top.ucf (revision 42) @@ -0,0 +1,36 @@ + +NET "clk" LOC = E12; # 50 MHz on-board clock oscillator +NET "reset" LOC = T14; # Push Button BTN_NORTH + +# UART Peripheral +NET "uart_stx" LOC = E15; # RS232 Serial port ( DTE Connector ) +NET "uart_srx" LOC = F16; # + +# GPIO +NET "io_pins<0>" LOC = R20; +NET "io_pins<1>" LOC = T19; +NET "io_pins<2>" LOC = U20; +NET "io_pins<3>" LOC = U19; +NET "io_pins<4>" LOC = V19; +NET "io_pins<5>" LOC = V20; +NET "io_pins<6>" LOC = Y22; +NET "io_pins<7>" LOC = W21; + +NET "i_pins<0>" LOC = V8; +NET "i_pins<1>" LOC = U10; +NET "i_pins<2>" LOC = U8; +NET "i_pins<3>" LOC = T9; +NET "i_pins<4>" LOC = T16; +NET "i_pins<5>" LOC = U15; +#NET "i_pins<6>" LOC = ; +NET "i_pins<7>" LOC = T15; + +################################################################################# +# Pin constraints including the IOSTANDARD and DRIVE +# Reference : Spartan-3A/3AN FPGA Starter Kit Board User Guide ( UG334 v1.1 ) +################################################################################# + +#NET "clk" LOC = E12 | IOSTANDARD = LVCMOS33; +#NET "uart_stx" LOC = E15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "uart_srx" LOC = F16 | IOSTANDARD = LVCMOS33; +#NET "reset" LOC = T14 | IOSTANDARD = LVCMOS33 | PULLDOWN ; Index: release-0.9/utils/contributions/gpio/rtl/minsoc_defines.v =================================================================== --- release-0.9/utils/contributions/gpio/rtl/minsoc_defines.v (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/minsoc_defines.v (revision 42) @@ -0,0 +1,130 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET; //rstn +`define POSITIVE_RESET; //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET +`define GPIO + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// GPIO Pins +// +`define GPIO_HAS_INPUT_PINS +//`define GPIO_HAS_OUTPUT_PINS +`define GPIO_HAS_BIDIR_PINS + +`define GPIO_NUM_INPUT 4'd8 +`define GPIO_NUM_OUTPUT 4'd0 +`define GPIO_NUM_BIDIR 4'd8 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_GPIO 6 +`define APP_INT_RES3 19:7 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_GPIO `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: release-0.9/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v =================================================================== --- release-0.9/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (revision 42) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:27 10/29/2009 +// Design Name: +// Module Name: minsoc_spartan_3a_starter_kit_ios +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module minsoc_spartan_3a_starter_kit_ios +( + // Signals from GPIO Core + ext_pad_o, + ext_pad_oe, + ext_pad_i, + + // Signals driving external pins + i_pins, + o_pins, + io_pins +); + parameter gpio_num = 32; + parameter i_line_num = 8; + parameter o_line_num = 8; + parameter io_line_num= 8; + + input [gpio_num-1:0] ext_pad_o; + input [gpio_num-1:0] ext_pad_oe; + output [gpio_num-1:0] ext_pad_i; + + input [i_line_num-1:0] i_pins; + output [o_line_num-1:0] o_pins; + inout [io_line_num-1:0] io_pins; + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_0 ( + .O(ext_pad_i[0]), // Buffer output + .IO(io_pins[0]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[0]), // Buffer input + .T(~ext_pad_oe[0]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_1 ( + .O(ext_pad_i[1]), // Buffer output + .IO(io_pins[1]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[1]), // Buffer input + .T(~ext_pad_oe[1]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_2 ( + .O(ext_pad_i[2]), // Buffer output + .IO(io_pins[2]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[2]), // Buffer input + .T(~ext_pad_oe[2]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_3 ( + .O(ext_pad_i[3]), // Buffer output + .IO(io_pins[3]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[3]), // Buffer input + .T(~ext_pad_oe[3]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_4 ( + .O(ext_pad_i[4]), // Buffer output + .IO(io_pins[4]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[4]), // Buffer input + .T(~ext_pad_oe[4]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_5 ( + .O(ext_pad_i[5]), // Buffer output + .IO(io_pins[5]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[5]), // Buffer input + .T(~ext_pad_oe[5]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_6 ( + .O(ext_pad_i[6]), // Buffer output + .IO(io_pins[6]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[6]), // Buffer input + .T(~ext_pad_oe[6]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_7 ( + .O(ext_pad_i[7]), // Buffer output + .IO(io_pins[7]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[7]), // Buffer input + .T(~ext_pad_oe[7]) // 3-state enable input + ); + + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_0 ( + .O(ext_pad_i[8]), // Buffer output + .I(i_pins[0]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_1 ( + .O(ext_pad_i[9]), // Buffer output + .I(i_pins[1]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_2 ( + .O(ext_pad_i[10]), // Buffer output + .I(i_pins[2]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_3 ( + .O(ext_pad_i[11]), // Buffer output + .I(i_pins[3]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_4 ( + .O(ext_pad_i[12]), // Buffer output + .I(i_pins[4]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_5 ( + .O(ext_pad_i[13]), // Buffer output + .I(i_pins[5]) // Buffer input (connect directly to top-level port) + ); + + /* PUSH Button NORTH is RESET. + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_6 ( + .O(ext_pad_i[14]), // Buffer output + .I(i_pins[6]) // Buffer input (connect directly to top-level port) + ); + */ + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_7 ( + .O(ext_pad_i[15]), // Buffer output + .I(i_pins[7]) // Buffer input (connect directly to top-level port) + ); +endmodule Index: release-0.9/utils/contributions/gpio/rtl/minsoc_top.v =================================================================== --- release-0.9/utils/contributions/gpio/rtl/minsoc_top.v (nonexistent) +++ release-0.9/utils/contributions/gpio/rtl/minsoc_top.v (revision 42) @@ -0,0 +1,1105 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +`include "gpio_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif + + // GPIO ports +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + ,i_pins + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + ,o_pins + `endif + `ifdef GPIO_HAS_BIDIR_PINS + ,io_pins + `endif +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// GPIO +// +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + input [`GPIO_NUM_INPUT-1:0] i_pins; + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + output [`GPIO_NUM_OUTPUT-1:0] o_pins; + `endif + `ifdef GPIO_HAS_BIDIR_PINS + inout [`GPIO_NUM_BIDIR-1:0] io_pins; + `endif +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [19:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// GPIO core slave i/f wires +// +wire [31:0] wb_gpio_dat_i; +wire [31:0] wb_gpio_dat_o; +wire [31:0] wb_gpio_adr_i; +wire [3:0] wb_gpio_sel_i; +wire wb_gpio_we_i; +wire wb_gpio_cyc_i; +wire wb_gpio_stb_i; +wire wb_gpio_ack_o; +wire wb_gpio_err_o; + +// +// Interface to GPIO core - Device specific core +// +wire [`GPIO_IOS:0] ext_pad_o; +wire [`GPIO_IOS:0] ext_pad_i; +wire [`GPIO_IOS:0] ext_pad_oe_o; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b1; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_op[2] ), + .cpu0_we_o ( dbg_op[0] ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_o(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_op[2] ), + .dbg_we_i ( dbg_op[0] ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +minsoc_onchip_ram_top # +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; +`endif + + +// +// Instantiation of the GPIO +// +`ifdef GPIO +gpio_top #( .gw(`GPIO_IOS + 1) ) +gpio_top_inst ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_gpio_adr_i[4:0] ), + .wb_dat_i ( wb_gpio_dat_i ), + .wb_dat_o ( wb_gpio_dat_o ), + .wb_we_i ( wb_gpio_we_i ), + .wb_stb_i ( wb_gpio_stb_i ), + .wb_cyc_i ( wb_gpio_cyc_i ), + .wb_ack_o ( wb_gpio_ack_o ), + .wb_sel_i ( wb_gpio_sel_i ), + + // Interrupt request + .wb_inta_o ( pic_ints[`APP_INT_GPIO] ), + + // GPIO external signals + .ext_pad_o ( ext_pad_o ), + .ext_pad_i ( ext_pad_i ), + .ext_padoe_o( ext_pad_oe_o ) + +); + +minsoc_spartan_3a_starter_kit_ios #( .gpio_num(`GPIO_IOS + 1), + `ifdef GPIO_HAS_INPUT_PINS + .i_line_num(`GPIO_NUM_INPUT), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_line_num(`GPIO_NUM_OUTPUT), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_line_num(`GPIO_NUM_BIDIR) + `endif +) minsoc_spartan_3a_starter_kit_ios_inst_0 ( + .ext_pad_o( ext_pad_o ), + .ext_pad_oe( ext_pad_oe_o ), + .ext_pad_i( ext_pad_i ), + `ifdef GPIO_HAS_INPUT_PINS + .i_pins( i_pins ), + `else + .i_pins( ), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_pins( o_pins ), + `else + .o_pins( ), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_pins( io_pins ) + `else + .io_pins( ) + `endif +); + +`else +assign wb_gpio_dat_o = 32'h0000_0000; +assign wb_gpio_ack_o = 1'b0; +`endif + + + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +eth_top eth_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_GPIO, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( wb_gpio_cyc_i ), + .t7_wb_stb_o ( wb_gpio_stb_i ), + .t7_wb_adr_o ( wb_gpio_adr_i ), + .t7_wb_sel_o ( wb_gpio_sel_i ), + .t7_wb_we_o ( wb_gpio_we_i ), + .t7_wb_dat_o ( wb_gpio_dat_i ), + .t7_wb_dat_i ( wb_gpio_dat_o ), + .t7_wb_ack_i ( wb_gpio_ack_o ), + .t7_wb_err_i ( wb_gpio_err_o ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule Index: release-0.9/utils/contributions/gpio/sw/gpio.c =================================================================== --- release-0.9/utils/contributions/gpio/sw/gpio.c (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/gpio.c (revision 42) @@ -0,0 +1,225 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" + +#include "gpio.h" + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + tick_init(); + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay(); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + report(0xdeaddead); + or32_exit(0); +} Index: release-0.9/utils/contributions/gpio/sw/udelay.c =================================================================== --- release-0.9/utils/contributions/gpio/sw/udelay.c (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/udelay.c (revision 42) @@ -0,0 +1,13 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../drivers/tick.h" + +extern int tick_int; + +void udelay(void) +{ + while (!tick_int); + tick_ack(); +} + Index: release-0.9/utils/contributions/gpio/sw/gpio.h =================================================================== --- release-0.9/utils/contributions/gpio/sw/gpio.h (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/gpio.h (revision 42) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: release-0.9/utils/contributions/gpio/sw/Makefile =================================================================== --- release-0.9/utils/contributions/gpio/sw/Makefile (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/Makefile (revision 42) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +drivers = ../drivers/libdrivers.a +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ Index: release-0.9/utils/contributions/gpio/sw/old/gpio.c =================================================================== --- release-0.9/utils/contributions/gpio/sw/old/gpio.c (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/old/gpio.c (revision 42) @@ -0,0 +1,351 @@ +#include "../support/support.h" +#include "../support/board.h" +#include "../support/uart.h" + +#include "../support/spr_defs.h" + +#include "gpio.h" + + +void uart_print_str(char *); +void uart_print_long(unsigned long); + +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void lpint_except(){} +void align_except(){} +void illegal_except(){} +/*void hpint_except(){ + +}*/ +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } +} + + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} + +/* + * + * + * + * + * + * + * + * + * + */ + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + gpio_config_bit( &gpio_1, DIP_0, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_1, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_2, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_3, IO_INPUT); + + uart_print_str("Demo 1 : Check for running LED patterns on board ...\n"); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay( 100000 ); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + gpio_config_bit( &gpio_1, PUSH_EAST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_EAST, POS_EDGE, hello_east ); + gpio_config_bit( &gpio_1, PUSH_WEST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_WEST, POS_EDGE, hello_west ); + gpio_config_bit( &gpio_1, PUSH_SOUTH, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_SOUTH, POS_EDGE, hello_south ); + + uart_print_str("Demo 2 : Press the DIP switches and watch corresponding LED glow ...\n"); + + + while (1) { + gpio_get_bit( &gpio_1, DIP_0, &t0 ); + gpio_get_bit( &gpio_1, DIP_1, &t1 ); + gpio_get_bit( &gpio_1, DIP_2, &t2 ); + gpio_get_bit( &gpio_1, DIP_3, &t3 ); + // + gpio_set_bit( &gpio_1, LED_0, t0 ); + gpio_set_bit( &gpio_1, LED_1, t1 ); + gpio_set_bit( &gpio_1, LED_2, t2 ); + gpio_set_bit( &gpio_1, LED_3, t3 ); + } + + + report(0xdeaddead); + or32_exit(0); +} Index: release-0.9/utils/contributions/gpio/sw/old/udelay.c =================================================================== --- release-0.9/utils/contributions/gpio/sw/old/udelay.c (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/old/udelay.c (revision 42) @@ -0,0 +1,17 @@ +#include "../support/support.h" +#include "../support/board.h" + + +void udelay(unsigned long); + +void udelay(unsigned long usecs) +{ + unsigned long i; + unsigned long cycles = usecs / (IN_CLK / 1000000 ); + unsigned long mem_dummy; + volatile unsigned long* ptr = &mem_dummy; + + for ( i=0; i< cycles; i++) + *ptr = 0xABCD; +} + Index: release-0.9/utils/contributions/gpio/sw/old/gpio.h =================================================================== --- release-0.9/utils/contributions/gpio/sw/old/gpio.h (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/old/gpio.h (revision 42) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: release-0.9/utils/contributions/gpio/sw/old/Makefile =================================================================== --- release-0.9/utils/contributions/gpio/sw/old/Makefile (nonexistent) +++ release-0.9/utils/contributions/gpio/sw/old/Makefile (revision 42) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 $(common) + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + Index: release-0.9/utils/cable_parallel.c =================================================================== --- release-0.9/utils/cable_parallel.c (nonexistent) +++ release-0.9/utils/cable_parallel.c (revision 42) @@ -0,0 +1,219 @@ +/* cable_parallel.c - Parallel cable drivers (XPC3 and XESS) for the Advanced JTAG Bridge + Copyright (C) 2001 Marko Mlinar, markom@opencores.org + Copyright (C) 2004 György Jeney, nog@sdf.lonestar.org + + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "cable_common.h" +#include "errcodes.h" + + +// Common functions used by both cable types +static int cable_parallel_out(uint8_t value); +static int cable_parallel_inout(uint8_t value, uint8_t *inval); + + +int fd; + + + +///////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------[ Parallel port specific functions ]---*/ +/////////////////////////////////////////////////////////////////////////////// + +int cable_parallel_init() +{ +/* + //#ifndef WIN32 + if (ioperm(base, 3, 1)) { + fprintf(stderr, "Couldn't get the port at %x\n", base); + perror("Root privileges are required.\n"); + return APP_ERR_INIT_FAILED; + } + printf("Connected to parallel port at %x\n", base); + printf("Dropping root privileges.\n"); + setreuid(getuid(), getuid()); + //#endif +*/ + int mode = IEEE1284_MODE_COMPAT; + fd = open("/dev/parport0", O_RDWR | O_NONBLOCK); + if (fd == -1) + { + perror("Not able to acquire the device desriptor\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPCLAIM) == -1) + { + perror("Fail to claim the interface for itself.\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPSETMODE, &mode) == -1) + { + perror("Setting compatibility mode failed.\n"); + return APP_ERR_INIT_FAILED; + } + + return APP_ERR_NONE; +} + + +int cable_parallel_opt(int c, char *str) +{ + switch(c) { + case 'p': +// if(!sscanf(str, "%x", &base)) { +// fprintf(stderr, "p parameter must have a hex number as parameter\n"); + return APP_ERR_BAD_PARAM; +// } + break; + default: + fprintf(stderr, "Unknown parameter '%c'\n", c); + return APP_ERR_BAD_PARAM; + } + return APP_ERR_NONE; +} + +/*-----------------------------------------[ Physical board wait function ]---*/ +void cable_parallel_phys_wait() +{ + /* Multiple users have reported poor performance of parallel cables, + * which has been traced to usleep() sleeping much longer than + * microseconds. The same users have reported error-free functionality + * and an order of magnitude improvement in upload speed. + * If you get strange data errors while running, add this sleep back + * in, or perhaps a busy-wait delay. + */ + /* usleep(10); */ +} + +/*----------------------------------------------[ xpc3 specific functions ]---*/ +int cable_xpc3_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + return cable_parallel_out(out); +} + +int cable_xpc3_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x10) /* S6 pin 13 */ + *inval = 1; + else + *inval = 0; + + return retval; +} + +/*----------------------------------------------[ xess specific functions ]---*/ +int cable_xess_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + return cable_parallel_out(out); +} + +uint8_t cable_xess_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x20) /* S5 pin 12*/ + *inval = 1; + else + *inval = 0; + + return retval; +} + + +/*----------------------------------------------[ common helper functions ]---*/ +// 'static' for internal access only + +static int cable_parallel_out(uint8_t value) +{ + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +} + +static int cable_parallel_inout(uint8_t value, uint8_t *inval) +{ + ioctl(fd, PPRSTATUS, inval); + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +}

release-0.9/utils/cable_parallel.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/utils/minsoc_wb_32_8_bridge.v =================================================================== --- release-0.9/utils/minsoc_wb_32_8_bridge.v (nonexistent) +++ release-0.9/utils/minsoc_wb_32_8_bridge.v (revision 42) @@ -0,0 +1,52 @@ + +module minsoc_wb_32_8_bridge( + wb_32_sel_i, + wb_32_dat_i, wb_32_dat_o, wb_32_adr_i, + + wb_8_dat_i, wb_8_dat_o, wb_8_adr_i +); + +input [3:0] wb_32_sel_i; + +input [31:0] wb_32_dat_i; +output reg [31:0] wb_32_dat_o; +input [31:0] wb_32_adr_i; + +output reg [7:0] wb_8_dat_i; +input [7:0] wb_8_dat_o; +output [31:0] wb_8_adr_i; + +reg [1:0] wb_8_adr; + +// put output to the correct byte in 32 bits using select line +always @(wb_32_sel_i or wb_8_dat_o) + case (wb_32_sel_i) + 4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + 4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0}; + 4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0}; + 4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0}; + 4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + default: wb_32_dat_o <= #1 0; + endcase // case(wb_sel_i) + +always @(wb_32_sel_i or wb_32_dat_i) +begin + case (wb_32_sel_i) + 4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0]; + 4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8]; + 4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16]; + 4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24]; + default : wb_8_dat_i = wb_32_dat_i[7:0]; + endcase // case(wb_sel_i) + case (wb_32_sel_i) + 4'b0001 : wb_8_adr = 2'h3; + 4'b0010 : wb_8_adr = 2'h2; + 4'b0100 : wb_8_adr = 2'h1; + 4'b1000 : wb_8_adr = 2'h0; + default : wb_8_adr = 2'h0; + endcase // case(wb_sel_i) +end + +assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr }; + +endmodule Index: release-0.9/doc/FAQ.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/FAQ.pdf =================================================================== --- release-0.9/doc/FAQ.pdf (nonexistent) +++ release-0.9/doc/FAQ.pdf (revision 42)

release-0.9/doc/FAQ.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/HOWTO.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/HOWTO.odt =================================================================== --- release-0.9/doc/src/HOWTO.odt (nonexistent) +++ release-0.9/doc/src/HOWTO.odt (revision 42)

release-0.9/doc/src/HOWTO.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/INSTALL.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/INSTALL.odt =================================================================== --- release-0.9/doc/src/INSTALL.odt (nonexistent) +++ release-0.9/doc/src/INSTALL.odt (revision 42)

release-0.9/doc/src/INSTALL.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/FAQ.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/FAQ.odt =================================================================== --- release-0.9/doc/src/FAQ.odt (nonexistent) +++ release-0.9/doc/src/FAQ.odt (revision 42)

release-0.9/doc/src/FAQ.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/synthesis_examples.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/synthesis_examples.odt =================================================================== --- release-0.9/doc/src/synthesis_examples.odt (nonexistent) +++ release-0.9/doc/src/synthesis_examples.odt (revision 42)

release-0.9/doc/src/synthesis_examples.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/minsoc.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/minsoc.odt =================================================================== --- release-0.9/doc/src/minsoc.odt (nonexistent) +++ release-0.9/doc/src/minsoc.odt (revision 42)

release-0.9/doc/src/minsoc.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/figures/or1200.gif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/figures/or1200.gif =================================================================== --- release-0.9/doc/src/figures/or1200.gif (nonexistent) +++ release-0.9/doc/src/figures/or1200.gif (revision 42)

release-0.9/doc/src/figures/or1200.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/figures/soc.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/figures/soc.odg =================================================================== --- release-0.9/doc/src/figures/soc.odg (nonexistent) +++ release-0.9/doc/src/figures/soc.odg (revision 42)

release-0.9/doc/src/figures/soc.odg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/src/status_progress.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/src/status_progress.odt =================================================================== --- release-0.9/doc/src/status_progress.odt (nonexistent) +++ release-0.9/doc/src/status_progress.odt (revision 42)

release-0.9/doc/src/status_progress.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/HOWTO.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/HOWTO.pdf =================================================================== --- release-0.9/doc/HOWTO.pdf (nonexistent) +++ release-0.9/doc/HOWTO.pdf (revision 42)

release-0.9/doc/HOWTO.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/README.txt =================================================================== --- release-0.9/doc/README.txt (nonexistent) +++ release-0.9/doc/README.txt (revision 42) @@ -0,0 +1,11 @@ +Welcome to MinSoC. In order to put the system up and running you still have to follow two steps. + +1. Follow the INSTALL.pdf document found in this same directory. It will guide you to install the OpenCores modules which are part of the MinSoC system but not delivered with it. Furthermore, it will guide you to install the tools required to compile OpenRISC firmware and to connect to the system (upload and debug firmware). + +2. Follow the HOWTO.pdf document found in this same directory. This document guides you to compile MinSoC firmwares, to simulate the system running its firmware, and to synthesize the system to create a FPGA bitfile to configure your FPGA. Finally, it also guides you in running your first firmware on your FPGA. + +IMPORTANT: By any arisen problems, doubts or special requirements, take a look into the FAQ.pdf document. It includes possible adaptations you can easily make to the system, most reported problems using MinSoC and the Advanced Debug System, and even some tweak possibilities. If you have a problem which is not described there or you cannot make it work, please start a thread about your problem on OpenRISC forum: http://opencores.org/forum,OpenRISC + +FINALLY: My system is up and running, what do I do next? The real system documentation is the minsoc.pdf document. It gives a thorough insight into MinSoC, its goals, design and ideas. It helps you to better understand the system and can give you a good idea of what to do next, after your system is up and running. + +I WANT TO TWEAK THINGS: check THESIS.txt \ No newline at end of file Index: release-0.9/doc/THESIS.txt =================================================================== --- release-0.9/doc/THESIS.txt (nonexistent) +++ release-0.9/doc/THESIS.txt (revision 42) @@ -0,0 +1,25 @@ +HELP, MY THESIS PROJECT ON OPENRISC IS PENDING +"I want to know how the OpenRisc processor is implemented internally. So, for example, how the simplest commands(like add, multiply) are executed inside it." + +This is not the first time I see this question lately. The best you can do is check or1200 specification on or1200 page of the OpenRISC project. However, this will not explain to you how the instructions are implemented, neither does the architecture manual found under Architecture of OpenRISC project. They only give you an understanding of the design and its global picture. + +To understand the implementation details, you have to read the source. You will be mostly interested in or1200_alu.v, though or1200_cpu.v and or1200_ctrl.v might be important to have the bigger picture. + +However, in order to do so, you have to understand HDL very well, so please go first to the following links: + +Learning HDL: +Verilog tutorial: http://www.asic-world.com/verilog/veritut.html +Coding parallelism: http://en.wikibooks.org/wiki/Microprocessor_Design/Add_and_Subtract_Blocks + +Another very good tutorial but for VHDL, this will help you understand basic coding techniques in HDL: +http://www.vhdl-online.de/tutorial/ + +Then you have to read the available documentation of OpenRISC: +First, architectural manual: http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf +Then or1200 implementation specification: http://opencores.org/svnget,or1k?file=/trunk/or1200/doc/openrisc1200_spec.pdf +Possibly the supplementary programmer's reference manual (specially if you want to include new instructions): http://opencores.org/svnget,or1k?file=/trunk/or1200/doc/openrisc1200_spec.pdf + +Finally you can go to the sources. + +Good luck and enjoy your time, +Raul Fajardo \ No newline at end of file Index: release-0.9/doc/INSTALL.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/INSTALL.pdf =================================================================== --- release-0.9/doc/INSTALL.pdf (nonexistent) +++ release-0.9/doc/INSTALL.pdf (revision 42)

release-0.9/doc/INSTALL.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/synthesis_examples.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/synthesis_examples.pdf =================================================================== --- release-0.9/doc/synthesis_examples.pdf (nonexistent) +++ release-0.9/doc/synthesis_examples.pdf (revision 42)

release-0.9/doc/synthesis_examples.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/minsoc.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/minsoc.pdf =================================================================== --- release-0.9/doc/minsoc.pdf (nonexistent) +++ release-0.9/doc/minsoc.pdf (revision 42)

release-0.9/doc/minsoc.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/status_progress.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-0.9/doc/status_progress.pdf =================================================================== --- release-0.9/doc/status_progress.pdf (nonexistent) +++ release-0.9/doc/status_progress.pdf (revision 42)

release-0.9/doc/status_progress.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-0.9/doc/lgpl-3.0.txt =================================================================== --- release-0.9/doc/lgpl-3.0.txt (nonexistent) +++ release-0.9/doc/lgpl-3.0.txt (revision 42) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. Additional Definitions. + + As used herein, "this License" refers to version 3 of the GNU Lesser +General Public License, and the "GNU GPL" refers to version 3 of the GNU +General Public License. + + "The Library" refers to a covered work governed by this License, +other than an Application or a Combined Work as defined below. + + An "Application" is any work that makes use of an interface provided +by the Library, but which is not otherwise based on the Library. +Defining a subclass of a class defined by the Library is deemed a mode +of using an interface provided by the Library. + + A "Combined Work" is a work produced by combining or linking an +Application with the Library. The particular version of the Library +with which the Combined Work was made is also called the "Linked +Version". + + The "Minimal Corresponding Source" for a Combined Work means the +Corresponding Source for the Combined Work, excluding any source code +for portions of the Combined Work that, considered in isolation, are +based on the Application, and not on the Linked Version. + + The "Corresponding Application Code" for a Combined Work means the +object code and/or source code for the Application, including any data +and utility programs needed for reproducing the Combined Work from the +Application, but excluding the System Libraries of the Combined Work. + + 1. Exception to Section 3 of the GNU GPL. + + You may convey a covered work under sections 3 and 4 of this License +without being bound by section 3 of the GNU GPL. + + 2. Conveying Modified Versions. + + If you modify a copy of the Library, and, in your modifications, a +facility refers to a function or data to be supplied by an Application +that uses the facility (other than as an argument passed when the +facility is invoked), then you may convey a copy of the modified +version: + + a) under this License, provided that you make a good faith effort to + ensure that, in the event an Application does not supply the + function or data, the facility still operates, and performs + whatever part of its purpose remains meaningful, or + + b) under the GNU GPL, with none of the additional permissions of + this License applicable to that copy. + + 3. Object Code Incorporating Material from Library Header Files. + + The object code form of an Application may incorporate material from +a header file that is part of the Library. You may convey such object +code under terms of your choice, provided that, if the incorporated +material is not limited to numerical parameters, data structure +layouts and accessors, or small macros, inline functions and templates +(ten or fewer lines in length), you do both of the following: + + a) Give prominent notice with each copy of the object code that the + Library is used in it and that the Library and its use are + covered by this License. + + b) Accompany the object code with a copy of the GNU GPL and this license + document. + + 4. Combined Works. + + You may convey a Combined Work under terms of your choice that, +taken together, effectively do not restrict modification of the +portions of the Library contained in the Combined Work and reverse +engineering for debugging such modifications, if you also do each of +the following: + + a) Give prominent notice with each copy of the Combined Work that + the Library is used in it and that the Library and its use are + covered by this License. + + b) Accompany the Combined Work with a copy of the GNU GPL and this license + document. + + c) For a Combined Work that displays copyright notices during + execution, include the copyright notice for the Library among + these notices, as well as a reference directing the user to the + copies of the GNU GPL and this license document. + + d) Do one of the following: + + 0) Convey the Minimal Corresponding Source under the terms of this + License, and the Corresponding Application Code in a form + suitable for, and under terms that permit, the user to + recombine or relink the Application with a modified version of + the Linked Version to produce a modified Combined Work, in the + manner specified by section 6 of the GNU GPL for conveying + Corresponding Source. + + 1) Use a suitable shared library mechanism for linking with the + Library. A suitable mechanism is one that (a) uses at run time + a copy of the Library already present on the user's computer + system, and (b) will operate properly with a modified version + of the Library that is interface-compatible with the Linked + Version. + + e) Provide Installation Information, but only if you would otherwise + be required to provide such information under section 6 of the + GNU GPL, and only to the extent that such information is + necessary to install and execute a modified version of the + Combined Work produced by recombining or relinking the + Application with a modified version of the Linked Version. (If + you use option 4d0, the Installation Information must accompany + the Minimal Corresponding Source and Corresponding Application + Code. If you use option 4d1, you must provide the Installation + Information in the manner specified by section 6 of the GNU GPL + for conveying Corresponding Source.) + + 5. Combined Libraries. + + You may place library facilities that are a work based on the +Library side by side in a single library together with other library +facilities that are not Applications and are not covered by this +License, and convey such a combined library under terms of your +choice, if you do both of the following: + + a) Accompany the combined library with a copy of the same work based + on the Library, uncombined with any other library facilities, + conveyed under the terms of this License. + + b) Give prominent notice with the combined library that part of it + is a work based on the Library, and explaining where to find the + accompanying uncombined form of the same work. + + 6. Revised Versions of the GNU Lesser General Public License. + + The Free Software Foundation may publish revised and/or new versions +of the GNU Lesser General Public License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library.

release-0.9/doc/lgpl-3.0.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/backend/ml509.ucf =================================================================== --- release-0.9/backend/ml509.ucf (nonexistent) +++ release-0.9/backend/ml509.ucf (revision 42) @@ -0,0 +1,45 @@ +NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI + +## #------------------------------------------------------------------------------ +## # IO Pad Location Constraints / Properties for Ethernet +## #------------------------------------------------------------------------------ + +#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; +#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; + +#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; +#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy +#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; +#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; +#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; +#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; +#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; +#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; + +## PHY Serial Management Interface pins +#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; +#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; + +## # Timing Constraints (these are recommended in documentation and +## # are unaltered except for the TIG) +#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; +#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; +#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; +#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; + +## # Timing ignores (to specify unconstrained paths) +#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock +#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; +#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: release-0.9/backend/spartan3a_dsp_kit.ucf =================================================================== --- release-0.9/backend/spartan3a_dsp_kit.ucf (nonexistent) +++ release-0.9/backend/spartan3a_dsp_kit.ucf (revision 42) @@ -0,0 +1,72 @@ +########################### +## +## Global signals +## +net "clk" loc = "f13"; #125MHz clock +net "reset" loc = "j17"; #SW5 +########################### + +########################### +## +## JTAG +## +#net "jtag_tms" loc = "aa23"; #SAM D0 +#net "jtag_tdi" loc = "u20"; #SAM D2 +#net "jtag_tdo" loc = "aa25"; #SAM D4 +#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 +#net "jtag_gnd" loc = "y23"; #SAM D8 +#net "jtag_vref" loc = "t20"; #SAM D10 +########################### + +############################# +## +## SPI Flash External Memory +## +#NET "spi_flash_mosi" LOC = "ab15"; +#NET "spi_flash_miso" LOC = "af24"; +#NET "spi_flash_sclk" LOC = "ae24"; +#NET "spi_flash_ss(1)" LOC = "ac25"; +#NET "spi_flash_ss(0)" LOC = "aa7"; +########################### + +########################### +## +## UART +## +net "uart_stx" loc = "p22"; +net "uart_srx" loc = "n21"; +########################### + +########################### +## +## ETH +## +NET "eth_txd(3)" LOC = "b1"; +NET "eth_txd(2)" LOC = "b2"; +NET "eth_txd(1)" LOC = "j9"; +NET "eth_txd(0)" LOC = "j8"; + +NET "eth_tx_en" LOC = "d3"; +NET "eth_tx_clk" LOC = "p2"; +NET "eth_tx_er" LOC = "e4"; + +NET "eth_rxd(3)" LOC = "d2"; +NET "eth_rxd(2)" LOC = "g5"; +NET "eth_rxd(1)" LOC = "g2"; +NET "eth_rxd(0)" LOC = "c2"; + +NET "eth_rx_er" LOC = "j3"; +NET "eth_rx_dv" LOC = "d1"; + +NET "eth_rx_clk" LOC = "p1"; + +NET "eth_mdio" LOC = "f5" | PULLUP; +NET "eth_crs" LOC = "g1"; +NET "eth_col" LOC = "y3"; +NET "eth_mdc" LOC = "f4"; + +NET "eth_trste" LOC = "g4"; + +NET "eth_fds_mdint" LOC = "j1"; +########################### +

release-0.9/backend/spartan3a_dsp_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/backend/spartan3e_starter_kit.ucf =================================================================== --- release-0.9/backend/spartan3e_starter_kit.ucf (nonexistent) +++ release-0.9/backend/spartan3e_starter_kit.ucf (revision 42) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#

release-0.9/backend/spartan3e_starter_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/eth/eth.c =================================================================== --- release-0.9/sw/eth/eth.c (nonexistent) +++ release-0.9/sw/eth/eth.c (revision 42) @@ -0,0 +1,62 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" +#include "../drivers/eth.h" + + +extern int eth_rx_len; +extern int eth_rx_done, eth_tx_done; +extern unsigned char * eth_rx_data; +extern unsigned char * eth_tx_data; + +void eth_receive() +{ + int i; + uart_print_str("Length: \n"); + uart_print_long(eth_rx_len); + uart_print_str("\n"); + uart_print_str("Data: \n"); + for ( i = 0; i < eth_rx_len; i++ ) + { + uart_print_short(eth_rx_data[i]); + uart_print_str("\n"); + } + eth_recv_ack(); +} + +int main() +{ + unsigned long lalala; + uart_init(); + + int_init(); + eth_init(); + int_add(UART_IRQ, &uart_interrupt); + int_add(ETH_IRQ, ð_interrupt); + + /* We can't use printf because in this simple example + we don't link C library. */ + uart_print_str("Hello World.\n\r"); + + eth_tx_data[0] = 0xFF; + eth_tx_data[1] = 0x2B; + eth_tx_data[2] = 0x40; + eth_tx_data[3] = 0x50; + + eth_send(4); + + while(1) + { + if (eth_rx_done) + { + eth_receive(); + } + } + + report(0xdeaddead); + or32_exit(0); +} +

release-0.9/sw/eth/eth.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/eth/Makefile =================================================================== --- release-0.9/sw/eth/Makefile (nonexistent) +++ release-0.9/sw/eth/Makefile (revision 42) @@ -0,0 +1,24 @@ +cases = eth-nocache eth-icdc +common = ../support/libsupport.a ../support/except.o +drivers = ../drivers/libdrivers.a + +all: $(cases) + +eth-nocache: eth.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +eth-icdc: eth.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +eth.o: eth.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +include ../support/Makefile.inc

release-0.9/sw/eth/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/uart/uart.c =================================================================== --- release-0.9/sw/uart/uart.c (nonexistent) +++ release-0.9/sw/uart/uart.c (revision 42) @@ -0,0 +1,21 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" + +int main() +{ + uart_init(); + + int_init(); + int_add(UART_IRQ, &uart_interrupt); + + /* We can't use printf because in this simple example + we don't link C library. */ + uart_print_str("Hello World.\n\r"); + + report(0xdeaddead); + or32_exit(0); +}

release-0.9/sw/uart/uart.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/uart/Makefile =================================================================== --- release-0.9/sw/uart/Makefile (nonexistent) +++ release-0.9/sw/uart/Makefile (revision 42) @@ -0,0 +1,24 @@ +cases = uart-nocache uart-icdc +common = ../support/libsupport.a ../support/except.o +drivers = ../drivers/libdrivers.a + +all: $(cases) + +uart-nocache: uart.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +uart-icdc: uart.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +uart.o: uart.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +include ../support/Makefile.inc

release-0.9/sw/uart/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/Makefile =================================================================== --- release-0.9/sw/utils/Makefile (nonexistent) +++ release-0.9/sw/utils/Makefile (revision 42) @@ -0,0 +1,58 @@ +#*$$HEADER*# +#******************************************************************************# +#* *# +#* H E A D E R I N F O R M A T I O N *# +#* *# +#******************************************************************************# + +## Project Name : ORPSoC v2 +## File Name : Makefile +## Prepared By : +## Project Start : + +#*$$COPYRIGHT NOTICE*# +#******************************************************************************# +#* *# +#* C O P Y R I G H T N O T I C E *# +#* *# +#******************************************************************************# +#* +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; +# version 2.1 of the License, a copy of which is available from +# http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#*$$DESCRIPTION*# +#******************************************************************************# +#* *# +#* D E S C R I P T I O N *# +#* *# +#******************************************************************************# +## +## Makefile for the ORPSoC software utilities +## + +PROGRAMS = bin2c bin2srec bin2flimg bin2hex bin2vmem +# NB: 'loader' not in that list + +CC = gcc +CFLAGS = -O2 -Wall + +% : %.c + @/bin/rm -f $@ + $(CC) -o $@ $(CFLAGS) $< + +all: $(PROGRAMS) + +clean: + /bin/rm -f $(PROGRAMS) *~ *.bak

release-0.9/sw/utils/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/bin2vmem.c =================================================================== --- release-0.9/sw/utils/bin2vmem.c (nonexistent) +++ release-0.9/sw/utils/bin2vmem.c (revision 42) @@ -0,0 +1,159 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2vmem.c +// Prepared By : jb, jb@orsoc.se +// Project Start : 2009-05-13 + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates VMEM output to stdout from binary images. +// Use with redirection like: ./bin2vmem app.bin > app.vmem +// To change either the number of bytes per word or word per line, change +// the following defines. +// Currently output is WORD addressed, NOT byte addressed +// eg: @00000000 00000000 00000000 00000000 00000000 +// @00000004 00000000 00000000 00000000 00000000 +// @00000008 00000000 00000000 00000000 00000000 +// @0000000c 00000000 00000000 00000000 00000000 +// etc.. +// + +#define WORDS_PER_LINE 4 +#define BYTES_PER_WORD 4 + +#include +#include +#include + +int main(int argc, char **argv) +{ + + FILE *fd; + int c; + int i = 0; + int write_size_word=0; // Disabled by default + int filename_index=1; + unsigned int image_size; + + // Counters keeping track of what we've printed + int current_addr = 0; + int word_counter = 0; + int byte_counter = 0; + + if(argc < 2) { + fprintf(stderr,"\n\tInsufficient options.\n"); + fprintf(stderr,"\tPlease specify a binary file to convert to VMEM\n"); + fprintf(stderr,"\n\tbin2vmem - creates vmem output to stdout from bin\n"); + exit(1); + } + + fd = fopen( argv[filename_index], "r" ); + + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + if (write_size_word) + { + // or1200 startup method of determining size of boot image we're copying by reading out + // the very first word in flash is used. Determine the length of this file + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + // Now we should have the size of the file in bytes. Let's ensure it's a word multiple + image_size+=3; + image_size &= 0xfffffffc; + + // Sanity check on image size + if (image_size < 8){ + fprintf(stderr, "Bad binary image. Size too small\n"); + return 1; + } + + // Now write out the image size + printf("@%8x", current_addr); + printf("%8x", image_size); + current_addr += WORDS_PER_LINE * BYTES_PER_WORD; + } + else + { + } + + + // Fix for the current bootloader software! Skip the first 4 bytes of application data. Hopefully it's not important. 030509 -- jb + //for(i=0;i<4;i++) + // c=fgetc(fd); + i=0; + int starting_new_line = 1; + // Now write out the binary data to VMEM format: @ADDRESSS XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX + while ((c = fgetc(fd)) != EOF) { + if (starting_new_line) + { + // New line - print the current addr and then increment it + printf("@%.8x", current_addr); + //current_addr += WORDS_PER_LINE * BYTES_PER_WORD; + current_addr += WORDS_PER_LINE; + starting_new_line = 0; + } + if (byte_counter == 0) + printf(" "); + + printf("%.2x", (unsigned int) c); // now print the actual char + + byte_counter++; + + if (byte_counter == BYTES_PER_WORD) + { + word_counter++; + byte_counter=0; + } + if (word_counter == WORDS_PER_LINE) + { + printf("\n"); + word_counter = 0; + starting_new_line = 1; + } + } + + return 0; +}

release-0.9/sw/utils/bin2vmem.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/bin2hex.c =================================================================== --- release-0.9/sw/utils/bin2hex.c (nonexistent) +++ release-0.9/sw/utils/bin2hex.c (revision 42) @@ -0,0 +1,152 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2hex.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates basic ASCII hex output to stdout from binary file input +// Compile and run the program with no options for usage. +// + +#include +#include +#include +/* Number of bytes before line is broken + For example if target flash is 8 bits wide, + define BREAK as 1. If it is 16 bits wide, + define it as 2 etc. +*/ +#define BREAK 1 + +int main(int argc, char **argv) +{ + + FILE *fd; + int c; + int i = 0; + int write_size_word=0; // Disabled by default + int filename_index=1; + int bytes_per_line=1; + int bytes_per_line_index=2; + unsigned int image_size; + + if(argc < 3) { + fprintf(stderr,"\n\tInsufficient options.\n"); + fprintf(stderr,"\tPlease specify, in this order: a binary file to\n"); + fprintf(stderr,"\tconvert and the number of bytes of data to putput\n"); + fprintf(stderr,"\tper line.\n"); + fprintf(stderr,"\tOptionally specify the option -size_word to output,\n"); + fprintf(stderr,"\tthe size of the image in the first 4 bytes. This is\n"); + fprintf(stderr,"\tused by some of the new OR1k bootloaders.\n\n"); + exit(1); + } + + if(argc == 4) + { + if (strcmp("-size_word", argv[3]) == 0) + // We will calculate the number of bytes first + write_size_word=1; + } + + fd = fopen( argv[filename_index], "r" ); + + bytes_per_line = atoi(argv[bytes_per_line_index]); + + if ((bytes_per_line == 0) || (bytes_per_line > 8)) + { + fprintf(stderr,"bytes per line incorrect or missing: %s\n",argv[bytes_per_line_index]); + exit(1); + } + + // Now subtract 1 from bytes_per_line + //if (bytes_per_line == 2) + // bytes_per_line--; + + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + if (write_size_word) + { + // or1200 startup method of determining size of boot image we're copying by reading out + // the very first word in flash is used. Determine the length of this file + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + // Now we should have the size of the file in bytes. Let's ensure it's a word multiple + image_size+=3; + image_size &= 0xfffffffc; + + // Sanity check on image size + if (image_size < 8){ + fprintf(stderr, "Bad binary image. Size too small\n"); + return 1; + } + + // Now write out the image size + i=0; + printf("%.2x",(image_size >> 24) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size >> 16) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size >> 8) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + } + + // Fix for the current bootloader software! Skip the first 4 bytes of application data. Hopefully it's not important. 030509 -- jb + for(i=0;i<4;i++) + c=fgetc(fd); + + i=0; + + // Now write out the binary data to hex format + while ((c = fgetc(fd)) != EOF) { + printf("%.2x", (unsigned int) c); + if (++i == bytes_per_line) { + printf("\n"); + i = 0; + } + } + + return 0; +}

release-0.9/sw/utils/bin2hex.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/bin2srec.c =================================================================== --- release-0.9/sw/utils/bin2srec.c (nonexistent) +++ release-0.9/sw/utils/bin2srec.c (revision 42) @@ -0,0 +1,99 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2srec.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates SREC file output to stdout from binary file +// + +#include +#include + +#define SMARK "S214" +#define SADDR 0x000000 +#define INIT_ADDR 0x100100 +#define SCHKSUM 0xff + +int main(int argc, char **argv) +{ + + FILE *fd; + int c, j; + unsigned long addr = INIT_ADDR; + unsigned char chksum; + + if(argc < 2) { + fprintf(stderr,"no input file specified\n"); + exit(1); + } + if(argc > 2) { + fprintf(stderr,"too many input files (more than one) specified\n"); + exit(1); + } + + fd = fopen( argv[1], "r" ); + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + while (!feof(fd)) { + j = 0; + chksum = SCHKSUM; + printf("%s%.6lx", SMARK, addr); + while (j < 16) { + c = fgetc(fd); + if (c == EOF) { + c = 0; + } + printf("%.2x", c); + chksum -= c; + j++; + } + + chksum -= addr & 0xff; + chksum -= (addr >> 8) & 0xff; + chksum -= (addr >> 16) & 0xff; + chksum -= 0x14; + printf("%.2x\r\n", chksum); + addr += 16; + } + return 0; +}

release-0.9/sw/utils/bin2srec.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/bin2flimg.c =================================================================== --- release-0.9/sw/utils/bin2flimg.c (nonexistent) +++ release-0.9/sw/utils/bin2flimg.c (revision 42) @@ -0,0 +1,92 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2flimg.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generate flimg output to stdout from binary file input +// + +#include +#include + +int main(int argc, char **argv) +{ + + FILE *fd; + int c, j, width; + unsigned long word; + + if(argc < 3) { + fprintf(stderr,"no input file specified\n"); + exit(1); + } + if(argc > 3) { + fprintf(stderr,"too many input files (more than one) specified\n"); + exit(1); + } + + width = atoi(argv[1]); + + fd = fopen( argv[2], "r" ); + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + while (!feof(fd)) { + j = 0; + word = 0; + while (j < width) { + c = fgetc(fd); + if (c == EOF) { + c = 0; + } + word = (word << 8) + c; + j++; + } + if(width == 1) + printf("%.2lx\n", word); + else if(width == 2) + printf("%.4lx\n", word); + else + printf("%.8lx\n", word); + } + return 0; +}

release-0.9/sw/utils/bin2flimg.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/utils/bin2c.c =================================================================== --- release-0.9/sw/utils/bin2c.c (nonexistent) +++ release-0.9/sw/utils/bin2c.c (revision 42) @@ -0,0 +1,70 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2c.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generate C file containing binary data in hex format in an array +// + +#include + +int main(void) +{ + + int c, i = 0; + + printf("#ifdef HAVE_CONFIG_H\n"); + printf("# include \"config.h\"\n"); + printf("#endif\n\n"); + printf("#ifdef EMBED\n"); + + printf("unsigned char flash_data[] = {\n"); + + while((c = getchar()) != EOF) { + printf("0x%.2x, ", c); + if(!(i % 32)) + printf("\n"); + i++; + } + + printf(" };\n"); + printf("#endif\n"); + return(0); +}

release-0.9/sw/utils/bin2c.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/drivers/eth.c =================================================================== --- release-0.9/sw/drivers/eth.c (nonexistent) +++ release-0.9/sw/drivers/eth.c (revision 42) @@ -0,0 +1,102 @@ +#include "../support/board.h" +#include "../support/support.h" +#include "eth.h" + +int eth_tx_done; +int eth_rx_done; +int eth_rx_len; +unsigned char eth_tx_packet[1536]; //max length +unsigned char eth_rx_packet[1536]; +unsigned char * eth_tx_data; +unsigned char * eth_rx_data; + +void eth_recv_ack(void) +{ + eth_rx_done = 0; + eth_rx_len = 0; + //accept further data (reset RXBD to empty) + REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 +} + +void eth_init() +{ + //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1 + REG32(ETH_BASE + ETH_MODER) = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD; + //PHY Address = 0x001 + REG32(ETH_BASE + ETH_MIIADDRESS) = 0x00000001; + + //enable all interrupts + REG32(ETH_BASE + ETH_INT_MASK) = ETH_RXB | ETH_TXB; + + //set MAC ADDRESS + REG32(ETH_BASE + ETH_MAC_ADDR1) = (OWN_MAC_ADDRESS_5 << 8) | OWN_MAC_ADDRESS_4; //low word = mac address high word + REG32(ETH_BASE + ETH_MAC_ADDR0) = (OWN_MAC_ADDRESS_3 << 24) | (OWN_MAC_ADDRESS_2 << 16) + | (OWN_MAC_ADDRESS_1 << 8) | OWN_MAC_ADDRESS_0; //mac address rest + + //configure TXBD0 + REG32(ETH_BASE + ETH_TXBD0H) = (unsigned long)eth_tx_packet; //address used for tx_data + REG32(ETH_BASE + ETH_TXBD0L) = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1 + + //configure RXBD0 + REG32(ETH_BASE + ETH_RXBD0H) = (unsigned long)eth_rx_packet; //address used for tx_data + REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 + + //set txdata + eth_tx_packet[0] = BROADCAST_ADDRESS_5; + eth_tx_packet[1] = BROADCAST_ADDRESS_4; + eth_tx_packet[2] = BROADCAST_ADDRESS_3; + eth_tx_packet[3] = BROADCAST_ADDRESS_2; + eth_tx_packet[4] = BROADCAST_ADDRESS_1; + eth_tx_packet[5] = BROADCAST_ADDRESS_0; + + eth_tx_packet[6] = OWN_MAC_ADDRESS_5; + eth_tx_packet[7] = OWN_MAC_ADDRESS_4; + eth_tx_packet[8] = OWN_MAC_ADDRESS_3; + eth_tx_packet[9] = OWN_MAC_ADDRESS_2; + eth_tx_packet[10] = OWN_MAC_ADDRESS_1; + eth_tx_packet[11] = OWN_MAC_ADDRESS_0; + + //erase interrupts + REG32(ETH_BASE + ETH_INT_SOURCE) = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB; + + eth_tx_done = 1; + eth_rx_done = 0; + eth_rx_len = 0; + eth_tx_data = ð_tx_packet[HDR_LEN]; + eth_rx_data = ð_rx_packet[HDR_LEN]; +} + +int eth_send(int length) +{ + if (!eth_tx_done) //if previous command not fully processed, bail out + return -1; + + int i; + + eth_tx_done = 0; + eth_tx_packet[12] = length >> 8; + eth_tx_packet[13] = length; + + REG32(ETH_BASE + ETH_TXBD0L) = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND; + + return length; +} + +void eth_interrupt() +{ + unsigned long source = REG32(ETH_BASE + ETH_INT_SOURCE); + if ( source & ETH_TXB ) + { + eth_tx_done = 1; + //erase interrupt + REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_TXB; + } + if ( source & ETH_RXB ) + { + eth_rx_done = 1; + eth_rx_len = (REG32(ETH_BASE + ETH_RXBD0L) >> 16) - HDR_LEN - CRC_LEN; + //erase interrupt + REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_RXB; + } +} + Index: release-0.9/sw/drivers/tick.h =================================================================== --- release-0.9/sw/drivers/tick.h (nonexistent) +++ release-0.9/sw/drivers/tick.h (revision 42) @@ -0,0 +1,4 @@ + +void tick_init(void); + +void tick_ack(void); Index: release-0.9/sw/drivers/interrupts.c =================================================================== --- release-0.9/sw/drivers/interrupts.c (nonexistent) +++ release-0.9/sw/drivers/interrupts.c (revision 42) @@ -0,0 +1,15 @@ + +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void align_except(){} +void illegal_except(){} +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + Index: release-0.9/sw/drivers/uart.h =================================================================== --- release-0.9/sw/drivers/uart.h (nonexistent) +++ release-0.9/sw/drivers/uart.h (revision 42) @@ -0,0 +1,9 @@ + +#include "../support/uart.h" + +void uart_print_str(char *); +void uart_print_long(unsigned long); + +void uart_interrupt(); +void uart_print_short(unsigned long ul); + Index: release-0.9/sw/drivers/can.c =================================================================== --- release-0.9/sw/drivers/can.c (nonexistent) +++ release-0.9/sw/drivers/can.c (revision 42) @@ -0,0 +1,150 @@ +#include "../support/board.h" +#include "../support/support.h" +#include "can.h" + +int can_rx_done, can_tx_done; + +int can_rx_rd_ptr; +int can_rx_wr_ptr; +int can_rx_buf_overflow; + +can_type can_rx_data[CAN_BUF_LEN], can_tx_data; + +can_type * can_get(void) +{ + if ( !can_rx_done ) + return NULL; + + can_rx_done--; + + int tmp; + tmp = can_rx_rd_ptr; + + if (can_rx_rd_ptr < CAN_BUF_LEN-1) + can_rx_rd_ptr++; + else + can_rx_rd_ptr = 0; + + return &can_rx_data[tmp]; +} + +void can_init(void) +{ + unsigned char sync_jmp, baudrate_presc, timing_seg1, timing_seg2, tripple_samp = 0; + unsigned char acpt_code, acpt_mask = 0; + unsigned char clk_div = 0 & CAN_BUS_CLKDIV_MASK; + + sync_jmp = 1; + baudrate_presc = 1; + timing_seg1 = 11; + timing_seg2 = 2; + tripple_samp = 1; + + acpt_code = 0x81; + acpt_mask = 0xFF; + + char timing0, timing1 = 0; + + timing0 = (sync_jmp << CAN_BUS_TIMING_0_SYNC_JMP_SHIFT) & CAN_BUS_TIMING_0_SYNC_JMP; + timing0 |= baudrate_presc & CAN_BUS_TIMING_0_BAUD_PRESC; + + timing1 = (tripple_samp << CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT) & CAN_BUS_TIMING_1_TRIPLE_SAMP; + timing1 |= (timing_seg2 << CAN_BUS_TIMING_1_TIME_SEG2_SHIFT) & CAN_BUS_TIMING_1_TIME_SEG2; + timing1 |= timing_seg1 & CAN_BUS_TIMING_1_TIME_SEG1; + + REG8(CAN_BASE+CAN_MODE) = CAN_MODE_RESET; + + REG8(CAN_BASE+CAN_BUS_TIMING_0) = timing0; + REG8(CAN_BASE+CAN_BUS_TIMING_1) = timing1; + + REG8(CAN_BASE+CAN_ACPT_CODE0) = acpt_code; + REG8(CAN_BASE+CAN_ACPT_MASK0) = acpt_mask; + + REG8(CAN_BASE+CAN_BUS_MODE) &= ~CAN_BUS_MODE_CLOCK_OFF & ~CAN_BUS_MODE_EXTENDED_MODE; + + REG8(CAN_BASE+CAN_MODE) &= ~CAN_MODE_RESET; + REG8(CAN_BASE+CAN_BUS_CLKDIV) = clk_div; + + REG8(CAN_BASE+CAN_MODE) |= CAN_MODE_TX_IRQ_EN | CAN_MODE_RECV_IRQ_EN; + + can_tx_done = 1; + can_rx_done = 0; + can_rx_rd_ptr = 0; + can_rx_wr_ptr = 0; + can_rx_buf_overflow = 0; +} + +void can_recv_basic() +{ + unsigned char byte0, byte1; + + byte0 = REG8(CAN_BASE+CAN_RX_BUF); + byte1 = REG8(CAN_BASE+CAN_RX_BUF+1); + + can_rx_data[can_rx_wr_ptr].data[0] = REG8(CAN_BASE+CAN_RX_BUF+2); + can_rx_data[can_rx_wr_ptr].data[1] = REG8(CAN_BASE+CAN_RX_BUF+3); + can_rx_data[can_rx_wr_ptr].data[2] = REG8(CAN_BASE+CAN_RX_BUF+4); + can_rx_data[can_rx_wr_ptr].data[3] = REG8(CAN_BASE+CAN_RX_BUF+5); + can_rx_data[can_rx_wr_ptr].data[4] = REG8(CAN_BASE+CAN_RX_BUF+6); + can_rx_data[can_rx_wr_ptr].data[5] = REG8(CAN_BASE+CAN_RX_BUF+7); + can_rx_data[can_rx_wr_ptr].data[6] = REG8(CAN_BASE+CAN_RX_BUF+8); + can_rx_data[can_rx_wr_ptr].data[7] = REG8(CAN_BASE+CAN_RX_BUF+9); + + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_RELEASE_BUFFER; + + can_rx_data[can_rx_wr_ptr].identifier = (byte0 << 3) | (byte1 >> 5); + can_rx_data[can_rx_wr_ptr].rtr = byte1 & 0x10; + can_rx_data[can_rx_wr_ptr].len = byte1 & 0x0F; + + if (can_rx_wr_ptr < CAN_BUF_LEN-1) + can_rx_wr_ptr++; + else + can_rx_wr_ptr = 0; + + if (can_rx_wr_ptr == can_rx_rd_ptr+1) //buffer overflow + { + can_rx_done = 1; + can_rx_buf_overflow++; + } + else + can_rx_done++; +} + +int can_send_basic() +{ + if (!can_tx_done) //if previous command not fully processed, bail out + return -1; + + can_tx_done = 0; + REG8(CAN_BASE+CAN_TX_BUF) = can_tx_data.identifier >> 3; + REG8(CAN_BASE+CAN_TX_BUF+1) = (can_tx_data.identifier << 5) | ((can_tx_data.rtr << 4) & 0x10) | (can_tx_data.len & 0x0F); + + REG8(CAN_BASE+CAN_TX_BUF+2) = can_tx_data.data[0]; + REG8(CAN_BASE+CAN_TX_BUF+3) = can_tx_data.data[1]; + REG8(CAN_BASE+CAN_TX_BUF+4) = can_tx_data.data[2]; + REG8(CAN_BASE+CAN_TX_BUF+5) = can_tx_data.data[3]; + REG8(CAN_BASE+CAN_TX_BUF+6) = can_tx_data.data[4]; + REG8(CAN_BASE+CAN_TX_BUF+7) = can_tx_data.data[5]; + REG8(CAN_BASE+CAN_TX_BUF+8) = can_tx_data.data[6]; + REG8(CAN_BASE+CAN_TX_BUF+9) = can_tx_data.data[7]; + + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_TX_REQ; + + return can_tx_data.len; +} + +void can_irq(void) +{ + unsigned char irq_req, rx_done; + irq_req = REG8(CAN_BASE+IRQ_READ); + rx_done = irq_req & CAN_IRQ_READ_RX; + can_tx_done = irq_req & CAN_IRQ_READ_TX; + if (rx_done) + can_recv_basic(); +} + +void can_abort(void) +{ + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_ABORT_TX; +} + Index: release-0.9/sw/drivers/i2c.h =================================================================== --- release-0.9/sw/drivers/i2c.h (nonexistent) +++ release-0.9/sw/drivers/i2c.h (revision 42) @@ -0,0 +1,62 @@ + +struct i2c_type +{ + unsigned char address; + unsigned char pointer; + unsigned short data; +}; + +struct i2c_mode +{ + unsigned char read_write; + unsigned char byte_word; + unsigned char ptr_set; +}; + +typedef struct i2c_type i2c_type; +typedef struct i2c_mode i2c_mode; + +#define I2C_BUF_LEN 10 + +void i2c_init(void); +void i2c_irq(void); + +i2c_type * i2c_get(void); //return pointer to first non read received data + +void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl); +int i2c_trans(i2c_mode * mode, i2c_type * data); //return (-1) or length (still processing previous) or asserted + +#define I2C_PRESC_LO 0x00 +#define I2C_PRESC_HI 0x01 + +#define I2C_CTR 0x02 + +#define I2C_TXR 0x03 +#define I2C_RXR 0x03 + +#define I2C_CR 0x04 +#define I2C_SR 0x04 + + +//BITS +#define I2C_CTR_EN 0x80 +#define I2C_CTR_IRQ_EN 0x40 + +#define I2C_TXR_ADR 0xFE +#define I2C_TXR_W 0x00 +#define I2C_TXR_R 0x01 + +#define I2C_CR_STA 0x80 +#define I2C_CR_STO 0x40 +#define I2C_CR_RD 0x20 +#define I2C_CR_WR 0x10 +#define I2C_CR_ACK 0x00 +#define I2C_CR_NACK 0x08 +#define I2C_CR_CLR_IRQ 0x01 + +#define I2C_SR_R_ACK 0x80 +#define I2C_SR_BUSY 0x40 +#define I2C_SR_ARB_LOST 0x20 +#define I2C_SR_TX_BUSY 0x02 +#define I2C_SR_IRQ_FLAG 0x01 + Index: release-0.9/sw/drivers/eth.h =================================================================== --- release-0.9/sw/drivers/eth.h (nonexistent) +++ release-0.9/sw/drivers/eth.h (revision 42) @@ -0,0 +1,111 @@ + +void eth_init(); +void eth_interrupt(); +void eth_recv_ack(void); + +int eth_send(int length); //return (-1) or length (still processing previous) or asserted + +#define ETH_MODER 0x00 +#define ETH_INT_SOURCE 0x04 +#define ETH_INT_MASK 0x08 +#define ETH_IPGT 0x0C +#define ETH_IPGR1 0x10 +#define ETH_IPGR2 0x14 +#define ETH_PACKETLEN 0x18 +#define ETH_COLLCONF 0x1C +#define ETH_TX_BD_NUM 0x20 +#define ETH_CTRLMODER 0x24 +#define ETH_MIIMODER 0x28 +#define ETH_MIICOMMAND 0x2C +#define ETH_MIIADDRESS 0x30 +#define ETH_MIITX_DATA 0x34 +#define ETH_MIIRX_DATA 0x38 +#define ETH_MIISTATUS 0x3C +#define ETH_MAC_ADDR0 0x40 +#define ETH_MAC_ADDR1 0x44 +#define ETH_HASH0_ADR 0x48 +#define ETH_HASH1_ADR 0x4C +#define ETH_TXCTRL 0x50 + +#define ETH_TXBD0H 0x404 +#define ETH_TXBD0L 0x400 + +#define ETH_RXBD0H 0x604 //this depends on TX_BD_NUM but this is the standard value +#define ETH_RXBD0L 0x600 //this depends on TX_BD_NUM but this is the standard value + +//MODER BITS +#define ETH_RECSMALL 0x00010000 +#define ETH_PAD 0x00008000 +#define ETH_HUGEN 0x00004000 +#define ETH_CRCEN 0x00002000 +#define ETH_DLYCRCEN 0x00001000 +#define ETH_FULLD 0x00000400 +#define ETH_EXDFREN 0x00000200 +#define ETH_NOBCKOF 0x00000100 +#define ETH_LOOPBCK 0x00000080 +#define ETH_IFG 0x00000040 +#define ETH_PRO 0x00000020 +#define ETH_IAM 0x00000010 +#define ETH_BRO 0x00000008 +#define ETH_NOPRE 0x00000004 +#define ETH_TXEN 0x00000002 +#define ETH_RXEN 0x00000001 + +//INTERRUPTS BITS +#define ETH_RXC 0x00000040 +#define ETH_TXC 0x00000020 +#define ETH_BUSY 0x00000010 +#define ETH_RXE 0x00000008 +#define ETH_RXB 0x00000004 +#define ETH_TXE 0x00000002 +#define ETH_TXB 0x00000001 + +//BUFFER DESCRIPTOR BITS +#define ETH_RXBD_EMPTY 0x00008000 +#define ETH_RXBD_IRQ 0x00004000 +#define ETH_RXBD_WRAP 0x00002000 +#define ETH_RXBD_CF 0x00000100 +#define ETH_RXBD_MISS 0x00000080 +#define ETH_RXBD_OR 0x00000040 +#define ETH_RXBD_IS 0x00000020 +#define ETH_RXBD_DN 0x00000010 +#define ETH_RXBD_TL 0x00000008 +#define ETH_RXBD_SF 0x00000004 +#define ETH_RXBD_CRC 0x00000002 +#define ETH_RXBD_LC 0x00000001 + +#define ETH_TXBD_READY 0x00008000 +#define ETH_TXBD_IRQ 0x00004000 +#define ETH_TXBD_WRAP 0x00002000 +#define ETH_TXBD_PAD 0x00001000 +#define ETH_TXBD_CRC 0x00000800 +#define ETH_TXBD_UR 0x00000100 +#define ETH_TXBD_RL 0x00000008 +#define ETH_TXBD_LC 0x00000004 +#define ETH_TXBD_DF 0x00000002 +#define ETH_TXBD_CS 0x00000001 + +//user defines +#define OWN_MAC_ADDRESS_5 0x55 +#define OWN_MAC_ADDRESS_4 0x47 +#define OWN_MAC_ADDRESS_3 0x34 +#define OWN_MAC_ADDRESS_2 0x22 +#define OWN_MAC_ADDRESS_1 0x88 +#define OWN_MAC_ADDRESS_0 0x92 + +#define BROADCAST_ADDRESS_5 0xFF +#define BROADCAST_ADDRESS_4 0xFF +#define BROADCAST_ADDRESS_3 0xFF +#define BROADCAST_ADDRESS_2 0xFF +#define BROADCAST_ADDRESS_1 0xFF +#define BROADCAST_ADDRESS_0 0xFF + +#define HDR_LEN 14 +#define CRC_LEN 4 +#define BD_SND ( ETH_TXBD_READY | ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) +#define RX_READY ( ETH_RXBD_EMPTY | ETH_RXBD_IRQ | ETH_RXBD_WRAP ) +#define TX_READY ( ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) + +//~user defines + + Index: release-0.9/sw/drivers/can.h =================================================================== --- release-0.9/sw/drivers/can.h (nonexistent) +++ release-0.9/sw/drivers/can.h (revision 42) @@ -0,0 +1,158 @@ + +struct can_type +{ + unsigned char rtr; + unsigned char len; + unsigned short identifier; + unsigned char data[8]; +}; + +typedef struct can_type can_type; + +#define CAN_BUF_LEN 10 + +void can_init(void); +void can_irq(void); + +can_type * can_get(void); //return pointer to first non read received data + +int can_send_basic(); //return (-1) or length (still processing previous) or asserted +void can_abort(void); + +//BOTH MODES +#define CAN_MODE 0x00 +#define CAN_CMD 0x01 +#define CAN_STATUS 0x02 +#define IRQ_READ 0x03 + +#define CAN_ACPT_CODE0 0x04 //only writable while in reset mode +#define CAN_ACPT_MASK0 0x05 //only writable while in reset mode + +#define CAN_BUS_TIMING_0 0x06 //only writable while in reset mode +#define CAN_BUS_TIMING_1 0x07 //only writable while in reset mode + +#define CAN_BUS_CLKDIV 0x1F //only writable while NOT in reset mode + +#define CAN_TX_BUF 0x0A //only accessable while NOT in reset mode +#define CAN_TX_LEN 10 + +#define CAN_RX_BUF 0x14 //free read access for basic mode +#define CAN_RX_LEN 10 + +//only accessable while in reset mode +#define CAN_BUS_MODE 0x1F + + +//EXTENDED MODE ONLY +//only for extended mode & only accessable while in reset mode +#define CAN_IRQ_EN_EXT 0x04 //also writable if NOT in reset mode + +//read only regs +#define CAN_ARBIT_LOSS_CNT 0x0B //cnt of arbitration loss +#define CAN_ERROR_CAPTURE_CODE 0x0C +#define CAN_RX_MSG_CNT 0x1D +//~read only regs + +#define CAN_ERROR_WARN_LIMIT 0x0D + +#define CAN_RX_ERR_CNT 0x0E +#define CAN_TX_ERR_CNT 0x0F + +#define CAN_ACPT_CODE0_EXT 0x10 //also writable if NOT in reset mode +#define CAN_ACPT_CODE1 0x11 +#define CAN_ACPT_CODE2 0x12 +#define CAN_ACPT_CODE3 0x13 + +#define CAN_ACPT_MASK0_EXT 0x14 //also writable if NOT in reset mode +#define CAN_ACPT_MASK1 0x15 +#define CAN_ACPT_MASK2 0x16 +#define CAN_ACPT_MASK3 0x17 + +#define CAN_TX_BUF_EXT 0x10 //accessable if transmit_buffer_status=1 +#define CAN_TX_LEN_EXT 13 //ignores reset mode + +#define CAN_RX_BUF_EXT 0x10 //read access only in NOT reset mode +#define CAN_RX_LEN_EXT 13 + + +//BITS DEFINITIONS + +//BASIC MODE +#define CAN_MODE_RESET 0x01 +#define CAN_MODE_LISTEN_ONLY_BASIC 0x20 +#define CAN_MODE_RECV_IRQ_EN 0x02 +#define CAN_MODE_TX_IRQ_EN 0x04 +#define CAN_MODE_ERROR_IRQ_EN 0x08 +#define CAN_MODE_OVERRUN_IRQ_EN 0x10 +//EXTENDED MODE +#define CAN_MODE_LISTEN_ONLY_EXT 0x02 +#define CAN_MODE_SELF_TEST_MODE 0x04 +#define CAN_MODE_ACPT_FILTER_MODE 0x08 + +//CMD +#define CAN_CMD_CLR_DATA_OVERRUN 0x08 +#define CAN_CMD_RELEASE_BUFFER 0x04 +#define CAN_CMD_TX_REQ 0x11 +#define CAN_CMD_ABORT_TX 0x02 + +//STATUS +#define CAN_STATUS_NODE_BUS_OFF 0x80 +#define CAN_STATUS_ERROR 0x40 +#define CAN_STATUS_TX 0x20 +#define CAN_STATUS_RX 0x10 +#define CAN_STATUS_TX_COMPLETE 0x08 +#define CAN_STATUS_TX_BUF 0x04 +#define CAN_STATUS_OVERRUN 0x02 +#define CAN_STATUS_RX_BUF 0x01 + +//IRQ READ +#define CAN_IRQ_READ_BUS_ERROR 0x80 +#define CAN_IRQ_READ_ARBIT_LOST 0x40 +#define CAN_IRQ_READ_ERROR_PASSIV 0x20 +#define CAN_IRQ_READ_OVERRUN 0x08 +#define CAN_IRQ_READ_ERROR 0x04 +#define CAN_IRQ_READ_TX 0x02 +#define CAN_IRQ_READ_RX 0x01 + +//BUS_TIMING_0 +#define CAN_BUS_TIMING_0_SYNC_JMP_SHIFT 6 +#define CAN_BUS_TIMING_0_SYNC_JMP 0xC0 +#define CAN_BUS_TIMING_0_BAUD_PRESC 0x3F + +//BUS_TIMING_1 +#define CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT 7 +#define CAN_BUS_TIMING_1_TRIPLE_SAMP 0x80 +#define CAN_BUS_TIMING_1_TIME_SEG2_SHIFT 4 +#define CAN_BUS_TIMING_1_TIME_SEG2 0x70 +#define CAN_BUS_TIMING_1_TIME_SEG1 0x0F + +//CLKDIV +//only writable while NOT in reset mode +#define CAN_BUS_CLKDIV_MASK 0x07 + + +//EXTENDED MODE ONLY +//CLKMODE +//only writable while in reset mode +#define CAN_BUS_MODE_CLOCK_OFF 0x08 +#define CAN_BUS_MODE_EXTENDED_MODE 0x80 + +//EXTENDED MODE IRQ +#define CAN_IRQ_EN_EXT_BUS_ERROR 0x80 +#define CAN_IRQ_EN_EXT_ARBIT_LOST 0x40 +#define CAN_IRQ_EN_EXT_ERROR_PASSIV 0x20 +#define CAN_IRQ_EN_EXT_OVERRUN 0x08 +#define CAN_IRQ_EN_EXT_ERROR 0x04 +#define CAN_IRQ_EN_EXT_TX 0x02 +#define CAN_IRQ_EN_EXT_RX 0x01 + +//EXTENDED ERROR CODES +#define CAN_ERROR_CAPTURE_CODE_TYPE_SHIFT 6 +#define CAN_ERROR_CAPTURE_CODE_TYPE 0xC0 +#define CAN_ERROR_CAPTURE_CODE_TYPE_BIT 0x0 +#define CAN_ERROR_CAPTURE_CODE_TYPE_FORM 0x1 +#define CAN_ERROR_CAPTURE_CODE_TYPE_STUFF 0x2 +#define CAN_ERROR_CAPTURE_CODE_TYPE_OTHER 0x3 +#define CAN_ERROR_CAPTURE_CODE_DIR 0x40 //1 = TX | 0 = RX +#define CAN_ERROR_CAPTURE_CODE_SEG 0x1F + Index: release-0.9/sw/drivers/tick.c =================================================================== --- release-0.9/sw/drivers/tick.c (nonexistent) +++ release-0.9/sw/drivers/tick.c (revision 42) @@ -0,0 +1,31 @@ +#include "../support/spr_defs.h" +#include "../support/support.h" +#include "tick.h" + +int tick_int; + +void tick_ack(void) +{ + tick_int--; +} + +void tick_init(void) +{ + mtspr(SPR_TTMR, 25000000 & SPR_TTMR_PERIOD); //1s +// mtspr(SPR_TTMR, 125000 & SPR_TTMR_PERIOD); //5ms + + mtspr(SPR_TTMR, mfspr(SPR_TTMR) | SPR_TTMR_RT | SPR_TTMR_IE); //restart after match, enable interrupt + mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt + + //set OR1200 to accept exceptions + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE); + + tick_int = 0; +} + +void tick_except(void) +{ + tick_int++; + mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt +} + Index: release-0.9/sw/drivers/uart.c =================================================================== --- release-0.9/sw/drivers/uart.c (nonexistent) +++ release-0.9/sw/drivers/uart.c (revision 42) @@ -0,0 +1,68 @@ +#include "../support/board.h" +#include "../support/support.h" +#include "../support/uart.h" +#include "uart.h" + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } + +} + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} + Index: release-0.9/sw/drivers/Makefile =================================================================== --- release-0.9/sw/drivers/Makefile (nonexistent) +++ release-0.9/sw/drivers/Makefile (revision 42) @@ -0,0 +1,25 @@ +all: libdrivers.a + +libdrivers.a: eth.o uart.o interrupts.o can.o i2c.o tick.o + $(OR32_TOOL_PREFIX)-ar cru libdrivers.a eth.o uart.o interrupts.o can.o i2c.o tick.o + $(OR32_TOOL_PREFIX)-ranlib libdrivers.a + +eth.o: eth.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +uart.o: uart.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +interrupts.o: interrupts.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +can.o: can.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +i2c.o: i2c.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +tick.o: tick.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +include ../support/Makefile.inc Index: release-0.9/sw/drivers/i2c.c =================================================================== --- release-0.9/sw/drivers/i2c.c (nonexistent) +++ release-0.9/sw/drivers/i2c.c (revision 42) @@ -0,0 +1,166 @@ +#include "../support/board.h" +#include "../support/support.h" +#include "i2c.h" + +int i2c_rd_done, i2c_wr_done; + +int i2c_pending_write; + +int i2c_rd_ptr, i2c_wr_ptr; + +int i2c_buf_overflow; +i2c_type i2c_data[I2C_BUF_LEN]; + +unsigned char start, pointer_write, write_hbyte, write_lbyte, read_hbyte, read_lbyte; +unsigned char cmd_list[5]; +unsigned char dat_list[5]; +int i2c_index; +int i2c_end; + +i2c_type * i2c_get(void) +{ + if ( !i2c_rd_done ) + return NULL; + + i2c_rd_done--; + + int tmp; + tmp = i2c_rd_ptr; + + if (i2c_rd_ptr < I2C_BUF_LEN-1) + i2c_rd_ptr++; + else + i2c_rd_ptr = 0; + + return &i2c_data[tmp]; +} + +void i2c_init(void) +{ + REG8(I2C_BASE+I2C_PRESC_HI) = 0x00; + REG8(I2C_BASE+I2C_PRESC_LO) = 49; //100kHz + REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN | I2C_CTR_IRQ_EN; + i2c_rd_done = 0; + i2c_wr_done = 0; + i2c_index = 0; + i2c_wr_ptr = 0; + i2c_rd_ptr = 0; + i2c_buf_overflow = 0; +} + +void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl) +{ + int ack, final_ack; + + ack = ( ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK; + final_ack = ( final_ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK; + + start = I2C_CR_STA | I2C_CR_WR | ack; + pointer_write = I2C_CR_WR | ack; + write_hbyte = I2C_CR_WR | ack; + write_lbyte = I2C_CR_WR | I2C_CR_STO | final_ack; + read_hbyte = I2C_CR_RD | ack; + read_lbyte = I2C_CR_RD | I2C_CR_STO | final_ack; +} + +void i2c_byte_transfer(void) +{ + if ( i2c_index > 0 ) + if ( cmd_list[i2c_index-1] == read_hbyte ) + i2c_data[i2c_wr_ptr].data = (REG8(I2C_BASE+I2C_RXR) << 8) & 0xFF00; + + REG8(I2C_BASE+I2C_TXR) = dat_list[i2c_index]; + REG8(I2C_BASE+I2C_CR) = cmd_list[i2c_index]; + + i2c_index++; +} + +void i2c_irq(void) +{ + REG8(I2C_BASE+I2C_CR) = I2C_CR_CLR_IRQ; + if (i2c_index <= i2c_end ) + i2c_byte_transfer(); + else + { + if ( cmd_list[i2c_index-1] == read_lbyte ) + i2c_data[i2c_wr_ptr].data |= REG8(I2C_BASE+I2C_RXR); + + i2c_index = 0; + + if ( i2c_pending_write ) + i2c_wr_done = 1; + else + { + if (i2c_wr_ptr < I2C_BUF_LEN-1) + i2c_wr_ptr++; + else + i2c_wr_ptr = 0; + + if (i2c_wr_ptr == i2c_rd_ptr+1) + { + i2c_rd_done = 1; + i2c_buf_overflow++; + } + else + i2c_rd_done++; + } + } +} + +int i2c_trans(i2c_mode * mode, i2c_type * data) +{ + if ( i2c_index != 0 ) //if previous command not fully processed, bail out + return -1; + + i2c_wr_done = 0; + + int i = 0; + + if ( mode->ptr_set || mode->read_write ) //start conditions with pointer set: (write always set ptr) + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_W; + cmd_list[i++] = start; + + dat_list[i] = data->pointer; + cmd_list[i++] = pointer_write; + + if ( !mode->read_write ) //REstart for read, NO-REstart for write + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_R; + cmd_list[i++] = start; + } + } + else //start conditions with NO pointer set (read only): ONE start + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_R; + cmd_list[i++] = start; + } + + if ( mode->byte_word ) //read/write high byte + { + dat_list[i] = data->data >> 8; + cmd_list[i++] = (mode->read_write) ? write_hbyte : read_hbyte; + } + + dat_list[i] = data->data; //read/write low byte + cmd_list[i] = (mode->read_write) ? write_lbyte : read_lbyte; + + i2c_end = i; + + if ( !mode->read_write ) //set data to 0 for read, avoid or implications ((short)data |= byte) + { + i2c_data[i2c_wr_ptr] = *data; + i2c_data[i2c_wr_ptr].data = 0x0000; + } + + i2c_pending_write = mode->read_write; + + i2c_index = 0; + i2c_byte_transfer(); + + return mode->read_write+1; +} + Index: release-0.9/sw/support/Makefile.inc =================================================================== --- release-0.9/sw/support/Makefile.inc (nonexistent) +++ release-0.9/sw/support/Makefile.inc (revision 42) @@ -0,0 +1,20 @@ +# File to be included in all makefiles + +OR32_TOOL_PREFIX=or32-elf + +#GCC_LIB_OPTS= -lgcc -liberty + +GCC_OPT=-mhard-mul -g -nostdlib + +ifdef UART_PRINTF +GCC_OPT += -DUART_PRINTF +endif + +FLASH_MEM_HEX_FILE_SUFFIX=-twobyte-sizefirst +SRAM_MEM_HEX_FILE_SUFFIX=-fourbyte + + +# Global clean rule +clean: + @echo "Cleaning `pwd`" + @rm -f *.o *.or32 *.log *.bin *.srec *.hex *.log stdout.txt *.vmem *.asm *.a stdout.txt

release-0.9/sw/support/Makefile.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/except.S =================================================================== --- release-0.9/sw/support/except.S (nonexistent) +++ release-0.9/sw/support/except.S (revision 42) @@ -0,0 +1,276 @@ +#include "spr_defs.h" + +// Linked from 0x200, so subtract 0x200 from each .org +.section .vectors, "ax" + +/* +.org 0x100 + +_reset: + l.nop + l.j _reset_except + l.nop +*/ +.org 0x000 + +_except_200: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _buserr_except + l.nop + +.org 0x100 + +_except_300: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _dpf_except + l.nop + +.org 0x200 + +_except_400: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _ipf_except + l.nop + +.org 0x300 + +_except_500: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _tick_except + l.nop + +.org 0x400 + +_except_600: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _align_except + l.nop + +.org 0x500 + +_except_700: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _illegal_except + l.nop + +.org 0x600 + +_except_800: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _ext_except //jmp to C interrupt handler (returns later to end_except) + l.nop + + +.org 0x700 + +_except_900: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _dtlbmiss_except + l.nop + +.org 0x800 + +_except_a00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _itlbmiss_except + l.nop + +.org 0x900 + +_except_b00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _range_except + l.nop + +.org 0xa00 + +_except_c00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _syscall_except + l.nop + +.org 0xb00 + +_except_d00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _res1_except + l.nop + +.org 0xc00 + +_except_e00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _trap_except + l.nop + +.org 0xd00 + +_except_f00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j _res2_except + l.nop + +store_regs: //save registers r3-r31 (except r9) to stack + l.sw 0x00(r1),r3 + l.sw 0x04(r1),r4 + l.sw 0x08(r1),r5 + l.sw 0x0c(r1),r6 + l.sw 0x10(r1),r7 + l.sw 0x14(r1),r8 + l.sw 0x1c(r1),r10 + l.sw 0x20(r1),r11 + l.sw 0x24(r1),r12 + l.sw 0x28(r1),r13 + l.sw 0x2c(r1),r14 + l.sw 0x30(r1),r15 + l.sw 0x34(r1),r16 + l.sw 0x38(r1),r17 + l.sw 0x3c(r1),r18 + l.sw 0x40(r1),r19 + l.sw 0x44(r1),r20 + l.sw 0x48(r1),r21 + l.sw 0x4c(r1),r22 + l.sw 0x50(r1),r23 + l.sw 0x54(r1),r24 + l.sw 0x58(r1),r25 + l.sw 0x5c(r1),r26 + l.sw 0x60(r1),r27 + l.sw 0x64(r1),r28 + l.sw 0x68(r1),r29 + l.sw 0x6c(r1),r30 + l.sw 0x70(r1),r31 + l.jr r9 + l.nop + +end_except: //load back registers from stack r3-r31 + l.lwz r3,0x00(r1) + l.lwz r4,0x04(r1) + l.lwz r5,0x08(r1) + l.lwz r6,0x0c(r1) + l.lwz r7,0x10(r1) + l.lwz r8,0x14(r1) + l.lwz r9,0x18(r1) + l.lwz r10,0x1c(r1) + l.lwz r11,0x20(r1) + l.lwz r12,0x24(r1) + l.lwz r13,0x28(r1) + l.lwz r14,0x2c(r1) + l.lwz r15,0x30(r1) + l.lwz r16,0x34(r1) + l.lwz r17,0x38(r1) + l.lwz r18,0x3c(r1) + l.lwz r19,0x40(r1) + l.lwz r20,0x44(r1) + l.lwz r21,0x48(r1) + l.lwz r22,0x4c(r1) + l.lwz r23,0x50(r1) + l.lwz r24,0x54(r1) + l.lwz r25,0x58(r1) + l.lwz r26,0x5c(r1) + l.lwz r27,0x60(r1) + l.lwz r28,0x64(r1) + l.lwz r29,0x68(r1) + l.lwz r30,0x6c(r1) + l.lwz r31,0x70(r1) + l.addi r1,r1,116 //free stack places + l.rfe //recover SR register and prior PC (jumps back to program) + l.nop +

release-0.9/sw/support/except.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/uart.c =================================================================== --- release-0.9/sw/support/uart.c (nonexistent) +++ release-0.9/sw/support/uart.c (revision 42) @@ -0,0 +1,77 @@ +#include "support.h" +#include "board.h" +#include "uart.h" + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +#define WAIT_FOR_XMITR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY) + +#define WAIT_FOR_THRE \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE) + +#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR) + +#define WAIT_FOR_CHAR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_DR) != UART_LSR_DR) + +#define UART_TX_BUFF_LEN 32 +#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1) + +char tx_buff[UART_TX_BUFF_LEN]; +volatile int tx_level, rx_level; + +void uart_init(void) +{ + int divisor; + + /* Reset receiver and transmiter */ + /* Set RX interrupt for each byte */ + REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1; + + /* Enable RX interrupt */ + REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI; + + /* Set 8 bit char, 1 stop bit, no parity */ + REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY); + + /* Set baud rate */ + divisor = IN_CLK/(16 * UART_BAUD_RATE); + REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB; + REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff; + REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff; + REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB); + + return; +} + +void uart_putc(char c) +{ + unsigned char lsr; + + WAIT_FOR_THRE; + REG8(UART_BASE + UART_TX) = c; + if(c == '\n') { + WAIT_FOR_THRE; + REG8(UART_BASE + UART_TX) = '\r'; + } + WAIT_FOR_XMITR; +} + + + +char uart_getc() +{ + unsigned char lsr; + char c; + +// WAIT_FOR_CHAR; + c = REG8(UART_BASE + UART_RX); + return c; +}

release-0.9/sw/support/uart.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/support.c =================================================================== --- release-0.9/sw/support/support.c (nonexistent) +++ release-0.9/sw/support/support.c (revision 42) @@ -0,0 +1,167 @@ +/* Support */ + +#ifndef OR32 +#include +#endif + +#include "spr_defs.h" +#include "support.h" +#include "int.h" + +#ifdef UART_PRINTF +//#include "snprintf.h" +#include "vfnprintf.h" +#include "uart.h" +#endif + +#if OR32 +void int_main(); + +void ext_except() +{ + int_main(); +} + +/* Start function, called by reset exception handler. */ +void reset () +{ + int i = main(); + or32_exit (i); +} + +/* return value by making a syscall */ +void or32_exit (int i) +{ + asm("l.add r3,r0,%0": : "r" (i)); + asm("l.nop %0": :"K" (NOP_EXIT)); + while (1); +} + +#ifdef UART_PRINTF + +static int uart_init_done = 0; + +#define PRINTFBUFFER_SIZE 512 +char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer + +void minsoc_printf(const char *fmt, ...) +{ + // init uart if not done already + if (!uart_init_done) + { + uart_init(); + uart_init_done = 1; + } + + va_list args; + va_start(args, fmt); + + //int str_l = vsnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args); + int str_l = vfnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args); + + if (!str_l) return; // no length string - just return + + int c=0; + // now print each char via the UART + while (c < str_l) + uart_putc(PRINTFBUFFER[c++]); + + va_end(args); +} + +#else +/* activate printf support in simulator */ +void minsoc_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + __asm__ __volatile__ (" l.addi\tr3,%1,0\n \ + l.addi\tr4,%2,0\n \ + l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args)); +} + +/* +void *memcpy (void *__restrict dstvoid, + __const void *__restrict srcvoid, size_t length) +{ + char *dst = dstvoid; + const char *src = (const char *) srcvoid; + + while (length--) + *dst++ = *src++; + return dst; +} +*/ +#endif + + + + + +/* print long */ +void report(unsigned long value) +{ + asm("l.addi\tr3,%0,0": :"r" (value)); + asm("l.nop %0": :"K" (NOP_REPORT)); +} + +/* just to satisfy linker */ +void __main() +{ +} + +/* start_TIMER */ +void start_timer(int x) +{ +} + +/* read_TIMER */ +/* Returns a value since started in uS */ +unsigned int read_timer(int x) +{ + unsigned long count = 0; + + /* Read the Time Stamp Counter */ +/* asm("simrdtsc %0" :"=r" (count)); */ + /*asm("l.sys 201"); */ + return count; +} + +/* For writing into SPR. */ +void mtspr(unsigned long spr, unsigned long value) +{ + asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); +} + +/* For reading SPR. */ +unsigned long mfspr(unsigned long spr) +{ + unsigned long value; + asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); + return value; +} + +#else +void report(unsigned long value) +{ + printf("report(0x%x);\n", (unsigned) value); +} + +/* start_TIMER */ +void start_timer(int tmrnum) +{ +} + +/* read_TIMER */ +/* Returns a value since started in uS */ +unsigned int read_timer(int tmrnum) +{ + struct timeval tv; + struct timezone tz; + + gettimeofday(&tv, &tz); + + return(tv.tv_sec*1000000+tv.tv_usec); +} + +#endif

release-0.9/sw/support/support.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/vfnprintf.c =================================================================== --- release-0.9/sw/support/vfnprintf.c (nonexistent) +++ release-0.9/sw/support/vfnprintf.c (revision 42) @@ -0,0 +1,686 @@ +// Ripped out of latest ecos build from http://sources-redhat.mirrors.airband.net/ecos/releases/ecos-3.0b1/ecos-3.0beta1.i386linux.tar.bz2 +// File: ecos-3.0b1/packages/language/c/libc/stdio/v3_0b1/src/output/vfnprintf.cxx + +// Hacked to pieces so it would work with OpenRISC compiler, not using libc +//=========================================================================== +// +// vfnprintf.c +// +// I/O routines for vfnprintf() for use with ANSI C library +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2000-04-20 +// Purpose: +// Description: +// Usage: +// +//####DESCRIPTIONEND#### +// +//=========================================================================== +// +// This code is based on original code with the following copyright: +// +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +// CONFIGURATION + +//#include // Configuration header +//#include // Configuration header for mb support + +// INCLUDES + +//#include // For mbtowc() +#include + + +//#include // Common type definitions and support +#define CYG_MACRO_START do { +#define CYG_MACRO_END } while (0) + +#define CYG_EMPTY_STATEMENT CYG_MACRO_START CYG_MACRO_END + +#define CYG_UNUSED_PARAM( _type_, _name_ ) CYG_MACRO_START \ + _type_ __tmp1 = (_name_); \ + _type_ __tmp2 = __tmp1; \ + __tmp1 = __tmp2; \ +CYG_MACRO_END + +#include // Variable argument definitions + +#include "vfnprintf.h" + + +# define BUF 40 + +/* + * Actual printf innards. + * + * This code is large and complicated... + */ + + +/* + * Macros for converting digits to letters and vice versa + */ +#define to_digit(c) ((c) - '0') +#define is_digit(c) ((unsigned)to_digit(c) <= 9) +#define to_char(n) ((n) + '0') + +/* + * Flags used during conversion. + */ +#define ALT 0x001 /* alternate form */ +#define HEXPREFIX 0x002 /* add 0x or 0X prefix */ +#define LADJUST 0x004 /* left adjustment */ +#define LONGDBL 0x008 /* long double; unimplemented */ +#define LONGINT 0x010 /* long integer */ +#define QUADINT 0x020 /* quad integer */ +#define SHORTINT 0x040 /* short integer */ +#define ZEROPAD 0x080 /* zero (as opposed to blank) pad */ +#define FPT 0x100 /* Floating point number */ +#define SIZET 0x200 /* size_t */ + +int +strlen(const char *s) +{ + const char *p; + + for (p = s; *p != '\0'; p++) + ; + return (s - p); +} + +void * +memcpy(void *dst, const void *src, size_t len) +{ + const char *csrc; + char *cdst; + int i; + + cdst = dst; + csrc = src; + for (i = len; i >= 0; i--) { + cdst[i] = csrc[i]; + } + return dst; +} + +// Function which prints back to the buffer, ptr, len bytes +// returns 1 if it should finish up, otherwise 0 to continue +int print_back_to_string(char * ptr, int len, size_t * n, int * ret, char ** stream) +{ +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + do { + int length = MIN( (int) len, *n - *ret - 1); + memcpy(*stream + *ret, ptr, length); + if (length < (int)len) { + *ret += length; + return 1; // finish up + } + + } while(0); + + return 0; +} + +//externC int +int +//vfnprintf ( FILE *stream, size_t n, const char *format, va_list arg) __THROW +vfnprintf ( char *stream, size_t n, const char *format, va_list arg) +{ + char *fmt; /* format string */ + int ch; /* character from fmt */ + int x, y; /* handy integers (short term usage) */ + char *cp; /* handy char pointer (short term usage) */ + int flags; /* flags as above */ + + int ret; /* return value accumulator */ + int width; /* width from format (%8d), or 0 */ + int prec; /* precision from format (%.3d), or -1 */ + char sign; /* sign prefix (' ', '+', '-', or \0) */ + wchar_t wc; + +#define quad_t long long +#define u_quad_t unsigned long long + + u_quad_t _uquad; /* integer arguments %[diouxX] */ + enum { OCT, DEC, HEX } base;/* base for [diouxX] conversion */ + int dprec; /* a copy of prec if [diouxX], 0 otherwise */ + int fieldsz; /* field size expanded by sign, etc */ + int realsz; /* field size expanded by dprec */ + int size; /* size of converted field or string */ + char *xdigs; /* digits for [xX] conversion */ +#define NIOV 8 + char buf[BUF]; /* space for %c, %[diouxX], %[eEfgG] */ + char ox[2]; /* space for 0x hex-prefix */ + + /* + * Choose PADSIZE to trade efficiency vs. size. If larger printf + * fields occur frequently, increase PADSIZE and make the initialisers + * below longer. + */ +#define PADSIZE 16 /* pad chunk size */ + static char blanks[PADSIZE] = + {' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '}; + static char zeroes[PADSIZE] = + {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'}; + + /* + * BEWARE, these `goto error' on error, and PAD uses `n'. + */ + + // We'll copy len bytes from (char*) ptr, into the output stream + // making sure we don't go over the end, so calculate length to be + // either the whole length we've been passed, or the whole length + // that is possible to write + // We finish if it was not possible to write the entire variable + // into the buffer, ie we had to write all we could, not all we + // wanted to. + /* + #define PRINT(ptr, len) \ + CYG_MACRO_START \ + int length = MIN( (int) len, n - ret - 1); \ + char* begin_stream_write = stream; \ + stream = memcpy(stream, ptr, length); \ + length = (unsigned long) stream - (unsigned long) begin_stream_write; \ + if (length < (int)len) { \ + ret += length; \ + goto done; \ + } \ + CYG_MACRO_END + */ + + //PRINT(with, PADSIZE); \ + //PRINT(with, x); \ + +#define PAD(howmany, with) \ + CYG_MACRO_START \ + if ((x = (howmany)) > 0) { \ + while (x > PADSIZE) { \ + if (print_back_to_string(with, PADSIZE, &n, &ret, &stream)) goto done; \ + x -= PADSIZE; \ + } \ + if (print_back_to_string(with, x, &n, &ret, &stream))goto done; \ + } \ + CYG_MACRO_END + + /* + * To extend shorts properly, we need both signed and unsigned + * argument extraction methods. + */ + +#define SARG() \ + (flags&QUADINT ? va_arg(arg, long long) : \ + flags&LONGINT ? va_arg(arg, long) : \ + flags&SHORTINT ? (long)(short)va_arg(arg, int) : \ + flags&SIZET ? (long)va_arg(arg, size_t) : \ + (long)va_arg(arg, int)) +#define UARG() \ + (flags&QUADINT ? va_arg(arg, unsigned long long) : \ + flags&LONGINT ? va_arg(arg, unsigned long) : \ + flags&SHORTINT ? (unsigned long)(unsigned short)va_arg(arg, int) : \ + flags&SIZET ? va_arg(arg, size_t) : \ + (unsigned long)va_arg(arg, unsigned int)) + + + xdigs = NULL; // stop compiler whinging + fmt = (char *)format; + ret = 0; + + /* + * Scan the format for conversions (`%' character). + */ + for (;;) { + cp = (char *)fmt; // char pointer - set to where we begin looking from + while ((x = ((wc = *fmt) != 0))) { // While, wc=next char and x is one while there's still chars left + fmt += x; // increment the pointer to the char + if (wc == '%') { // check if it's the beginning of + fmt--; // Decrement the char pointer, actually + break; + } + } + if ((y = fmt - cp) != 0) { // y is length of string to copy out just now + //PRINT(cp, y); // Copy macro + if(print_back_to_string(cp, y, &n, &ret, &stream)) goto done; // Copy macro + ret += y; // increment return chars + } + if ((x <= 0) || (ret >= (int)n)) // @@@ this check with n isn't good enough + goto done; + fmt++; /* skip over '%' */ + + flags = 0; + dprec = 0; + width = 0; + prec = -1; + sign = '\0'; + + rflag: ch = *fmt++; + reswitch: switch (ch) { + case ' ': + /* + * ``If the space and + flags both appear, the space + * flag will be ignored.'' + * -- ANSI X3J11 + */ + if (!sign) + sign = ' '; + goto rflag; + case '#': + flags |= ALT; + goto rflag; + case '*': + /* + * ``A negative field width argument is taken as a + * - flag followed by a positive field width.'' + * -- ANSI X3J11 + * They don't exclude field widths read from args. + */ + if ((width = va_arg(arg, int)) >= 0) + goto rflag; + width = -width; + /* FALLTHROUGH */ + case '-': + flags |= LADJUST; + goto rflag; + case '+': + sign = '+'; + goto rflag; + case '.': + if ((ch = *fmt++) == '*') { + x = va_arg(arg, int); + prec = x < 0 ? -1 : x; + goto rflag; + } + x = 0; + while (is_digit(ch)) { + x = 10 * x + to_digit(ch); + ch = *fmt++; + } + prec = x < 0 ? -1 : x; + goto reswitch; + case '0': + /* + * ``Note that 0 is taken as a flag, not as the + * beginning of a field width.'' + * -- ANSI X3J11 + */ + flags |= ZEROPAD; + goto rflag; + case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + x = 0; + do { + x = 10 * x + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); + width = x; + goto reswitch; + case 'h': + flags |= SHORTINT; + goto rflag; + case 'l': + if (*fmt == 'l') { + fmt++; + flags |= QUADINT; + } else { + flags |= LONGINT; + } + goto rflag; + case 'q': + flags |= QUADINT; + goto rflag; + case 'c': + *(cp = buf) = va_arg(arg, int); + size = 1; + sign = '\0'; + break; + case 'D': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'd': + case 'i': + _uquad = SARG(); +#ifndef _NO_LONGLONG + if ((quad_t)_uquad < 0) +#else + if ((long) _uquad < 0) +#endif + { + + _uquad = -_uquad; + sign = '-'; + } + base = DEC; + goto number; + + case 'e': + case 'E': + case 'f': + case 'g': + case 'G': + // Output nothing at all + (void) va_arg(arg, double); // take off arg anyway + cp = ""; + size = 0; + sign = '\0'; + break; + + case 'n': +#ifndef _NO_LONGLONG + if (flags & QUADINT) + *va_arg(arg, quad_t *) = ret; + else +#endif + if (flags & LONGINT) + *va_arg(arg, long *) = ret; + else if (flags & SHORTINT) + *va_arg(arg, short *) = ret; + else if (flags & SIZET) + *va_arg(arg, size_t *) = ret; + else + *va_arg(arg, int *) = ret; + continue; /* no output */ + case 'O': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'o': + _uquad = UARG(); + base = OCT; + goto nosign; + case 'p': + /* + * ``The argument shall be a pointer to void. The + * value of the pointer is converted to a sequence + * of printable characters, in an implementation- + * defined manner.'' + * -- ANSI X3J11 + */ + /* NOSTRICT */ + _uquad = (unsigned long)va_arg(arg, void *); + base = HEX; + xdigs = (char *)"0123456789abcdef"; + flags |= HEXPREFIX; + ch = 'x'; + goto nosign; + case 's': + if ((cp = va_arg(arg, char *)) == NULL) + cp = (char *)"(null)"; + if (prec >= 0) { + /* + * can't use strlen; can only look for the + * NUL in the first `prec' characters, and + * strlen() will go further. + */ + char *p = (char *)memchr(cp, 0, prec); + + if (p != NULL) { + size = p - cp; + if (size > prec) + size = prec; + } else + size = prec; + } else + size = strlen(cp); + sign = '\0'; + break; + case 'U': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'u': + _uquad = UARG(); + base = DEC; + goto nosign; + case 'X': + xdigs = (char *)"0123456789ABCDEF"; + goto hex; + case 'x': + xdigs = (char *)"0123456789abcdef"; + hex: _uquad = UARG(); + base = HEX; + /* leading 0x/X only if non-zero */ + if (flags & ALT && _uquad != 0) + flags |= HEXPREFIX; + + /* unsigned conversions */ + nosign: sign = '\0'; + /* + * ``... diouXx conversions ... if a precision is + * specified, the 0 flag will be ignored.'' + * -- ANSI X3J11 + */ + number: if ((dprec = prec) >= 0) + flags &= ~ZEROPAD; + + /* + * ``The result of converting a zero value with an + * explicit precision of zero is no characters.'' + * -- ANSI X3J11 + */ + cp = buf + BUF; + if (_uquad != 0 || prec != 0) { + /* + * Unsigned mod is hard, and unsigned mod + * by a constant is easier than that by + * a variable; hence this switch. + */ + switch (base) { + case OCT: + do { + *--cp = to_char(_uquad & 7); + _uquad >>= 3; + } while (_uquad); + /* handle octal leading 0 */ + if (flags & ALT && *cp != '0') + *--cp = '0'; + break; + + case DEC: + if (!(flags & QUADINT)) { + /* many numbers are 1 digit */ + unsigned long v = (unsigned long)_uquad; + while (v >= 10) { + /* The following is usually faster than using a modulo */ + unsigned long next = v / 10; + *--cp = to_char(v - (next * 10)); + v = next; + } + *--cp = to_char(v); + } + else { + while (_uquad >= 10) { + /* The following is usually faster than using a modulo */ + u_quad_t next = _uquad / 10; + *--cp = to_char(_uquad - (next * 10)); + _uquad = next; + } + *--cp = to_char(_uquad); + } + break; + + case HEX: + do { + *--cp = xdigs[_uquad & 15]; + _uquad >>= 4; + } while (_uquad); + break; + + default: + cp = (char *)"bug in vfprintf: bad base"; + size = strlen(cp); + goto skipsize; + } + } + size = buf + BUF - cp; + skipsize: + break; + case 'z': + flags |= SIZET; + goto rflag; + default: /* "%?" prints ?, unless ? is NUL */ + if (ch == '\0') + goto done; + /* pretend it was %c with argument ch */ + cp = buf; + *cp = ch; + size = 1; + sign = '\0'; + break; + } + + /* + * All reasonable formats wind up here. At this point, `cp' + * points to a string which (if not flags&LADJUST) should be + * padded out to `width' places. If flags&ZEROPAD, it should + * first be prefixed by any sign or other prefix; otherwise, + * it should be blank padded before the prefix is emitted. + * After any left-hand padding and prefixing, emit zeroes + * required by a decimal [diouxX] precision, then print the + * string proper, then emit zeroes required by any leftover + * floating precision; finally, if LADJUST, pad with blanks. + * + * Compute actual size, so we know how much to pad. + * fieldsz excludes decimal prec; realsz includes it. + */ +#ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT + fieldsz = size + fpprec; +#else + fieldsz = size; +#endif + if (sign) + fieldsz++; + else if (flags & HEXPREFIX) + fieldsz+= 2; + realsz = dprec > fieldsz ? dprec : fieldsz; + + /* right-adjusting blank padding */ + if ((flags & (LADJUST|ZEROPAD)) == 0) { + if (width - realsz > 0) { + PAD(width - realsz, blanks); + ret += width - realsz; + } + } + + /* prefix */ + if (sign) { + //PRINT(&sign, 1); + if(print_back_to_string(&sign, 1, &n, &ret, &stream))goto done; + ret++; + } else if (flags & HEXPREFIX) { + ox[0] = '0'; + ox[1] = ch; + //PRINT(ox, 2); + if(print_back_to_string(ox, 2, &n, &ret, &stream))goto done; + ret += 2; + } + + /* right-adjusting zero padding */ + if ((flags & (LADJUST|ZEROPAD)) == ZEROPAD) { + if (width - realsz > 0) { + PAD(width - realsz, zeroes); + ret += width - realsz; + } + } + + if (dprec - fieldsz > 0) { + /* leading zeroes from decimal precision */ + PAD(dprec - fieldsz, zeroes); + ret += dprec - fieldsz; + } + + /* the string or number proper */ + //PRINT(cp, size); + if(print_back_to_string(cp,size, &n, &ret, &stream))goto done; + ret += size; + +#ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT + /* trailing f.p. zeroes */ + PAD(fpprec, zeroes); + ret += fpprec; +#endif + + /* left-adjusting padding (always blank) */ + if (flags & LADJUST) { + if (width - realsz > 0) { + PAD(width - realsz, blanks); + ret += width - realsz; + } + } + + } + + done: + error: + return ret;// remove this error stuff (((Cyg_OutputStream *) stream)->get_error() ? EOF : ret); + /* NOTREACHED */ +} + + + +// EOF vfnprintf.c

release-0.9/sw/support/vfnprintf.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/support.h =================================================================== --- release-0.9/sw/support/support.h (nonexistent) +++ release-0.9/sw/support/support.h (revision 42) @@ -0,0 +1,69 @@ +/* Support file for or32 tests. This file should is included + in each test. It calls main() function and add support for + basic functions */ + +#ifndef SUPPORT_H +#define SUPPORT_H + +#include +#include +#include +#define OR1K 1 //ME added +#if OR1K + +/* Register access macros */ +#define REG8(add) *((volatile unsigned char *)(add)) +#define REG16(add) *((volatile unsigned short *)(add)) +#define REG32(add) *((volatile unsigned long *)(add)) + +void or32_printf(const char *fmt, ...); + +/* For writing into SPR. */ +void mtspr(unsigned long spr, unsigned long value); + +/* For reading SPR. */ +unsigned long mfspr(unsigned long spr); + +#else /* OR1K */ + +#include + +#endif /* OR1K */ + +#define printf or32_printf + +/* Function to be called at entry point - not defined here. */ +int main (); + +/* Prints out a value */ +void report(unsigned long value); + +/* return value by making a syscall */ +extern void or32_exit (int i) __attribute__ ((__noreturn__)); + +/* memcpy clone */ +/* +extern void *memcpy (void *__restrict __dest, + __const void *__restrict __src, size_t __n); +*/ + +/* Timer functions */ +extern void start_timer(int); +extern unsigned int read_timer(int); + +extern unsigned long excpt_buserr; +extern unsigned long excpt_dpfault; +extern unsigned long excpt_ipfault; +extern unsigned long excpt_tick; +extern unsigned long excpt_align; +extern unsigned long excpt_illinsn; +extern unsigned long excpt_int; +extern unsigned long excpt_dtlbmiss; +extern unsigned long excpt_itlbmiss; +extern unsigned long excpt_range; +extern unsigned long excpt_syscall; +extern unsigned long excpt_break; +extern unsigned long excpt_trap; + + +#endif /* SUPPORT_H */

release-0.9/sw/support/support.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/board.h =================================================================== --- release-0.9/sw/support/board.h (nonexistent) +++ release-0.9/sw/support/board.h (revision 42) @@ -0,0 +1,52 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + +#define TICKS_PER_SEC 100 + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define BOARD_DEF_IP 0x0a010185 +#define BOARD_DEF_MASK 0xff000000 +#define BOARD_DEF_GW 0x0a010101 + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + + +/* Whether online help is available -- saves space */ +#define HELP_ENABLED 1 + +/* Whether self check is enabled */ +#define SELF_CHECK 1 + +#endif

release-0.9/sw/support/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/Makefile =================================================================== --- release-0.9/sw/support/Makefile (nonexistent) +++ release-0.9/sw/support/Makefile (revision 42) @@ -0,0 +1,37 @@ +all: libsupport.a reset-nocache.o reset-ic.o reset-dc.o reset-icdc.o + +libsupport.a: support.o int.o except.o uart.o vfnprintf.o + $(OR32_TOOL_PREFIX)-ar cru libsupport.a support.o except.o int.o uart.o vfnprintf.o + $(OR32_TOOL_PREFIX)-ranlib libsupport.a + +support.o: support.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +reset-nocache.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=0 -o $@ $? + +reset-dc.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=1 -o $@ $? + +reset-ic.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=0 -o $@ $? + +reset-icdc.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=1 -o $@ $? + +except.o: except.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +uart.o: uart.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +#snprintf.o: snprintf.c +# $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -O2 -c -o $@ $? + +vfnprintf.o: vfnprintf.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +int.o: int.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +include Makefile.inc

release-0.9/sw/support/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/int.c =================================================================== --- release-0.9/sw/support/int.c (nonexistent) +++ release-0.9/sw/support/int.c (revision 42) @@ -0,0 +1,83 @@ +/* This file is part of test microkernel for OpenRISC 1000. */ +/* (C) 2001 Simon Srot, srot@opencores.org */ + +#include "support.h" +#include "spr_defs.h" +#include "int.h" + +#ifdef OR1K + +/* Interrupt handlers table */ +struct ihnd int_handlers[MAX_INT_HANDLERS]; + +/* Initialize routine */ +int int_init() +{ + int i; + + for(i = 0; i < MAX_INT_HANDLERS; i++) { + int_handlers[i].handler = 0; + int_handlers[i].arg = 0; + } + mtspr(SPR_PICMR, 0x00000000); + + //set OR1200 to accept exceptions + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + + return 0; +} + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + int_handlers[vect].handler = handler; + int_handlers[vect].arg = arg; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Disable interrupt */ +int int_disable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect)); + + return 0; +} + +/* Enable interrupt */ +int int_enable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Main interrupt handler */ +void int_main() +{ + unsigned long picsr = mfspr(SPR_PICSR); //process only the interrupts asserted at signal catch, ignore all during process + unsigned long i = 0; + + while(i < 32) { + if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { + (*int_handlers[i].handler)(int_handlers[i].arg); + } + i++; + } + + mtspr(SPR_PICSR, 0); //clear interrupt status: all modules have level interrupts, which have to be cleared by software, +} //thus this is safe, since non processed interrupts will get re-asserted soon enough + + +#endif

release-0.9/sw/support/int.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/int.h =================================================================== --- release-0.9/sw/support/int.h (nonexistent) +++ release-0.9/sw/support/int.h (revision 42) @@ -0,0 +1,15 @@ + +/* Number of interrupt handlers */ +#define MAX_INT_HANDLERS 32 + +/* Handler entry */ +struct ihnd { + void (*handler)(void *); + void *arg; +}; + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg); + +/* Initialize routine */ +int int_init();

release-0.9/sw/support/int.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/reset.S =================================================================== --- release-0.9/sw/support/reset.S (nonexistent) +++ release-0.9/sw/support/reset.S (revision 42) @@ -0,0 +1,113 @@ +/* Support file for c based tests */ +#include "spr_defs.h" +#include "board.h" +#include "mc.h" + + .section .stack + .space STACK_SIZE +_stack: + + .section .reset, "ax" + + .org 0x100 +_reset_vector: + l.nop + l.nop + l.addi r2,r0,0x0 + l.addi r3,r0,0x0 + l.addi r4,r0,0x0 + l.addi r5,r0,0x0 + l.addi r6,r0,0x0 + l.addi r7,r0,0x0 + l.addi r8,r0,0x0 + l.addi r9,r0,0x0 + l.addi r10,r0,0x0 + l.addi r11,r0,0x0 + l.addi r12,r0,0x0 + l.addi r13,r0,0x0 + l.addi r14,r0,0x0 + l.addi r15,r0,0x0 + l.addi r16,r0,0x0 + l.addi r17,r0,0x0 + l.addi r18,r0,0x0 + l.addi r19,r0,0x0 + l.addi r20,r0,0x0 + l.addi r21,r0,0x0 + l.addi r22,r0,0x0 + l.addi r23,r0,0x0 + l.addi r24,r0,0x0 + l.addi r25,r0,0x0 + l.addi r26,r0,0x0 + l.addi r27,r0,0x0 + l.addi r28,r0,0x0 + l.addi r29,r0,0x0 + l.addi r30,r0,0x0 + l.addi r31,r0,0x0 + +/* + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,MC_BA_MASK + l.addi r5,r0,0x00 + l.sw 0(r3),r5 + */ + l.movhi r3,hi(_start) + l.ori r3,r3,lo(_start) + l.jr r3 + l.nop + + .section .text + +_start: + +.if IC | DC + /* Flush IC and/or DC */ + l.addi r10,r0,0 + l.addi r11,r0,0 + l.addi r12,r0,0 +.if IC + l.addi r11,r0,IC_SIZE +.endif +.if DC + l.addi r12,r0,DC_SIZE +.endif + l.sfleu r12,r11 + l.bf loop + l.nop + l.add r11,r0,r12 +loop: +.if IC + l.mtspr r0,r10,SPR_ICBIR +.endif +.if DC + l.mtspr r0,r10,SPR_DCBIR +.endif + l.sfne r10,r11 + l.bf loop + l.addi r10,r10,16 + + /* Enable IC and/or DC */ + l.addi r10,r0,(SPR_SR_SM) +.if IC + l.ori r10,r10,(SPR_SR_ICE) +.endif +.if DC + l.ori r10,r10,(SPR_SR_DCE) +.endif + l.mtspr r0,r10,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop +.endif + + /* Set stack pointer */ + l.movhi r1,hi(_stack) + l.ori r1,r1,lo(_stack) + + /* Jump to main */ + l.movhi r2,hi(_reset) + l.ori r2,r2,lo(_reset) + l.jr r2 + l.nop +

release-0.9/sw/support/reset.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/mc.h =================================================================== --- release-0.9/sw/support/mc.h (nonexistent) +++ release-0.9/sw/support/mc.h (revision 42) @@ -0,0 +1,111 @@ +/* mc.h -- Simulation of Memory Controller + Copyright (C) 2001 by Marko Mlinar, markom@opencores.org + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/* Prototypes */ +#ifndef __MC_H +#define __MC_H + +#define N_CE (8) + +#define MC_CSR (0x00) +#define MC_POC (0x04) +#define MC_BA_MASK (0x08) +#define MC_CSC(i) (0x10 + (i) * 8) +#define MC_TMS(i) (0x14 + (i) * 8) + +#define MC_ADDR_SPACE (MC_CSC(N_CE)) + +/* POC register field definition */ +#define MC_POC_EN_BW_OFFSET 0 +#define MC_POC_EN_BW_WIDTH 2 +#define MC_POC_EN_MEMTYPE_OFFSET 2 +#define MC_POC_EN_MEMTYPE_WIDTH 2 + +/* CSC register field definition */ +#define MC_CSC_EN_OFFSET 0 +#define MC_CSC_MEMTYPE_OFFSET 1 +#define MC_CSC_MEMTYPE_WIDTH 2 +#define MC_CSC_BW_OFFSET 4 +#define MC_CSC_BW_WIDTH 2 +#define MC_CSC_MS_OFFSET 6 +#define MC_CSC_MS_WIDTH 2 +#define MC_CSC_WP_OFFSET 8 +#define MC_CSC_BAS_OFFSET 9 +#define MC_CSC_KRO_OFFSET 10 +#define MC_CSC_PEN_OFFSET 11 +#define MC_CSC_SEL_OFFSET 16 +#define MC_CSC_SEL_WIDTH 8 + +#define MC_CSC_MEMTYPE_SDRAM 0 +#define MC_CSC_MEMTYPE_SSRAM 1 +#define MC_CSC_MEMTYPE_ASYNC 2 +#define MC_CSC_MEMTYPE_SYNC 3 + +#define MC_CSR_VALID 0xFF000703LU +#define MC_POC_VALID 0x0000000FLU +#define MC_BA_MASK_VALID 0x000000FFLU +#define MC_CSC_VALID 0x00FF0FFFLU +#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU +#define MC_TMS_SSRAM_VALID 0x00000000LU +#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU +#define MC_TMS_SYNC_VALID 0x01FFFFFFLU +#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */ + +/* TMS register field definition SDRAM */ +#define MC_TMS_SDRAM_TRFC_OFFSET 24 +#define MC_TMS_SDRAM_TRFC_WIDTH 4 +#define MC_TMS_SDRAM_TRP_OFFSET 20 +#define MC_TMS_SDRAM_TRP_WIDTH 4 +#define MC_TMS_SDRAM_TRCD_OFFSET 17 +#define MC_TMS_SDRAM_TRCD_WIDTH 4 +#define MC_TMS_SDRAM_TWR_OFFSET 15 +#define MC_TMS_SDRAM_TWR_WIDTH 2 +#define MC_TMS_SDRAM_WBL_OFFSET 9 +#define MC_TMS_SDRAM_OM_OFFSET 7 +#define MC_TMS_SDRAM_OM_WIDTH 2 +#define MC_TMS_SDRAM_CL_OFFSET 4 +#define MC_TMS_SDRAM_CL_WIDTH 3 +#define MC_TMS_SDRAM_BT_OFFSET 3 +#define MC_TMS_SDRAM_BL_OFFSET 0 +#define MC_TMS_SDRAM_BL_WIDTH 3 + +/* TMS register field definition ASYNC */ +#define MC_TMS_ASYNC_TWWD_OFFSET 20 +#define MC_TMS_ASYNC_TWWD_WIDTH 6 +#define MC_TMS_ASYNC_TWD_OFFSET 16 +#define MC_TMS_ASYNC_TWD_WIDTH 4 +#define MC_TMS_ASYNC_TWPW_OFFSET 12 +#define MC_TMS_ASYNC_TWPW_WIDTH 4 +#define MC_TMS_ASYNC_TRDZ_OFFSET 8 +#define MC_TMS_ASYNC_TRDZ_WIDTH 4 +#define MC_TMS_ASYNC_TRDV_OFFSET 0 +#define MC_TMS_ASYNC_TRDV_WIDTH 8 + +/* TMS register field definition SYNC */ +#define MC_TMS_SYNC_TTO_OFFSET 16 +#define MC_TMS_SYNC_TTO_WIDTH 9 +#define MC_TMS_SYNC_TWR_OFFSET 12 +#define MC_TMS_SYNC_TWR_WIDTH 4 +#define MC_TMS_SYNC_TRDZ_OFFSET 8 +#define MC_TMS_SYNC_TRDZ_WIDTH 4 +#define MC_TMS_SYNC_TRDV_OFFSET 0 +#define MC_TMS_SYNC_TRDV_WIDTH 8 + +#endif

release-0.9/sw/support/mc.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/spr_defs.h =================================================================== --- release-0.9/sw/support/spr_defs.h (nonexistent) +++ release-0.9/sw/support/spr_defs.h (revision 42) @@ -0,0 +1,449 @@ +/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file is also used by microkernel test bench. Among +others it is also used in assembly file(s). */ + +/* Definition of special-purpose registers (SPRs) */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +#if 0 +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) +#else +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) +#endif +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \ + SPR_DTLBTR_UWE | \ + SPR_DTLBTR_SRE | \ + SPR_DTLBTR_SWE ) +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \ + SPR_ITLBTR_UXE ) + + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000001 +#define SPR_DCR_CC_LESS 0x00000002 +#define SPR_DCR_CC_LESSE 0x00000003 +#define SPR_DCR_CC_GREAT 0x00000004 +#define SPR_DCR_CC_GREATE 0x00000005 +#define SPR_DCR_CC_NEQUAL 0x00000006 + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PRINTF 0x0003 /* Simprintf instruction */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */

release-0.9/sw/support/spr_defs.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/orp.cfg =================================================================== --- release-0.9/sw/support/orp.cfg (nonexistent) +++ release-0.9/sw/support/orp.cfg (revision 42) @@ -0,0 +1,901 @@ +/* sim.cfg -- Simulator configuration script file + Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. +It contains the default configuration and help about configuring +the simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* INTRODUCTION + + The ork1sim has various parameters, that are set in configuration files + like this one. The user can switch between configurations at startup by + specifying the required configuration file with the -f option. + If no configuration file is specified or1ksim searches for the default + configuration file sim.cfg. First it searches for './sim.cfg'. If this + file is not found, it searches for '~/or1k/sim.cfg'. If this file is + not found too, it reverts to the built-in default configuration. + + NOTE: Users should not rely on the built-in configuration, since the + default configuration may differ between version. + Rather create a configuration file that sets all critical values. + + This file may contain (standard C) comments only - no // support. + + Configure files may be be included, using: + include "file_name_to_include" + + Like normal configuration files, the included file is divided into + sections. Each section is described in detail also. + + Some section have subsections. One example of such a subsection is: + + device + instance specific parameters... + enddevice + + which creates a device instance. +*/ + + +/* MEMORY SECTION + + This section specifies how the memory is generated and the blocks + it consists of. + + type = random/unknown/pattern + Specifies the initial memory values. + 'random' generates random memory using seed 'random_seed'. + 'pattern' fills memory with 'pattern'. + 'unknown' does not specify how memory should be generated, + leaving the memory in a undefined state. This is the fastest + option. + + random_seed = + random seed for randomizer, used if type = 'random'. + + pattern = + pattern to fill memory, used if type = 'pattern'. + + nmemories = + number of memory instances connected + + baseaddr = + memory start address + + size = + memory size + + name = "" + memory block name + + ce = + chip enable index of the memory instance + + mc = + memory controller this memory is connected to + + delayr = + cycles, required for read access, -1 if instance does not support reading + + delayw = + cycles, required for write access, -1 if instance does not support writing + + log = "" + filename, where to log memory accesses to, no log, if log command is not specified +*/ + + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0x04000000 + size = 0x00200000 + delayr = 1 + delayw = -1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x00200000 + delayr = 1 + delayw = 5 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "ICM" + mc = 0 + ce = 2 + baseaddr = 0x00800000 + size = 0x00004000 + delayr = 1 + delayw = 1 +end + + +/* IMMU SECTION + + This section configures the Instruction Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = + number of ITLB sets; must be power of two + + nways = + number of ITLB ways + + pagesize = + instruction page size; must be power of two + + entrysize = + instruction entry size in bytes + + ustates = + number of ITLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = + number of cycles immu hit costs + + missdelay = + number of cycles immu miss costs +*/ + +section immu + + enabled = 1 + nsets = 32 + nways = 1 + pagesize = 8192 + +end + + +/* DMMU SECTION + + This section configures the Data Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = + number of DTLB sets; must be power of two + + nways = + number of DTLB ways + + pagesize = + data page size; must be power of two + + entrysize = + data entry size in bytes + + ustates = + number of DTLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = + number of cycles dmmu hit costs + + missdelay = + number of cycles dmmu miss costs +*/ + +section dmmu + enabled = 1 + nsets = 32 + nways = 1 + pagesize = 8192 +end + + +/* IC SECTION + + This section configures the Instruction Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = + number of IC sets; must be power of two + + nways = + number of IC ways + + blocksize = + IC block size in bytes; must be power of two + + ustates = + number of IC usage states (2, 3, 4 etc., max is 4) + + hitdelay = + number of cycles ic hit costs + + missdelay = + number of cycles ic miss costs +*/ + +section ic + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 +end + + +/* DC SECTION + + This section configures the Data Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = + number of DC sets; must be power of two + + nways = + number of DC ways + + blocksize = + DC block size in bytes; must be power of two + + ustates = + number of DC usage states (2, 3, 4 etc., max is 4) + + load_hitdelay = + number of cycles dc load hit costs + + load_missdelay = + number of cycles dc load miss costs + + store_hitdelay = + number of cycles dc load hit costs + + store_missdelay = + number of cycles dc load miss costs +*/ + +section dc + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 +end + + +/* SIM SECTION + + This section specifies how or1ksim should behave. + + verbose = 0/1 + '0': don't print extra messages + '1': print extra messages + + debug = 0-9 + 0 : no debug messages + 1-9: debug message level. + higher numbers produce more messages + + profile = 0/1 + '0': don't generate profiling file 'sim.profile' + '1': don't generate profiling file 'sim.profile' + + prof_fn = "" + optional filename for the profiling file. + valid only if 'profile' is set + + mprofile = 0/1 + '0': don't generate memory profiling file 'sim.mprofile' + '1': generate memory profiling file 'sim.mprofile' + + mprof_fn = "" + optional filename for the memory profiling file. + valid only if 'mprofile' is set + + history = 0/1 + '0': don't track execution flow + '1': track execution flow + Execution flow can be tracked for the simulator's + 'hist' command. Useful for back-trace debugging. + + iprompt = 0/1 + '0': start in (so what do we start in ???) + '1': start in interactive prompt. + + exe_log = 0/1 + '0': don't generate execution log. + '1': generate execution log. + + exe_log = default/hardware/simple/software + type of execution log, default is used when not specified + + exe_log_start = + index of first instruction to start logging, default = 0 + + exe_log_end = + index of last instruction to end logging; not limited, if omitted + + exe_log_marker = + specifies number of instructions before horizontal marker is + printed; if zero, markers are disabled (default) + + exe_log_fn = "" + filename for the exection log file. + valid only if 'exe_log' is set + + clkcycle = [ps|ns|us|ms] + specifies time measurement for one cycle +*/ + +section sim + verbose = 1 + debug = 0 + profile = 0 + prof_fn = "sim.profile" + + history = 1 + /* iprompt = 0 */ + exe_log = 1 + exe_log_type = hardware +/* exe_log_start = 0 */ +/* exe_log_end = 2000000 */ +/* exe_log_marker = 50 */ + exe_log_fn = "executed.log" + +/* clkcycle = 10000ns */ + +end + + +/* SECTION VAPI + + This section configures the Verification API, used for Advanced + Core Verification. + + enabled = 0/1 + '0': disbable VAPI server + '1': enable/start VAPI server + + server_port = + TCP/IP port to start VAPI server on + + log_enabled = 0/1 + '0': disable VAPI requests logging + '1': enable VAPI requests logging + + hide_device_id = 0/1 + '0': don't log device id (for compatability with old version) + '1': log device id + + + vapi_fn = + filename for the log file. + valid only if log_enabled is set +*/ + +section VAPI + enabled = 0 + server_port = 9998 + log_enabled = 0 + vapi_log_fn = "vapi.log" +end + + +/* CPU SECTION + + This section specifies various CPU parameters. + + ver = + rev = + specifies version and revision of the CPU used + + upr = + changes the upr register + + sr = + sets the initial Supervision Register value + + superscalar = 0/1 + '0': CPU is scalar + '1': CPU is superscalar + (modify cpu/or32/execute.c to tune superscalar model) + + hazards = 0/1 + '0': don't track data hazards in superscalar CPU + '1': track data hazards in superscalar CPU + If tracked, data hazards can be displayed using the + simulator's 'r' command. + + dependstats = 0/1 + '0': don't calculate inter-instruction dependencies. + '1': calculate inter-instruction dependencies. + If calculated, inter-instruction dependencies can be + displayed using the simulator's 'stat' command. + + sbuf_len = + length of store buffer (<= 256), 0 = disabled +*/ + +section cpu + ver = 0x1200 + rev = 0x0001 + /* upr = */ + superscalar = 0 + hazards = 1 + dependstats = 1 + sbuf_len = 1 +end + + +/* PM SECTION + + This section specifies Power Management parameters + + enabled = 0/1 + '0': disable power management + '1': enable power management +*/ + +section pm + enabled = 0 +end + + +/* BPB SECTION + + This section specifies how branch prediction should behave. + + enabled = 0/1 + '0': disable branch prediction + '1': enable branch prediction + + btic = 0/1 + '0': disable branch target instruction cache model + '1': enable branch target instruction cache model + + sbp_bf_fwd = 0/1 + Static branch prediction for 'l.bf' + '0': don't use forward prediction + '1': use forward prediction + + sbp_bnf_fwd = 0/1 + Static branch prediction for 'l.bnf' + '0': don't use forward prediction + '1': use forward prediction + + hitdelay = + number of cycles bpb hit costs + + missdelay = + number of cycles bpb miss costs +*/ + +section bpb + enabled = 1 + btic = 1 + sbp_bf_fwd = 0 + sbp_bnf_fwd = 0 + hitdelay = 0 + missdelay = 0 +end + + +/* DEBUG SECTION + + This sections specifies how the debug unit should behave. + + enabled = 0/1 + '0': disable debug unit + '1': enable debug unit + + gdb_enabled = 0/1 + '0': don't start gdb server + '1': start gdb server at port 'server_port' + + server_port = + TCP/IP port to start gdb server on + valid only if gdb_enabled is set + + vapi_id = + Used to create "fake" vapi log file containing the JTAG proxy messages. +*/ +/* +section debug + enabled = 1 + gdb_enabled = 1 + server_port = 12345 +end +*/ + +/* MC SECTION + + This section configures the memory controller + + enabled = 0/1 + '0': disable memory controller + '1': enable memory controller + + baseaddr = + address of first MC register + + POC = + Power On Configuration register + + index = + Index of this memory controller amongst all the memory controllers +*/ + +section mc + enabled = 1 + baseaddr = 0x60000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + + +/* UART SECTION + + This section configures the UARTs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + address of first UART register for this device + + + channel = : + + The channel parameter indicates the source of received UART characters + and the sink for transmitted UART characters. + + The can be either "file", "xterm", "tcp", "fd", or "tty" + (without quotes). + + A) To send/receive characters from a pair of files, use a file + channel: + + channel=file:, + + B) To create an interactive terminal window, use an xterm channel: + + channel=xterm:[]* + + C) To create a bidirectional tcp socket which one could, for example, + access via telnet, use a tcp channel: + + channel=tcp: + + D) To cause the UART to read/write from existing numeric file + descriptors, use an fd channel: + + channel=fd:, + + E) To connect the UART to a physical serial port, create a tty + channel: + + channel=tty:device=/dev/ttyS0,baud=9600 + + irq = + irq number for this device + + 16550 = 0/1 + '0': this device is a UART16450 + '1': this device is a UART16550 + + jitter = + in msecs... time to block, -1 to disable it + + vapi_id = + VAPI id of this instance +*/ + +section uart + enabled = 1 + baseaddr = 0x90000000 + irq = 2 + /*channel = "file:uart0.rx,uart0.tx"*/ + channel = "tcp:10084" + jitter = -1 /* async behaviour */ + 16550 = 1 +end + + +/* DMA SECTION + + This section configures the DMAs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + address of first DMA register for this device + + irq = + irq number for this device + + vapi_id = + VAPI id of this instance +*/ + +section dma + enabled = 1 + baseaddr = 0x9a000000 + irq = 11 +end + + +/* ETHERNET SECTION + + This section configures the ETHERNETs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + address of first ethernet register for this device + + dma = + which controller is this ethernet "connected" to + + irq = + ethernet mac IRQ level + + rtx_type = + use 0 - file interface, 1 - socket interface + + rx_channel = + DMA channel used for RX + + tx_channel = + DMA channel used for TX + + rxfile = "" + filename, where to read data from + + txfile = "" + filename, where to write data to + + sockif = "" + interface name of ethernet socket + + vapi_id = + VAPI id of this instance +*/ + +section ethernet + enabled = 1 + baseaddr = 0x92000000 + dma = 0 + irq = 4 + rtx_type = 0 + tx_channel = 0 + rx_channel = 1 + rxfile = "eth0.rx" + txfile = "eth0.tx" + sockif = "eth0" +end + + +/* GPIO SECTION + + This section configures the GPIOs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + address of first GPIO register for this device + + irq = + irq number for this device + + base_vapi_id = + first VAPI id of this instance + GPIO uses 8 consecutive VAPI IDs +*/ + +section gpio + enabled = 0 + baseaddr = 0x91000000 + irq = 3 + base_vapi_id = 0x0200 +end + +/* VGA SECTION + + This section configures the VGA/LCD controller + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + address of first VGA register + + irq = + irq number for this device + + refresh_rate = + number of cycles between screen dumps + + filename = "" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ + +section vga + enabled = 1 + baseaddr = 0x97100000 + irq = 8 + refresh_rate = 100000 + filename = "primary" +end + + +/* TICK TIMER SECTION + + This section configures tick timer + + enabled = 0/1 + whether tick timer is enabled +*/ +/* +section tick + enabled = 1 + irq = 3 +end +*/ +/* +section pic + enabled = 1 + edge_trigger = 1 +end +*/ + +/* FB SECTION + + This section configures the frame buffer + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = + base address of frame buffer + + paladdr = + base address of first palette entry + + refresh_rate = + number of cycles between screen dumps + + filename = "" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ +/* +section fb + enabled = 1 + baseaddr = 0x97000000 + refresh_rate = 1000000 + filename = "primary" +end +*/ + +/* KBD SECTION + + This section configures the PS/2 compatible keyboard + + baseaddr = + base address of the keyboard device + + rxfile = "" + filename, where to read data from +*/ +/* +section kbd + enabled = 1 + irq = 5 + baseaddr = 0x94000000 + rxfile = "kbd.rx" +end +*/ + +/* ATA SECTION + + This section configures the ATA/ATAPI host controller + + baseaddr = + address of first ATA register + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + irq = + irq number for this device + + debug = + debug level for ata models. + 0: no debug messages + 1: verbose messages + 3: normal messages (more messages than verbose) + 5: debug messages (normal debug messages) + 7: flow control messages (debug statemachine flows) + 9: low priority message (display everything the code does) + + dev_type0/1 = + ata device 0 type + 0: NO_CONNeCT: none (not connected) + 1: FILE : simulated harddisk + 2: LOCAL : local system harddisk + + dev_file0/1 = "" + filename for simulated ATA device + valid only if dev_type0 == 1 + + dev_size0/1 = + size of simulated hard-disk (in MBytes) + valid only if dev_type0 == 1 + + dev_packet0/1 = + 0: simulated ATA device does NOT implement PACKET command feature set + 1: simulated ATA device does implement PACKET command feature set + + FIXME: irq number +*/ +/* +section ata + enabled = 0 + baseaddr = 0x9e000000 + irq = 15 + + dev_type0 = 1 + dev_file0 = "/tmp/sim_atadev0" + dev_size0 = 1 + dev_packet0 = 0 + + dev_type1 = 0 + dev_file1 = "" + dev_size1 = 0 + dev_packet1 = 0 +end +*/ +

release-0.9/sw/support/orp.cfg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/orp.ld =================================================================== --- release-0.9/sw/support/orp.ld (nonexistent) +++ release-0.9/sw/support/orp.ld (revision 42) @@ -0,0 +1,69 @@ +/* +MEMORY + { + vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000 + flash : ORIGIN = 0x04000000, LENGTH = 0x00200000 + ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000 + icm : ORIGIN = 0x00800000, LENGTH = 0x00004000 + } + */ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

release-0.9/sw/support/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/uart.h =================================================================== --- release-0.9/sw/support/uart.h (nonexistent) +++ release-0.9/sw/support/uart.h (revision 42) @@ -0,0 +1,122 @@ + +void uart_init(void); +void uart_putc(char); +char uart_getc(void); + +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_EFR 2 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_SCR 7 /* I/O: Scratch Register */ + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_TOI 0x0c /* Receive time out interrupt */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */ +

release-0.9/sw/support/uart.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sw/support/vfnprintf.h =================================================================== --- release-0.9/sw/support/vfnprintf.h (nonexistent) +++ release-0.9/sw/support/vfnprintf.h (revision 42) @@ -0,0 +1,2 @@ + +int vfnprintf ( char *stream, size_t n, const char *format, va_list arg);

release-0.9/sw/support/vfnprintf.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/run/start_server =================================================================== --- release-0.9/sim/run/start_server (nonexistent) +++ release-0.9/sim/run/start_server (revision 42) @@ -0,0 +1,2 @@ +#!/bin/sh +adv_jtag_bridge -x0 -l 0:4 -c 0x8 vpi

release-0.9/sim/run/start_server Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/run/run_bench =================================================================== --- release-0.9/sim/run/run_bench (nonexistent) +++ release-0.9/sim/run/run_bench (revision 42) @@ -0,0 +1,2 @@ +#!/bin/sh +vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name=$1

release-0.9/sim/run/run_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/run/generate_bench =================================================================== --- release-0.9/sim/run/generate_bench (nonexistent) +++ release-0.9/sim/run/generate_bench (revision 42) @@ -0,0 +1,2 @@ +#!/bin/sh +iverilog -c ../bin/minsoc_model.txt -o minsoc_bench

release-0.9/sim/run/generate_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/bin/minsoc_model.txt =================================================================== --- release-0.9/sim/bin/minsoc_model.txt (nonexistent) +++ release-0.9/sim/bin/minsoc_model.txt (revision 42) @@ -0,0 +1,138 @@ ++incdir+../../bench/verilog ++incdir+../../bench/verilog/vpi ++incdir+../../bench/verilog/sim_lib ++incdir+../../rtl/verilog ++incdir+../../rtl/verilog/minsoc_startup ++incdir+../../rtl/verilog/or1200/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl ++incdir+../../rtl/verilog/uart16550/rtl/verilog ++incdir+../../rtl/verilog/ethmac/rtl/verilog +../../bench/verilog/minsoc_bench_defines.v +../../bench/verilog/minsoc_bench.v +../../bench/verilog/minsoc_memory_model.v +../../bench/verilog/vpi/dbg_comm_vpi.v +../../bench/verilog/sim_lib/fpga_memory_primitives.v +../../rtl/verilog/minsoc_top.v +../../rtl/verilog/minsoc_startup/spi_top.v +../../rtl/verilog/minsoc_startup/spi_defines.v +../../rtl/verilog/minsoc_startup/spi_shift.v +../../rtl/verilog/minsoc_startup/spi_clgen.v +../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v +../../rtl/verilog/minsoc_tc_top.v +../../rtl/verilog/minsoc_onchip_ram.v +../../rtl/verilog/minsoc_clock_manager.v +#../../rtl/verilog/minsoc_onchip_ram_top.v +../../rtl/verilog/minsoc_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_du.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v +../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v +../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v +../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v +../../rtl/verilog/or1200/rtl/verilog/or1200_if.v +../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v +../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_except.v +../../rtl/verilog/or1200/rtl/verilog/or1200_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v +../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v +../../rtl/verilog/uart16550/rtl/verilog/uart_top.v +../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v +../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v +../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v +../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v +../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v +../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v +../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v +../../rtl/verilog/uart16550/rtl/verilog/raminfr.v +../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v +../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v +../../rtl/verilog/ethmac/rtl/verilog/eth_top.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v +../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v +../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v +../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v +../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v +../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v +../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v +../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v +../../rtl/verilog/ethmac/rtl/verilog/eth_random.v +../../rtl/verilog/ethmac/rtl/verilog/eth_register.v +../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v +../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

release-0.9/sim/bin/minsoc_model.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/bin/minsoc_memory.txt =================================================================== --- release-0.9/sim/bin/minsoc_memory.txt (nonexistent) +++ release-0.9/sim/bin/minsoc_memory.txt (revision 42) @@ -0,0 +1,138 @@ ++incdir+../../bench/verilog ++incdir+../../bench/verilog/vpi ++incdir+../../bench/verilog/sim_lib ++incdir+../../rtl/verilog ++incdir+../../rtl/verilog/minsoc_startup ++incdir+../../rtl/verilog/or1200/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl ++incdir+../../rtl/verilog/uart16550/rtl/verilog ++incdir+../../rtl/verilog/ethmac/rtl/verilog +../../bench/verilog/minsoc_bench_defines.v +../../bench/verilog/minsoc_bench.v +#../../bench/verilog/minsoc_memory_model.v +../../bench/verilog/vpi/dbg_comm_vpi.v +../../bench/verilog/sim_lib/fpga_memory_primitives.v +../../rtl/verilog/minsoc_top.v +../../rtl/verilog/minsoc_startup/spi_top.v +../../rtl/verilog/minsoc_startup/spi_defines.v +../../rtl/verilog/minsoc_startup/spi_shift.v +../../rtl/verilog/minsoc_startup/spi_clgen.v +../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v +../../rtl/verilog/minsoc_tc_top.v +../../rtl/verilog/minsoc_onchip_ram.v +../../rtl/verilog/minsoc_clock_manager.v +../../rtl/verilog/minsoc_onchip_ram_top.v +../../rtl/verilog/minsoc_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_du.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v +../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v +../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v +../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v +../../rtl/verilog/or1200/rtl/verilog/or1200_if.v +../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v +../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_except.v +../../rtl/verilog/or1200/rtl/verilog/or1200_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v +../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v +../../rtl/verilog/uart16550/rtl/verilog/uart_top.v +../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v +../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v +../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v +../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v +../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v +../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v +../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v +../../rtl/verilog/uart16550/rtl/verilog/raminfr.v +../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v +../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v +../../rtl/verilog/ethmac/rtl/verilog/eth_top.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v +../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v +../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v +../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v +../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v +../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v +../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v +../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v +../../rtl/verilog/ethmac/rtl/verilog/eth_random.v +../../rtl/verilog/ethmac/rtl/verilog/eth_register.v +../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v +../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

release-0.9/sim/bin/minsoc_memory.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/sim/results/wave.do.sav =================================================================== --- release-0.9/sim/results/wave.do.sav (nonexistent) +++ release-0.9/sim/results/wave.do.sav (revision 42) @@ -0,0 +1,49 @@ +[size] 1280 1001 +[pos] -1 -1 +*-29.000000 16828000000 285000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] minsoc_bench. +[treeopen] minsoc_bench.minsoc_top_0. +@28 +minsoc_bench.reset +minsoc_bench.minsoc_top_0.or1200_top.iwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.iwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.iwb_dat_i[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.iwb_ack_i +minsoc_bench.minsoc_top_0.or1200_top.dwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.dwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.dwb_dat_o[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.dwb_ack_i +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_sprs.sr[15:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_dataa[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_datab[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag_we +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.result[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.alu_op[3:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_a[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_b[31:0] +@28 +minsoc_bench.uart_stx +minsoc_bench.minsoc_top_0.uart_top.wb_cyc_i +minsoc_bench.minsoc_top_0.uart_top.wb_stb_i +minsoc_bench.minsoc_top_0.uart_top.wb_we_i +@22 +minsoc_bench.minsoc_top_0.uart_top.wb_adr_i[4:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_i[7:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_o[7:0] +@28 +minsoc_bench.minsoc_top_0.uart_top.wb_ack_o +minsoc_bench.minsoc_top_0.spi_flash_ss[1:0] +minsoc_bench.minsoc_top_0.spi_flash_sclk +minsoc_bench.minsoc_top_0.spi_flash_miso

release-0.9/sim/results/wave.do.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_top.v =================================================================== --- release-0.9/rtl/verilog/minsoc_top.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_top.v (revision 42) @@ -0,0 +1,994 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire dbg_we; +wire dbg_stb; +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [`OR1200_PIC_INTS-1:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) + rif_ack_int <= 1'b1; + + if ( rif_ack_int == 1'b1 ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b0; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_stb ), + .cpu0_we_o ( dbg_we ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_i(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_stb ), + .dbg_we_i ( dbg_we ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +minsoc_onchip_ram_top # +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; + +assign pic_ints[`APP_INT_UART] = 1'b0; +`endif + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +eth_top eth_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; +assign wb_es_err_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; + +assign pic_ints[`APP_INT_ETH] = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_RES1, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( ), + .t7_wb_stb_o ( ), + .t7_wb_adr_o ( ), + .t7_wb_sel_o ( ), + .t7_wb_we_o ( ), + .t7_wb_dat_o ( ), + .t7_wb_dat_i ( 32'h0000_0000 ), + .t7_wb_ack_i ( 1'b0 ), + .t7_wb_err_i ( 1'b1 ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule

release-0.9/rtl/verilog/minsoc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_defines.v =================================================================== --- release-0.9/rtl/verilog/minsoc_defines.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_defines.v (revision 42) @@ -0,0 +1,117 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif

release-0.9/rtl/verilog/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_startup/spi_top.v =================================================================== --- release-0.9/rtl/verilog/minsoc_startup/spi_top.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_startup/spi_top.v (revision 42) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_top + ( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i + ); + + parameter divider_len = 2; + parameter divider = 0; + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:2] wb_adr_i; // lower address bits + input [31:0] wb_dat_i; // databus input + output [31:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [31:0] wb_dat_o; + reg wb_ack_o; + + // Internal signals + // reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + + wire [5:0] char_len; + reg char_len_ctrl; // char len + reg go; // go + + wire spi_ctrl_sel; // ctrl register select + wire spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire lsb; // lsb first on line + wire ass; // automatic slave select + + // Address decoder + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + case (wb_adr_i[`SPI_OFS_BITS]) + `SPI_RX_0: wb_dat_o <= rx; + `SPI_CTRL: wb_dat_o <= {18'd0, ctrl}; + `SPI_DEVIDE: wb_dat_o <= divider; + `SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat_o <= rx; + endcase + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + {go,char_len_ctrl} <= #Tp 2'b01; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + char_len_ctrl <= #Tp wb_dat_i[5]; + if (wb_sel_i[1]) + go <= #Tp wb_dat_i[8]; + end + else if(tip && last_bit && pos_edge) + go <= #Tp 1'b0; + end + + assign char_len = char_len_ctrl ? 6'd32 : 6'd8; +`ifdef SPI_CTRL_ASS + assign ass = 1'b1; +`else + assign ass = 1'b0; +`endif +`ifdef SPI_CTRL_LSB + assign lsb = 1'b1; +`else + assign lsb = 1'b0; +`endif +`ifdef SPI_CTRL_RX_NEGEDGE + assign rx_negedge = 1'b1; +`else + assign rx_negedge = 1'b0; +`endif +`ifdef SPI_CTRL_TX_NEGEDGE + assign tx_negedge = 1'b1; +`else + assign tx_negedge = 1'b0; +`endif + + assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len}; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_flash_clgen + # + ( + .divider_len(divider_len), + .divider(divider) + ) + clgen + ( + .clk_in(wb_clk_i), + .rst(wb_rst_i), + .go(go), + .enable(tip), + .last_clk(last_bit), + .clk_out(sclk_pad_o), + .pos_edge(pos_edge), + .neg_edge(neg_edge) + ); + + spi_flash_shift shift + ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel & wb_we_i), + .byte_sel(wb_sel_i), + .go(go), + .pos_edge(pos_edge), + .neg_edge(neg_edge), + .lsb(lsb), + .rx_negedge(rx_negedge), + .tx_negedge(tx_negedge), + .tip(tip), + .last(last_bit), + .p_in(wb_dat_i), + .p_out(rx), + .s_clk(sclk_pad_o), + .s_in(miso_pad_i), + .s_out(mosi_pad_o) + ); + +endmodule +

release-0.9/rtl/verilog/minsoc_startup/spi_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_startup/spi_clgen.v =================================================================== --- release-0.9/rtl/verilog/minsoc_startup/spi_clgen.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_startup/spi_clgen.v (revision 42) @@ -0,0 +1,110 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge); + + parameter divider_len = 2; + parameter divider = 1; + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + //input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [divider_len-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {divider_len{1'b0}}; + assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {divider_len{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule

release-0.9/rtl/verilog/minsoc_startup/spi_clgen.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_startup/spi_shift.v =================================================================== --- release-0.9/rtl/verilog/minsoc_startup/spi_shift.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_startup/spi_shift.v (revision 42) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_shift + ( + clk, rst, latch, byte_sel, len, go, + pos_edge, neg_edge, + lsb, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input tx_negedge; + input rx_negedge; + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + if (rst) + data <= #Tp `SPI_CHAR_RST; + else + if (latch & !tip) + begin + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + end + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + +endmodule +

release-0.9/rtl/verilog/minsoc_startup/spi_shift.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_startup/spi_defines.v =================================================================== --- release-0.9/rtl/verilog/minsoc_startup/spi_defines.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_startup/spi_defines.v (revision 42) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 4 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +//`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 6 + `define SPI_CHAR_RST 32'h03000000 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB 2 // Can be set from 1 to 2 + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 +`define SPI_CTRL_BIT_RST 14'h420 +// +// Control register bits +// +//`define SPI_CTRL_LSB +`define SPI_CTRL_TX_NEGEDGE +//`define SPI_CTRL_RX_NEGEDGE +

release-0.9/rtl/verilog/minsoc_startup/spi_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_startup/OR1K_startup_generic.v =================================================================== --- release-0.9/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (revision 42) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module OR1K_startup + ( + input [6:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + input wb_clk, + input wb_rst + ); + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_dat_o <= 32'h15000000; + else + case (wb_adr_i) + 0 : wb_dat_o <= 32'h18000000; + 1 : wb_dat_o <= 32'hA8200000; + 2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 }; + 3 : wb_dat_o <= 32'hA8A00520; + 4 : wb_dat_o <= 32'hA8600001; + 5 : wb_dat_o <= 32'h04000014; + 6 : wb_dat_o <= 32'hD4041818; + 7 : wb_dat_o <= 32'h04000012; + 8 : wb_dat_o <= 32'hD4040000; + 9 : wb_dat_o <= 32'hE0431804; + 10 : wb_dat_o <= 32'h0400000F; + 11 : wb_dat_o <= 32'h9C210008; + 12 : wb_dat_o <= 32'h0400000D; + 13 : wb_dat_o <= 32'hE1031804; + 14 : wb_dat_o <= 32'hE4080000; + 15 : wb_dat_o <= 32'h0FFFFFFB; + 16 : wb_dat_o <= 32'hD4081800; + 17 : wb_dat_o <= 32'h04000008; + 18 : wb_dat_o <= 32'h9C210004; + 19 : wb_dat_o <= 32'hD4011800; + 20 : wb_dat_o <= 32'hE4011000; + 21 : wb_dat_o <= 32'h0FFFFFFC; + 22 : wb_dat_o <= 32'hA8C00100; + 23 : wb_dat_o <= 32'h44003000; + 24 : wb_dat_o <= 32'hD4040018; + 25 : wb_dat_o <= 32'hD4042810; + 26 : wb_dat_o <= 32'h84640010; + 27 : wb_dat_o <= 32'hBC030520; + 28 : wb_dat_o <= 32'h13FFFFFE; + 29 : wb_dat_o <= 32'h15000000; + 30 : wb_dat_o <= 32'h44004800; + 31 : wb_dat_o <= 32'h84640000; + endcase + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; + +endmodule // OR1K_startup

release-0.9/rtl/verilog/minsoc_startup/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_tc_top.v =================================================================== --- release-0.9/rtl/verilog/minsoc_tc_top.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_tc_top.v (revision 42) @@ -0,0 +1,1684 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i) + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, + t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, + t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, + t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, + t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, + t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, + t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, + t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule

release-0.9/rtl/verilog/minsoc_tc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_onchip_ram.v =================================================================== --- release-0.9/rtl/verilog/minsoc_onchip_ram.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_onchip_ram.v (revision 42) @@ -0,0 +1,458 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This block is a wrapper with common single-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// single-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Single-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage Single-Port Sync RAM //// +//// - Virtual Silicon Single-Port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// +//// - Altera LPM //// +//// //// +//// To Do: //// +//// - fix avant! two-port ram //// +//// - add additional RAMs //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// +// Revision 2.1 2009/08/23 16:41:00 fajardo +// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY +// This actually models appropriately the behavior of the FPGA internal RAMs +// +// Revision 2.0 2009/09/10 11:30:00 fajardo +// Added tri-state buffering for altera output +// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY +// +// Revision 1.9 2009/08/18 15:15:00 fajardo +// Added tri-state buffering for xilinx and generic memory output +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2004/06/08 18:15:32 lampret +// Changed behavior of the simulation generic models +// +// Revision 1.7 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.3.4.1 2003/12/09 11:46:48 simons +// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. +// +// Revision 1.3 2003/04/07 01:19:07 lampret +// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. +// +// Revision 1.2 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "minsoc_defines.v" + +module minsoc_onchip_ram( +`ifdef BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, doq +); + +// +// Default address and data buses width +// +parameter aw = 11; +parameter dw = 8; + +`ifdef BIST +// +// RAM BIST +// +input mbist_si_i; +input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Generic synchronous single-port RAM interface +// +input clk; // Clock +input rst; // Reset +input ce; // Chip enable input +input we; // Write enable input +input oe; // Output enable input +input [aw-1:0] addr; // address bus inputs +input [dw-1:0] di; // input data bus +output [dw-1:0] doq; // output data bus + +// +// Decide memory implementation for Xilinx FPGAs +// +`ifdef SPARTAN2 + `define MINSOC_XILINX_RAMB4 +`elsif VIRTEX + `define MINSOC_XILINX_RAMB4 +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3E + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3A + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX2 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX4 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX5 + `define MINSOC_XILINX_RAMB16 +`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5 + + +// +// Internal wires and registers +// + +`ifdef ARTISAN_SSP +`else +`ifdef VIRTUALSILICON_SSP +`else +`ifdef BIST +assign mbist_so_o = mbist_si_i; +`endif +`endif +`endif + + +`ifdef GENERIC_MEMORY +// +// Generic single-port synchronous RAM model +// + +// +// Generic RAM's registers and wires +// +reg [dw-1:0] mem [(1<

release-0.9/rtl/verilog/minsoc_onchip_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_onchip_ram_top.v =================================================================== --- release-0.9/rtl/verilog/minsoc_onchip_ram_top.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_onchip_ram_top.v (revision 42) @@ -0,0 +1,259 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// + + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule

release-0.9/rtl/verilog/minsoc_onchip_ram_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_clock_manager.v =================================================================== --- release-0.9/rtl/verilog/minsoc_clock_manager.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_clock_manager.v (revision 42) @@ -0,0 +1,255 @@ + +`include "minsoc_defines.v" + +module minsoc_clock_manager( + clk_i, + clk_o +); + +// +// Parameters +// +parameter divisor = 5; + +input clk_i; +output clk_o; + +`ifdef NO_CLOCK_DIVISION +assign clk_o = clk_i; + +`elsif GENERIC_CLOCK_DIVISION +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; +`elsif FPGA_CLOCK_DIVISION + +`ifdef ALTERA_FPGA +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; + +`elsif XILINX_FPGA + +`ifdef SPARTAN2 + `define MINSOC_DLL +`elsif VIRTEX + `define MINSOC_DLL +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define MINSOC_DCM +`elsif VIRTEX2 + `define MINSOC_DCM +`endif // !SPARTAN3/VIRTEX2 + +`ifdef SPARTAN3E + `define MINSOC_DCM_SP +`elsif SPARTAN3A + `define MINSOC_DCM_SP +`endif // !SPARTAN3E/SPARTAN3A + +`ifdef VIRTEX4 + `define MINSOC_DCM_ADV + `define MINSOC_DCM_COMPONENT "VIRTEX4" +`elsif VIRTEX5 + `define MINSOC_DCM_ADV + `define MINSOC_DCM_COMPONENT "VIRTEX5" +`endif // !VIRTEX4/VIRTEX5 + +wire CLKIN_IN; +wire CLKDV_OUT; + +assign CLKIN_IN = clk_i; +assign clk_o = CLKDV_OUT; + +wire CLKIN_IBUFG; +wire CLK0_BUF; +wire CLKFB_IN; +wire CLKDV_BUF; + +IBUFG CLKIN_IBUFG_INST ( + .I(CLKIN_IN), + .O(CLKIN_IBUFG) +); + +BUFG CLK0_BUFG_INST ( + .I(CLK0_BUF), + .O(CLKFB_IN) +); + +BUFG CLKDV_BUFG_INST ( + .I(CLKDV_BUF), + .O(CLKDV_OUT) +); + +`ifdef MINSOC_DLL + +CLKDLL #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0 + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF Values + .STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE +) CLKDLL_inst ( + .CLK0(CLK0_BUF), // 0 degree DLL CLK output + .CLK180(), // 180 degree DLL CLK output + .CLK270(), // 270 degree DLL CLK output + .CLK2X(), // 2X DLL CLK output + .CLK90(), // 90 degree DLL CLK output + .CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE) + .LOCKED(), // DLL LOCK status output + .CLKFB(CLKFB_IN), // DLL clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL) + .RST(1'b0) // DLL asynchronous reset input +); + +`elsif MINSOC_DCM + +DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF values + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif MINSOC_DCM_SP + +DCM_SP #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_SP_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif MINSOC_DCM_ADV + +DCM_ADV #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED, + // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE" + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE" + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5" + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE" +) DCM_ADV_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP) + .DRDY(), // Ready output signal from the DRP + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .DADDR(7'h00), // 7-bit address for the DRP + .DCLK(1'b0), // Clock for the DRP + .DEN(1'b0), // Enable input for the DRP + .DI(16'h0000), // 16-bit data input for the DRP + .DWE(1'b0), // Active high allows for writing configuration memory + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV +`endif // !ALTERA_FPGA/XILINX_FPGA +`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION + + +endmodule

release-0.9/rtl/verilog/minsoc_clock_manager.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-0.9/rtl/verilog/minsoc_xilinx_internal_jtag.v =================================================================== --- release-0.9/rtl/verilog/minsoc_xilinx_internal_jtag.v (nonexistent) +++ release-0.9/rtl/verilog/minsoc_xilinx_internal_jtag.v (revision 42) @@ -0,0 +1,441 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// xilinx_internal_jtag.v //// +//// //// +//// //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// // +// This file is a wrapper for the various Xilinx internal BSCAN // +// TAP devices. It is designed to take the place of a separate TAP // +// controller in Xilinx systems, to allow a user to access a CPU // +// debug module (such as that of the OR1200) through the FPGA's // +// dedicated JTAG / configuration port. // +// // +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xilinx_internal_jtag.v,v $ +// Revision 1.3 2009/06/16 02:54:23 Nathan +// Changed some signal names for better consistency between different hardware modules. +// +// Revision 1.2 2009/05/17 20:54:16 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/18 20:07:32 Nathan +// Changed the directory structure to match existing projects. +// +// Revision 1.4 2008/07/11 08:26:10 Nathan +// Ran through dos2unix +// +// Revision 1.3 2008/07/11 08:25:52 Nathan +// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4. +// +// Revision 1.2 2008/06/09 19:34:14 Nathan +// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools. +// +// Revision 1.1 2008/05/22 19:54:07 Nathan +// Initial version +// + + +`include "minsoc_defines.v" + +// Note that the SPARTAN BSCAN controllers have more than one channel. +// This implementation always uses channel 1, this is not configurable. +// If you want to use another channel, then it is probably because you +// want to attach multiple devices to the BSCAN device, which means +// you'll be making changes to this file anyway. +// Virtex BSCAN devices are instantiated separately for each channel. +// To select something other than the default (1), change