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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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    /minsoc/trunk/backend
    from Rev 15 to Rev 40
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Rev 15 → Rev 40

/ml509.ucf
0,0 → 1,45
NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
 
## #------------------------------------------------------------------------------
## # IO Pad Location Constraints / Properties for Ethernet
## #------------------------------------------------------------------------------
 
#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25;
#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
 
#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25;
#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy
#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33;
#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33;
#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33;
#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33;
#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33;
#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33;
 
## PHY Serial Management Interface pins
#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25;
#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25;
 
## # Timing Constraints (these are recommended in documentation and
## # are unaltered except for the TIG)
#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP";
#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP";
#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
 
## # Timing ignores (to specify unconstrained paths)
#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock
#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;

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