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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/bench
    from Rev 69 to Rev 71
    Reverse comparison

Rev 69 → Rev 71

/verilog/minsoc_memory_model.v
51,6 → 51,7
// Created interface and tested
//
 
`include "timescale.v"
 
module minsoc_memory_model (
wb_clk_i, wb_rst_i,
/verilog/minsoc_bench.v
2,6 → 2,8
`include "minsoc_defines.v"
`include "or1200_defines.v"
 
`include "timescale.v"
 
module minsoc_bench();
 
`ifdef POSITIVE_RESET
/verilog/vpi/dbg_comm_vpi.v
74,6 → 74,7
//
//
 
`include "timescale.v"
 
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.

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