OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/prj/sim
    from Rev 97 to Rev 91
    ↔ Reverse comparison
  •

Rev 97 → Rev 91

/minsoc_top.src
0,0 → 1,22
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
/minsoc.src
0,0 → 1,149
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v
/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
/uart_top.src
0,0 → 1,12
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v
/adbg_top.src
0,0 → 1,11
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/ethmac.src
0,0 → 1,26
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
/or1200_top.src
0,0 → 1,64
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
/jtag_top.src
0,0 → 1,3
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v

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