URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/prj/src
- from Rev 141 to Rev 158
- ↔ Reverse comparison
Rev 141 → Rev 158
/minsoc_top.prj
1,6 → 1,7
PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog) |
PROJECT_SRC=(minsoc_defines.v |
timescale.v |
interconnect_defines.v |
minsoc_top.v |
minsoc_tc_top.v |
minsoc_onchip_ram.v |
/adbg_top.prj
1,11 → 1,16
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog |
PROJECT_SRC=(adbg_wb_biu.v |
adbg_wb_module.v |
adbg_or1k_module.v |
adbg_wb_defines.v |
PROJECT_SRC=(adbg_crc32.v |
adbg_defines.v |
adbg_crc32.v |
adbg_jsp_biu.v |
adbg_jsp_module.v |
adbg_or1k_biu.v |
adbg_or1k_defines.v |
adbg_or1k_module.v |
adbg_or1k_status_reg.v |
adbg_top.v) |
adbg_top.v |
adbg_wb_biu.v |
adbg_wb_defines.v |
adbg_wb_module.v |
bytefifo.v |
syncflop.v |
syncreg.v) |