URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/sim
- from Rev 10 to Rev 2
- ↔ Reverse comparison
Rev 10 → Rev 2
/bin/minsoc_model_fast.txt
1,6 → 1,5
+incdir+../../bench/verilog |
+incdir+../../bench/verilog/vpi |
+incdir+../../bench/verilog/sim_lib |
+incdir+../../rtl/verilog |
+incdir+../../rtl/verilog/minsoc_startup |
+incdir+../../rtl/verilog/or1200/rtl/verilog |
16,7 → 15,6
#../../bench/verilog/eth_phy_defines.v |
#../../bench/verilog/eth_phy.v |
../../bench/verilog/vpi/dbg_comm_vpi.v |
../../bench/verilog/sim_lib/fpga_memory_primitives.v |
../../rtl/verilog/minsoc_top.v |
../../rtl/verilog/minsoc_startup/spi_top.v |
../../rtl/verilog/minsoc_startup/spi_defines.v |
/bin/minsoc_memory_complete.txt
1,6 → 1,5
+incdir+../../bench/verilog |
+incdir+../../bench/verilog/vpi |
+incdir+../../bench/verilog/sim_lib |
+incdir+../../rtl/verilog |
+incdir+../../rtl/verilog/minsoc_startup |
+incdir+../../rtl/verilog/or1200/rtl/verilog |
16,7 → 15,6
../../bench/verilog/eth_phy_defines.v |
../../bench/verilog/eth_phy.v |
../../bench/verilog/vpi/dbg_comm_vpi.v |
../../bench/verilog/sim_lib/fpga_memory_primitives.v |
../../rtl/verilog/minsoc_top.v |
../../rtl/verilog/minsoc_startup/spi_top.v |
../../rtl/verilog/minsoc_startup/spi_defines.v |
/bin/minsoc_memory_fast.txt
1,6 → 1,5
+incdir+../../bench/verilog |
+incdir+../../bench/verilog/vpi |
+incdir+../../bench/verilog/sim_lib |
+incdir+../../rtl/verilog |
+incdir+../../rtl/verilog/minsoc_startup |
+incdir+../../rtl/verilog/or1200/rtl/verilog |
16,7 → 15,6
#../../bench/verilog/eth_phy_defines.v |
#../../bench/verilog/eth_phy.v |
../../bench/verilog/vpi/dbg_comm_vpi.v |
../../bench/verilog/sim_lib/fpga_memory_primitives.v |
../../rtl/verilog/minsoc_top.v |
../../rtl/verilog/minsoc_startup/spi_top.v |
../../rtl/verilog/minsoc_startup/spi_defines.v |
/bin/minsoc_model_complete.txt
1,6 → 1,5
+incdir+../../bench/verilog |
+incdir+../../bench/verilog/vpi |
+incdir+../../bench/verilog/sim_lib |
+incdir+../../rtl/verilog |
+incdir+../../rtl/verilog/minsoc_startup |
+incdir+../../rtl/verilog/or1200/rtl/verilog |
16,7 → 15,6
../../bench/verilog/eth_phy_defines.v |
../../bench/verilog/eth_phy.v |
../../bench/verilog/vpi/dbg_comm_vpi.v |
../../bench/verilog/sim_lib/fpga_memory_primitives.v |
../../rtl/verilog/minsoc_top.v |
../../rtl/verilog/minsoc_startup/spi_top.v |
../../rtl/verilog/minsoc_startup/spi_defines.v |