URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/syn/buildSupport
- from Rev 64 to Rev 63
- ↔ Reverse comparison
Rev 64 → Rev 63
/eth_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"} |
-ifn ./buildSupport/eth_top.prj |
-ifmt Verilog |
-ofn eth_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top eth_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/or1200_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"} |
-ifn ./buildSupport/or1200_top.prj |
-ifmt Verilog |
-ofn or1200_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top or1200_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/minsoc_top.prj
1,5 → 1,5
`include "../backend/minsoc_defines.v" |
`include "../rtl/verilog/minsoc_xilinx_internal_jtag.v" |
`include "../rtl/verilog/minsoc_defines.v" |
`include "../rtl/verilog/minsoc_clock_manager.v" |
`include "../rtl/verilog/altera_pll.v" |
`include "../rtl/verilog/minsoc_tc_top.v" |
7,12 → 7,8
`include "../rtl/verilog/minsoc_top.v" |
`include "../rtl/verilog/minsoc_onchip_ram.v" |
`include "../rtl/verilog/xilinx_dcm.v" |
`include "../rtl/verilog/minsoc_startup/spi_shift.v" |
`include "../rtl/verilog/minsoc_startup/spi_clgen.v" |
`include "../rtl/verilog/minsoc_startup/spi_top.v" |
`include "../rtl/verilog/minsoc_startup/spi_defines.v" |
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" |
`include "./blackboxes/adbg_top.v" |
`include "./blackboxes/eth_top.v" |
`include "./blackboxes/uart_top.v" |
`include "./blackboxes/or1200_top.v" |
`include "./blackboxes/or1200_top.v" |
`include "./blackboxes/OR1K_startup_generic.v" |
/minsoc_startup_top.prj
0,0 → 1,5
`include "../rtl/verilog/minsoc_startup/spi_shift.v" |
`include "../rtl/verilog/minsoc_startup/spi_clgen.v" |
`include "../rtl/verilog/minsoc_startup/spi_top.v" |
`include "../rtl/verilog/minsoc_startup/spi_defines.v" |
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" |
/minsoc_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"} |
-ifn ./buildSupport/minsoc_top.prj |
-ifmt Verilog |
-ofn minsoc_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top minsoc_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf yes |
/minsoc_startup_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/" "../rtl/verilog/minsoc_startup/" "../rtl/verilog/or1200/rtl/verilog"} |
-ifn ./buildSupport/minsoc_startup_top.prj |
-ifmt Verilog |
-ofn minsoc_startup_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top OR1K_startup |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/uart_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"} |
-ifn ./buildSupport/uart_top.prj |
-ifmt Verilog |
-ofn uart_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top uart_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/adbg_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"} |
-ifn ./buildSupport/adbg_top.prj |
-ifmt Verilog |
-ofn adbg_top |
-ofmt NGC |
-p xc3sd1800a-4-fg676 |
-top adbg_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |