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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/syn/buildSupport
    from Rev 85 to Rev 64
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  •

Rev 85 → Rev 64

/minsoc_top.prj
0,0 → 1,18
`include "../backend/minsoc_defines.v"
`include "../rtl/verilog/minsoc_xilinx_internal_jtag.v"
`include "../rtl/verilog/minsoc_clock_manager.v"
`include "../rtl/verilog/altera_pll.v"
`include "../rtl/verilog/minsoc_tc_top.v"
`include "../rtl/verilog/minsoc_onchip_ram_top.v"
`include "../rtl/verilog/minsoc_top.v"
`include "../rtl/verilog/minsoc_onchip_ram.v"
`include "../rtl/verilog/xilinx_dcm.v"
`include "../rtl/verilog/minsoc_startup/spi_shift.v"
`include "../rtl/verilog/minsoc_startup/spi_clgen.v"
`include "../rtl/verilog/minsoc_startup/spi_top.v"
`include "../rtl/verilog/minsoc_startup/spi_defines.v"
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
`include "./blackboxes/adbg_top.v"
`include "./blackboxes/eth_top.v"
`include "./blackboxes/uart_top.v"
`include "./blackboxes/or1200_top.v"
/or1200_top.prj
0,0 → 1,77
`include "../rtl/verilog/or1200/rtl/verilog/or1200_tt.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_div.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_du.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_div.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_pic.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_defines.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_rf.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_fcmp.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_except.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_sb.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_pre_norm_mul.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_pm.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_alu.v"
`include "../rtl/verilog/or1200/rtl/verilog/timescale.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_arith.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_mul.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_if.v"
`include "../rtl/verilog/or1200/rtl/verilog/or1200_fpu_addsub.v"
/uart_top.prj
0,0 → 1,12
`include "../rtl/verilog/uart16550/rtl/verilog/uart_wb.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_regs.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_defines.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v"
`include "../rtl/verilog/uart16550/rtl/verilog/raminfr.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v"
`include "../rtl/verilog/uart16550/rtl/verilog/timescale.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v"
`include "../rtl/verilog/uart16550/rtl/verilog/uart_top.v"
/adbg_top.prj
0,0 → 1,15
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncreg.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v"
`include "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncflop.v"
/eth_top.prj
0,0 → 1,27
`include "../rtl/verilog/ethmac/rtl/verilog/eth_miim.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_crc.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_register.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_random.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_top.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_registers.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_cop.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_defines.v"
`include "../rtl/verilog/ethmac/rtl/verilog/timescale.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v"
`include "../rtl/verilog/ethmac/rtl/verilog/xilinx_dist_ram_16x32.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v"
`include "../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v"

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