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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/syn
    from Rev 64 to Rev 63
    ↔ Reverse comparison
  •

Rev 64 → Rev 63

/src/minsoc_top.xst File deleted \ No newline at end of file
/src/uart_top.xst File deleted \ No newline at end of file
/src/adbg_top.xst File deleted \ No newline at end of file
/src/Makefile File deleted
/src/eth_top.xst File deleted \ No newline at end of file
/src/or1200_top.xst File deleted \ No newline at end of file
/buildSupport/eth_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"}
-ifn ./buildSupport/eth_top.prj
-ifmt Verilog
-ofn eth_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top eth_top
-opt_mode Speed
-opt_level 1
-iobuf no
/buildSupport/or1200_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"}
-ifn ./buildSupport/or1200_top.prj
-ifmt Verilog
-ofn or1200_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top or1200_top
-opt_mode Speed
-opt_level 1
-iobuf no
/buildSupport/minsoc_top.prj
1,5 → 1,5
`include "../backend/minsoc_defines.v"
`include "../rtl/verilog/minsoc_xilinx_internal_jtag.v"
`include "../rtl/verilog/minsoc_defines.v"
`include "../rtl/verilog/minsoc_clock_manager.v"
`include "../rtl/verilog/altera_pll.v"
`include "../rtl/verilog/minsoc_tc_top.v"
7,12 → 7,8
`include "../rtl/verilog/minsoc_top.v"
`include "../rtl/verilog/minsoc_onchip_ram.v"
`include "../rtl/verilog/xilinx_dcm.v"
`include "../rtl/verilog/minsoc_startup/spi_shift.v"
`include "../rtl/verilog/minsoc_startup/spi_clgen.v"
`include "../rtl/verilog/minsoc_startup/spi_top.v"
`include "../rtl/verilog/minsoc_startup/spi_defines.v"
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
`include "./blackboxes/adbg_top.v"
`include "./blackboxes/eth_top.v"
`include "./blackboxes/uart_top.v"
`include "./blackboxes/or1200_top.v"
`include "./blackboxes/or1200_top.v"
`include "./blackboxes/OR1K_startup_generic.v"
/buildSupport/minsoc_startup_top.prj
0,0 → 1,5
`include "../rtl/verilog/minsoc_startup/spi_shift.v"
`include "../rtl/verilog/minsoc_startup/spi_clgen.v"
`include "../rtl/verilog/minsoc_startup/spi_top.v"
`include "../rtl/verilog/minsoc_startup/spi_defines.v"
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
/buildSupport/minsoc_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"}
-ifn ./buildSupport/minsoc_top.prj
-ifmt Verilog
-ofn minsoc_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top minsoc_top
-opt_mode Speed
-opt_level 1
-iobuf yes
/buildSupport/minsoc_startup_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/" "../rtl/verilog/minsoc_startup/" "../rtl/verilog/or1200/rtl/verilog"}
-ifn ./buildSupport/minsoc_startup_top.prj
-ifmt Verilog
-ofn minsoc_startup_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top OR1K_startup
-opt_mode Speed
-opt_level 1
-iobuf no
/buildSupport/uart_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"}
-ifn ./buildSupport/uart_top.prj
-ifmt Verilog
-ofn uart_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top uart_top
-opt_mode Speed
-opt_level 1
-iobuf no
/buildSupport/adbg_top.xst
0,0 → 1,12
set -tmpdir "./xst"
run
-vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"}
-ifn ./buildSupport/adbg_top.prj
-ifmt Verilog
-ofn adbg_top
-ofmt NGC
-p xc3sd1800a-4-fg676
-top adbg_top
-opt_mode Speed
-opt_level 1
-iobuf no
/blackboxes/OR1K_startup_generic.v
0,0 → 1,15
 
`include "minsoc_defines.v"
 
module OR1K_startup
(
input [6:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
input wb_clk,
input wb_rst
);
endmodule // OR1K_startup
blackboxes/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 63) @@ -0,0 +1,133 @@ +ROOT = /home/rfajardo/ongoing/or1k/risc_raul +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +MINSOC_STARTUP_RTL = $(MINSOC_RTL)/minsoc_startup +UART_RTL = $(MINSOC_RTL)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(MINSOC_RTL)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +OR1200_RTL = $(MINSOC_RTL)/or1200/rtl/verilog +ETH_RTL = $(MINSOC_RTL)/ethmac/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " or1200: Synthesize the OR1200 processor" + @echo " debug: Synthesize the debug interface" + @echo " uart: Synthesize the UART" + @echo " eth: Synthesize the ethernet controller" + @echo " startup: Synthesize the modules to automatically start-up the firmware on power on" + +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -rf _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -rf _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + mkdir xst + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst + +startup: minsoc_startup_top.ngc +minsoc_startup_top.ngc: $(MINSOC_STARTUP_RTL)/*.v buildSupport/minsoc_startup_top.xst buildSupport/minsoc_startup_top.prj + mkdir xst + xst -ifn "buildSupport/minsoc_startup_top.xst" + rm -f minsoc_startup_top_xst.xrpt + rm -f minsoc_startup_top.srp + rm -f minsoc_startup_top.lso + rm -rf _xmsgs + rm -rf xst + +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + mkdir xst + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst + +eth: eth_top.ngc +eth_top.ngc: $(ETH_RTL)/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj + mkdir xst + xst -ifn "buildSupport/eth_top.xst" + rm -f eth_top_xst.xrpt + rm -f eth_top.srp + rm -f eth_top.lso + rm -rf _xmsgs + rm -rf xst + +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + mkdir xst + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst + +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + mkdir xst + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst + +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc3sd1800a-4-fg676 -uc $(MINSOC)/backend/spartan3a_dsp_kit.ucf -aul minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs + +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs + +minsoc_par.ncd: minsoc.ncd + par -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs + +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs

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