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    /minsoc
    from Rev 173 to Rev 172
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Rev 173 → Rev 172

/trunk/backend/nexys3/nexys3_master.ucf File deleted
/trunk/backend/nexys3/configure File deleted
trunk/backend/nexys3/configure Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/nexys3/gcc-opt.mk =================================================================== --- trunk/backend/nexys3/gcc-opt.mk (revision 173) +++ trunk/backend/nexys3/gcc-opt.mk (nonexistent) @@ -1 +0,0 @@ -GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: trunk/backend/nexys3/minsoc_bench_defines.v =================================================================== --- trunk/backend/nexys3/minsoc_bench_defines.v (revision 173) +++ trunk/backend/nexys3/minsoc_bench_defines.v (nonexistent) @@ -1,29 +0,0 @@ -//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) -`define GENERIC_FPGA -`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. -`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) -//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) - -`define FREQ_NUM_FOR_NS 100000000 - -`define FREQ 25000000 -`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) - -`define ETH_PHY_FREQ 25000000 -`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns - -`define UART_BAUDRATE 115200 - -`define VPI_DEBUG - -//`define WAVEFORM_OUTPUT - -//`define START_UP //pass firmware over spi to or1k_startup - -`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware - //only use with the memory model. - //If you use the original memory (`define MEMORY_MODEL - //commented out), comment this too. - -`define TEST_UART -//`define TEST_ETHERNET
trunk/backend/nexys3/minsoc_bench_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/nexys3/minsoc_defines.v =================================================================== --- trunk/backend/nexys3/minsoc_defines.v (revision 173) +++ trunk/backend/nexys3/minsoc_defines.v (nonexistent) @@ -1,126 +0,0 @@ -// -// Define FPGA manufacturer -// -//`define GENERIC_FPGA -//`define ALTERA_FPGA -`define XILINX_FPGA - -// -// Define Xilinx FPGA family -// -`ifdef XILINX_FPGA -//`define SPARTAN2 -//`define SPARTAN3 -//`define SPARTAN3E -//`define SPARTAN3A -`define SPARTAN6 -//`define VIRTEX -//`define VIRTEX2 -//`define VIRTEX4 -//`define VIRTEX5 - -// -// Define Altera FPGA family -// -`elsif ALTERA_FPGA -//`define ARRIA_GX -//`define ARRIA_II_GX -//`define CYCLONE_I -//`define CYCLONE_II -`define CYCLONE_III -//`define CYCLONE_III_LS -//`define CYCLONE_IV_E -//`define CYCLONE_IV_GS -//`define MAX_II -//`define MAX_V -//`define MAX3000A -//`define MAX7000AE -//`define MAX7000B -//`define MAX7000S -//`define STRATIX -//`define STRATIX_II -//`define STRATIX_II_GX -//`define STRATIX_III -`endif - -// -// Memory -// -`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, - //memory is composed by blocks of address width 11 - //Address width of memory -> select memory depth, - //2 powers MEMORY_ADR_WIDTH defines the memory depth - //the memory data width is 32 bit, - //memory amount in Bytes = 4*memory depth - -// -// Memory type (uncomment something if ASIC or generic memory) -// -//`define GENERIC_MEMORY -//`define AVANT_ATP -//`define VIRAGE_SSP -//`define VIRTUALSILICON_SSP - - -// -// TAP selection -// -//`define GENERIC_TAP -`define FPGA_TAP - -// -// Clock Division selection -// -//`define NO_CLOCK_DIVISION -//`define GENERIC_CLOCK_DIVISION -`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. - -// -// Define division -// -`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded - //down to an even value in FPGA case, check minsoc_clock_manager - //for allowed divisors. - //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION - //INSTEAD. - -// -// Reset polarity -// -`define NEGATIVE_RESET //rstn -//`define POSITIVE_RESET //rst - -// -// Start-up circuit (only necessary later to load firmware automatically from SPI memory) -// -//`define START_UP - -// -// Connected modules -// -`define UART -//`define JSP -//`define ETHERNET - -// -// Ethernet reset -// -//`define ETH_RESET 1'b0 -`define ETH_RESET 1'b1 - -// -// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen -// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set -// -`ifdef GENERIC_FPGA - `undef FPGA_TAP - `undef FPGA_CLOCK_DIVISION - `undef XILINX_FPGA - `undef SPARTAN6 - - `define GENERIC_TAP - `define GENERIC_MEMORY - `ifndef NO_CLOCK_DIVISION - `define GENERIC_CLOCK_DIVISION - `endif -`endif Index: trunk/backend/nexys3/board.h =================================================================== --- trunk/backend/nexys3/board.h (revision 173) +++ trunk/backend/nexys3/board.h (nonexistent) @@ -1,26 +0,0 @@ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define MC_ENABLED 0 - -#define IC_ENABLE 0 -#define IC_SIZE 8192 -#define DC_ENABLE 0 -#define DC_SIZE 8192 - - -#define IN_CLK 20000000 - - -#define STACK_SIZE 0x01000 - -#define UART_BAUD_RATE 19200 - -#define ETH_MACADDR0 0x00 -#define ETH_MACADDR1 0x12 -#define ETH_MACADDR2 0x34 -#define ETH_MACADDR3 0x56 -#define ETH_MACADDR4 0x78 -#define ETH_MACADDR5 0x9a - -#endif
trunk/backend/nexys3/board.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/nexys3/orp.ld =================================================================== --- trunk/backend/nexys3/orp.ld (revision 173) +++ trunk/backend/nexys3/orp.ld (nonexistent) @@ -1,60 +0,0 @@ -MEMORY - { - reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 - vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 - ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ - } - -SECTIONS -{ - .reset : - { - *(.reset) - } > reset - - - - .vectors : - { - _vec_start = .; - *(.vectors) - _vec_end = .; - } > vectors - - .text : - { - *(.text) - } > ram - - .rodata : - { - *(.rodata) - *(.rodata.*) - } > ram - - .icm : - { - _icm_start = .; - *(.icm) - _icm_end = .; - } > ram - - .data : - { - _dst_beg = .; - *(.data) - _dst_end = .; - } > ram - - .bss : - { - *(.bss) - } > ram - - .stack (NOLOAD) : - { - *(.stack) - _src_addr = .; - } > ram - -}
trunk/backend/nexys3/orp.ld Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/verilog/xilinx_dcm.v =================================================================== --- trunk/rtl/verilog/xilinx_dcm.v (revision 173) +++ trunk/rtl/verilog/xilinx_dcm.v (revision 172) @@ -31,8 +31,6 @@ `define XILINX_DCM_SP `elsif SPARTAN3A `define XILINX_DCM_SP -`elsif SPARTAN6 - `define XILINX_DCM_SP `endif // !SPARTAN3E/SPARTAN3A `ifdef VIRTEX4
/trunk/rtl/verilog/minsoc_onchip_ram.v
176,9 → 176,7
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN6
`define MINSOC_XILINX_RAMB16
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
 
 
//
/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v
251,39 → 251,7
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
 
 
//-----------------------------------------------------------------------
`else
`ifdef SPARTAN6
 
wire capture_dr_o;
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1) // Chain number.
)
BSCAN_SPARTAN6_inst (
.CAPTURE(capture_dr_o), // 1-bit Scan Data Register Capture instruction.
.DRCK(drck), // 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles during the CAPTUREDR and SHIFTDR states.
.RESET(test_logic_reset_o), // 1-bit Scan register reset instruction.
.RUNTEST(), // 1-bit Asserted when TAP controller is in Run Test Idle state. Make sure is the same name as BSCAN primitive used in Spartan products.
.SEL(debug_select_o), // 1-bit Scan mode Select instruction.
.SHIFT(shift_dr_o), // 1-bit Scan Chain Shift instruction.
.TCK(tck_o), // 1-bit Scan Clock. Fabric connection to TAP Clock pin.
.TDI(tdi_o), // 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA.
.TMS(), // 1-bit Test Mode Select. Fabric connection to TAP.
.UPDATE(update_dr_o), // 1-bit Scan Register Update instruction.
.TDO(debug_tdo_i) // 1-bit Scan Chain Input.
);
// End of BSCAN_SPARTAN6_inst instantiation
assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
 
 
 
`else
`ifdef VIRTEX
 
// Note that this version is missing three outputs.
468,8 → 436,6
`endif
`endif
`endif
`endif // !`ifdef SPARTAN3
`endif // !`ifdef SPARTAN2
`endif
 
endmodule

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