OpenCores

0,0 → 1,143

trunk/rtl/verilog/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/backend/ml509/ml509.ucf =================================================================== --- trunk/backend/ml509/ml509.ucf (revision 64) +++ trunk/backend/ml509/ml509.ucf (nonexistent) @@ -1,45 +0,0 @@ -NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI -NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors -NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI -NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI - -## #------------------------------------------------------------------------------ -## # IO Pad Location Constraints / Properties for Ethernet -## #------------------------------------------------------------------------------ - -#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; -#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; - -#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; -#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; -#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy -#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; -#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; -#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; -#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; -#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; -#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; - -## PHY Serial Management Interface pins -#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; -#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; - -## # Timing Constraints (these are recommended in documentation and -## # are unaltered except for the TIG) -#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; -#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; -#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; -#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; - -## # Timing ignores (to specify unconstrained paths) -#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock -#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; -#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; -#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; -#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: trunk/backend/spartan3e_starter_kit/board.h =================================================================== --- trunk/backend/spartan3e_starter_kit/board.h (revision 64) +++ trunk/backend/spartan3e_starter_kit/board.h (nonexistent) @@ -1,40 +0,0 @@ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define MC_ENABLED 0 - -#define IC_ENABLE 0 -#define IC_SIZE 8192 -#define DC_ENABLE 0 -#define DC_SIZE 8192 - - -#define IN_CLK 25000000 - - -#define STACK_SIZE 0x01000 - -#define UART_BAUD_RATE 115200 - -#define UART_BASE 0x90000000 -#define UART_IRQ 2 -#define ETH_BASE 0x92000000 -#define ETH_IRQ 4 -#define I2C_BASE 0x9D000000 -#define I2C_IRQ 3 -#define CAN_BASE 0x94000000 -#define CAN_IRQ 5 - -#define MC_BASE_ADDR 0x60000000 -#define SPI_BASE 0xa0000000 - -#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ - -#define ETH_MACADDR0 0x00 -#define ETH_MACADDR1 0x12 -#define ETH_MACADDR2 0x34 -#define ETH_MACADDR3 0x56 -#define ETH_MACADDR4 0x78 -#define ETH_MACADDR5 0x9a - -#endif

trunk/backend/spartan3e_starter_kit/board.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3e_starter_kit/orp.ld =================================================================== --- trunk/backend/spartan3e_starter_kit/orp.ld (revision 64) +++ trunk/backend/spartan3e_starter_kit/orp.ld (nonexistent) @@ -1,60 +0,0 @@ -MEMORY - { - reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 - vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 - ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ - } - -SECTIONS -{ - .reset : - { - *(.reset) - } > reset - - - - .vectors : - { - _vec_start = .; - *(.vectors) - _vec_end = .; - } > vectors - - .text : - { - *(.text) - } > ram - - .rodata : - { - *(.rodata) - *(.rodata.*) - } > ram - - .icm : - { - _icm_start = .; - *(.icm) - _icm_end = .; - } > ram - - .data : - { - _dst_beg = .; - *(.data) - _dst_end = .; - } > ram - - .bss : - { - *(.bss) - } > ram - - .stack (NOLOAD) : - { - *(.stack) - _src_addr = .; - } > ram - -}

trunk/backend/spartan3e_starter_kit/orp.ld Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3e_starter_kit/configure =================================================================== --- trunk/backend/spartan3e_starter_kit/configure (revision 64) +++ trunk/backend/spartan3e_starter_kit/configure (nonexistent) @@ -1,81 +0,0 @@ -#!/bin/bash - -#new boards have to udpate this -BOARD=spartan3e_starter_kit #this has to have the name of the directory this file is in -DEVICE_PART='xc3s500e-4-fg320' -CONSTRAINT_FILE='spartan3e_starter_kit.ucf' -#~new boards update - -#system workings -MINSOC_DIR=`pwd`/../.. -BACKEND_DIR=$MINSOC_DIR/backend -SYN_DIR=$MINSOC_DIR/syn -SYNSRC_DIR=$SYN_DIR/src -SYNSUPPORT_DIR=$SYN_DIR/buildSupport - -SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile) - -FIND_PART='DEVICE_PART' -FIND_CONSTRAINT='CONSTRAINT_FILE' - -BOARD_DIR=$BACKEND_DIR/$BOARD -BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE) - -in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` -if [ -z $in_minsoc ] -then - echo "" - echo " !!!WARNING!!!" - echo "This script cannot be run out of a board directory inside minsoc/backend," - echo "because it relies on the directory structure of the minsoc system." - echo "" - exit 1 -fi - -echo "" -echo "Configuring SoC board's specific files for firmware compilation, " -echo "testbench generation and synthesis." -echo "Firmware and testbench looks for board specific files under minsoc/backend." -echo "Synthesis work under minsoc/syn." -echo "" -echo "" - -if [ $CONSTRAINT_FILE == 'NONE' ] -then - echo "Skipping synthesis preparation. Standard implementation can only be simulated." -else - echo "Device part for files under minsoc/syn/src will be patched and stored " - echo "temporarily." - echo "Afterwards, they are copied to minsoc/syn/buildSupport." - echo "__________________________________________________________________________" - echo "" - for file in "${SYN_FILES[@]}" - do - echo "Updating synthesis file, $file..." - echo "Copying $file to synthesis directory..." - echo "" - sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE - sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file - rm TMPFILE - done - - echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..." - mv $SYNSUPPORT_DIR/Makefile $SYN_DIR -fi -echo "" -echo "" - - -echo "Copying board specific SoC files to backend directory." -echo "__________________________________________________________________________" -echo "" -for file in "${BOARD_FILES[@]}" -do - if [ $file != NONE ] - then - echo "Copying $file, to backend directory..." - cp $BOARD_DIR/$file $BACKEND_DIR - fi -done -echo "" -echo ""

trunk/backend/spartan3e_starter_kit/configure Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf =================================================================== --- trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (revision 64) +++ trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (nonexistent) @@ -1,64 +0,0 @@ -# -# Soldered 50MHz clock. -# -NET "clk" LOC = "C9"; - -# -# Use button "south" as reset. -# -NET "reset" LOC = "K17" | PULLDOWN ; - -# -# UART serial port (RS232 DCE) - connector DB9 female. -# -NET "uart_srx" LOC = "R7"; -NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; - -########################### -## -## ETH -## -#NET "eth_txd(3)" LOC = "t5"; -#NET "eth_txd(2)" LOC = "r5"; -#NET "eth_txd(1)" LOC = "t15"; -#NET "eth_txd(0)" LOC = "r11"; -# -#NET "eth_tx_en" LOC = "p15"; -#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; -#NET "eth_tx_er" LOC = "r6"; -# -#NET "eth_rxd(3)" LOC = "v14"; -#NET "eth_rxd(2)" LOC = "u11"; -#NET "eth_rxd(1)" LOC = "t11"; -#NET "eth_rxd(0)" LOC = "v8"; -# -#NET "eth_rx_er" LOC = "u14"; -#NET "eth_rx_dv" LOC = "v2"; -# -#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; -# -#NET "eth_mdio" LOC = "u5" | PULLUP; -#NET "eth_crs" LOC = "u13"; -#NET "eth_col" LOC = "u6"; -#NET "eth_mdc" LOC = "p9"; -# -#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) -# -#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) -########################### - -# -# JTAG signals - on J4 6-pin accessory header. -# - -#NET "jtag_tms" LOC = "D7" | PULLDOWN ; -#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; -#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; -#NET "jtag_tck" LOC = "E8" | PULLDOWN ; - -#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) -#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) - -# -# End of file. -#

trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3e_starter_kit/minsoc_defines.v =================================================================== --- trunk/backend/spartan3e_starter_kit/minsoc_defines.v (revision 64) +++ trunk/backend/spartan3e_starter_kit/minsoc_defines.v (nonexistent) @@ -1,148 +0,0 @@ -// -// Define FPGA manufacturer -// -//`define GENERIC_FPGA -//`define ALTERA_FPGA -`define XILINX_FPGA - -// -// Define Xilinx FPGA family -// -`ifdef XILINX_FPGA -//`define SPARTAN2 -//`define SPARTAN3 -`define SPARTAN3E -//`define SPARTAN3A -//`define VIRTEX -//`define VIRTEX2 -//`define VIRTEX4 -//`define VIRTEX5 - -// -// Define Altera FPGA family -// -`elsif ALTERA_FPGA -//`define ARRIA_GX -//`define ARRIA_II_GX -//`define CYCLONE_I -//`define CYCLONE_II -`define CYCLONE_III -//`define CYCLONE_III_LS -//`define CYCLONE_IV_E -//`define CYCLONE_IV_GS -//`define MAX_II -//`define MAX_V -//`define MAX3000A -//`define MAX7000AE -//`define MAX7000B -//`define MAX7000S -//`define STRATIX -//`define STRATIX_II -//`define STRATIX_II_GX -//`define STRATIX_III -`endif - -// -// Memory -// -`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, - //memory is composed by blocks of address width 11 - //Address width of memory -> select memory depth, - //2 powers MEMORY_ADR_WIDTH defines the memory depth - //the memory data width is 32 bit, - //memory amount in Bytes = 4*memory depth - -// -// Memory type (uncomment something if ASIC or generic memory) -// -//`define GENERIC_MEMORY -//`define AVANT_ATP -//`define VIRAGE_SSP -//`define VIRTUALSILICON_SSP - - -// -// TAP selection -// -//`define GENERIC_TAP -`define FPGA_TAP - -// -// Clock Division selection -// -//`define NO_CLOCK_DIVISION -//`define GENERIC_CLOCK_DIVISION -`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. - -// -// Define division -// -`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded - //down to an even value in FPGA case, check minsoc_clock_manager - //for allowed divisors. - //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION - //INSTEAD. - -// -// Reset polarity -// -//`define NEGATIVE_RESET //rstn -`define POSITIVE_RESET //rst - -// -// Start-up circuit (only necessary later to load firmware automatically from SPI memory) -// -//`define START_UP - -// -// Connected modules -// -`define UART -//`define ETHERNET - -// -// Ethernet reset -// -`define ETH_RESET 1'b0 -//`define ETH_RESET 1'b1 - -// -// Interrupts -// -`define APP_INT_RES1 1:0 -`define APP_INT_UART 2 -`define APP_INT_RES2 3 -`define APP_INT_ETH 4 -`define APP_INT_PS2 5 -`define APP_INT_RES3 19:6 - -// -// Address map -// -`define APP_ADDR_DEC_W 8 -`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 -`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 -`define APP_ADDR_DECP_W 4 -`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 -`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 -`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 -`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d -`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 -`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 -`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e -`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f - -// -// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen -// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set -// -`ifdef GENERIC_FPGA - `undef FPGA_TAP - `undef FPGA_CLOCK_DIVISION - - `define GENERIC_TAP - `define GENERIC_MEMORY - `ifndef NO_CLOCK_DIVISION - `define GENERIC_CLOCK_DIVISION - `endif -`endif

trunk/backend/spartan3e_starter_kit/minsoc_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3a_dsp_kit/configure =================================================================== --- trunk/backend/spartan3a_dsp_kit/configure (revision 64) +++ trunk/backend/spartan3a_dsp_kit/configure (nonexistent) @@ -1,81 +0,0 @@ -#!/bin/bash - -#new boards have to udpate this -BOARD=spartan3a_dsp_kit #this has to have the name of the directory this file is in -DEVICE_PART='xc3sd1800a-4-fg676' -CONSTRAINT_FILE='spartan3a_dsp_kit.ucf' -#~new boards update - -#system workings -MINSOC_DIR=`pwd`/../.. -BACKEND_DIR=$MINSOC_DIR/backend -SYN_DIR=$MINSOC_DIR/syn -SYNSRC_DIR=$SYN_DIR/src -SYNSUPPORT_DIR=$SYN_DIR/buildSupport - -SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile) - -FIND_PART='DEVICE_PART' -FIND_CONSTRAINT='CONSTRAINT_FILE' - -BOARD_DIR=$BACKEND_DIR/$BOARD -BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE) - -in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` -if [ -z $in_minsoc ] -then - echo "" - echo " !!!WARNING!!!" - echo "This script cannot be run out of a board directory inside minsoc/backend," - echo "because it relies on the directory structure of the minsoc system." - echo "" - exit 1 -fi - -echo "" -echo "Configuring SoC board's specific files for firmware compilation, " -echo "testbench generation and synthesis." -echo "Firmware and testbench looks for board specific files under minsoc/backend." -echo "Synthesis work under minsoc/syn." -echo "" -echo "" - -if [ $CONSTRAINT_FILE == 'NONE' ] -then - echo "Skipping synthesis preparation. Standard implementation can only be simulated." -else - echo "Device part for files under minsoc/syn/src will be patched and stored " - echo "temporarily." - echo "Afterwards, they are copied to minsoc/syn/buildSupport." - echo "__________________________________________________________________________" - echo "" - for file in "${SYN_FILES[@]}" - do - echo "Updating synthesis file, $file..." - echo "Copying $file to synthesis directory..." - echo "" - sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE - sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file - rm TMPFILE - done - - echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..." - mv $SYNSUPPORT_DIR/Makefile $SYN_DIR -fi -echo "" -echo "" - - -echo "Copying board specific SoC files to backend directory." -echo "__________________________________________________________________________" -echo "" -for file in "${BOARD_FILES[@]}" -do - if [ $file != NONE ] - then - echo "Copying $file, to backend directory..." - cp $BOARD_DIR/$file $BACKEND_DIR - fi -done -echo "" -echo ""

trunk/backend/spartan3a_dsp_kit/configure Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf =================================================================== --- trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (revision 64) +++ trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (nonexistent) @@ -1,72 +0,0 @@ -########################### -## -## Global signals -## -net "clk" loc = "f13"; #125MHz clock -net "reset" loc = "j17"; #SW5 -########################### - -########################### -## -## JTAG -## -#net "jtag_tms" loc = "aa23"; #SAM D0 -#net "jtag_tdi" loc = "u20"; #SAM D2 -#net "jtag_tdo" loc = "aa25"; #SAM D4 -#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 -#net "jtag_gnd" loc = "y23"; #SAM D8 -#net "jtag_vref" loc = "t20"; #SAM D10 -########################### - -############################# -## -## SPI Flash External Memory -## -NET "spi_flash_mosi" LOC = "ab15"; -NET "spi_flash_miso" LOC = "af24"; -NET "spi_flash_sclk" LOC = "ae24"; -NET "spi_flash_ss(1)" LOC = "ac25"; -NET "spi_flash_ss(0)" LOC = "aa7"; -########################### - -########################### -## -## UART -## -net "uart_stx" loc = "p22"; -net "uart_srx" loc = "n21"; -########################### - -########################### -## -## ETH -## -NET "eth_txd(3)" LOC = "b1"; -NET "eth_txd(2)" LOC = "b2"; -NET "eth_txd(1)" LOC = "j9"; -NET "eth_txd(0)" LOC = "j8"; - -NET "eth_tx_en" LOC = "d3"; -NET "eth_tx_clk" LOC = "p2"; -NET "eth_tx_er" LOC = "e4"; - -NET "eth_rxd(3)" LOC = "d2"; -NET "eth_rxd(2)" LOC = "g5"; -NET "eth_rxd(1)" LOC = "g2"; -NET "eth_rxd(0)" LOC = "c2"; - -NET "eth_rx_er" LOC = "j3"; -NET "eth_rx_dv" LOC = "d1"; - -NET "eth_rx_clk" LOC = "p1"; - -NET "eth_mdio" LOC = "f5" | PULLUP; -NET "eth_crs" LOC = "g1"; -NET "eth_col" LOC = "y3"; -NET "eth_mdc" LOC = "f4"; - -NET "eth_trste" LOC = "g4"; - -NET "eth_fds_mdint" LOC = "j1"; -########################### -

trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3a_dsp_kit/minsoc_defines.v =================================================================== --- trunk/backend/spartan3a_dsp_kit/minsoc_defines.v (revision 64) +++ trunk/backend/spartan3a_dsp_kit/minsoc_defines.v (nonexistent) @@ -1,148 +0,0 @@ -// -// Define FPGA manufacturer -// -//`define GENERIC_FPGA -//`define ALTERA_FPGA -`define XILINX_FPGA - -// -// Define Xilinx FPGA family -// -`ifdef XILINX_FPGA -//`define SPARTAN2 -//`define SPARTAN3 -//`define SPARTAN3E -`define SPARTAN3A -//`define VIRTEX -//`define VIRTEX2 -//`define VIRTEX4 -//`define VIRTEX5 - -// -// Define Altera FPGA family -// -`elsif ALTERA_FPGA -//`define ARRIA_GX -//`define ARRIA_II_GX -//`define CYCLONE_I -//`define CYCLONE_II -`define CYCLONE_III -//`define CYCLONE_III_LS -//`define CYCLONE_IV_E -//`define CYCLONE_IV_GS -//`define MAX_II -//`define MAX_V -//`define MAX3000A -//`define MAX7000AE -//`define MAX7000B -//`define MAX7000S -//`define STRATIX -//`define STRATIX_II -//`define STRATIX_II_GX -//`define STRATIX_III -`endif - -// -// Memory -// -`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, - //memory is composed by blocks of address width 11 - //Address width of memory -> select memory depth, - //2 powers MEMORY_ADR_WIDTH defines the memory depth - //the memory data width is 32 bit, - //memory amount in Bytes = 4*memory depth - -// -// Memory type (uncomment something if ASIC or generic memory) -// -//`define GENERIC_MEMORY -//`define AVANT_ATP -//`define VIRAGE_SSP -//`define VIRTUALSILICON_SSP - - -// -// TAP selection -// -//`define GENERIC_TAP -`define FPGA_TAP - -// -// Clock Division selection -// -//`define NO_CLOCK_DIVISION -//`define GENERIC_CLOCK_DIVISION -`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. - -// -// Define division -// -`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded - //down to an even value in FPGA case, check minsoc_clock_manager - //for allowed divisors. - //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION - //INSTEAD. - -// -// Reset polarity -// -//`define NEGATIVE_RESET //rstn -`define POSITIVE_RESET //rst - -// -// Start-up circuit (only necessary later to load firmware automatically from SPI memory) -// -//`define START_UP - -// -// Connected modules -// -`define UART -`define ETHERNET - -// -// Ethernet reset -// -//`define ETH_RESET 1'b0 -`define ETH_RESET 1'b1 - -// -// Interrupts -// -`define APP_INT_RES1 1:0 -`define APP_INT_UART 2 -`define APP_INT_RES2 3 -`define APP_INT_ETH 4 -`define APP_INT_PS2 5 -`define APP_INT_RES3 19:6 - -// -// Address map -// -`define APP_ADDR_DEC_W 8 -`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 -`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 -`define APP_ADDR_DECP_W 4 -`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 -`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 -`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 -`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d -`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 -`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 -`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e -`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f - -// -// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen -// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set -// -`ifdef GENERIC_FPGA - `undef FPGA_TAP - `undef FPGA_CLOCK_DIVISION - - `define GENERIC_TAP - `define GENERIC_MEMORY - `ifndef NO_CLOCK_DIVISION - `define GENERIC_CLOCK_DIVISION - `endif -`endif Index: trunk/backend/spartan3a_dsp_kit/board.h =================================================================== --- trunk/backend/spartan3a_dsp_kit/board.h (revision 64) +++ trunk/backend/spartan3a_dsp_kit/board.h (nonexistent) @@ -1,40 +0,0 @@ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define MC_ENABLED 0 - -#define IC_ENABLE 0 -#define IC_SIZE 8192 -#define DC_ENABLE 0 -#define DC_SIZE 8192 - - -#define IN_CLK 25000000 - - -#define STACK_SIZE 0x01000 - -#define UART_BAUD_RATE 115200 - -#define UART_BASE 0x90000000 -#define UART_IRQ 2 -#define ETH_BASE 0x92000000 -#define ETH_IRQ 4 -#define I2C_BASE 0x9D000000 -#define I2C_IRQ 3 -#define CAN_BASE 0x94000000 -#define CAN_IRQ 5 - -#define MC_BASE_ADDR 0x60000000 -#define SPI_BASE 0xa0000000 - -#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ - -#define ETH_MACADDR0 0x00 -#define ETH_MACADDR1 0x12 -#define ETH_MACADDR2 0x34 -#define ETH_MACADDR3 0x56 -#define ETH_MACADDR4 0x78 -#define ETH_MACADDR5 0x9a - -#endif

trunk/backend/spartan3a_dsp_kit/board.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3a_dsp_kit/orp.ld =================================================================== --- trunk/backend/spartan3a_dsp_kit/orp.ld (revision 64) +++ trunk/backend/spartan3a_dsp_kit/orp.ld (nonexistent) @@ -1,60 +0,0 @@ -MEMORY - { - reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 - vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 - ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ - } - -SECTIONS -{ - .reset : - { - *(.reset) - } > reset - - - - .vectors : - { - _vec_start = .; - *(.vectors) - _vec_end = .; - } > vectors - - .text : - { - *(.text) - } > ram - - .rodata : - { - *(.rodata) - *(.rodata.*) - } > ram - - .icm : - { - _icm_start = .; - *(.icm) - _icm_end = .; - } > ram - - .data : - { - _dst_beg = .; - *(.data) - _dst_end = .; - } > ram - - .bss : - { - *(.bss) - } > ram - - .stack (NOLOAD) : - { - *(.stack) - _src_addr = .; - } > ram - -}

trunk/backend/spartan3a_dsp_kit/orp.ld Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/std/minsoc_defines.v =================================================================== --- trunk/backend/std/minsoc_defines.v (revision 64) +++ trunk/backend/std/minsoc_defines.v (nonexistent) @@ -1,148 +0,0 @@ -// -// Define FPGA manufacturer -// -`define GENERIC_FPGA -//`define ALTERA_FPGA -//`define XILINX_FPGA - -// -// Define Xilinx FPGA family -// -`ifdef XILINX_FPGA -//`define SPARTAN2 -//`define SPARTAN3 -//`define SPARTAN3E -`define SPARTAN3A -//`define VIRTEX -//`define VIRTEX2 -//`define VIRTEX4 -//`define VIRTEX5 - -// -// Define Altera FPGA family -// -`elsif ALTERA_FPGA -//`define ARRIA_GX -//`define ARRIA_II_GX -//`define CYCLONE_I -//`define CYCLONE_II -`define CYCLONE_III -//`define CYCLONE_III_LS -//`define CYCLONE_IV_E -//`define CYCLONE_IV_GS -//`define MAX_II -//`define MAX_V -//`define MAX3000A -//`define MAX7000AE -//`define MAX7000B -//`define MAX7000S -//`define STRATIX -//`define STRATIX_II -//`define STRATIX_II_GX -//`define STRATIX_III -`endif - -// -// Memory -// -`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, - //memory is composed by blocks of address width 11 - //Address width of memory -> select memory depth, - //2 powers MEMORY_ADR_WIDTH defines the memory depth - //the memory data width is 32 bit, - //memory amount in Bytes = 4*memory depth - -// -// Memory type (uncomment something if ASIC or generic memory) -// -//`define GENERIC_MEMORY -//`define AVANT_ATP -//`define VIRAGE_SSP -//`define VIRTUALSILICON_SSP - - -// -// TAP selection -// -//`define GENERIC_TAP -`define FPGA_TAP - -// -// Clock Division selection -// -//`define NO_CLOCK_DIVISION -//`define GENERIC_CLOCK_DIVISION -`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. - -// -// Define division -// -`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded - //down to an even value in FPGA case, check minsoc_clock_manager - //for allowed divisors. - //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION - //INSTEAD. - -// -// Reset polarity -// -`define NEGATIVE_RESET //rstn -//`define POSITIVE_RESET //rst - -// -// Start-up circuit (only necessary later to load firmware automatically from SPI memory) -// -//`define START_UP - -// -// Connected modules -// -`define UART -`define ETHERNET - -// -// Ethernet reset -// -`define ETH_RESET 1'b0 -//`define ETH_RESET 1'b1 - -// -// Interrupts -// -`define APP_INT_RES1 1:0 -`define APP_INT_UART 2 -`define APP_INT_RES2 3 -`define APP_INT_ETH 4 -`define APP_INT_PS2 5 -`define APP_INT_RES3 19:6 - -// -// Address map -// -`define APP_ADDR_DEC_W 8 -`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 -`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 -`define APP_ADDR_DECP_W 4 -`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 -`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 -`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 -`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d -`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 -`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 -`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e -`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f - -// -// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen -// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set -// -`ifdef GENERIC_FPGA - `undef FPGA_TAP - `undef FPGA_CLOCK_DIVISION - - `define GENERIC_TAP - `define GENERIC_MEMORY - `ifndef NO_CLOCK_DIVISION - `define GENERIC_CLOCK_DIVISION - `endif -`endif

trunk/backend/std/minsoc_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/std/board.h =================================================================== --- trunk/backend/std/board.h (revision 64) +++ trunk/backend/std/board.h (nonexistent) @@ -1,40 +0,0 @@ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define MC_ENABLED 0 - -#define IC_ENABLE 0 -#define IC_SIZE 8192 -#define DC_ENABLE 0 -#define DC_SIZE 8192 - - -#define IN_CLK 25000000 - - -#define STACK_SIZE 0x01000 - -#define UART_BAUD_RATE 115200 - -#define UART_BASE 0x90000000 -#define UART_IRQ 2 -#define ETH_BASE 0x92000000 -#define ETH_IRQ 4 -#define I2C_BASE 0x9D000000 -#define I2C_IRQ 3 -#define CAN_BASE 0x94000000 -#define CAN_IRQ 5 - -#define MC_BASE_ADDR 0x60000000 -#define SPI_BASE 0xa0000000 - -#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ - -#define ETH_MACADDR0 0x00 -#define ETH_MACADDR1 0x12 -#define ETH_MACADDR2 0x34 -#define ETH_MACADDR3 0x56 -#define ETH_MACADDR4 0x78 -#define ETH_MACADDR5 0x9a - -#endif

trunk/backend/std/board.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/std/orp.ld =================================================================== --- trunk/backend/std/orp.ld (revision 64) +++ trunk/backend/std/orp.ld (nonexistent) @@ -1,60 +0,0 @@ -MEMORY - { - reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 - vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 - ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ - } - -SECTIONS -{ - .reset : - { - *(.reset) - } > reset - - - - .vectors : - { - _vec_start = .; - *(.vectors) - _vec_end = .; - } > vectors - - .text : - { - *(.text) - } > ram - - .rodata : - { - *(.rodata) - *(.rodata.*) - } > ram - - .icm : - { - _icm_start = .; - *(.icm) - _icm_end = .; - } > ram - - .data : - { - _dst_beg = .; - *(.data) - _dst_end = .; - } > ram - - .bss : - { - *(.bss) - } > ram - - .stack (NOLOAD) : - { - *(.stack) - _src_addr = .; - } > ram - -}

trunk/backend/std/orp.ld Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/backend/spartan3a_dsp_kit.ucf =================================================================== --- trunk/backend/spartan3a_dsp_kit.ucf (nonexistent) +++ trunk/backend/spartan3a_dsp_kit.ucf (revision 63) @@ -0,0 +1,72 @@ +########################### +## +## Global signals +## +net "clk" loc = "f13"; #125MHz clock +net "reset" loc = "j17"; #SW5 +########################### + +########################### +## +## JTAG +## +#net "jtag_tms" loc = "aa23"; #SAM D0 +#net "jtag_tdi" loc = "u20"; #SAM D2 +#net "jtag_tdo" loc = "aa25"; #SAM D4 +#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 +#net "jtag_gnd" loc = "y23"; #SAM D8 +#net "jtag_vref" loc = "t20"; #SAM D10 +########################### + +############################# +## +## SPI Flash External Memory +## +#NET "spi_flash_mosi" LOC = "ab15"; +#NET "spi_flash_miso" LOC = "af24"; +#NET "spi_flash_sclk" LOC = "ae24"; +#NET "spi_flash_ss(1)" LOC = "ac25"; +#NET "spi_flash_ss(0)" LOC = "aa7"; +########################### + +########################### +## +## UART +## +net "uart_stx" loc = "p22"; +net "uart_srx" loc = "n21"; +########################### + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "b1"; +#NET "eth_txd(2)" LOC = "b2"; +#NET "eth_txd(1)" LOC = "j9"; +#NET "eth_txd(0)" LOC = "j8"; +# +#NET "eth_tx_en" LOC = "d3"; +#NET "eth_tx_clk" LOC = "p2"; +#NET "eth_tx_er" LOC = "e4"; +# +#NET "eth_rxd(3)" LOC = "d2"; +#NET "eth_rxd(2)" LOC = "g5"; +#NET "eth_rxd(1)" LOC = "g2"; +#NET "eth_rxd(0)" LOC = "c2"; +# +#NET "eth_rx_er" LOC = "j3"; +#NET "eth_rx_dv" LOC = "d1"; +# +#NET "eth_rx_clk" LOC = "p1"; +# +#NET "eth_mdio" LOC = "f5" | PULLUP; +#NET "eth_crs" LOC = "g1"; +#NET "eth_col" LOC = "y3"; +#NET "eth_mdc" LOC = "f4"; +# +#NET "eth_trste" LOC = "g4"; +# +#NET "eth_fds_mdint" LOC = "j1"; +########################### +

trunk/backend/spartan3a_dsp_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/backend/ml509.ucf =================================================================== --- trunk/backend/ml509.ucf (nonexistent) +++ trunk/backend/ml509.ucf (revision 63) @@ -0,0 +1,45 @@ +NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI + +## #------------------------------------------------------------------------------ +## # IO Pad Location Constraints / Properties for Ethernet +## #------------------------------------------------------------------------------ + +#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; +#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; + +#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; +#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy +#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; +#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; +#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; +#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; +#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; +#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; + +## PHY Serial Management Interface pins +#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; +#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; + +## # Timing Constraints (these are recommended in documentation and +## # are unaltered except for the TIG) +#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; +#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; +#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; +#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; + +## # Timing ignores (to specify unconstrained paths) +#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock +#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; +#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: trunk/backend/spartan3e_starter_kit.ucf =================================================================== --- trunk/backend/spartan3e_starter_kit.ucf (nonexistent) +++ trunk/backend/spartan3e_starter_kit.ucf (revision 63) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#

trunk/backend/spartan3e_starter_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/src/minsoc_top.xst =================================================================== --- trunk/syn/src/minsoc_top.xst (revision 64) +++ trunk/syn/src/minsoc_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir "./xst" -run --vlgincdir {"../backend" "../rtl/verilog/" "../rtl/verilog/minsoc_startup" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"} --ifn ./buildSupport/minsoc_top.prj --ifmt Verilog --ofn minsoc_top --ofmt NGC --p DEVICE_PART --top minsoc_top --opt_mode Speed --opt_level 1 --iobuf yes \ No newline at end of file Index: trunk/syn/src/uart_top.xst =================================================================== --- trunk/syn/src/uart_top.xst (revision 64) +++ trunk/syn/src/uart_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir "./xst" -run --vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"} --ifn ./buildSupport/uart_top.prj --ifmt Verilog --ofn uart_top --ofmt NGC --p DEVICE_PART --top uart_top --opt_mode Speed --opt_level 1 --iobuf no \ No newline at end of file Index: trunk/syn/src/adbg_top.xst =================================================================== --- trunk/syn/src/adbg_top.xst (revision 64) +++ trunk/syn/src/adbg_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir "./xst" -run --vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"} --ifn ./buildSupport/adbg_top.prj --ifmt Verilog --ofn adbg_top --ofmt NGC --p DEVICE_PART --top adbg_top --opt_mode Speed --opt_level 1 --iobuf no \ No newline at end of file Index: trunk/syn/src/Makefile =================================================================== --- trunk/syn/src/Makefile (revision 64) +++ trunk/syn/src/Makefile (nonexistent) @@ -1,91 +0,0 @@ -MINSOC = ../ -MINSOC_DEFINES = ${MINSOC}/backend -MINSOC_RTL = ${MINSOC}/rtl/verilog -MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup -UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog -ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware -DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog -OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog -ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog - -help: - @echo " all: Synthesize and implement the SoC, then generate a bit stream" - @echo "" - @echo " soc: Synthesize the SoC" - @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" - @echo " map: Express the SoC netlist in the target hardware" - @echo " par: Place the target hardware, then route the wires" - @echo " bitgen: Generate a programming file for the target FPGA" - @echo "" - @echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" - @echo " or1200: Synthesize the OR1200 processor" - @echo " debug: Synthesize the debug interface" - @echo " uart: Synthesize the UART" - @echo " eth: Synthesize the Ethernet controller" - @echo "" - @echo " clean: Delete all superfluous files generated by Xilinx tools" - @echo " distclean: Delete all generated files" - -all: minsoc.bit -soc: minsoc_top.ngc -translate: minsoc.ngd -map: minsoc.ncd -par: minsoc_par.ncd -bitgen: minsoc.bit -modules: or1200 debug uart eth -MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc eth_top.ngc - -prepare: - rm -rf xst - mkdir xst -clean: - rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt - rm -rf _xmsgs xst xlnx_auto_0_xdb -distclean: - rm -rf *.ngc *.ncd *.ngd *.bit - make clean - -minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v buildSupport/minsoc_top.xst buildSupport/minsoc_top.prj - make prepare - xst -ifn "buildSupport/minsoc_top.xst" - make clean - -uart: uart_top.ngc -uart_top.ngc: ${UART_RTL}/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj - make prepare - xst -ifn "buildSupport/uart_top.xst" - make clean - -eth: eth_top.ngc -eth_top.ngc: ${ETH_RTL}/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj - make prepare - xst -ifn "buildSupport/eth_top.xst" - make clean - -debug: adbg_top.ngc -adbg_top.ngc: ${DEBUG_RTL}/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj - make prepare - xst -ifn "buildSupport/adbg_top.xst" - make clean - -or1200: or1200_top.ngc -or1200_top.ngc: ${OR1200_RTL}/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj - make prepare - xst -ifn "buildSupport/or1200_top.xst" - make clean - -minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) - ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd - make clean - -minsoc.ncd: minsoc.ngd - map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd - make clean - -minsoc_par.ncd: minsoc.ncd - par -ol high -w -xe n minsoc.ncd minsoc_par.ncd - make clean - -minsoc.bit: minsoc_par.ncd - bitgen -d -w minsoc_par.ncd minsoc.bit - make clean Index: trunk/syn/src/eth_top.xst =================================================================== --- trunk/syn/src/eth_top.xst (revision 64) +++ trunk/syn/src/eth_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir "./xst" -run --vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"} --ifn ./buildSupport/eth_top.prj --ifmt Verilog --ofn eth_top --ofmt NGC --p DEVICE_PART --top eth_top --opt_mode Speed --opt_level 1 --iobuf no \ No newline at end of file Index: trunk/syn/src/or1200_top.xst =================================================================== --- trunk/syn/src/or1200_top.xst (revision 64) +++ trunk/syn/src/or1200_top.xst (nonexistent) @@ -1,12 +0,0 @@ -set -tmpdir "./xst" -run --vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"} --ifn ./buildSupport/or1200_top.prj --ifmt Verilog --ofn or1200_top --ofmt NGC --p DEVICE_PART --top or1200_top --opt_mode Speed --opt_level 1 --iobuf no \ No newline at end of file Index: trunk/syn/buildSupport/eth_top.xst =================================================================== --- trunk/syn/buildSupport/eth_top.xst (nonexistent) +++ trunk/syn/buildSupport/eth_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"} +-ifn ./buildSupport/eth_top.prj +-ifmt Verilog +-ofn eth_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top eth_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: trunk/syn/buildSupport/or1200_top.xst =================================================================== --- trunk/syn/buildSupport/or1200_top.xst (nonexistent) +++ trunk/syn/buildSupport/or1200_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"} +-ifn ./buildSupport/or1200_top.prj +-ifmt Verilog +-ofn or1200_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top or1200_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: trunk/syn/buildSupport/minsoc_top.prj =================================================================== --- trunk/syn/buildSupport/minsoc_top.prj (revision 64) +++ trunk/syn/buildSupport/minsoc_top.prj (revision 63) @@ -1,5 +1,5 @@ -`include "../backend/minsoc_defines.v" `include "../rtl/verilog/minsoc_xilinx_internal_jtag.v" +`include "../rtl/verilog/minsoc_defines.v" `include "../rtl/verilog/minsoc_clock_manager.v" `include "../rtl/verilog/altera_pll.v" `include "../rtl/verilog/minsoc_tc_top.v" @@ -7,12 +7,8 @@ `include "../rtl/verilog/minsoc_top.v" `include "../rtl/verilog/minsoc_onchip_ram.v" `include "../rtl/verilog/xilinx_dcm.v" -`include "../rtl/verilog/minsoc_startup/spi_shift.v" -`include "../rtl/verilog/minsoc_startup/spi_clgen.v" -`include "../rtl/verilog/minsoc_startup/spi_top.v" -`include "../rtl/verilog/minsoc_startup/spi_defines.v" -`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" `include "./blackboxes/adbg_top.v" `include "./blackboxes/eth_top.v" `include "./blackboxes/uart_top.v" -`include "./blackboxes/or1200_top.v" \ No newline at end of file +`include "./blackboxes/or1200_top.v" +`include "./blackboxes/OR1K_startup_generic.v" \ No newline at end of file Index: trunk/syn/buildSupport/minsoc_startup_top.prj =================================================================== --- trunk/syn/buildSupport/minsoc_startup_top.prj (nonexistent) +++ trunk/syn/buildSupport/minsoc_startup_top.prj (revision 63) @@ -0,0 +1,5 @@ +`include "../rtl/verilog/minsoc_startup/spi_shift.v" +`include "../rtl/verilog/minsoc_startup/spi_clgen.v" +`include "../rtl/verilog/minsoc_startup/spi_top.v" +`include "../rtl/verilog/minsoc_startup/spi_defines.v" +`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" \ No newline at end of file Index: trunk/syn/buildSupport/minsoc_top.xst =================================================================== --- trunk/syn/buildSupport/minsoc_top.xst (nonexistent) +++ trunk/syn/buildSupport/minsoc_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"} +-ifn ./buildSupport/minsoc_top.prj +-ifmt Verilog +-ofn minsoc_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top minsoc_top +-opt_mode Speed +-opt_level 1 +-iobuf yes \ No newline at end of file Index: trunk/syn/buildSupport/minsoc_startup_top.xst =================================================================== --- trunk/syn/buildSupport/minsoc_startup_top.xst (nonexistent) +++ trunk/syn/buildSupport/minsoc_startup_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/" "../rtl/verilog/minsoc_startup/" "../rtl/verilog/or1200/rtl/verilog"} +-ifn ./buildSupport/minsoc_startup_top.prj +-ifmt Verilog +-ofn minsoc_startup_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top OR1K_startup +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: trunk/syn/buildSupport/uart_top.xst =================================================================== --- trunk/syn/buildSupport/uart_top.xst (nonexistent) +++ trunk/syn/buildSupport/uart_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"} +-ifn ./buildSupport/uart_top.prj +-ifmt Verilog +-ofn uart_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top uart_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: trunk/syn/buildSupport/adbg_top.xst =================================================================== --- trunk/syn/buildSupport/adbg_top.xst (nonexistent) +++ trunk/syn/buildSupport/adbg_top.xst (revision 63) @@ -0,0 +1,12 @@ +set -tmpdir "./xst" +run +-vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"} +-ifn ./buildSupport/adbg_top.prj +-ifmt Verilog +-ofn adbg_top +-ofmt NGC +-p xc3sd1800a-4-fg676 +-top adbg_top +-opt_mode Speed +-opt_level 1 +-iobuf no \ No newline at end of file Index: trunk/syn/blackboxes/OR1K_startup_generic.v =================================================================== --- trunk/syn/blackboxes/OR1K_startup_generic.v (nonexistent) +++ trunk/syn/blackboxes/OR1K_startup_generic.v (revision 63) @@ -0,0 +1,15 @@ + +`include "minsoc_defines.v" + +module OR1K_startup + ( + input [6:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + input wb_clk, + input wb_rst + ); + +endmodule // OR1K_startup

trunk/syn/blackboxes/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Makefile =================================================================== --- trunk/syn/Makefile (nonexistent) +++ trunk/syn/Makefile (revision 63) @@ -0,0 +1,133 @@ +ROOT = /home/rfajardo/ongoing/or1k/risc_raul +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +MINSOC_STARTUP_RTL = $(MINSOC_RTL)/minsoc_startup +UART_RTL = $(MINSOC_RTL)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(MINSOC_RTL)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +OR1200_RTL = $(MINSOC_RTL)/or1200/rtl/verilog +ETH_RTL = $(MINSOC_RTL)/ethmac/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " or1200: Synthesize the OR1200 processor" + @echo " debug: Synthesize the debug interface" + @echo " uart: Synthesize the UART" + @echo " eth: Synthesize the ethernet controller" + @echo " startup: Synthesize the modules to automatically start-up the firmware on power on" + +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -rf _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -rf _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + mkdir xst + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst + +startup: minsoc_startup_top.ngc +minsoc_startup_top.ngc: $(MINSOC_STARTUP_RTL)/*.v buildSupport/minsoc_startup_top.xst buildSupport/minsoc_startup_top.prj + mkdir xst + xst -ifn "buildSupport/minsoc_startup_top.xst" + rm -f minsoc_startup_top_xst.xrpt + rm -f minsoc_startup_top.srp + rm -f minsoc_startup_top.lso + rm -rf _xmsgs + rm -rf xst + +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + mkdir xst + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst + +eth: eth_top.ngc +eth_top.ngc: $(ETH_RTL)/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj + mkdir xst + xst -ifn "buildSupport/eth_top.xst" + rm -f eth_top_xst.xrpt + rm -f eth_top.srp + rm -f eth_top.lso + rm -rf _xmsgs + rm -rf xst + +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + mkdir xst + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst + +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + mkdir xst + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst + +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc3sd1800a-4-fg676 -uc $(MINSOC)/backend/spartan3a_dsp_kit.ucf -aul minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs + +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs + +minsoc_par.ncd: minsoc.ncd + par -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs + +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs Index: trunk/sw/support/common.mk =================================================================== --- trunk/sw/support/common.mk (revision 64) +++ trunk/sw/support/common.mk (nonexistent) @@ -1,21 +0,0 @@ -$(LIB_SUPPORT): $(SUPPORT_DIR)/support.o $(SUPPORT_DIR)/tick.o $(SUPPORT_DIR)/int.o - $(OR32_TOOL_PREFIX)-ar cru $(SUPPORT_DIR)/libsupport.a $(SUPPORT_DIR)/support.o $(SUPPORT_DIR)/tick.o $(SUPPORT_DIR)/int.o - $(OR32_TOOL_PREFIX)-ranlib $(SUPPORT_DIR)/libsupport.a - -$(SUPPORT_DIR)/support.o: $(SUPPORT_DIR)/support.c $(OR1200_HDR) $(SUPPORT_HDR) $(SUPPORT_DIR)/int.h $(UART_HDR) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< - -$(SUPPORT_DIR)/tick.o: $(SUPPORT_DIR)/tick.c $(OR1200_HDR) $(SUPPORT_HDR) $(SUPPORT_DIR)/tick.h - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< - -$(SUPPORT_DIR)/int.o: $(SUPPORT_DIR)/int.c $(SUPPORT_HDR) $(OR1200_HDR) $(SUPPORT_DIR)/int.h - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< - -$(EXCPT_HNDLR): $(SUPPORT_DIR)/except.S $(OR1200_HDR) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $< - -$(RESET_NOCACHE): $(SUPPORT_DIR)/reset.S $(BOARD_HDR) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=0 -o $@ $< - -$(RESET_ICDC): $(SUPPORT_DIR)/reset.S $(BOARD_HDR) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=1 -o $@ $<

trunk/sw/support/common.mk Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sw/support/Makefile =================================================================== --- trunk/sw/support/Makefile (revision 64) +++ trunk/sw/support/Makefile (revision 63) @@ -1,5 +1,31 @@ -include Makefile.inc +all: libsupport.a reset-nocache.o reset-ic.o reset-dc.o reset-icdc.o except.o -all_internal: $(RESET_NOCACHE) $(RESET_ICDC) $(EXCPT_HNDLR) $(LIB_SUPPORT) +libsupport.a: support.o tick.o int.o + $(OR32_TOOL_PREFIX)-ar cru libsupport.a support.o tick.o int.o + $(OR32_TOOL_PREFIX)-ranlib libsupport.a -include common.mk \ No newline at end of file +support.o: support.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +reset-nocache.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=0 -o $@ $? + +reset-dc.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=1 -o $@ $? + +reset-ic.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=0 -o $@ $? + +reset-icdc.o: reset.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=1 -o $@ $? + +except.o: except.S + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +int.o: int.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +tick.o: tick.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $? + +include Makefile.inc

trunk/sw/support/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sw/support/reset.S =================================================================== --- trunk/sw/support/reset.S (revision 64) +++ trunk/sw/support/reset.S (revision 63) @@ -1,6 +1,6 @@ /* Support file for c based tests */ #include "or1200.h" -#include "../../backend/board.h" +#include "board.h" .section .stack .space STACK_SIZE

/trunk/sw/support/tick.c

1,5 → 1,5

/trunk/sw/support/board.h

0,0 → 1,40

trunk/sw/support/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sw/support/Makefile.inc =================================================================== --- trunk/sw/support/Makefile.inc (revision 64) +++ trunk/sw/support/Makefile.inc (revision 63) @@ -1,42 +1,20 @@ # File to be included in all makefiles -ROOTDIR = .. - -BACKEND_DIR := $(ROOTDIR)/../backend -SUPPORT_DIR := $(ROOTDIR)/support -DRIVERS_DIR := $(ROOTDIR)/drivers -UTILS_DIR := $(ROOTDIR)/utils - -OR1200_HDR := $(SUPPORT_DIR)/or1200.h -BOARD_HDR := $(BACKEND_DIR)/board.h -SUPPORT_HDR := $(SUPPORT_DIR)/support.h -UART_HDR := $(DRIVERS_DIR)/uart.h -ETH_HDR := $(DRIVERS_DIR)/eth.h - -RESET_NOCACHE := $(SUPPORT_DIR)/reset-nocache.o -RESET_ICDC := $(SUPPORT_DIR)/reset-icdc.o - -EXCPT_HNDLR := $(SUPPORT_DIR)/except.o -LIB_SUPPORT := $(SUPPORT_DIR)/libsupport.a - -SUPPORT := $(EXCPT_HNDLR) $(LIB_SUPPORT) -DRIVERS := $(DRIVERS_DIR)/libdrivers.a - -LINKER_SCRIPT := $(BACKEND_DIR)/orp.ld - OR32_TOOL_PREFIX=or32-elf -GCC_OPT=-mhard-mul -mhard-div -g -nostdlib +#GCC_LIB_OPTS= -lgcc -liberty -BIN2HEX = $(UTILS_DIR)/bin2hex +GCC_OPT=-mhard-mul -g -nostdlib ifdef UART_PRINTF GCC_OPT += -DUART_PRINTF endif -all: all_internal +FLASH_MEM_HEX_FILE_SUFFIX=-twobyte-sizefirst +SRAM_MEM_HEX_FILE_SUFFIX=-fourbyte + # Global clean rule clean: @echo "Cleaning `pwd`" - @rm -f *.o *.or32 *.log *.bin *.srec *.hex *.log stdout.txt *.vmem *.asm *.a stdout.txt \ No newline at end of file + @rm -f *.o *.or32 *.log *.bin *.srec *.hex *.log stdout.txt *.vmem *.asm *.a stdout.txt

/trunk/sw/support/orp.ld

0,0 → 1,69

trunk/sw/support/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sw/eth/common.mk =================================================================== --- trunk/sw/eth/common.mk (revision 64) +++ trunk/sw/eth/common.mk (nonexistent) @@ -1,22 +0,0 @@ -eth-nocache.hex: eth-nocache.bin - $(BIN2HEX) $? 1 -size_word > $@ - -eth-nocache.bin: eth-nocache.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ - -eth-nocache.or32: eth.o $(RESET_NOCACHE) $(SUPPORT) $(DRIVERS) $(LINKER_SCRIPT) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) eth.o $(RESET_NOCACHE) $(SUPPORT) $(DRIVERS) -o $@ - - -eth-icdc.hex: eth-icdc.bin - $(BIN2HEX) $? 1 -size_word > $@ - -eth-icdc.bin: eth-icdc.or32 - $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ - -eth-icdc.or32: eth.o $(RESET_ICDC) $(SUPPORT) $(DRIVERS) $(LINKER_SCRIPT) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) eth.o $(RESET_ICDC) $(SUPPORT) $(DRIVERS) -o $@ - - -eth.o: eth.c $(BOARD_HDR) $(SUPPORT_HDR) $(OR1200_HDR) $(UART_HDR) $(ETH_HDR) - $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $< -c -o $@

trunk/sw/eth/common.mk Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sw/eth/Makefile =================================================================== --- trunk/sw/eth/Makefile (nonexistent) +++ trunk/sw/eth/Makefile (revision 63) @@ -0,0 +1,24 @@ +cases = eth-nocache eth-icdc +common = ../support/except.o ../support/libsupport.a +drivers = ../drivers/libdrivers.a + +all: $(cases) + +eth-nocache: eth.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +eth-icdc: eth.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +eth.o: eth.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +include ../support/Makefile.inc

trunk/sw/eth/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sw/eth/eth.c =================================================================== --- trunk/sw/eth/eth.c (revision 64) +++ trunk/sw/eth/eth.c (revision 63) @@ -1,5 +1,5 @@ -#include "../../backend/board.h" #include "../support/support.h" +#include "../support/board.h" #include "../support/or1200.h"

/trunk/sw/uart/common.mk File deleted

trunk/sw/uart/common.mk Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sw/uart/Makefile =================================================================== --- trunk/sw/uart/Makefile (nonexistent) +++ trunk/sw/uart/Makefile (revision 63) @@ -0,0 +1,24 @@ +cases = uart-nocache uart-icdc +common = ../support/except.o ../support/libsupport.a +drivers = ../drivers/libdrivers.a + +all: $(cases) + +uart-nocache: uart.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +uart-icdc: uart.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +uart.o: uart.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +include ../support/Makefile.inc

trunk/sw/uart/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sw/uart/uart.c =================================================================== --- trunk/sw/uart/uart.c (revision 64) +++ trunk/sw/uart/uart.c (revision 63) @@ -1,5 +1,5 @@ -#include "../../backend/board.h" #include "../support/support.h" +#include "../support/board.h" #include "../support/or1200.h" #include "../drivers/uart.h"

/trunk/sw/drivers/common.mk File deleted

/trunk/sw/drivers/eth.c

1,4 → 1,4