URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc
- from Rev 70 to Rev 69
- ↔ Reverse comparison
Rev 70 → Rev 69
/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
1,3 → 1,6
|
`timescale 1ns/100ps |
|
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |
/trunk/backend/std/minsoc_bench_defines.v
1,3 → 1,6
|
`timescale 1ns/100ps |
|
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |
/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v
1,3 → 1,6
|
`timescale 1ns/100ps |
|
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |
/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v
1,3 → 1,6
|
`timescale 1ns/100ps |
|
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |
/trunk/sim/modelsim/run_sim.sh
File deleted
trunk/sim/modelsim/run_sim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/sim/modelsim/compile_design.sh
===================================================================
--- trunk/sim/modelsim/compile_design.sh (revision 70)
+++ trunk/sim/modelsim/compile_design.sh (nonexistent)
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt
\ No newline at end of file
trunk/sim/modelsim/compile_design.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/sim/modelsim/prepare_modelsim.sh
===================================================================
--- trunk/sim/modelsim/prepare_modelsim.sh (revision 70)
+++ trunk/sim/modelsim/prepare_modelsim.sh (nonexistent)
@@ -1,4 +0,0 @@
-#!/bin/bash
-
-vlib minsoc
-vmap minsoc ./minsoc
trunk/sim/modelsim/prepare_modelsim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/sim/bin/minsoc_verilog_files.txt
===================================================================
--- trunk/sim/bin/minsoc_verilog_files.txt (revision 70)
+++ trunk/sim/bin/minsoc_verilog_files.txt (revision 69)
@@ -16,7 +16,6 @@
../../bench/verilog/minsoc_memory_model.v
../../bench/verilog/vpi/dbg_comm_vpi.v
../../bench/verilog/sim_lib/fpga_memory_primitives.v
-../../rtl/verilog/timescale.v
../../rtl/verilog/minsoc_top.v
../../rtl/verilog/minsoc_startup/spi_top.v
../../rtl/verilog/minsoc_startup/spi_defines.v
Index: trunk/rtl/verilog/timescale.v
===================================================================
--- trunk/rtl/verilog/timescale.v (revision 70)
+++ trunk/rtl/verilog/timescale.v (nonexistent)
@@ -1 +0,0 @@
-`timescale 10ns/1ns