Subversion Repositories minsoc

/minsoc_bench_defines.v

minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: configure =================================================================== --- configure (nonexistent) +++ configure (revision 139) @@ -0,0 +1,112 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=altera_3c25_board #this has to have the name of the directory this file is in +DEVICE_PART=EP3C25Q240C8 +CONSTRAINT_FILE='altera_3c25_board.ucf' +FAMILY_PART="Cyclone III" +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/altera +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/altera + +PROJECT_FILE=minsoc_top.qsf + +SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_FAMILY='FAMILY_PART' +FIND_VERSION='SW_VERSION' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part and family for files under $SYNSRC_DIR will patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$PROJECT_FILE > TMPFILE + sed "s/$FIND_FAMILY/$FAMILY_PART/g" TMPFILE > TMPFILE2 + #sed "s/$FIND_VERSION/$SW_VERSION/g" TMPFILE> TMPFILE + echo "Adding settings from constraint file..." + cat $CONSTRAINT_FILE >> TMPFILE2 + + echo "Generating quartus settings from prj files in $SYNSRC_DIR" + for file in "${SYN_FILES[@]}" + do + echo "Adding settings from file $file..." + cat $SYNSRC_DIR/$file >> TMPFILE2 + done + mv TMPFILE2 $SYNSUPPORT_DIR/$PROJECT_FILE + rm TMPFILE + echo "" + echo "Generated quartus settings file in $SYNSUPPORT_DIR/$PROJECT_FILE" + echo "" + + echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..." + cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "For synthesis help go to $SYN_DIR and type \"make\"." + echo "" + echo "" +fi + +echo "Configuration done."

configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_defines.v =================================================================== --- minsoc_defines.v (nonexistent) +++ minsoc_defines.v (revision 139) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef ALTERA_FPGA + `undef CYCLONE_III + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: gcc-opt.mk =================================================================== --- gcc-opt.mk (nonexistent) +++ gcc-opt.mk (revision 139) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: altera_3c25_board.ucf =================================================================== --- altera_3c25_board.ucf (nonexistent) +++ altera_3c25_board.ucf (revision 139) @@ -0,0 +1,16 @@ +# Altera 3c25 board based pinout and definitions. +# This file uses quartus qsf file format for compose final config file. + +# RS232 Port +set_location_assignment PIN_12 -to uart_srx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_srx +set_location_assignment PIN_14 -to uart_stx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_stx + +# 50 Mhz Pin +set_location_assignment PIN_152 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# Reset pin. +set_location_assignment PIN_200 -to reset +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset Index: board.h =================================================================== --- board.h (nonexistent) +++ board.h (revision 139) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif

board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: orp.ld =================================================================== --- orp.ld (nonexistent) +++ orp.ld (revision 139) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property