URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/tags/release-0.9/sw/support
- from Rev 36 to Rev 42
- ↔ Reverse comparison
Rev 36 → Rev 42
/Makefile.inc
0,0 → 1,20
# File to be included in all makefiles |
|
OR32_TOOL_PREFIX=or32-elf |
|
#GCC_LIB_OPTS= -lgcc -liberty |
|
GCC_OPT=-mhard-mul -g -nostdlib |
|
ifdef UART_PRINTF |
GCC_OPT += -DUART_PRINTF |
endif |
|
FLASH_MEM_HEX_FILE_SUFFIX=-twobyte-sizefirst |
SRAM_MEM_HEX_FILE_SUFFIX=-fourbyte |
|
|
# Global clean rule |
clean: |
@echo "Cleaning `pwd`" |
@rm -f *.o *.or32 *.log *.bin *.srec *.hex *.log stdout.txt *.vmem *.asm *.a stdout.txt |
Makefile.inc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: except.S
===================================================================
--- except.S (nonexistent)
+++ except.S (revision 42)
@@ -0,0 +1,276 @@
+#include "spr_defs.h"
+
+// Linked from 0x200, so subtract 0x200 from each .org
+.section .vectors, "ax"
+
+/*
+.org 0x100
+
+_reset:
+ l.nop
+ l.j _reset_except
+ l.nop
+*/
+.org 0x000
+
+_except_200:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _buserr_except
+ l.nop
+
+.org 0x100
+
+_except_300:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _dpf_except
+ l.nop
+
+.org 0x200
+
+_except_400:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _ipf_except
+ l.nop
+
+.org 0x300
+
+_except_500:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _tick_except
+ l.nop
+
+.org 0x400
+
+_except_600:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _align_except
+ l.nop
+
+.org 0x500
+
+_except_700:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _illegal_except
+ l.nop
+
+.org 0x600
+
+_except_800:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _ext_except //jmp to C interrupt handler (returns later to end_except)
+ l.nop
+
+
+.org 0x700
+
+_except_900:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _dtlbmiss_except
+ l.nop
+
+.org 0x800
+
+_except_a00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _itlbmiss_except
+ l.nop
+
+.org 0x900
+
+_except_b00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _range_except
+ l.nop
+
+.org 0xa00
+
+_except_c00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _syscall_except
+ l.nop
+
+.org 0xb00
+
+_except_d00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _res1_except
+ l.nop
+
+.org 0xc00
+
+_except_e00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _trap_except
+ l.nop
+
+.org 0xd00
+
+_except_f00:
+ l.nop
+ l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
+ l.sw 0x18(r1),r9 //save register r9(return addr) to stack
+ l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
+ l.nop
+
+ l.movhi r9,hi(end_except) //set return addr to end_except instruction
+ l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
+ l.j _res2_except
+ l.nop
+
+store_regs: //save registers r3-r31 (except r9) to stack
+ l.sw 0x00(r1),r3
+ l.sw 0x04(r1),r4
+ l.sw 0x08(r1),r5
+ l.sw 0x0c(r1),r6
+ l.sw 0x10(r1),r7
+ l.sw 0x14(r1),r8
+ l.sw 0x1c(r1),r10
+ l.sw 0x20(r1),r11
+ l.sw 0x24(r1),r12
+ l.sw 0x28(r1),r13
+ l.sw 0x2c(r1),r14
+ l.sw 0x30(r1),r15
+ l.sw 0x34(r1),r16
+ l.sw 0x38(r1),r17
+ l.sw 0x3c(r1),r18
+ l.sw 0x40(r1),r19
+ l.sw 0x44(r1),r20
+ l.sw 0x48(r1),r21
+ l.sw 0x4c(r1),r22
+ l.sw 0x50(r1),r23
+ l.sw 0x54(r1),r24
+ l.sw 0x58(r1),r25
+ l.sw 0x5c(r1),r26
+ l.sw 0x60(r1),r27
+ l.sw 0x64(r1),r28
+ l.sw 0x68(r1),r29
+ l.sw 0x6c(r1),r30
+ l.sw 0x70(r1),r31
+ l.jr r9
+ l.nop
+
+end_except: //load back registers from stack r3-r31
+ l.lwz r3,0x00(r1)
+ l.lwz r4,0x04(r1)
+ l.lwz r5,0x08(r1)
+ l.lwz r6,0x0c(r1)
+ l.lwz r7,0x10(r1)
+ l.lwz r8,0x14(r1)
+ l.lwz r9,0x18(r1)
+ l.lwz r10,0x1c(r1)
+ l.lwz r11,0x20(r1)
+ l.lwz r12,0x24(r1)
+ l.lwz r13,0x28(r1)
+ l.lwz r14,0x2c(r1)
+ l.lwz r15,0x30(r1)
+ l.lwz r16,0x34(r1)
+ l.lwz r17,0x38(r1)
+ l.lwz r18,0x3c(r1)
+ l.lwz r19,0x40(r1)
+ l.lwz r20,0x44(r1)
+ l.lwz r21,0x48(r1)
+ l.lwz r22,0x4c(r1)
+ l.lwz r23,0x50(r1)
+ l.lwz r24,0x54(r1)
+ l.lwz r25,0x58(r1)
+ l.lwz r26,0x5c(r1)
+ l.lwz r27,0x60(r1)
+ l.lwz r28,0x64(r1)
+ l.lwz r29,0x68(r1)
+ l.lwz r30,0x6c(r1)
+ l.lwz r31,0x70(r1)
+ l.addi r1,r1,116 //free stack places
+ l.rfe //recover SR register and prior PC (jumps back to program)
+ l.nop
+
except.S
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart.c
===================================================================
--- uart.c (nonexistent)
+++ uart.c (revision 42)
@@ -0,0 +1,77 @@
+#include "support.h"
+#include "board.h"
+#include "uart.h"
+
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
+#define WAIT_FOR_XMITR \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
+
+#define WAIT_FOR_THRE \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
+
+#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
+
+#define WAIT_FOR_CHAR \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
+
+#define UART_TX_BUFF_LEN 32
+#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
+
+char tx_buff[UART_TX_BUFF_LEN];
+volatile int tx_level, rx_level;
+
+void uart_init(void)
+{
+ int divisor;
+
+ /* Reset receiver and transmiter */
+ /* Set RX interrupt for each byte */
+ REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
+
+ /* Enable RX interrupt */
+ REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
+
+ /* Set 8 bit char, 1 stop bit, no parity */
+ REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
+
+ /* Set baud rate */
+ divisor = IN_CLK/(16 * UART_BAUD_RATE);
+ REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
+ REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
+ REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
+ REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
+
+ return;
+}
+
+void uart_putc(char c)
+{
+ unsigned char lsr;
+
+ WAIT_FOR_THRE;
+ REG8(UART_BASE + UART_TX) = c;
+ if(c == '\n') {
+ WAIT_FOR_THRE;
+ REG8(UART_BASE + UART_TX) = '\r';
+ }
+ WAIT_FOR_XMITR;
+}
+
+
+
+char uart_getc()
+{
+ unsigned char lsr;
+ char c;
+
+// WAIT_FOR_CHAR;
+ c = REG8(UART_BASE + UART_RX);
+ return c;
+}
uart.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: support.c
===================================================================
--- support.c (nonexistent)
+++ support.c (revision 42)
@@ -0,0 +1,167 @@
+/* Support */
+
+#ifndef OR32
+#include
+#endif
+
+#include "spr_defs.h"
+#include "support.h"
+#include "int.h"
+
+#ifdef UART_PRINTF
+//#include "snprintf.h"
+#include "vfnprintf.h"
+#include "uart.h"
+#endif
+
+#if OR32
+void int_main();
+
+void ext_except()
+{
+ int_main();
+}
+
+/* Start function, called by reset exception handler. */
+void reset ()
+{
+ int i = main();
+ or32_exit (i);
+}
+
+/* return value by making a syscall */
+void or32_exit (int i)
+{
+ asm("l.add r3,r0,%0": : "r" (i));
+ asm("l.nop %0": :"K" (NOP_EXIT));
+ while (1);
+}
+
+#ifdef UART_PRINTF
+
+static int uart_init_done = 0;
+
+#define PRINTFBUFFER_SIZE 512
+char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer
+
+void minsoc_printf(const char *fmt, ...)
+{
+ // init uart if not done already
+ if (!uart_init_done)
+ {
+ uart_init();
+ uart_init_done = 1;
+ }
+
+ va_list args;
+ va_start(args, fmt);
+
+ //int str_l = vsnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
+ int str_l = vfnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
+
+ if (!str_l) return; // no length string - just return
+
+ int c=0;
+ // now print each char via the UART
+ while (c < str_l)
+ uart_putc(PRINTFBUFFER[c++]);
+
+ va_end(args);
+}
+
+#else
+/* activate printf support in simulator */
+void minsoc_printf(const char *fmt, ...)
+{
+ va_list args;
+ va_start(args, fmt);
+ __asm__ __volatile__ (" l.addi\tr3,%1,0\n \
+ l.addi\tr4,%2,0\n \
+ l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args));
+}
+
+/*
+void *memcpy (void *__restrict dstvoid,
+ __const void *__restrict srcvoid, size_t length)
+{
+ char *dst = dstvoid;
+ const char *src = (const char *) srcvoid;
+
+ while (length--)
+ *dst++ = *src++;
+ return dst;
+}
+*/
+#endif
+
+
+
+
+
+/* print long */
+void report(unsigned long value)
+{
+ asm("l.addi\tr3,%0,0": :"r" (value));
+ asm("l.nop %0": :"K" (NOP_REPORT));
+}
+
+/* just to satisfy linker */
+void __main()
+{
+}
+
+/* start_TIMER */
+void start_timer(int x)
+{
+}
+
+/* read_TIMER */
+/* Returns a value since started in uS */
+unsigned int read_timer(int x)
+{
+ unsigned long count = 0;
+
+ /* Read the Time Stamp Counter */
+/* asm("simrdtsc %0" :"=r" (count)); */
+ /*asm("l.sys 201"); */
+ return count;
+}
+
+/* For writing into SPR. */
+void mtspr(unsigned long spr, unsigned long value)
+{
+ asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
+}
+
+/* For reading SPR. */
+unsigned long mfspr(unsigned long spr)
+{
+ unsigned long value;
+ asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
+ return value;
+}
+
+#else
+void report(unsigned long value)
+{
+ printf("report(0x%x);\n", (unsigned) value);
+}
+
+/* start_TIMER */
+void start_timer(int tmrnum)
+{
+}
+
+/* read_TIMER */
+/* Returns a value since started in uS */
+unsigned int read_timer(int tmrnum)
+{
+ struct timeval tv;
+ struct timezone tz;
+
+ gettimeofday(&tv, &tz);
+
+ return(tv.tv_sec*1000000+tv.tv_usec);
+}
+
+#endif
support.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: vfnprintf.c
===================================================================
--- vfnprintf.c (nonexistent)
+++ vfnprintf.c (revision 42)
@@ -0,0 +1,686 @@
+// Ripped out of latest ecos build from http://sources-redhat.mirrors.airband.net/ecos/releases/ecos-3.0b1/ecos-3.0beta1.i386linux.tar.bz2
+// File: ecos-3.0b1/packages/language/c/libc/stdio/v3_0b1/src/output/vfnprintf.cxx
+
+// Hacked to pieces so it would work with OpenRISC compiler, not using libc
+//===========================================================================
+//
+// vfnprintf.c
+//
+// I/O routines for vfnprintf() for use with ANSI C library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jlarmour
+// Contributors:
+// Date: 2000-04-20
+// Purpose:
+// Description:
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+//
+// This code is based on original code with the following copyright:
+//
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Chris Torek.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+// CONFIGURATION
+
+//#include // Configuration header
+//#include // Configuration header for mb support
+
+// INCLUDES
+
+//#include // For mbtowc()
+#include
+
+
+//#include // Common type definitions and support
+#define CYG_MACRO_START do {
+#define CYG_MACRO_END } while (0)
+
+#define CYG_EMPTY_STATEMENT CYG_MACRO_START CYG_MACRO_END
+
+#define CYG_UNUSED_PARAM( _type_, _name_ ) CYG_MACRO_START \
+ _type_ __tmp1 = (_name_); \
+ _type_ __tmp2 = __tmp1; \
+ __tmp1 = __tmp2; \
+CYG_MACRO_END
+
+#include // Variable argument definitions
+
+#include "vfnprintf.h"
+
+
+# define BUF 40
+
+/*
+ * Actual printf innards.
+ *
+ * This code is large and complicated...
+ */
+
+
+/*
+ * Macros for converting digits to letters and vice versa
+ */
+#define to_digit(c) ((c) - '0')
+#define is_digit(c) ((unsigned)to_digit(c) <= 9)
+#define to_char(n) ((n) + '0')
+
+/*
+ * Flags used during conversion.
+ */
+#define ALT 0x001 /* alternate form */
+#define HEXPREFIX 0x002 /* add 0x or 0X prefix */
+#define LADJUST 0x004 /* left adjustment */
+#define LONGDBL 0x008 /* long double; unimplemented */
+#define LONGINT 0x010 /* long integer */
+#define QUADINT 0x020 /* quad integer */
+#define SHORTINT 0x040 /* short integer */
+#define ZEROPAD 0x080 /* zero (as opposed to blank) pad */
+#define FPT 0x100 /* Floating point number */
+#define SIZET 0x200 /* size_t */
+
+int
+strlen(const char *s)
+{
+ const char *p;
+
+ for (p = s; *p != '\0'; p++)
+ ;
+ return (s - p);
+}
+
+void *
+memcpy(void *dst, const void *src, size_t len)
+{
+ const char *csrc;
+ char *cdst;
+ int i;
+
+ cdst = dst;
+ csrc = src;
+ for (i = len; i >= 0; i--) {
+ cdst[i] = csrc[i];
+ }
+ return dst;
+}
+
+// Function which prints back to the buffer, ptr, len bytes
+// returns 1 if it should finish up, otherwise 0 to continue
+int print_back_to_string(char * ptr, int len, size_t * n, int * ret, char ** stream)
+{
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+ do {
+ int length = MIN( (int) len, *n - *ret - 1);
+ memcpy(*stream + *ret, ptr, length);
+ if (length < (int)len) {
+ *ret += length;
+ return 1; // finish up
+ }
+
+ } while(0);
+
+ return 0;
+}
+
+//externC int
+int
+//vfnprintf ( FILE *stream, size_t n, const char *format, va_list arg) __THROW
+vfnprintf ( char *stream, size_t n, const char *format, va_list arg)
+{
+ char *fmt; /* format string */
+ int ch; /* character from fmt */
+ int x, y; /* handy integers (short term usage) */
+ char *cp; /* handy char pointer (short term usage) */
+ int flags; /* flags as above */
+
+ int ret; /* return value accumulator */
+ int width; /* width from format (%8d), or 0 */
+ int prec; /* precision from format (%.3d), or -1 */
+ char sign; /* sign prefix (' ', '+', '-', or \0) */
+ wchar_t wc;
+
+#define quad_t long long
+#define u_quad_t unsigned long long
+
+ u_quad_t _uquad; /* integer arguments %[diouxX] */
+ enum { OCT, DEC, HEX } base;/* base for [diouxX] conversion */
+ int dprec; /* a copy of prec if [diouxX], 0 otherwise */
+ int fieldsz; /* field size expanded by sign, etc */
+ int realsz; /* field size expanded by dprec */
+ int size; /* size of converted field or string */
+ char *xdigs; /* digits for [xX] conversion */
+#define NIOV 8
+ char buf[BUF]; /* space for %c, %[diouxX], %[eEfgG] */
+ char ox[2]; /* space for 0x hex-prefix */
+
+ /*
+ * Choose PADSIZE to trade efficiency vs. size. If larger printf
+ * fields occur frequently, increase PADSIZE and make the initialisers
+ * below longer.
+ */
+#define PADSIZE 16 /* pad chunk size */
+ static char blanks[PADSIZE] =
+ {' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '};
+ static char zeroes[PADSIZE] =
+ {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'};
+
+ /*
+ * BEWARE, these `goto error' on error, and PAD uses `n'.
+ */
+
+ // We'll copy len bytes from (char*) ptr, into the output stream
+ // making sure we don't go over the end, so calculate length to be
+ // either the whole length we've been passed, or the whole length
+ // that is possible to write
+ // We finish if it was not possible to write the entire variable
+ // into the buffer, ie we had to write all we could, not all we
+ // wanted to.
+ /*
+ #define PRINT(ptr, len) \
+ CYG_MACRO_START \
+ int length = MIN( (int) len, n - ret - 1); \
+ char* begin_stream_write = stream; \
+ stream = memcpy(stream, ptr, length); \
+ length = (unsigned long) stream - (unsigned long) begin_stream_write; \
+ if (length < (int)len) { \
+ ret += length; \
+ goto done; \
+ } \
+ CYG_MACRO_END
+ */
+
+ //PRINT(with, PADSIZE); \
+ //PRINT(with, x); \
+
+#define PAD(howmany, with) \
+ CYG_MACRO_START \
+ if ((x = (howmany)) > 0) { \
+ while (x > PADSIZE) { \
+ if (print_back_to_string(with, PADSIZE, &n, &ret, &stream)) goto done; \
+ x -= PADSIZE; \
+ } \
+ if (print_back_to_string(with, x, &n, &ret, &stream))goto done; \
+ } \
+ CYG_MACRO_END
+
+ /*
+ * To extend shorts properly, we need both signed and unsigned
+ * argument extraction methods.
+ */
+
+#define SARG() \
+ (flags&QUADINT ? va_arg(arg, long long) : \
+ flags&LONGINT ? va_arg(arg, long) : \
+ flags&SHORTINT ? (long)(short)va_arg(arg, int) : \
+ flags&SIZET ? (long)va_arg(arg, size_t) : \
+ (long)va_arg(arg, int))
+#define UARG() \
+ (flags&QUADINT ? va_arg(arg, unsigned long long) : \
+ flags&LONGINT ? va_arg(arg, unsigned long) : \
+ flags&SHORTINT ? (unsigned long)(unsigned short)va_arg(arg, int) : \
+ flags&SIZET ? va_arg(arg, size_t) : \
+ (unsigned long)va_arg(arg, unsigned int))
+
+
+ xdigs = NULL; // stop compiler whinging
+ fmt = (char *)format;
+ ret = 0;
+
+ /*
+ * Scan the format for conversions (`%' character).
+ */
+ for (;;) {
+ cp = (char *)fmt; // char pointer - set to where we begin looking from
+ while ((x = ((wc = *fmt) != 0))) { // While, wc=next char and x is one while there's still chars left
+ fmt += x; // increment the pointer to the char
+ if (wc == '%') { // check if it's the beginning of
+ fmt--; // Decrement the char pointer, actually
+ break;
+ }
+ }
+ if ((y = fmt - cp) != 0) { // y is length of string to copy out just now
+ //PRINT(cp, y); // Copy macro
+ if(print_back_to_string(cp, y, &n, &ret, &stream)) goto done; // Copy macro
+ ret += y; // increment return chars
+ }
+ if ((x <= 0) || (ret >= (int)n)) // @@@ this check with n isn't good enough
+ goto done;
+ fmt++; /* skip over '%' */
+
+ flags = 0;
+ dprec = 0;
+ width = 0;
+ prec = -1;
+ sign = '\0';
+
+ rflag: ch = *fmt++;
+ reswitch: switch (ch) {
+ case ' ':
+ /*
+ * ``If the space and + flags both appear, the space
+ * flag will be ignored.''
+ * -- ANSI X3J11
+ */
+ if (!sign)
+ sign = ' ';
+ goto rflag;
+ case '#':
+ flags |= ALT;
+ goto rflag;
+ case '*':
+ /*
+ * ``A negative field width argument is taken as a
+ * - flag followed by a positive field width.''
+ * -- ANSI X3J11
+ * They don't exclude field widths read from args.
+ */
+ if ((width = va_arg(arg, int)) >= 0)
+ goto rflag;
+ width = -width;
+ /* FALLTHROUGH */
+ case '-':
+ flags |= LADJUST;
+ goto rflag;
+ case '+':
+ sign = '+';
+ goto rflag;
+ case '.':
+ if ((ch = *fmt++) == '*') {
+ x = va_arg(arg, int);
+ prec = x < 0 ? -1 : x;
+ goto rflag;
+ }
+ x = 0;
+ while (is_digit(ch)) {
+ x = 10 * x + to_digit(ch);
+ ch = *fmt++;
+ }
+ prec = x < 0 ? -1 : x;
+ goto reswitch;
+ case '0':
+ /*
+ * ``Note that 0 is taken as a flag, not as the
+ * beginning of a field width.''
+ * -- ANSI X3J11
+ */
+ flags |= ZEROPAD;
+ goto rflag;
+ case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ x = 0;
+ do {
+ x = 10 * x + to_digit(ch);
+ ch = *fmt++;
+ } while (is_digit(ch));
+ width = x;
+ goto reswitch;
+ case 'h':
+ flags |= SHORTINT;
+ goto rflag;
+ case 'l':
+ if (*fmt == 'l') {
+ fmt++;
+ flags |= QUADINT;
+ } else {
+ flags |= LONGINT;
+ }
+ goto rflag;
+ case 'q':
+ flags |= QUADINT;
+ goto rflag;
+ case 'c':
+ *(cp = buf) = va_arg(arg, int);
+ size = 1;
+ sign = '\0';
+ break;
+ case 'D':
+ flags |= LONGINT;
+ /*FALLTHROUGH*/
+ case 'd':
+ case 'i':
+ _uquad = SARG();
+#ifndef _NO_LONGLONG
+ if ((quad_t)_uquad < 0)
+#else
+ if ((long) _uquad < 0)
+#endif
+ {
+
+ _uquad = -_uquad;
+ sign = '-';
+ }
+ base = DEC;
+ goto number;
+
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'g':
+ case 'G':
+ // Output nothing at all
+ (void) va_arg(arg, double); // take off arg anyway
+ cp = "";
+ size = 0;
+ sign = '\0';
+ break;
+
+ case 'n':
+#ifndef _NO_LONGLONG
+ if (flags & QUADINT)
+ *va_arg(arg, quad_t *) = ret;
+ else
+#endif
+ if (flags & LONGINT)
+ *va_arg(arg, long *) = ret;
+ else if (flags & SHORTINT)
+ *va_arg(arg, short *) = ret;
+ else if (flags & SIZET)
+ *va_arg(arg, size_t *) = ret;
+ else
+ *va_arg(arg, int *) = ret;
+ continue; /* no output */
+ case 'O':
+ flags |= LONGINT;
+ /*FALLTHROUGH*/
+ case 'o':
+ _uquad = UARG();
+ base = OCT;
+ goto nosign;
+ case 'p':
+ /*
+ * ``The argument shall be a pointer to void. The
+ * value of the pointer is converted to a sequence
+ * of printable characters, in an implementation-
+ * defined manner.''
+ * -- ANSI X3J11
+ */
+ /* NOSTRICT */
+ _uquad = (unsigned long)va_arg(arg, void *);
+ base = HEX;
+ xdigs = (char *)"0123456789abcdef";
+ flags |= HEXPREFIX;
+ ch = 'x';
+ goto nosign;
+ case 's':
+ if ((cp = va_arg(arg, char *)) == NULL)
+ cp = (char *)"(null)";
+ if (prec >= 0) {
+ /*
+ * can't use strlen; can only look for the
+ * NUL in the first `prec' characters, and
+ * strlen() will go further.
+ */
+ char *p = (char *)memchr(cp, 0, prec);
+
+ if (p != NULL) {
+ size = p - cp;
+ if (size > prec)
+ size = prec;
+ } else
+ size = prec;
+ } else
+ size = strlen(cp);
+ sign = '\0';
+ break;
+ case 'U':
+ flags |= LONGINT;
+ /*FALLTHROUGH*/
+ case 'u':
+ _uquad = UARG();
+ base = DEC;
+ goto nosign;
+ case 'X':
+ xdigs = (char *)"0123456789ABCDEF";
+ goto hex;
+ case 'x':
+ xdigs = (char *)"0123456789abcdef";
+ hex: _uquad = UARG();
+ base = HEX;
+ /* leading 0x/X only if non-zero */
+ if (flags & ALT && _uquad != 0)
+ flags |= HEXPREFIX;
+
+ /* unsigned conversions */
+ nosign: sign = '\0';
+ /*
+ * ``... diouXx conversions ... if a precision is
+ * specified, the 0 flag will be ignored.''
+ * -- ANSI X3J11
+ */
+ number: if ((dprec = prec) >= 0)
+ flags &= ~ZEROPAD;
+
+ /*
+ * ``The result of converting a zero value with an
+ * explicit precision of zero is no characters.''
+ * -- ANSI X3J11
+ */
+ cp = buf + BUF;
+ if (_uquad != 0 || prec != 0) {
+ /*
+ * Unsigned mod is hard, and unsigned mod
+ * by a constant is easier than that by
+ * a variable; hence this switch.
+ */
+ switch (base) {
+ case OCT:
+ do {
+ *--cp = to_char(_uquad & 7);
+ _uquad >>= 3;
+ } while (_uquad);
+ /* handle octal leading 0 */
+ if (flags & ALT && *cp != '0')
+ *--cp = '0';
+ break;
+
+ case DEC:
+ if (!(flags & QUADINT)) {
+ /* many numbers are 1 digit */
+ unsigned long v = (unsigned long)_uquad;
+ while (v >= 10) {
+ /* The following is usually faster than using a modulo */
+ unsigned long next = v / 10;
+ *--cp = to_char(v - (next * 10));
+ v = next;
+ }
+ *--cp = to_char(v);
+ }
+ else {
+ while (_uquad >= 10) {
+ /* The following is usually faster than using a modulo */
+ u_quad_t next = _uquad / 10;
+ *--cp = to_char(_uquad - (next * 10));
+ _uquad = next;
+ }
+ *--cp = to_char(_uquad);
+ }
+ break;
+
+ case HEX:
+ do {
+ *--cp = xdigs[_uquad & 15];
+ _uquad >>= 4;
+ } while (_uquad);
+ break;
+
+ default:
+ cp = (char *)"bug in vfprintf: bad base";
+ size = strlen(cp);
+ goto skipsize;
+ }
+ }
+ size = buf + BUF - cp;
+ skipsize:
+ break;
+ case 'z':
+ flags |= SIZET;
+ goto rflag;
+ default: /* "%?" prints ?, unless ? is NUL */
+ if (ch == '\0')
+ goto done;
+ /* pretend it was %c with argument ch */
+ cp = buf;
+ *cp = ch;
+ size = 1;
+ sign = '\0';
+ break;
+ }
+
+ /*
+ * All reasonable formats wind up here. At this point, `cp'
+ * points to a string which (if not flags&LADJUST) should be
+ * padded out to `width' places. If flags&ZEROPAD, it should
+ * first be prefixed by any sign or other prefix; otherwise,
+ * it should be blank padded before the prefix is emitted.
+ * After any left-hand padding and prefixing, emit zeroes
+ * required by a decimal [diouxX] precision, then print the
+ * string proper, then emit zeroes required by any leftover
+ * floating precision; finally, if LADJUST, pad with blanks.
+ *
+ * Compute actual size, so we know how much to pad.
+ * fieldsz excludes decimal prec; realsz includes it.
+ */
+#ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT
+ fieldsz = size + fpprec;
+#else
+ fieldsz = size;
+#endif
+ if (sign)
+ fieldsz++;
+ else if (flags & HEXPREFIX)
+ fieldsz+= 2;
+ realsz = dprec > fieldsz ? dprec : fieldsz;
+
+ /* right-adjusting blank padding */
+ if ((flags & (LADJUST|ZEROPAD)) == 0) {
+ if (width - realsz > 0) {
+ PAD(width - realsz, blanks);
+ ret += width - realsz;
+ }
+ }
+
+ /* prefix */
+ if (sign) {
+ //PRINT(&sign, 1);
+ if(print_back_to_string(&sign, 1, &n, &ret, &stream))goto done;
+ ret++;
+ } else if (flags & HEXPREFIX) {
+ ox[0] = '0';
+ ox[1] = ch;
+ //PRINT(ox, 2);
+ if(print_back_to_string(ox, 2, &n, &ret, &stream))goto done;
+ ret += 2;
+ }
+
+ /* right-adjusting zero padding */
+ if ((flags & (LADJUST|ZEROPAD)) == ZEROPAD) {
+ if (width - realsz > 0) {
+ PAD(width - realsz, zeroes);
+ ret += width - realsz;
+ }
+ }
+
+ if (dprec - fieldsz > 0) {
+ /* leading zeroes from decimal precision */
+ PAD(dprec - fieldsz, zeroes);
+ ret += dprec - fieldsz;
+ }
+
+ /* the string or number proper */
+ //PRINT(cp, size);
+ if(print_back_to_string(cp,size, &n, &ret, &stream))goto done;
+ ret += size;
+
+#ifdef CYGSEM_LIBC_STDIO_PRINTF_FLOATING_POINT
+ /* trailing f.p. zeroes */
+ PAD(fpprec, zeroes);
+ ret += fpprec;
+#endif
+
+ /* left-adjusting padding (always blank) */
+ if (flags & LADJUST) {
+ if (width - realsz > 0) {
+ PAD(width - realsz, blanks);
+ ret += width - realsz;
+ }
+ }
+
+ }
+
+ done:
+ error:
+ return ret;// remove this error stuff (((Cyg_OutputStream *) stream)->get_error() ? EOF : ret);
+ /* NOTREACHED */
+}
+
+
+
+// EOF vfnprintf.c
vfnprintf.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: support.h
===================================================================
--- support.h (nonexistent)
+++ support.h (revision 42)
@@ -0,0 +1,69 @@
+/* Support file for or32 tests. This file should is included
+ in each test. It calls main() function and add support for
+ basic functions */
+
+#ifndef SUPPORT_H
+#define SUPPORT_H
+
+#include
+#include
+#include
+#define OR1K 1 //ME added
+#if OR1K
+
+/* Register access macros */
+#define REG8(add) *((volatile unsigned char *)(add))
+#define REG16(add) *((volatile unsigned short *)(add))
+#define REG32(add) *((volatile unsigned long *)(add))
+
+void or32_printf(const char *fmt, ...);
+
+/* For writing into SPR. */
+void mtspr(unsigned long spr, unsigned long value);
+
+/* For reading SPR. */
+unsigned long mfspr(unsigned long spr);
+
+#else /* OR1K */
+
+#include
+
+#endif /* OR1K */
+
+#define printf or32_printf
+
+/* Function to be called at entry point - not defined here. */
+int main ();
+
+/* Prints out a value */
+void report(unsigned long value);
+
+/* return value by making a syscall */
+extern void or32_exit (int i) __attribute__ ((__noreturn__));
+
+/* memcpy clone */
+/*
+extern void *memcpy (void *__restrict __dest,
+ __const void *__restrict __src, size_t __n);
+*/
+
+/* Timer functions */
+extern void start_timer(int);
+extern unsigned int read_timer(int);
+
+extern unsigned long excpt_buserr;
+extern unsigned long excpt_dpfault;
+extern unsigned long excpt_ipfault;
+extern unsigned long excpt_tick;
+extern unsigned long excpt_align;
+extern unsigned long excpt_illinsn;
+extern unsigned long excpt_int;
+extern unsigned long excpt_dtlbmiss;
+extern unsigned long excpt_itlbmiss;
+extern unsigned long excpt_range;
+extern unsigned long excpt_syscall;
+extern unsigned long excpt_break;
+extern unsigned long excpt_trap;
+
+
+#endif /* SUPPORT_H */
support.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: board.h
===================================================================
--- board.h (nonexistent)
+++ board.h (revision 42)
@@ -0,0 +1,52 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define MC_ENABLED 0
+
+#define IC_ENABLE 0
+#define IC_SIZE 8192
+#define DC_ENABLE 0
+#define DC_SIZE 8192
+
+
+#define IN_CLK 25000000
+
+#define TICKS_PER_SEC 100
+
+#define STACK_SIZE 0x01000
+
+#define UART_BAUD_RATE 115200
+
+#define UART_BASE 0x90000000
+#define UART_IRQ 2
+#define ETH_BASE 0x92000000
+#define ETH_IRQ 4
+#define I2C_BASE 0x9D000000
+#define I2C_IRQ 3
+#define CAN_BASE 0x94000000
+#define CAN_IRQ 5
+
+#define MC_BASE_ADDR 0x60000000
+#define SPI_BASE 0xa0000000
+
+#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
+
+#define BOARD_DEF_IP 0x0a010185
+#define BOARD_DEF_MASK 0xff000000
+#define BOARD_DEF_GW 0x0a010101
+
+#define ETH_MACADDR0 0x00
+#define ETH_MACADDR1 0x12
+#define ETH_MACADDR2 0x34
+#define ETH_MACADDR3 0x56
+#define ETH_MACADDR4 0x78
+#define ETH_MACADDR5 0x9a
+
+
+/* Whether online help is available -- saves space */
+#define HELP_ENABLED 1
+
+/* Whether self check is enabled */
+#define SELF_CHECK 1
+
+#endif
board.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 42)
@@ -0,0 +1,37 @@
+all: libsupport.a reset-nocache.o reset-ic.o reset-dc.o reset-icdc.o
+
+libsupport.a: support.o int.o except.o uart.o vfnprintf.o
+ $(OR32_TOOL_PREFIX)-ar cru libsupport.a support.o except.o int.o uart.o vfnprintf.o
+ $(OR32_TOOL_PREFIX)-ranlib libsupport.a
+
+support.o: support.c
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $?
+
+reset-nocache.o: reset.S
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=0 -o $@ $?
+
+reset-dc.o: reset.S
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=0 -DDC=1 -o $@ $?
+
+reset-ic.o: reset.S
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=0 -o $@ $?
+
+reset-icdc.o: reset.S
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -DIC=1 -DDC=1 -o $@ $?
+
+except.o: except.S
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $?
+
+uart.o: uart.c
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $?
+
+#snprintf.o: snprintf.c
+# $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -O2 -c -o $@ $?
+
+vfnprintf.o: vfnprintf.c
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $?
+
+int.o: int.c
+ $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) -c -o $@ $?
+
+include Makefile.inc
Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: int.c
===================================================================
--- int.c (nonexistent)
+++ int.c (revision 42)
@@ -0,0 +1,83 @@
+/* This file is part of test microkernel for OpenRISC 1000. */
+/* (C) 2001 Simon Srot, srot@opencores.org */
+
+#include "support.h"
+#include "spr_defs.h"
+#include "int.h"
+
+#ifdef OR1K
+
+/* Interrupt handlers table */
+struct ihnd int_handlers[MAX_INT_HANDLERS];
+
+/* Initialize routine */
+int int_init()
+{
+ int i;
+
+ for(i = 0; i < MAX_INT_HANDLERS; i++) {
+ int_handlers[i].handler = 0;
+ int_handlers[i].arg = 0;
+ }
+ mtspr(SPR_PICMR, 0x00000000);
+
+ //set OR1200 to accept exceptions
+ mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
+
+ return 0;
+}
+
+/* Add interrupt handler */
+int int_add(unsigned long vect, void (* handler)(void *), void *arg)
+{
+ if(vect >= MAX_INT_HANDLERS)
+ return -1;
+
+ int_handlers[vect].handler = handler;
+ int_handlers[vect].arg = arg;
+
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
+
+ return 0;
+}
+
+/* Disable interrupt */
+int int_disable(unsigned long vect)
+{
+ if(vect >= MAX_INT_HANDLERS)
+ return -1;
+
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
+
+ return 0;
+}
+
+/* Enable interrupt */
+int int_enable(unsigned long vect)
+{
+ if(vect >= MAX_INT_HANDLERS)
+ return -1;
+
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
+
+ return 0;
+}
+
+/* Main interrupt handler */
+void int_main()
+{
+ unsigned long picsr = mfspr(SPR_PICSR); //process only the interrupts asserted at signal catch, ignore all during process
+ unsigned long i = 0;
+
+ while(i < 32) {
+ if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
+ (*int_handlers[i].handler)(int_handlers[i].arg);
+ }
+ i++;
+ }
+
+ mtspr(SPR_PICSR, 0); //clear interrupt status: all modules have level interrupts, which have to be cleared by software,
+} //thus this is safe, since non processed interrupts will get re-asserted soon enough
+
+
+#endif
int.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: int.h
===================================================================
--- int.h (nonexistent)
+++ int.h (revision 42)
@@ -0,0 +1,15 @@
+
+/* Number of interrupt handlers */
+#define MAX_INT_HANDLERS 32
+
+/* Handler entry */
+struct ihnd {
+ void (*handler)(void *);
+ void *arg;
+};
+
+/* Add interrupt handler */
+int int_add(unsigned long vect, void (* handler)(void *), void *arg);
+
+/* Initialize routine */
+int int_init();
int.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: reset.S
===================================================================
--- reset.S (nonexistent)
+++ reset.S (revision 42)
@@ -0,0 +1,113 @@
+/* Support file for c based tests */
+#include "spr_defs.h"
+#include "board.h"
+#include "mc.h"
+
+ .section .stack
+ .space STACK_SIZE
+_stack:
+
+ .section .reset, "ax"
+
+ .org 0x100
+_reset_vector:
+ l.nop
+ l.nop
+ l.addi r2,r0,0x0
+ l.addi r3,r0,0x0
+ l.addi r4,r0,0x0
+ l.addi r5,r0,0x0
+ l.addi r6,r0,0x0
+ l.addi r7,r0,0x0
+ l.addi r8,r0,0x0
+ l.addi r9,r0,0x0
+ l.addi r10,r0,0x0
+ l.addi r11,r0,0x0
+ l.addi r12,r0,0x0
+ l.addi r13,r0,0x0
+ l.addi r14,r0,0x0
+ l.addi r15,r0,0x0
+ l.addi r16,r0,0x0
+ l.addi r17,r0,0x0
+ l.addi r18,r0,0x0
+ l.addi r19,r0,0x0
+ l.addi r20,r0,0x0
+ l.addi r21,r0,0x0
+ l.addi r22,r0,0x0
+ l.addi r23,r0,0x0
+ l.addi r24,r0,0x0
+ l.addi r25,r0,0x0
+ l.addi r26,r0,0x0
+ l.addi r27,r0,0x0
+ l.addi r28,r0,0x0
+ l.addi r29,r0,0x0
+ l.addi r30,r0,0x0
+ l.addi r31,r0,0x0
+
+/*
+ l.movhi r3,hi(MC_BASE_ADDR)
+ l.ori r3,r3,MC_BA_MASK
+ l.addi r5,r0,0x00
+ l.sw 0(r3),r5
+ */
+ l.movhi r3,hi(_start)
+ l.ori r3,r3,lo(_start)
+ l.jr r3
+ l.nop
+
+ .section .text
+
+_start:
+
+.if IC | DC
+ /* Flush IC and/or DC */
+ l.addi r10,r0,0
+ l.addi r11,r0,0
+ l.addi r12,r0,0
+.if IC
+ l.addi r11,r0,IC_SIZE
+.endif
+.if DC
+ l.addi r12,r0,DC_SIZE
+.endif
+ l.sfleu r12,r11
+ l.bf loop
+ l.nop
+ l.add r11,r0,r12
+loop:
+.if IC
+ l.mtspr r0,r10,SPR_ICBIR
+.endif
+.if DC
+ l.mtspr r0,r10,SPR_DCBIR
+.endif
+ l.sfne r10,r11
+ l.bf loop
+ l.addi r10,r10,16
+
+ /* Enable IC and/or DC */
+ l.addi r10,r0,(SPR_SR_SM)
+.if IC
+ l.ori r10,r10,(SPR_SR_ICE)
+.endif
+.if DC
+ l.ori r10,r10,(SPR_SR_DCE)
+.endif
+ l.mtspr r0,r10,SPR_SR
+ l.nop
+ l.nop
+ l.nop
+ l.nop
+ l.nop
+.endif
+
+ /* Set stack pointer */
+ l.movhi r1,hi(_stack)
+ l.ori r1,r1,lo(_stack)
+
+ /* Jump to main */
+ l.movhi r2,hi(_reset)
+ l.ori r2,r2,lo(_reset)
+ l.jr r2
+ l.nop
+
reset.S
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mc.h
===================================================================
--- mc.h (nonexistent)
+++ mc.h (revision 42)
@@ -0,0 +1,111 @@
+/* mc.h -- Simulation of Memory Controller
+ Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* Prototypes */
+#ifndef __MC_H
+#define __MC_H
+
+#define N_CE (8)
+
+#define MC_CSR (0x00)
+#define MC_POC (0x04)
+#define MC_BA_MASK (0x08)
+#define MC_CSC(i) (0x10 + (i) * 8)
+#define MC_TMS(i) (0x14 + (i) * 8)
+
+#define MC_ADDR_SPACE (MC_CSC(N_CE))
+
+/* POC register field definition */
+#define MC_POC_EN_BW_OFFSET 0
+#define MC_POC_EN_BW_WIDTH 2
+#define MC_POC_EN_MEMTYPE_OFFSET 2
+#define MC_POC_EN_MEMTYPE_WIDTH 2
+
+/* CSC register field definition */
+#define MC_CSC_EN_OFFSET 0
+#define MC_CSC_MEMTYPE_OFFSET 1
+#define MC_CSC_MEMTYPE_WIDTH 2
+#define MC_CSC_BW_OFFSET 4
+#define MC_CSC_BW_WIDTH 2
+#define MC_CSC_MS_OFFSET 6
+#define MC_CSC_MS_WIDTH 2
+#define MC_CSC_WP_OFFSET 8
+#define MC_CSC_BAS_OFFSET 9
+#define MC_CSC_KRO_OFFSET 10
+#define MC_CSC_PEN_OFFSET 11
+#define MC_CSC_SEL_OFFSET 16
+#define MC_CSC_SEL_WIDTH 8
+
+#define MC_CSC_MEMTYPE_SDRAM 0
+#define MC_CSC_MEMTYPE_SSRAM 1
+#define MC_CSC_MEMTYPE_ASYNC 2
+#define MC_CSC_MEMTYPE_SYNC 3
+
+#define MC_CSR_VALID 0xFF000703LU
+#define MC_POC_VALID 0x0000000FLU
+#define MC_BA_MASK_VALID 0x000000FFLU
+#define MC_CSC_VALID 0x00FF0FFFLU
+#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
+#define MC_TMS_SSRAM_VALID 0x00000000LU
+#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
+#define MC_TMS_SYNC_VALID 0x01FFFFFFLU
+#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
+
+/* TMS register field definition SDRAM */
+#define MC_TMS_SDRAM_TRFC_OFFSET 24
+#define MC_TMS_SDRAM_TRFC_WIDTH 4
+#define MC_TMS_SDRAM_TRP_OFFSET 20
+#define MC_TMS_SDRAM_TRP_WIDTH 4
+#define MC_TMS_SDRAM_TRCD_OFFSET 17
+#define MC_TMS_SDRAM_TRCD_WIDTH 4
+#define MC_TMS_SDRAM_TWR_OFFSET 15
+#define MC_TMS_SDRAM_TWR_WIDTH 2
+#define MC_TMS_SDRAM_WBL_OFFSET 9
+#define MC_TMS_SDRAM_OM_OFFSET 7
+#define MC_TMS_SDRAM_OM_WIDTH 2
+#define MC_TMS_SDRAM_CL_OFFSET 4
+#define MC_TMS_SDRAM_CL_WIDTH 3
+#define MC_TMS_SDRAM_BT_OFFSET 3
+#define MC_TMS_SDRAM_BL_OFFSET 0
+#define MC_TMS_SDRAM_BL_WIDTH 3
+
+/* TMS register field definition ASYNC */
+#define MC_TMS_ASYNC_TWWD_OFFSET 20
+#define MC_TMS_ASYNC_TWWD_WIDTH 6
+#define MC_TMS_ASYNC_TWD_OFFSET 16
+#define MC_TMS_ASYNC_TWD_WIDTH 4
+#define MC_TMS_ASYNC_TWPW_OFFSET 12
+#define MC_TMS_ASYNC_TWPW_WIDTH 4
+#define MC_TMS_ASYNC_TRDZ_OFFSET 8
+#define MC_TMS_ASYNC_TRDZ_WIDTH 4
+#define MC_TMS_ASYNC_TRDV_OFFSET 0
+#define MC_TMS_ASYNC_TRDV_WIDTH 8
+
+/* TMS register field definition SYNC */
+#define MC_TMS_SYNC_TTO_OFFSET 16
+#define MC_TMS_SYNC_TTO_WIDTH 9
+#define MC_TMS_SYNC_TWR_OFFSET 12
+#define MC_TMS_SYNC_TWR_WIDTH 4
+#define MC_TMS_SYNC_TRDZ_OFFSET 8
+#define MC_TMS_SYNC_TRDZ_WIDTH 4
+#define MC_TMS_SYNC_TRDV_OFFSET 0
+#define MC_TMS_SYNC_TRDV_WIDTH 8
+
+#endif
mc.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spr_defs.h
===================================================================
--- spr_defs.h (nonexistent)
+++ spr_defs.h (revision 42)
@@ -0,0 +1,449 @@
+/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+
+This file is part of OpenRISC 1000 Architectural Simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+/* This file is also used by microkernel test bench. Among
+others it is also used in assembly file(s). */
+
+/* Definition of special-purpose registers (SPRs) */
+
+#define MAX_GRPS (32)
+#define MAX_SPRS_PER_GRP_BITS (11)
+#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
+#define MAX_SPRS (0x10000)
+
+/* Base addresses for the groups */
+#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
+
+/* System control and status group */
+#define SPR_VR (SPRGROUP_SYS + 0)
+#define SPR_UPR (SPRGROUP_SYS + 1)
+#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
+#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
+#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
+#define SPR_DCCFGR (SPRGROUP_SYS + 5)
+#define SPR_ICCFGR (SPRGROUP_SYS + 6)
+#define SPR_DCFGR (SPRGROUP_SYS + 7)
+#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
+#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
+#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
+#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
+#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
+#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
+#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
+#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
+#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
+
+#if 0
+/* Data MMU group */
+#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
+#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
+#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
+#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
+#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
+
+/* Instruction MMU group */
+#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
+#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
+#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
+#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
+#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
+#else
+/* Data MMU group */
+#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
+#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
+#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
+#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
+#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
+
+/* Instruction MMU group */
+#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
+#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
+#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
+#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
+#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
+#endif
+/* Data cache group */
+#define SPR_DCCR (SPRGROUP_DC + 0)
+#define SPR_DCBPR (SPRGROUP_DC + 1)
+#define SPR_DCBFR (SPRGROUP_DC + 2)
+#define SPR_DCBIR (SPRGROUP_DC + 3)
+#define SPR_DCBWR (SPRGROUP_DC + 4)
+#define SPR_DCBLR (SPRGROUP_DC + 5)
+#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
+#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
+
+/* Instruction cache group */
+#define SPR_ICCR (SPRGROUP_IC + 0)
+#define SPR_ICBPR (SPRGROUP_IC + 1)
+#define SPR_ICBIR (SPRGROUP_IC + 2)
+#define SPR_ICBLR (SPRGROUP_IC + 3)
+#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
+#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
+
+/* MAC group */
+#define SPR_MACLO (SPRGROUP_MAC + 1)
+#define SPR_MACHI (SPRGROUP_MAC + 2)
+
+/* Debug group */
+#define SPR_DVR(N) (SPRGROUP_D + (N))
+#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
+#define SPR_DMR1 (SPRGROUP_D + 16)
+#define SPR_DMR2 (SPRGROUP_D + 17)
+#define SPR_DWCR0 (SPRGROUP_D + 18)
+#define SPR_DWCR1 (SPRGROUP_D + 19)
+#define SPR_DSR (SPRGROUP_D + 20)
+#define SPR_DRR (SPRGROUP_D + 21)
+
+/* Performance counters group */
+#define SPR_PCCR(N) (SPRGROUP_PC + (N))
+#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
+
+/* Power management group */
+#define SPR_PMR (SPRGROUP_PM + 0)
+
+/* PIC group */
+#define SPR_PICMR (SPRGROUP_PIC + 0)
+#define SPR_PICPR (SPRGROUP_PIC + 1)
+#define SPR_PICSR (SPRGROUP_PIC + 2)
+
+/* Tick Timer group */
+#define SPR_TTMR (SPRGROUP_TT + 0)
+#define SPR_TTCR (SPRGROUP_TT + 1)
+
+/*
+ * Bit definitions for the Version Register
+ *
+ */
+#define SPR_VR_VER 0xffff0000 /* Processor version */
+#define SPR_VR_REV 0x0000003f /* Processor revision */
+
+/*
+ * Bit definitions for the Unit Present Register
+ *
+ */
+#define SPR_UPR_UP 0x00000001 /* UPR present */
+#define SPR_UPR_DCP 0x00000002 /* Data cache present */
+#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
+#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
+#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
+#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
+#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
+#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
+#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
+#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
+#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
+#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
+#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
+#define SPR_UPR_PMP 0x00002000 /* Power management present */
+#define SPR_UPR_PICP 0x00004000 /* PIC present */
+#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
+#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
+#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
+#define SPR_UPR_CUST 0xff000000 /* Custom units */
+
+/*
+ * Bit definitions for the Supervision Register
+ *
+ */
+#define SPR_SR_CID 0xf0000000 /* Context ID */
+#define SPR_SR_FO 0x00008000 /* Fixed one */
+#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
+#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
+#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
+#define SPR_SR_OV 0x00000800 /* Overflow flag */
+#define SPR_SR_CY 0x00000400 /* Carry flag */
+#define SPR_SR_F 0x00000200 /* Condition Flag */
+#define SPR_SR_CE 0x00000100 /* CID Enable */
+#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
+#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
+#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
+#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
+#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
+#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
+#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
+#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
+
+/*
+ * Bit definitions for the Data MMU Control Register
+ *
+ */
+#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Instruction MMU Control Register
+ *
+ */
+#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Data TLB Match Register
+ *
+ */
+#define SPR_DTLBMR_V 0x00000001 /* Valid */
+#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
+#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Data TLB Translate Register
+ *
+ */
+#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_DTLBTR_A 0x00000010 /* Accessed */
+#define SPR_DTLBTR_D 0x00000020 /* Dirty */
+#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
+#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
+#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
+#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
+#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
+#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
+ SPR_DTLBTR_UWE | \
+ SPR_DTLBTR_SRE | \
+ SPR_DTLBTR_SWE )
+/*
+ * Bit definitions for the Instruction TLB Match Register
+ *
+ */
+#define SPR_ITLBMR_V 0x00000001 /* Valid */
+#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
+#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Instruction TLB Translate Register
+ *
+ */
+#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_ITLBTR_A 0x00000010 /* Accessed */
+#define SPR_ITLBTR_D 0x00000020 /* Dirty */
+#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
+#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
+#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
+#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
+ SPR_ITLBTR_UXE )
+
+
+/*
+ * Bit definitions for Data Cache Control register
+ *
+ */
+#define SPR_DCCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Insn Cache Control register
+ *
+ */
+#define SPR_ICCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Debug Control registers
+ *
+ */
+#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
+#define SPR_DCR_CC 0x0000000e /* Compare condition */
+#define SPR_DCR_SC 0x00000010 /* Signed compare */
+#define SPR_DCR_CT 0x000000e0 /* Compare to */
+
+/* Bit results with SPR_DCR_CC mask */
+#define SPR_DCR_CC_MASKED 0x00000000
+#define SPR_DCR_CC_EQUAL 0x00000001
+#define SPR_DCR_CC_LESS 0x00000002
+#define SPR_DCR_CC_LESSE 0x00000003
+#define SPR_DCR_CC_GREAT 0x00000004
+#define SPR_DCR_CC_GREATE 0x00000005
+#define SPR_DCR_CC_NEQUAL 0x00000006
+
+/* Bit results with SPR_DCR_CT mask */
+#define SPR_DCR_CT_DISABLED 0x00000000
+#define SPR_DCR_CT_IFEA 0x00000020
+#define SPR_DCR_CT_LEA 0x00000040
+#define SPR_DCR_CT_SEA 0x00000060
+#define SPR_DCR_CT_LD 0x00000080
+#define SPR_DCR_CT_SD 0x000000a0
+#define SPR_DCR_CT_LSEA 0x000000c0
+
+/*
+ * Bit definitions for Debug Mode 1 register
+ *
+ */
+#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
+#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
+#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
+#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
+#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
+#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
+#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
+#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
+#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
+#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
+#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
+#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
+#define SPR_DMR1_BT 0x00800000 /* Branch trace */
+#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
+
+/*
+ * Bit definitions for Debug Mode 2 register
+ *
+ */
+#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
+#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
+
+/*
+ * Bit definitions for Debug watchpoint counter registers
+ *
+ */
+#define SPR_DWCR_COUNT 0x0000ffff /* Count */
+#define SPR_DWCR_MATCH 0xffff0000 /* Match */
+
+/*
+ * Bit definitions for Debug stop register
+ *
+ */
+#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
+#define SPR_DSR_AE 0x00000020 /* Alignment exception */
+#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DSR_RE 0x00000400 /* Range exception */
+#define SPR_DSR_SCE 0x00000800 /* System call exception */
+#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
+#define SPR_DSR_TE 0x00002000 /* Trap exception */
+
+/*
+ * Bit definitions for Debug reason register
+ *
+ */
+#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
+#define SPR_DRR_AE 0x00000020 /* Alignment exception */
+#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DRR_RE 0x00000400 /* Range exception */
+#define SPR_DRR_SCE 0x00000800 /* System call exception */
+#define SPR_DRR_TE 0x00001000 /* Trap exception */
+
+/*
+ * Bit definitions for Performance counters mode registers
+ *
+ */
+#define SPR_PCMR_CP 0x00000001 /* Counter present */
+#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
+#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
+#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
+#define SPR_PCMR_LA 0x00000010 /* Load access event */
+#define SPR_PCMR_SA 0x00000020 /* Store access event */
+#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
+#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
+#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
+#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
+#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
+#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
+#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
+#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
+#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
+#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
+
+/*
+ * Bit definitions for the Power management register
+ *
+ */
+#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
+#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
+#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
+#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
+#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
+
+/*
+ * Bit definitions for PICMR
+ *
+ */
+#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
+
+/*
+ * Bit definitions for PICPR
+ *
+ */
+#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
+
+/*
+ * Bit definitions for PICSR
+ *
+ */
+#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
+
+/*
+ * Bit definitions for Tick Timer Control Register
+ *
+ */
+#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
+#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
+#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
+#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
+#define SPR_TTMR_RT 0x40000000 /* Restart tick */
+#define SPR_TTMR_SR 0x80000000 /* Single run */
+#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
+#define SPR_TTMR_M 0xc0000000 /* Tick mode */
+
+/*
+ * l.nop constants
+ *
+ */
+#define NOP_NOP 0x0000 /* Normal nop instruction */
+#define NOP_EXIT 0x0001 /* End of simulation */
+#define NOP_REPORT 0x0002 /* Simple report */
+#define NOP_PRINTF 0x0003 /* Simprintf instruction */
+#define NOP_REPORT_FIRST 0x0400 /* Report with number */
+#define NOP_REPORT_LAST 0x03ff /* Report with number */
spr_defs.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: orp.cfg
===================================================================
--- orp.cfg (nonexistent)
+++ orp.cfg (revision 42)
@@ -0,0 +1,901 @@
+/* sim.cfg -- Simulator configuration script file
+ Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
+
+This file is part of OpenRISC 1000 Architectural Simulator.
+It contains the default configuration and help about configuring
+the simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+
+/* INTRODUCTION
+
+ The ork1sim has various parameters, that are set in configuration files
+ like this one. The user can switch between configurations at startup by
+ specifying the required configuration file with the -f option.
+ If no configuration file is specified or1ksim searches for the default
+ configuration file sim.cfg. First it searches for './sim.cfg'. If this
+ file is not found, it searches for '~/or1k/sim.cfg'. If this file is
+ not found too, it reverts to the built-in default configuration.
+
+ NOTE: Users should not rely on the built-in configuration, since the
+ default configuration may differ between version.
+ Rather create a configuration file that sets all critical values.
+
+ This file may contain (standard C) comments only - no // support.
+
+ Configure files may be be included, using:
+ include "file_name_to_include"
+
+ Like normal configuration files, the included file is divided into
+ sections. Each section is described in detail also.
+
+ Some section have subsections. One example of such a subsection is:
+
+ device
+ instance specific parameters...
+ enddevice
+
+ which creates a device instance.
+*/
+
+
+/* MEMORY SECTION
+
+ This section specifies how the memory is generated and the blocks
+ it consists of.
+
+ type = random/unknown/pattern
+ Specifies the initial memory values.
+ 'random' generates random memory using seed 'random_seed'.
+ 'pattern' fills memory with 'pattern'.
+ 'unknown' does not specify how memory should be generated,
+ leaving the memory in a undefined state. This is the fastest
+ option.
+
+ random_seed =
+ random seed for randomizer, used if type = 'random'.
+
+ pattern =
+ pattern to fill memory, used if type = 'pattern'.
+
+ nmemories =
+ number of memory instances connected
+
+ baseaddr =
+ memory start address
+
+ size =
+ memory size
+
+ name = ""
+ memory block name
+
+ ce =
+ chip enable index of the memory instance
+
+ mc =
+ memory controller this memory is connected to
+
+ delayr =
+ cycles, required for read access, -1 if instance does not support reading
+
+ delayw =
+ cycles, required for write access, -1 if instance does not support writing
+
+ log = ""
+ filename, where to log memory accesses to, no log, if log command is not specified
+*/
+
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0x04000000
+ size = 0x00200000
+ delayr = 1
+ delayw = -1
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x00200000
+ delayr = 1
+ delayw = 5
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "ICM"
+ mc = 0
+ ce = 2
+ baseaddr = 0x00800000
+ size = 0x00004000
+ delayr = 1
+ delayw = 1
+end
+
+
+/* IMMU SECTION
+
+ This section configures the Instruction Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of ITLB sets; must be power of two
+
+ nways =
+ number of ITLB ways
+
+ pagesize =
+ instruction page size; must be power of two
+
+ entrysize =
+ instruction entry size in bytes
+
+ ustates =
+ number of ITLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles immu hit costs
+
+ missdelay =
+ number of cycles immu miss costs
+*/
+
+section immu
+
+ enabled = 1
+ nsets = 32
+ nways = 1
+ pagesize = 8192
+
+end
+
+
+/* DMMU SECTION
+
+ This section configures the Data Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DTLB sets; must be power of two
+
+ nways =
+ number of DTLB ways
+
+ pagesize =
+ data page size; must be power of two
+
+ entrysize =
+ data entry size in bytes
+
+ ustates =
+ number of DTLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles dmmu hit costs
+
+ missdelay =
+ number of cycles dmmu miss costs
+*/
+
+section dmmu
+ enabled = 1
+ nsets = 32
+ nways = 1
+ pagesize = 8192
+end
+
+
+/* IC SECTION
+
+ This section configures the Instruction Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of IC sets; must be power of two
+
+ nways =
+ number of IC ways
+
+ blocksize =
+ IC block size in bytes; must be power of two
+
+ ustates =
+ number of IC usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles ic hit costs
+
+ missdelay =
+ number of cycles ic miss costs
+*/
+
+section ic
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+end
+
+
+/* DC SECTION
+
+ This section configures the Data Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DC sets; must be power of two
+
+ nways =
+ number of DC ways
+
+ blocksize =
+ DC block size in bytes; must be power of two
+
+ ustates =
+ number of DC usage states (2, 3, 4 etc., max is 4)
+
+ load_hitdelay =
+ number of cycles dc load hit costs
+
+ load_missdelay =
+ number of cycles dc load miss costs
+
+ store_hitdelay =
+ number of cycles dc load hit costs
+
+ store_missdelay =
+ number of cycles dc load miss costs
+*/
+
+section dc
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+end
+
+
+/* SIM SECTION
+
+ This section specifies how or1ksim should behave.
+
+ verbose = 0/1
+ '0': don't print extra messages
+ '1': print extra messages
+
+ debug = 0-9
+ 0 : no debug messages
+ 1-9: debug message level.
+ higher numbers produce more messages
+
+ profile = 0/1
+ '0': don't generate profiling file 'sim.profile'
+ '1': don't generate profiling file 'sim.profile'
+
+ prof_fn = ""
+ optional filename for the profiling file.
+ valid only if 'profile' is set
+
+ mprofile = 0/1
+ '0': don't generate memory profiling file 'sim.mprofile'
+ '1': generate memory profiling file 'sim.mprofile'
+
+ mprof_fn = ""
+ optional filename for the memory profiling file.
+ valid only if 'mprofile' is set
+
+ history = 0/1
+ '0': don't track execution flow
+ '1': track execution flow
+ Execution flow can be tracked for the simulator's
+ 'hist' command. Useful for back-trace debugging.
+
+ iprompt = 0/1
+ '0': start in (so what do we start in ???)
+ '1': start in interactive prompt.
+
+ exe_log = 0/1
+ '0': don't generate execution log.
+ '1': generate execution log.
+
+ exe_log = default/hardware/simple/software
+ type of execution log, default is used when not specified
+
+ exe_log_start =
+ index of first instruction to start logging, default = 0
+
+ exe_log_end =
+ index of last instruction to end logging; not limited, if omitted
+
+ exe_log_marker =
+ specifies number of instructions before horizontal marker is
+ printed; if zero, markers are disabled (default)
+
+ exe_log_fn = ""
+ filename for the exection log file.
+ valid only if 'exe_log' is set
+
+ clkcycle = [ps|ns|us|ms]
+ specifies time measurement for one cycle
+*/
+
+section sim
+ verbose = 1
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ history = 1
+ /* iprompt = 0 */
+ exe_log = 1
+ exe_log_type = hardware
+/* exe_log_start = 0 */
+/* exe_log_end = 2000000 */
+/* exe_log_marker = 50 */
+ exe_log_fn = "executed.log"
+
+/* clkcycle = 10000ns */
+
+end
+
+
+/* SECTION VAPI
+
+ This section configures the Verification API, used for Advanced
+ Core Verification.
+
+ enabled = 0/1
+ '0': disbable VAPI server
+ '1': enable/start VAPI server
+
+ server_port =
+ TCP/IP port to start VAPI server on
+
+ log_enabled = 0/1
+ '0': disable VAPI requests logging
+ '1': enable VAPI requests logging
+
+ hide_device_id = 0/1
+ '0': don't log device id (for compatability with old version)
+ '1': log device id
+
+
+ vapi_fn =
+ filename for the log file.
+ valid only if log_enabled is set
+*/
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+ log_enabled = 0
+ vapi_log_fn = "vapi.log"
+end
+
+
+/* CPU SECTION
+
+ This section specifies various CPU parameters.
+
+ ver =
+ rev =
+ specifies version and revision of the CPU used
+
+ upr =
+ changes the upr register
+
+ sr =
+ sets the initial Supervision Register value
+
+ superscalar = 0/1
+ '0': CPU is scalar
+ '1': CPU is superscalar
+ (modify cpu/or32/execute.c to tune superscalar model)
+
+ hazards = 0/1
+ '0': don't track data hazards in superscalar CPU
+ '1': track data hazards in superscalar CPU
+ If tracked, data hazards can be displayed using the
+ simulator's 'r' command.
+
+ dependstats = 0/1
+ '0': don't calculate inter-instruction dependencies.
+ '1': calculate inter-instruction dependencies.
+ If calculated, inter-instruction dependencies can be
+ displayed using the simulator's 'stat' command.
+
+ sbuf_len =
+ length of store buffer (<= 256), 0 = disabled
+*/
+
+section cpu
+ ver = 0x1200
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 1
+ dependstats = 1
+ sbuf_len = 1
+end
+
+
+/* PM SECTION
+
+ This section specifies Power Management parameters
+
+ enabled = 0/1
+ '0': disable power management
+ '1': enable power management
+*/
+
+section pm
+ enabled = 0
+end
+
+
+/* BPB SECTION
+
+ This section specifies how branch prediction should behave.
+
+ enabled = 0/1
+ '0': disable branch prediction
+ '1': enable branch prediction
+
+ btic = 0/1
+ '0': disable branch target instruction cache model
+ '1': enable branch target instruction cache model
+
+ sbp_bf_fwd = 0/1
+ Static branch prediction for 'l.bf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ sbp_bnf_fwd = 0/1
+ Static branch prediction for 'l.bnf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ hitdelay =
+ number of cycles bpb hit costs
+
+ missdelay =
+ number of cycles bpb miss costs
+*/
+
+section bpb
+ enabled = 1
+ btic = 1
+ sbp_bf_fwd = 0
+ sbp_bnf_fwd = 0
+ hitdelay = 0
+ missdelay = 0
+end
+
+
+/* DEBUG SECTION
+
+ This sections specifies how the debug unit should behave.
+
+ enabled = 0/1
+ '0': disable debug unit
+ '1': enable debug unit
+
+ gdb_enabled = 0/1
+ '0': don't start gdb server
+ '1': start gdb server at port 'server_port'
+
+ server_port =
+ TCP/IP port to start gdb server on
+ valid only if gdb_enabled is set
+
+ vapi_id =
+ Used to create "fake" vapi log file containing the JTAG proxy messages.
+*/
+/*
+section debug
+ enabled = 1
+ gdb_enabled = 1
+ server_port = 12345
+end
+*/
+
+/* MC SECTION
+
+ This section configures the memory controller
+
+ enabled = 0/1
+ '0': disable memory controller
+ '1': enable memory controller
+
+ baseaddr =
+ address of first MC register
+
+ POC =
+ Power On Configuration register
+
+ index =
+ Index of this memory controller amongst all the memory controllers
+*/
+
+section mc
+ enabled = 1
+ baseaddr = 0x60000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+
+/* UART SECTION
+
+ This section configures the UARTs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first UART register for this device
+
+
+ channel = :
+
+ The channel parameter indicates the source of received UART characters
+ and the sink for transmitted UART characters.
+
+ The can be either "file", "xterm", "tcp", "fd", or "tty"
+ (without quotes).
+
+ A) To send/receive characters from a pair of files, use a file
+ channel:
+
+ channel=file:,
+
+ B) To create an interactive terminal window, use an xterm channel:
+
+ channel=xterm:[]*
+
+ C) To create a bidirectional tcp socket which one could, for example,
+ access via telnet, use a tcp channel:
+
+ channel=tcp:
+
+ D) To cause the UART to read/write from existing numeric file
+ descriptors, use an fd channel:
+
+ channel=fd:,
+
+ E) To connect the UART to a physical serial port, create a tty
+ channel:
+
+ channel=tty:device=/dev/ttyS0,baud=9600
+
+ irq =
+ irq number for this device
+
+ 16550 = 0/1
+ '0': this device is a UART16450
+ '1': this device is a UART16550
+
+ jitter =
+ in msecs... time to block, -1 to disable it
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section uart
+ enabled = 1
+ baseaddr = 0x90000000
+ irq = 2
+ /*channel = "file:uart0.rx,uart0.tx"*/
+ channel = "tcp:10084"
+ jitter = -1 /* async behaviour */
+ 16550 = 1
+end
+
+
+/* DMA SECTION
+
+ This section configures the DMAs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first DMA register for this device
+
+ irq =
+ irq number for this device
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section dma
+ enabled = 1
+ baseaddr = 0x9a000000
+ irq = 11
+end
+
+
+/* ETHERNET SECTION
+
+ This section configures the ETHERNETs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first ethernet register for this device
+
+ dma =
+ which controller is this ethernet "connected" to
+
+ irq =
+ ethernet mac IRQ level
+
+ rtx_type =
+ use 0 - file interface, 1 - socket interface
+
+ rx_channel =
+ DMA channel used for RX
+
+ tx_channel =
+ DMA channel used for TX
+
+ rxfile = ""
+ filename, where to read data from
+
+ txfile = ""
+ filename, where to write data to
+
+ sockif = ""
+ interface name of ethernet socket
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section ethernet
+ enabled = 1
+ baseaddr = 0x92000000
+ dma = 0
+ irq = 4
+ rtx_type = 0
+ tx_channel = 0
+ rx_channel = 1
+ rxfile = "eth0.rx"
+ txfile = "eth0.tx"
+ sockif = "eth0"
+end
+
+
+/* GPIO SECTION
+
+ This section configures the GPIOs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first GPIO register for this device
+
+ irq =
+ irq number for this device
+
+ base_vapi_id =
+ first VAPI id of this instance
+ GPIO uses 8 consecutive VAPI IDs
+*/
+
+section gpio
+ enabled = 0
+ baseaddr = 0x91000000
+ irq = 3
+ base_vapi_id = 0x0200
+end
+
+/* VGA SECTION
+
+ This section configures the VGA/LCD controller
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first VGA register
+
+ irq =
+ irq number for this device
+
+ refresh_rate =
+ number of cycles between screen dumps
+
+ filename = ""
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+
+section vga
+ enabled = 1
+ baseaddr = 0x97100000
+ irq = 8
+ refresh_rate = 100000
+ filename = "primary"
+end
+
+
+/* TICK TIMER SECTION
+
+ This section configures tick timer
+
+ enabled = 0/1
+ whether tick timer is enabled
+*/
+/*
+section tick
+ enabled = 1
+ irq = 3
+end
+*/
+/*
+section pic
+ enabled = 1
+ edge_trigger = 1
+end
+*/
+
+/* FB SECTION
+
+ This section configures the frame buffer
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ base address of frame buffer
+
+ paladdr =
+ base address of first palette entry
+
+ refresh_rate =
+ number of cycles between screen dumps
+
+ filename = ""
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+/*
+section fb
+ enabled = 1
+ baseaddr = 0x97000000
+ refresh_rate = 1000000
+ filename = "primary"
+end
+*/
+
+/* KBD SECTION
+
+ This section configures the PS/2 compatible keyboard
+
+ baseaddr =
+ base address of the keyboard device
+
+ rxfile = ""
+ filename, where to read data from
+*/
+/*
+section kbd
+ enabled = 1
+ irq = 5
+ baseaddr = 0x94000000
+ rxfile = "kbd.rx"
+end
+*/
+
+/* ATA SECTION
+
+ This section configures the ATA/ATAPI host controller
+
+ baseaddr =
+ address of first ATA register
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ irq =
+ irq number for this device
+
+ debug =
+ debug level for ata models.
+ 0: no debug messages
+ 1: verbose messages
+ 3: normal messages (more messages than verbose)
+ 5: debug messages (normal debug messages)
+ 7: flow control messages (debug statemachine flows)
+ 9: low priority message (display everything the code does)
+
+ dev_type0/1 =
+ ata device 0 type
+ 0: NO_CONNeCT: none (not connected)
+ 1: FILE : simulated harddisk
+ 2: LOCAL : local system harddisk
+
+ dev_file0/1 = ""
+ filename for simulated ATA device
+ valid only if dev_type0 == 1
+
+ dev_size0/1 =
+ size of simulated hard-disk (in MBytes)
+ valid only if dev_type0 == 1
+
+ dev_packet0/1 =
+ 0: simulated ATA device does NOT implement PACKET command feature set
+ 1: simulated ATA device does implement PACKET command feature set
+
+ FIXME: irq number
+*/
+/*
+section ata
+ enabled = 0
+ baseaddr = 0x9e000000
+ irq = 15
+
+ dev_type0 = 1
+ dev_file0 = "/tmp/sim_atadev0"
+ dev_size0 = 1
+ dev_packet0 = 0
+
+ dev_type1 = 0
+ dev_file1 = ""
+ dev_size1 = 0
+ dev_packet1 = 0
+end
+*/
+
orp.cfg
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: orp.ld
===================================================================
--- orp.ld (nonexistent)
+++ orp.ld (revision 42)
@@ -0,0 +1,69 @@
+/*
+MEMORY
+ {
+ vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
+ flash : ORIGIN = 0x04000000, LENGTH = 0x00200000
+ ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
+ icm : ORIGIN = 0x00800000, LENGTH = 0x00004000
+ }
+ */
+MEMORY
+ {
+ reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
+ vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
+ ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
+ }
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.reset)
+ } > reset
+
+
+
+ .vectors :
+ {
+ _vec_start = .;
+ *(.vectors)
+ _vec_end = .;
+ } > vectors
+
+ .text :
+ {
+ *(.text)
+ } > ram
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ } > ram
+
+ .icm :
+ {
+ _icm_start = .;
+ *(.icm)
+ _icm_end = .;
+ } > ram
+
+ .data :
+ {
+ _dst_beg = .;
+ *(.data)
+ _dst_end = .;
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ } > ram
+
+ .stack (NOLOAD) :
+ {
+ *(.stack)
+ _src_addr = .;
+ } > ram
+
+}
orp.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart.h
===================================================================
--- uart.h (nonexistent)
+++ uart.h (revision 42)
@@ -0,0 +1,122 @@
+
+void uart_init(void);
+void uart_putc(char);
+char uart_getc(void);
+
+#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
+#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
+#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
+#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
+#define UART_IER 1 /* Out: Interrupt Enable Register */
+#define UART_IIR 2 /* In: Interrupt ID Register */
+#define UART_FCR 2 /* Out: FIFO Control Register */
+#define UART_EFR 2 /* I/O: Extended Features Register */
+ /* (DLAB=1, 16C660 only) */
+#define UART_LCR 3 /* Out: Line Control Register */
+#define UART_MCR 4 /* Out: Modem Control Register */
+#define UART_LSR 5 /* In: Line Status Register */
+#define UART_MSR 6 /* In: Modem Status Register */
+#define UART_SCR 7 /* I/O: Scratch Register */
+
+/*
+ * These are the definitions for the FIFO Control Register
+ * (16650 only)
+ */
+#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+/* 16650 redefinitions */
+#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
+#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
+#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
+#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
+#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+#define UART_LCR_SBC 0x40 /* Set break control */
+#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
+#define UART_LCR_EPAR 0x10 /* Even parity select */
+#define UART_LCR_PARITY 0x08 /* Parity Enable */
+#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT 0x40 /* Transmitter empty */
+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI 0x10 /* Break interrupt indicator */
+#define UART_LSR_FE 0x08 /* Frame error indicator */
+#define UART_LSR_PE 0x04 /* Parity error indicator */
+#define UART_LSR_OE 0x02 /* Overrun error indicator */
+#define UART_LSR_DR 0x01 /* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_TOI 0x0c /* Receive time out interrupt */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2 0x08 /* Out2 complement */
+#define UART_MCR_OUT1 0x04 /* Out1 complement */
+#define UART_MCR_RTS 0x02 /* RTS complement */
+#define UART_MCR_DTR 0x01 /* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+
+/*
+ * These are the definitions for the Extended Features Register
+ * (StarTech 16C660 only, when DLAB=1)
+ */
+#define UART_EFR_CTS 0x80 /* CTS flow control */
+#define UART_EFR_RTS 0x40 /* RTS flow control */
+#define UART_EFR_SCD 0x20 /* Special character detect */
+#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
+
uart.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: vfnprintf.h
===================================================================
--- vfnprintf.h (nonexistent)
+++ vfnprintf.h (revision 42)
@@ -0,0 +1,2 @@
+
+int vfnprintf ( char *stream, size_t n, const char *format, va_list arg);
vfnprintf.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property