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https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk/bench/verilog
- from Rev 28 to Rev 58
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Rev 28 → Rev 58
/minsoc_bench_defines.v
4,6 → 4,7
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
`undef NEGATIVE_RESET |
`define POSITIVE_RESET |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|