URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/sim
- from Rev 73 to Rev 75
- ↔ Reverse comparison
Rev 73 → Rev 75
/bin/minsoc_verilog_files.txt
117,7 → 117,7
../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_top.v |
../../rtl/verilog/ethmac/rtl/verilog/ethmac.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v |
125,7 → 125,7
../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v |
../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v |
../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v |