URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/syn
- from Rev 63 to Rev 64
- ↔ Reverse comparison
Rev 63 → Rev 64
/Makefile
File deleted
/src/eth_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/ethmac/rtl/verilog/"} |
-ifn ./buildSupport/eth_top.prj |
-ifmt Verilog |
-ofn eth_top |
-ofmt NGC |
-p DEVICE_PART |
-top eth_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/src/or1200_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/or1200/rtl/verilog/"} |
-ifn ./buildSupport/or1200_top.prj |
-ifmt Verilog |
-ofn or1200_top |
-ofmt NGC |
-p DEVICE_PART |
-top or1200_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/src/minsoc_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../backend" "../rtl/verilog/" "../rtl/verilog/minsoc_startup" "../rtl/verilog/or1200/rtl/verilog/" "../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "../rtl/verilog/ethmac/rtl/verilog/" "../rtl/verilog/uart16550/rtl/verilog/"} |
-ifn ./buildSupport/minsoc_top.prj |
-ifmt Verilog |
-ofn minsoc_top |
-ofmt NGC |
-p DEVICE_PART |
-top minsoc_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf yes |
/src/uart_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/uart16550/rtl/verilog/"} |
-ifn ./buildSupport/uart_top.prj |
-ifmt Verilog |
-ofn uart_top |
-ofmt NGC |
-p DEVICE_PART |
-top uart_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/src/adbg_top.xst
0,0 → 1,12
set -tmpdir "./xst" |
run |
-vlgincdir {"../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/"} |
-ifn ./buildSupport/adbg_top.prj |
-ifmt Verilog |
-ofn adbg_top |
-ofmt NGC |
-p DEVICE_PART |
-top adbg_top |
-opt_mode Speed |
-opt_level 1 |
-iobuf no |
/src/Makefile
0,0 → 1,91
MINSOC = ../ |
MINSOC_DEFINES = ${MINSOC}/backend |
MINSOC_RTL = ${MINSOC}/rtl/verilog |
MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup |
UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog |
ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware |
DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog |
OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog |
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog |
|
help: |
@echo " all: Synthesize and implement the SoC, then generate a bit stream" |
@echo "" |
@echo " soc: Synthesize the SoC" |
@echo " translate: Convert the SoC's ngc file to an ngd file for mapping" |
@echo " map: Express the SoC netlist in the target hardware" |
@echo " par: Place the target hardware, then route the wires" |
@echo " bitgen: Generate a programming file for the target FPGA" |
@echo "" |
@echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" |
@echo " or1200: Synthesize the OR1200 processor" |
@echo " debug: Synthesize the debug interface" |
@echo " uart: Synthesize the UART" |
@echo " eth: Synthesize the Ethernet controller" |
@echo "" |
@echo " clean: Delete all superfluous files generated by Xilinx tools" |
@echo " distclean: Delete all generated files" |
|
all: minsoc.bit |
soc: minsoc_top.ngc |
translate: minsoc.ngd |
map: minsoc.ncd |
par: minsoc_par.ncd |
bitgen: minsoc.bit |
modules: or1200 debug uart eth |
MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc eth_top.ngc |
|
prepare: |
rm -rf xst |
mkdir xst |
clean: |
rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt |
rm -rf _xmsgs xst xlnx_auto_0_xdb |
distclean: |
rm -rf *.ngc *.ncd *.ngd *.bit |
make clean |
|
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v buildSupport/minsoc_top.xst buildSupport/minsoc_top.prj |
make prepare |
xst -ifn "buildSupport/minsoc_top.xst" |
make clean |
|
uart: uart_top.ngc |
uart_top.ngc: ${UART_RTL}/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj |
make prepare |
xst -ifn "buildSupport/uart_top.xst" |
make clean |
|
eth: eth_top.ngc |
eth_top.ngc: ${ETH_RTL}/*.v buildSupport/eth_top.xst buildSupport/eth_top.prj |
make prepare |
xst -ifn "buildSupport/eth_top.xst" |
make clean |
|
debug: adbg_top.ngc |
adbg_top.ngc: ${DEBUG_RTL}/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj |
make prepare |
xst -ifn "buildSupport/adbg_top.xst" |
make clean |
|
or1200: or1200_top.ngc |
or1200_top.ngc: ${OR1200_RTL}/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj |
make prepare |
xst -ifn "buildSupport/or1200_top.xst" |
make clean |
|
minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) |
ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd |
make clean |
|
minsoc.ncd: minsoc.ngd |
map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd |
make clean |
|
minsoc_par.ncd: minsoc.ncd |
par -ol high -w -xe n minsoc.ncd minsoc_par.ncd |
make clean |
|
minsoc.bit: minsoc_par.ncd |
bitgen -d -w minsoc_par.ncd minsoc.bit |
make clean |
/buildSupport/minsoc_startup_top.xst
File deleted
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/buildSupport/or1200_top.xst
File deleted
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/buildSupport/eth_top.xst
File deleted
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/buildSupport/minsoc_startup_top.prj
File deleted
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/buildSupport/uart_top.xst
File deleted
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/buildSupport/adbg_top.xst
File deleted
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/buildSupport/minsoc_top.xst
File deleted
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/buildSupport/minsoc_top.prj
1,5 → 1,5
`include "../backend/minsoc_defines.v" |
`include "../rtl/verilog/minsoc_xilinx_internal_jtag.v" |
`include "../rtl/verilog/minsoc_defines.v" |
`include "../rtl/verilog/minsoc_clock_manager.v" |
`include "../rtl/verilog/altera_pll.v" |
`include "../rtl/verilog/minsoc_tc_top.v" |
7,8 → 7,12
`include "../rtl/verilog/minsoc_top.v" |
`include "../rtl/verilog/minsoc_onchip_ram.v" |
`include "../rtl/verilog/xilinx_dcm.v" |
`include "../rtl/verilog/minsoc_startup/spi_shift.v" |
`include "../rtl/verilog/minsoc_startup/spi_clgen.v" |
`include "../rtl/verilog/minsoc_startup/spi_top.v" |
`include "../rtl/verilog/minsoc_startup/spi_defines.v" |
`include "../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" |
`include "./blackboxes/adbg_top.v" |
`include "./blackboxes/eth_top.v" |
`include "./blackboxes/uart_top.v" |
`include "./blackboxes/or1200_top.v" |
`include "./blackboxes/OR1K_startup_generic.v" |
`include "./blackboxes/or1200_top.v" |
/blackboxes/OR1K_startup_generic.v
File deleted
blackboxes/OR1K_startup_generic.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
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