URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/trunk/bench/verilog/minsoc_bench_defines.v
3,15 → 3,17
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define NO_CLOCK_DIVISION |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
`define POSITIVE_RESET |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
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`define FREQ_NUM_FOR_NS 1000000000 |
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`define FREQ 25000000 |
`define CLK_PERIOD (1000000000/`FREQ) |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
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`define ETH_PHY_FREQ 25000000 |
`define ETH_PHY_PERIOD (1000000000/`ETH_PHY_FREQ) //40ns |
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns |
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`define UART_BAUDRATE 115200 |
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/trunk/bench/verilog/minsoc_bench.v
44,7 → 44,7
// TASKS registers to communicate with interfaces |
// |
`ifdef ETHERNET |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) |
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536) |
localparam ETH_HDR = 14; |
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) |
62,6 → 62,11
initial begin |
reset = 1'b0; |
clock = 1'b0; |
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`ifndef NO_CLOCK_DIVISION |
minsoc_top_0.clk_adjust.clk_int = 1'b0; |
minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000; |
`endif |
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uart_srx = 1'b1; |
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258,16 → 263,16
// |
//SPI START_UP |
`ifdef START_UP |
task send_spi; |
input [7:0] data_in; |
integer i; |
task send_spi; |
input [7:0] data_in; |
integer i; |
begin |
i = 7; |
for ( i = 7 ; i >= 0; i = i - 1 ) begin |
i = 7; |
for ( i = 7 ; i >= 0; i = i - 1 ) begin |
spi_miso = data_in[i]; |
@ (posedge spi_sclk); |
end |
end |
@ (posedge spi_sclk); |
end |
end |
endtask |
`endif |
//~SPI START_UP |
274,7 → 279,7
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//UART |
`ifdef UART |
localparam UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD; |
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE); |
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task uart_send; |
input [7:0] data; |
333,82 → 338,82
// |
// TASKS to communicate with interfaces |
// |
//MAC_DATA |
//MAC_DATA |
// |
`ifdef ETHERNET |
`ifdef ETHERNET |
reg [31:0] crc32_result; |
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task get_mac; |
integer conta; |
reg LSB; |
begin |
conta = 0; |
LSB = 1; |
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task get_mac; |
integer conta; |
reg LSB; |
begin |
conta = 0; |
LSB = 1; |
@ ( posedge eth_tx_en); |
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repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte) |
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while ( eth_tx_en == 1'b1 ) begin |
@ (negedge eth_tx_clk) begin |
if ( LSB == 1'b1 ) |
eth_rx_data[conta][3:0] = eth_txd; |
else begin |
eth_rx_data[conta][7:4] = eth_txd; |
conta = conta + 1; |
end |
LSB = ~LSB; |
end |
end |
end |
endtask |
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while ( eth_tx_en == 1'b1 ) begin |
@ (negedge eth_tx_clk) begin |
if ( LSB == 1'b1 ) |
eth_rx_data[conta][3:0] = eth_txd; |
else begin |
eth_rx_data[conta][7:4] = eth_txd; |
conta = conta + 1; |
end |
LSB = ~LSB; |
end |
end |
end |
endtask |
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task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) |
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518 |
integer conta; |
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518 |
integer conta; |
begin |
if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin |
//DEST MAC |
eth_tx_data[0] = 8'h55; |
eth_tx_data[1] = 8'h47; |
eth_tx_data[2] = 8'h34; |
eth_tx_data[3] = 8'h22; |
eth_tx_data[4] = 8'h88; |
eth_tx_data[5] = 8'h92; |
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//SOURCE MAC |
eth_tx_data[6] = 8'h3D; |
eth_tx_data[7] = 8'h4F; |
eth_tx_data[8] = 8'h1A; |
eth_tx_data[9] = 8'hBE; |
eth_tx_data[10] = 8'h68; |
eth_tx_data[11] = 8'h72; |
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//LEN |
eth_tx_data[12] = length[7:4]; |
eth_tx_data[13] = length[3:0]; |
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//DATA input by task caller |
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//PAD |
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin |
eth_tx_data[conta] = 8'h00; |
end |
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gencrc32(conta); |
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eth_tx_data[conta] = crc32_result[31:24]; |
eth_tx_data[conta+1] = crc32_result[23:16]; |
eth_tx_data[conta+2] = crc32_result[15:8]; |
eth_tx_data[conta+3] = crc32_result[7:0]; |
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if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin |
//DEST MAC |
eth_tx_data[0] = 8'h55; |
eth_tx_data[1] = 8'h47; |
eth_tx_data[2] = 8'h34; |
eth_tx_data[3] = 8'h22; |
eth_tx_data[4] = 8'h88; |
eth_tx_data[5] = 8'h92; |
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//SOURCE MAC |
eth_tx_data[6] = 8'h3D; |
eth_tx_data[7] = 8'h4F; |
eth_tx_data[8] = 8'h1A; |
eth_tx_data[9] = 8'hBE; |
eth_tx_data[10] = 8'h68; |
eth_tx_data[11] = 8'h72; |
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//LEN |
eth_tx_data[12] = length[7:4]; |
eth_tx_data[13] = length[3:0]; |
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//DATA input by task caller |
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//PAD |
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin |
eth_tx_data[conta] = 8'h00; |
end |
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gencrc32(conta); |
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eth_tx_data[conta] = crc32_result[31:24]; |
eth_tx_data[conta+1] = crc32_result[23:16]; |
eth_tx_data[conta+2] = crc32_result[15:8]; |
eth_tx_data[conta+3] = crc32_result[7:0]; |
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send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 ); |
end |
else |
$display("Warning: Ethernet packet is to big to be sent."); |
end |
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endtask |
$display("Warning: Ethernet packet is to big to be sent."); |
end |
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endtask |
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task send_rx_packet; |
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555 |
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 |
467,42 → 472,42
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end |
endtask // send_rx_packet |
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//CRC32 |
localparam [31:0] CRC32_POLY = 32'h04C11DB7; |
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//CRC32 |
localparam [31:0] CRC32_POLY = 32'h04C11DB7; |
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task gencrc32; |
input [31:0] crc32_length; |
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integer byte, bit; |
reg msb; |
reg [7:0] current_byte; |
reg [31:0] temp; |
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begin |
crc32_result = 32'hffffffff; |
for (byte = 0; byte < crc32_length; byte = byte + 1) begin |
current_byte = eth_tx_data[byte]; |
for (bit = 0; bit < 8; bit = bit + 1) begin |
msb = crc32_result[31]; |
crc32_result = crc32_result << 1; |
if (msb != current_byte[bit]) begin |
crc32_result = crc32_result ^ CRC32_POLY; |
crc32_result[0] = 1; |
end |
end |
end |
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// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit. |
// |
// Mirror: |
for (bit = 0; bit < 32; bit = bit + 1) |
temp[31-bit] = crc32_result[bit]; |
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// Swap and Complement: |
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; |
end |
endtask |
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integer byte, bit; |
reg msb; |
reg [7:0] current_byte; |
reg [31:0] temp; |
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begin |
crc32_result = 32'hffffffff; |
for (byte = 0; byte < crc32_length; byte = byte + 1) begin |
current_byte = eth_tx_data[byte]; |
for (bit = 0; bit < 8; bit = bit + 1) begin |
msb = crc32_result[31]; |
crc32_result = crc32_result << 1; |
if (msb != current_byte[bit]) begin |
crc32_result = crc32_result ^ CRC32_POLY; |
crc32_result[0] = 1; |
end |
end |
end |
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// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit. |
// |
// Mirror: |
for (bit = 0; bit < 32; bit = bit + 1) |
temp[31-bit] = crc32_result[bit]; |
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// Swap and Complement: |
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; |
end |
endtask |
//~CRC32 |
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//Generate tx and rx clocks |
513,8 → 518,8
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; |
end |
//~Generate tx and rx clocks |
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`endif // !ETHERNET |
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`endif // !ETHERNET |
//~MAC_DATA |
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/trunk/doc/src/howto.odt
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/trunk/doc/howto.pdf
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