URL
https://opencores.org/ocsvn/mips32r1/mips32r1/trunk
Subversion Repositories mips32r1
Compare Revisions
- This comparison shows the changes necessary to convert path
/mips32r1/trunk/Hardware
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Processor.v
233,7 → 233,6
.EX_RtRd (EX_RtRd), |
.MEM_RtRd (M_RtRd), |
.WB_RtRd (WB_RtRd), |
.ID_Link (ID_Link), |
.EX_Link (EX_Link), |
.EX_RegWrite (EX_RegWrite), |
.MEM_RegWrite (M_RegWrite), |
/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MIPS_Parameters.v
58,12 → 58,11
|
/*** Processor Endianness *** |
|
MIPS32 allows user-mode addresses to be configured as big- or little-endian. For simplicity |
reasons, this processor fixes the endianness to little endian. To add support for both |
modes, the Data Memory Controller should be updated as well as CP0, which should change |
the 'RE' bit in the Status register from a wire to a writable register. |
The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's |
endianness. A processor in user mode may switch to reverse endianness, which will be |
the opposite of this parameter. |
*/ |
parameter Big_Endian = 0; |
parameter Big_Endian = 1; |
|
|
|
/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v
31,7 → 31,6
input [4:0] EX_RtRd, |
input [4:0] MEM_RtRd, |
input [4:0] WB_RtRd, |
input ID_Link, |
input EX_Link, |
input EX_RegWrite, |
input MEM_RegWrite, |
/MIPS32_Standalone/Processor.v
233,7 → 233,6
.EX_RtRd (EX_RtRd), |
.MEM_RtRd (M_RtRd), |
.WB_RtRd (WB_RtRd), |
.ID_Link (ID_Link), |
.EX_Link (EX_Link), |
.EX_RegWrite (EX_RegWrite), |
.MEM_RegWrite (M_RegWrite), |
/MIPS32_Standalone/MIPS_Parameters.v
58,12 → 58,11
|
/*** Processor Endianness *** |
|
MIPS32 allows user-mode addresses to be configured as big- or little-endian. For simplicity |
reasons, this processor fixes the endianness to little endian. To add support for both |
modes, the Data Memory Controller should be updated as well as CP0, which should change |
the 'RE' bit in the Status register from a wire to a writable register. |
The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's |
endianness. A processor in user mode may switch to reverse endianness, which will be |
the opposite of this parameter. |
*/ |
parameter Big_Endian = 0; |
parameter Big_Endian = 1; |
|
|
|
/MIPS32_Standalone/Hazard_Detection.v
31,7 → 31,6
input [4:0] EX_RtRd, |
input [4:0] MEM_RtRd, |
input [4:0] WB_RtRd, |
input ID_Link, |
input EX_Link, |
input EX_RegWrite, |
input MEM_RegWrite, |