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https://opencores.org/ocsvn/mips32r1/mips32r1/trunk
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/trunk/Hardware/XUPV5-LX110T_SoC/HOWTO
0,0 → 1,72
MIPS32-R1 SoC HOWTO |
------------------- |
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This document is a step-by-step procedure for building the MIPS32 hardware |
and software and running it on the XUPV5-LX110T FPGA development board. With |
minimal changes, other hardware platforms may be used as well (see XXX) |
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Procedure |
--------- |
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1. Build the software toolchain. Instructions for doing this are located |
in the "Software/toolchain" directory. |
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2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the |
"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is |
a Xilinx ISE 14.1 project file. |
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3. Build the hardware project and generate the programming .bit file. |
Send the programming file to the board through Impact (you may need |
to create a new Impact project file for your system, but no options |
are needed other than the configuration .bit file targeted for the |
Virtex-5 device). A default program built into the BRAM will print |
a hello message to the LCD screen. |
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Alternatively, a pre-build .bit file is located in the |
"Hardware/XUPV5-LX110T_SoC" directory. |
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4. Compile any of the software demos located in "Software/demos" using |
the Makefile included with the demo. One of the output files from |
the compilation will have a .xum extension. This is binary file that |
contains the code and data for the program. Use the XUM Bootloader |
software (Windows) to send the .xum file over a serial port to the |
FPGA. When the program is sent, the CPU will reset and run it. |
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FAQ |
--- |
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Q: What if I don't have the XUPV5-LX110T board? |
A: If you have the same Virtex 5 FPGA but a different board, all you need |
to do is update the pin locations in the User Constraints File (.ucf) |
and either make sure your clock input is 100 MHz or adjust the PLL |
in the clocking module of the design accordingly. Note that some |
hardware such as the LCD screen or piezo speaker may not be present |
on your board, in which case you should remove them from the design. |
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Q: What if I don't have a Virtex 5 FPGA? |
A: Any FPGA can implement this design if it has enough logic resources. |
There are only two Xilinx-specific modules in the MIPS32 SoC design; |
the clocking module and BRAM module. Replace these with whatever suits |
your hardware. Note however that the MIPS32 memory interface uses |
byte-width write enables to memory (4 bits per 32-bit word), so if you |
use Block Memory or equivalents they must either support this or |
you must fake it somehow. You must also update the UCF. |
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Q: What if I don't have or use the Xilinx development tools? |
A: If you only care about the MIPS32 processor and not the full SoC, start |
with the "Hardware/MIPS32_Standalone" directory which contains only |
Verilog files. The top-most module is "Processor.v". For the full SoC, |
copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory |
to whatever development environment you use. This directory contains |
all of the Verilog files with "Top.v" as the head. The "Clocks" and |
"BRAM" directories will need to be customized for your environment, |
as well as the pin constraints. |
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Q: Is there a non-Windows version of the bootloader? |
A: No, but the boot protocol is simple and can be implemented for any OS. |
See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/ |
uart_bootloader_v2.v" for a description of the protocol. If you |
implement another version of the bootloader, please contribute it back |
to the project. |
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/trunk/README
19,7 → 19,8
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-> XUPV5-LX110T_SoC: Full System-on-Chip for XUPV5 board and Xilinx ISE 14.1 |
Project Navigator. Useful as a starting point for other |
boards as well. |
boards as well. See "HOWTO" in this directory for more |
information. |
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Software: |
-> demos: Software demos for XUM |
34,4 → 35,5
the GNU LGPL. See the file 'LEGAL' in this same directory for more information. |
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Enjoy! |
Enjoy! |
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