mkjpeg/branches/16rgb/trunk/tb/matlab/test.bmp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: mkjpeg/branches/16rgb/trunk/tb/modelsim.ini =================================================================== --- mkjpeg/branches/16rgb/trunk/tb/modelsim.ini (nonexistent) +++ mkjpeg/branches/16rgb/trunk/tb/modelsim.ini (revision 48) @@ -0,0 +1,1067 @@ +; Copyright 1991-2008 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile=1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VcomZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VcomZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageNoSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VHDL generate blocks. Default is on. +CoverGenerate = 1 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +vlog95compat = 0 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal to or more than 1M are +; marked as sparse) +SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VlogZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VlogZeroInOptions = "" + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VoptZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VoptZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VLOG generate blocks. Default is on. +CoverGenerate = 1 + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is on. +CoverCells = 0 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; Allow VHDL FF recognition. This may make major reductions in +; coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Allow VHDL subprogram inlining. Change Verilog gates to +; continuous assignments. +CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobeDefault". +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupPerInstanceDefault". +; SVCovergroupPerInstanceDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vsim] + +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Enables certain code coverage exclusions automatically. Set AutoExclusions = none to disable. +AutoExclusions = fsm + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; Info and Warning are disabled by default +; IgnoreSVAInfo = 0 +; IgnoreSVAWarning = 0 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI out-of-the-blue call. +; Out-of-the-blue call refers to a SystemVerilog export function call +; directly from a C function that don't have the proper context setup +; as done in DPI-C import C functions. When this is enabled, one can +; call a DPI export function (but not task) from any C code. +; The default is 0 (disabled). +; DpiOutOfTheBlue = 1 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + + +; Should the tool conform to the 2001 or 2005 VPI object model +; Note that System Verilog objects are only available in the 2005 object model +; The tool default is the latest available LRM behavior +; Options here are: 2001 2005 latest +; PliCompatDefault = 2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading. +; This is necessary when C++ files have been compiled with aCC's -AA option. +; The default behavior is to use /usr/lib/libCsup.sl. +; UseCsupV2 = 1 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block or vsim switch -assertdebug is used and the visibility flag "+acc=a" is turned on in vopt. +; For PSL, Default is on only when vsim switch "-assertdebug" is used and the visibility flag "+acc=a" is turned on in vopt. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to not include them. +; ToggleVlogIntegers = 1 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off. +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enable or disable generation of more detailed information about the sampling of covergroup, +; cross, and coverpoints. It provides the details of the number of times the covergroup +; instance and type were sampled, as well as details about why covergroup, cross and +; coverpoint were not covered. A non-zero value is to enable this feature. 0 is to +; disable this feature. Default is 0; +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VsimZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VsimZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the complexity of +; the constraint scenario (both in memory and time spent during evaluation) +; exceeds the specified limit. This value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +StdArithNoWarnings = 1 +NumericStdNoWarnings = 1 +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both + +; Control transcripting of Verilog display system task messages. +; These system tasks include $display[bho], $strobe[bho], +; Smonitor{bho], and $write[bho]. They also include the analogous +; file I/O tasks that write to STDOUT (i.e. $fwrite or $fdisplay). +; The default is to have messages appear only in the transcript. +; The other settings are to send messages to the wlf file only +; (messages that are recorded in the wlf file can be viewed in the +; MsgViewer) or to both the transcript and the wlf file. The valid +; values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + Index: mkjpeg/branches/16rgb/trunk/design/control/CtrlSM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/control/CtrlSM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/control/CtrlSM.vhd (revision 48) @@ -0,0 +1,333 @@ +------------------------------------------------------------------------------- +-- File Name : CtrlSM.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : CtrlSM +-- +-- Content : CtrlSM +-- +-- Description : CtrlSM core +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity CtrlSM is + port + ( + CLK : in std_logic; + RST : in std_logic; + + -- output IF + outif_almost_full : in std_logic; + + -- HOST IF + sof : in std_logic; + img_size_x : in std_logic_vector(15 downto 0); + img_size_y : in std_logic_vector(15 downto 0); + jpeg_ready : out std_logic; + jpeg_busy : out std_logic; + cmp_max : in std_logic_vector(1 downto 0); + + -- FDCT + fdct_start : out std_logic; + fdct_ready : in std_logic; + fdct_sm_settings : out T_SM_SETTINGS; + + -- ZIGZAG + zig_start : out std_logic; + zig_ready : in std_logic; + zig_sm_settings : out T_SM_SETTINGS; + + -- Quantizer + qua_start : out std_logic; + qua_ready : in std_logic; + qua_sm_settings : out T_SM_SETTINGS; + + -- RLE + rle_start : out std_logic; + rle_ready : in std_logic; + rle_sm_settings : out T_SM_SETTINGS; + + -- Huffman + huf_start : out std_logic; + huf_ready : in std_logic; + huf_sm_settings : out T_SM_SETTINGS; + + -- ByteStuffdr + bs_start : out std_logic; + bs_ready : in std_logic; + bs_sm_settings : out T_SM_SETTINGS; + + -- JFIF GEN + jfif_start : out std_logic; + jfif_ready : in std_logic; + jfif_eoi : out std_logic; + + -- OUT MUX + out_mux_ctrl : out std_logic + ); +end entity CtrlSM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of CtrlSM is + + + constant NUM_STAGES : integer := 6; + + type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI); + type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0); + + type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS; + signal Reg : T_ARR_SM_SETTINGS; + signal main_state : T_STATE; + signal start : std_logic_vector(NUM_STAGES+1 downto 1); + signal idle : std_logic_vector(NUM_STAGES+1 downto 1); + signal start_PB : std_logic_vector(NUM_STAGES downto 1); + signal ready_PB : std_logic_vector(NUM_STAGES downto 1); + signal fsm : ARR_FSM; + signal start1_d : std_logic; + signal RSM : T_SM_SETTINGS; + signal out_mux_ctrl_s : std_logic; + signal out_mux_ctrl_s2 : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + fdct_sm_settings <= Reg(1); + zig_sm_settings <= Reg(2); + qua_sm_settings <= Reg(3); + rle_sm_settings <= Reg(4); + huf_sm_settings <= Reg(5); + bs_sm_settings <= Reg(6); + + fdct_start <= start_PB(1); + ready_PB(1) <= fdct_ready; + + zig_start <= start_PB(2); + ready_PB(2) <= zig_ready; + + qua_start <= start_PB(3); + ready_PB(3) <= qua_ready; + + rle_start <= start_PB(4); + ready_PB(4) <= rle_ready; + + huf_start <= start_PB(5); + ready_PB(5) <= huf_ready; + + bs_start <= start_PB(6); + ready_PB(6) <= bs_ready; + + ----------------------------------------------------------------------------- + -- CTRLSM 1..NUM_STAGES + ----------------------------------------------------------------------------- + G_S_CTRL_SM : for i in 1 to NUM_STAGES generate + + -- CTRLSM 1..NUM_STAGES + U_S_CTRL_SM : entity work.SingleSM + port map + ( + CLK => CLK, + RST => RST, + -- from/to SM(m) + start_i => start(i), + idle_o => idle(i), + -- from/to SM(m+1) + idle_i => idle(i+1), + start_o => start(i+1), + -- from/to processing block + pb_rdy_i => ready_PB(i), + pb_start_o => start_PB(i), + -- state out + fsm_o => fsm(i) + ); + end generate G_S_CTRL_SM; + + idle(NUM_STAGES+1) <= not outif_almost_full; + + ------------------------------------------------------------------- + -- Regs + ------------------------------------------------------------------- + G_REG_SM : for i in 1 to NUM_STAGES generate + p_reg1 : process(CLK, RST) + begin + if RST = '1' then + Reg(i) <= C_SM_SETTINGS; + elsif CLK'event and CLK = '1' then + if start(i) = '1' then + if i = 1 then + Reg(i).x_cnt <= RSM.x_cnt; + Reg(i).y_cnt <= RSM.y_cnt; + Reg(i).cmp_idx <= RSM.cmp_idx; + else + Reg(i) <= Reg(i-1); + end if; + end if; + end if; + end process; + end generate G_REG_SM; + + ------------------------------------------------------------------- + -- Main_SM + ------------------------------------------------------------------- + p_main_sm : process(CLK, RST) + begin + if RST = '1' then + main_state <= IDLES; + start(1) <= '0'; + start1_d <= '0'; + jpeg_ready <= '0'; + RSM.x_cnt <= (others => '0'); + RSM.y_cnt <= (others => '0'); + jpeg_busy <= '0'; + RSM.cmp_idx <= (others => '0'); + out_mux_ctrl_s <= '0'; + out_mux_ctrl_s2 <= '0'; + jfif_eoi <= '0'; + out_mux_ctrl <= '0'; + jfif_start <= '0'; + elsif CLK'event and CLK = '1' then + start(1) <= '0'; + start1_d <= start(1); + jpeg_ready <= '0'; + jfif_start <= '0'; + out_mux_ctrl_s2 <= out_mux_ctrl_s; + out_mux_ctrl <= out_mux_ctrl_s2; + + case main_state is + ------------------------------- + -- IDLE + ------------------------------- + when IDLES => + if sof = '1' then + RSM.x_cnt <= (others => '0'); + RSM.y_cnt <= (others => '0'); + jfif_start <= '1'; + out_mux_ctrl_s <= '0'; + jfif_eoi <= '0'; + main_state <= JFIF; + end if; + + ------------------------------- + -- JFIF + ------------------------------- + when JFIF => + if jfif_ready = '1' then + out_mux_ctrl_s <= '1'; + main_state <= HORIZ; + end if; + + ------------------------------- + -- HORIZ + ------------------------------- + when HORIZ => + if RSM.x_cnt < unsigned(img_size_x) then + main_state <= COMP; + else + RSM.x_cnt <= (others => '0'); + main_state <= VERT; + end if; + + ------------------------------- + -- COMP + ------------------------------- + when COMP => + if idle(1) = '1' and start(1) = '0' then + if RSM.cmp_idx < unsigned(cmp_max) then + start(1) <= '1'; + else + RSM.cmp_idx <= (others => '0'); + RSM.x_cnt <= RSM.x_cnt + 8; + main_state <= HORIZ; + end if; + end if; + + ------------------------------- + -- VERT + ------------------------------- + when VERT => + if RSM.y_cnt < unsigned(img_size_y)-8 then + RSM.x_cnt <= (others => '0'); + RSM.y_cnt <= RSM.y_cnt + 8; + main_state <= HORIZ; + else + if idle(NUM_STAGES downto 1) = (NUM_STAGES-1 downto 0 => '1') then + main_state <= EOI; + jfif_eoi <= '1'; + out_mux_ctrl_s <= '0'; + jfif_start <= '1'; + end if; + end if; + + ------------------------------- + -- VERT + ------------------------------- + when EOI => + if jfif_ready = '1' then + jpeg_ready <= '1'; + main_state <= IDLES; + end if; + + ------------------------------- + -- others + ------------------------------- + when others => + main_state <= IDLES; + + end case; + + if start1_d = '1' then + RSM.cmp_idx <= RSM.cmp_idx + 1; + end if; + + if main_state = IDLES then + jpeg_busy <= '0'; + else + jpeg_busy <= '1'; + end if; + + end if; + end process; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/top/JpegEnc.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/top/JpegEnc.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/top/JpegEnc.vhd (revision 48) @@ -0,0 +1,529 @@ +------------------------------------------------------------------------------- +-- File Name : JpegEnc.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : JpegEnc +-- +-- Content : JPEG Encoder Top Level +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity JpegEnc is + port + ( + CLK : in std_logic; + RST : in std_logic; + + -- OPB + OPB_ABus : in std_logic_vector(31 downto 0); + OPB_BE : in std_logic_vector(3 downto 0); + OPB_DBus_in : in std_logic_vector(31 downto 0); + OPB_RNW : in std_logic; + OPB_select : in std_logic; + OPB_DBus_out : out std_logic_vector(31 downto 0); + OPB_XferAck : out std_logic; + OPB_retry : out std_logic; + OPB_toutSup : out std_logic; + OPB_errAck : out std_logic; + + -- IMAGE RAM + iram_wdata : in std_logic_vector(23 downto 0); + iram_wren : in std_logic; + iram_fifo_afull : out std_logic; + + -- OUT RAM + ram_byte : out std_logic_vector(7 downto 0); + ram_wren : out std_logic; + ram_wraddr : out std_logic_vector(23 downto 0); + outif_almost_full : in std_logic + ); +end entity JpegEnc; + + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of JpegEnc is + + signal qdata : std_logic_vector(7 downto 0); + signal qaddr : std_logic_vector(6 downto 0); + signal qwren : std_logic; + signal jpeg_ready : std_logic; + signal jpeg_busy : std_logic; + signal outram_base_addr : std_logic_vector(9 downto 0); + signal num_enc_bytes : std_logic_vector(23 downto 0); + signal img_size_x : std_logic_vector(15 downto 0); + signal img_size_y : std_logic_vector(15 downto 0); + signal sof : std_logic; + signal jpg_iram_rden : std_logic; + signal jpg_iram_rdaddr : std_logic_vector(31 downto 0); + signal jpg_iram_rdata : std_logic_vector(23 downto 0); + signal fdct_start : std_logic; + signal fdct_ready : std_logic; + signal zig_start : std_logic; + signal zig_ready : std_logic; + signal qua_start : std_logic; + signal qua_ready : std_logic; + signal rle_start : std_logic; + signal rle_ready : std_logic; + signal huf_start : std_logic; + signal huf_ready : std_logic; + signal bs_start : std_logic; + signal bs_ready : std_logic; + signal zz_buf_sel : std_logic; + signal zz_rd_addr : std_logic_vector(5 downto 0); + signal zz_data : std_logic_vector(11 downto 0); + signal rle_buf_sel : std_logic; + signal rle_rdaddr : std_logic_vector(5 downto 0); + signal rle_data : std_logic_vector(11 downto 0); + signal qua_buf_sel : std_logic; + signal qua_rdaddr : std_logic_vector(5 downto 0); + signal qua_data : std_logic_vector(11 downto 0); + signal huf_buf_sel : std_logic; + signal huf_rdaddr : std_logic_vector(5 downto 0); + signal huf_rden : std_logic; + signal huf_runlength : std_logic_vector(3 downto 0); + signal huf_size : std_logic_vector(3 downto 0); + signal huf_amplitude : std_logic_vector(11 downto 0); + signal huf_dval : std_logic; + signal bs_buf_sel : std_logic; + signal bs_fifo_empty : std_logic; + signal bs_rd_req : std_logic; + signal bs_packed_byte : std_logic_vector(7 downto 0); + signal huf_fifo_empty : std_logic; + signal zz_rden : std_logic; + signal fdct_sm_settings : T_SM_SETTINGS; + signal zig_sm_settings : T_SM_SETTINGS; + signal qua_sm_settings : T_SM_SETTINGS; + signal rle_sm_settings : T_SM_SETTINGS; + signal huf_sm_settings : T_SM_SETTINGS; + signal bs_sm_settings : T_SM_SETTINGS; + signal cmp_max : std_logic_vector(1 downto 0); + signal image_size_reg : std_logic_vector(31 downto 0); + signal jfif_ram_byte : std_logic_vector(7 downto 0); + signal jfif_ram_wren : std_logic; + signal jfif_ram_wraddr : std_logic_vector(23 downto 0); + signal out_mux_ctrl : std_logic; + signal img_size_wr : std_logic; + signal jfif_start : std_logic; + signal jfif_ready : std_logic; + signal bs_ram_byte : std_logic_vector(7 downto 0); + signal bs_ram_wren : std_logic; + signal bs_ram_wraddr : std_logic_vector(23 downto 0); + signal jfif_eoi : std_logic; + signal fdct_block_cnt : std_logic_vector(12 downto 0); + signal fdct_fifo_rd : std_logic; + signal fdct_fifo_empty : std_logic; + signal fdct_fifo_q : std_logic_vector(23 downto 0); + signal fdct_fifo_hf_full : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- Host Interface + ------------------------------------------------------------------- + U_HostIF : entity work.HostIF + port map + ( + CLK => CLK, + RST => RST, + -- OPB + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_DBus_in => OPB_DBus_in, + OPB_RNW => OPB_RNW, + OPB_select => OPB_select, + OPB_DBus_out => OPB_DBus_out, + OPB_XferAck => OPB_XferAck, + OPB_retry => OPB_retry, + OPB_toutSup => OPB_toutSup, + OPB_errAck => OPB_errAck, + + -- Quantizer RAM + qdata => qdata, + qaddr => qaddr, + qwren => qwren, + + -- CTRL + jpeg_ready => jpeg_ready, + jpeg_busy => jpeg_busy, + + -- ByteStuffer + outram_base_addr => outram_base_addr, + num_enc_bytes => num_enc_bytes, + + -- global + img_size_x => img_size_x, + img_size_y => img_size_y, + img_size_wr => img_size_wr, + sof => sof, + cmp_max => cmp_max + ); + + ------------------------------------------------------------------- + -- BUF_FIFO + ------------------------------------------------------------------- + U_BUF_FIFO : entity work.BUF_FIFO + port map + ( + CLK => CLK, + RST => RST, + -- HOST PROG + img_size_x => img_size_x, + img_size_y => img_size_y, + sof => sof, + + -- HOST DATA + iram_wren => iram_wren, + iram_wdata => iram_wdata, + fifo_almost_full => iram_fifo_afull, + + -- FDCT + fdct_block_cnt => fdct_block_cnt, + fdct_fifo_rd => fdct_fifo_rd, + fdct_fifo_empty => fdct_fifo_empty, + fdct_fifo_q => fdct_fifo_q, + fdct_fifo_hf_full => fdct_fifo_hf_full + ); + + ------------------------------------------------------------------- + -- Controller + ------------------------------------------------------------------- + U_CtrlSM : entity work.CtrlSM + port map + ( + CLK => CLK, + RST => RST, + + -- output IF + outif_almost_full => outif_almost_full, + + -- HOST IF + sof => sof, + img_size_x => img_size_x, + img_size_y => img_size_y, + jpeg_ready => jpeg_ready, + jpeg_busy => jpeg_busy, + cmp_max => cmp_max, + + -- FDCT + fdct_start => fdct_start, + fdct_ready => fdct_ready, + fdct_sm_settings => fdct_sm_settings, + + -- ZIGZAG + zig_start => zig_start, + zig_ready => zig_ready, + zig_sm_settings => zig_sm_settings, + + -- Quantizer + qua_start => qua_start, + qua_ready => qua_ready, + qua_sm_settings => qua_sm_settings, + + -- RLE + rle_start => rle_start, + rle_ready => rle_ready, + rle_sm_settings => rle_sm_settings, + + -- Huffman + huf_start => huf_start, + huf_ready => huf_ready, + huf_sm_settings => huf_sm_settings, + + -- ByteStuffdr + bs_start => bs_start, + bs_ready => bs_ready, + bs_sm_settings => bs_sm_settings, + + -- JFIF GEN + jfif_start => jfif_start, + jfif_ready => jfif_ready, + jfif_eoi => jfif_eoi, + + -- OUT MUX + out_mux_ctrl => out_mux_ctrl + ); + + ------------------------------------------------------------------- + -- FDCT + ------------------------------------------------------------------- + U_FDCT : entity work.FDCT + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => fdct_start, + ready_pb => fdct_ready, + fdct_sm_settings => fdct_sm_settings, + + -- BUF_FIFO + bf_block_cnt => fdct_block_cnt, + bf_fifo_rd => fdct_fifo_rd, + bf_fifo_empty => fdct_fifo_empty, + bf_fifo_q => fdct_fifo_q, + bf_fifo_hf_full => fdct_fifo_hf_full, + + -- ZIG ZAG + zz_buf_sel => zz_buf_sel, + zz_rd_addr => zz_rd_addr, + zz_data => zz_data, + zz_rden => zz_rden, + + -- HOST + img_size_x => img_size_x, + img_size_y => img_size_y, + sof => sof + ); + + ------------------------------------------------------------------- + -- ZigZag top level + ------------------------------------------------------------------- + U_ZZ_TOP : entity work.ZZ_TOP + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => zig_start, + ready_pb => zig_ready, + zig_sm_settings => zig_sm_settings, + + -- Quantizer + qua_buf_sel => qua_buf_sel, + qua_rdaddr => qua_rdaddr, + qua_data => qua_data, + + -- FDCT + fdct_buf_sel => zz_buf_sel, + fdct_rd_addr => zz_rd_addr, + fdct_data => zz_data, + fdct_rden => zz_rden + ); + + ------------------------------------------------------------------- + -- Quantizer top level + ------------------------------------------------------------------- + U_QUANT_TOP : entity work.QUANT_TOP + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => qua_start, + ready_pb => qua_ready, + qua_sm_settings => qua_sm_settings, + + -- RLE + rle_buf_sel => rle_buf_sel, + rle_rdaddr => rle_rdaddr, + rle_data => rle_data, + + -- ZIGZAG + zig_buf_sel => qua_buf_sel, + zig_rd_addr => qua_rdaddr, + zig_data => qua_data, + + -- HOST + qdata => qdata, + qaddr => qaddr, + qwren => qwren + ); + + ------------------------------------------------------------------- + -- RLE TOP + ------------------------------------------------------------------- + U_RLE_TOP : entity work.RLE_TOP + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => rle_start, + ready_pb => rle_ready, + rle_sm_settings => rle_sm_settings, + + -- HUFFMAN + huf_buf_sel => huf_buf_sel, + huf_rden => huf_rden, + huf_runlength => huf_runlength, + huf_size => huf_size, + huf_amplitude => huf_amplitude, + huf_dval => huf_dval, + huf_fifo_empty => huf_fifo_empty, + + -- Quantizer + qua_buf_sel => rle_buf_sel, + qua_rd_addr => rle_rdaddr, + qua_data => rle_data, + + -- HostIF + sof => sof + ); + + ------------------------------------------------------------------- + -- Huffman Encoder + ------------------------------------------------------------------- + U_Huffman : entity work.Huffman + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => huf_start, + ready_pb => huf_ready, + huf_sm_settings => huf_sm_settings, + + -- HOST IF + sof => sof, + img_size_x => img_size_x, + img_size_y => img_size_y, + cmp_max => cmp_max, + + -- RLE + rle_buf_sel => huf_buf_sel, + rd_en => huf_rden, + runlength => huf_runlength, + VLI_size => huf_size, + VLI => huf_amplitude, + d_val => huf_dval, + rle_fifo_empty => huf_fifo_empty, + + -- Byte Stuffer + bs_buf_sel => bs_buf_sel, + bs_fifo_empty => bs_fifo_empty, + bs_rd_req => bs_rd_req, + bs_packed_byte => bs_packed_byte + ); + + + ------------------------------------------------------------------- + -- Byte Stuffer + ------------------------------------------------------------------- + U_ByteStuffer : entity work.ByteStuffer + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start_pb => bs_start, + ready_pb => bs_ready, + + -- HOST IF + sof => sof, + num_enc_bytes => num_enc_bytes, + outram_base_addr => outram_base_addr, + + -- Huffman + huf_buf_sel => bs_buf_sel, + huf_fifo_empty => bs_fifo_empty, + huf_rd_req => bs_rd_req, + huf_packed_byte => bs_packed_byte, + + -- OUT RAM + ram_byte => bs_ram_byte, + ram_wren => bs_ram_wren, + ram_wraddr => bs_ram_wraddr + ); + + ------------------------------------------------------------------- + -- JFIF Generator + ------------------------------------------------------------------- + U_JFIFGen : entity work.JFIFGen + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + start => jfif_start, + ready => jfif_ready, + eoi => jfif_eoi, + + -- ByteStuffer + num_enc_bytes => num_enc_bytes, + + -- HOST IF + qwren => qwren, + qwaddr => qaddr, + qwdata => qdata, + image_size_reg => image_size_reg, + image_size_reg_wr => img_size_wr, + + -- OUT RAM + ram_byte => jfif_ram_byte, + ram_wren => jfif_ram_wren, + ram_wraddr => jfif_ram_wraddr + ); + + image_size_reg <= img_size_x & img_size_y; + + ------------------------------------------------------------------- + -- OutMux + ------------------------------------------------------------------- + U_OutMux : entity work.OutMux + port map + ( + CLK => CLK, + RST => RST, + -- CTRL + out_mux_ctrl => out_mux_ctrl, + + -- ByteStuffer + bs_ram_byte => bs_ram_byte, + bs_ram_wren => bs_ram_wren, + bs_ram_wraddr => bs_ram_wraddr, + -- ByteStuffer + jfif_ram_byte => jfif_ram_byte, + jfif_ram_wren => jfif_ram_wren, + jfif_ram_wraddr => jfif_ram_wraddr, + + -- OUT RAM + ram_byte => ram_byte, + ram_wren => ram_wren, + ram_wraddr => ram_wraddr + ); + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- Index: mkjpeg/branches/16rgb/trunk/design/common/JPEG_PKG.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/common/JPEG_PKG.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/common/JPEG_PKG.vhd (revision 48) @@ -0,0 +1,73 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : JPEG_PKG +-- Design : JPEG_ENC +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : JPEG_PKG.VHD +-- Created : Sat Mar 7 2009 +-- +-------------------------------------------------------------------------------- +-- +-- Description : Package for JPEG core +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use ieee.numeric_std.all; + +package JPEG_PKG is + + -- do not change, constant + constant C_HDR_SIZE : integer := 623; + + -- warning! this parameter heavily affects memory size required + -- if expected image width is known change this parameter to match this + -- otherwise some onchip RAM will be wasted and never used + constant C_MAX_LINE_WIDTH : integer := 1280; + + -- 0=highest clock per pixel performance + -- 1=memory used by BUF_FIFO halved, speed performance reduced by circa 18% + constant C_MEMORY_OPTIMIZED : integer := 0; + + type T_SM_SETTINGS is record + x_cnt : unsigned(15 downto 0); + y_cnt : unsigned(15 downto 0); + cmp_idx : unsigned(1 downto 0); + end record; + + constant C_SM_SETTINGS : T_SM_SETTINGS := + ( + (others => '0'), + (others => '0'), + (others => '0') + ); + + function log2(n : natural) return natural; + +end package JPEG_PKG; + +package body JPEG_PKG is + + ----------------------------------------------------------------------------- + function log2(n : natural) + return natural is + begin + for i in 0 to 31 loop + if (2**i) >= n then + return i; + end if; + end loop; + return 32; + end log2; + ----------------------------------------------------------------------------- + +end package body JPEG_PKG; \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/common/SingleSM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/common/SingleSM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/common/SingleSM.vhd (revision 48) @@ -0,0 +1,125 @@ +------------------------------------------------------------------------------- +-- File Name : SingleSM.vhd +-- +-- Project : +-- +-- Module : +-- +-- Content : +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +------------------------------------------------------------------------------- +-- History : +-- 20080301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +entity SingleSM is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- from/to SM(m) + start_i : in std_logic; + idle_o : out std_logic; + -- from/to SM(m+1) + idle_i : in std_logic; + start_o : out std_logic; + -- from/to processing block + pb_rdy_i : in std_logic; + pb_start_o : out std_logic; + -- state debug + fsm_o : out std_logic_vector(1 downto 0) + ); +end entity SingleSM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture SingleSM_rtl of SingleSM is + + +------------------------------------------------------------------------------- +-- Architecture: Signal definition. +------------------------------------------------------------------------------- + type T_STATE is (IDLE, WAIT_FOR_BLK_RDY, WAIT_FOR_BLK_IDLE); + + signal state : T_STATE; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + fsm_o <= "00" when state = IDLE else + "01" when state = WAIT_FOR_BLK_RDY else + "10" when state = WAIT_FOR_BLK_IDLE else + "11"; + + ------------------------------------------------------------------------------ + -- FSM + ------------------------------------------------------------------------------ + p_fsm : process(CLK, RST) + begin + if RST = '1' then + idle_o <= '0'; + start_o <= '0'; + pb_start_o <= '0'; + state <= IDLE; + elsif CLK'event and CLK = '1' then + idle_o <= '0'; + start_o <= '0'; + pb_start_o <= '0'; + + case state is + when IDLE => + idle_o <= '1'; + -- this fsm is started + if start_i = '1' then + state <= WAIT_FOR_BLK_RDY; + -- start processing block associated with this FSM + pb_start_o <= '1'; + idle_o <= '0'; + end if; + + when WAIT_FOR_BLK_RDY => + -- wait until processing block completes + if pb_rdy_i = '1' then + -- wait until next FSM is idle before starting it + if idle_i = '1' then + state <= IDLE; + start_o <= '1'; + else + state <= WAIT_FOR_BLK_IDLE; + end if; + end if; + + when WAIT_FOR_BLK_IDLE => + if idle_i = '1' then + state <= IDLE; + start_o <= '1'; + end if; + + when others => + idle_o <= '0'; + start_o <= '0'; + pb_start_o <= '0'; + state <= IDLE; + + end case; + + end if; + end process; + +end architecture SingleSM_rtl; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- Index: mkjpeg/branches/16rgb/trunk/design/common/FIFO.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/common/FIFO.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/common/FIFO.vhd (revision 48) @@ -0,0 +1,230 @@ +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.all; + +entity RAMF is + generic ( + RAMD_W : INTEGER := 12; + RAMA_W : INTEGER := 6 + ); + port ( + d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0); + waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0); + raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0) + ); +end RAMF; + +architecture RTL of RAMF is + type mem_type is array ((2**RAMA_W)-1 downto 0) of + STD_LOGIC_VECTOR(RAMD_W-1 downto 0); + signal mem : mem_type; + signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0); + +begin + + ------------------------------------------------------------------------------- + q_sg: + ------------------------------------------------------------------------------- + q <= mem(TO_INTEGER(UNSIGNED(read_addr))); + + ------------------------------------------------------------------------------- + read_proc: -- register read address + ------------------------------------------------------------------------------- + process (clk) + begin + if clk = '1' and clk'event then + read_addr <= raddr; + end if; + end process; + + ------------------------------------------------------------------------------- + write_proc: --write access + ------------------------------------------------------------------------------- + process (clk) begin + if clk = '1' and clk'event then + if we = '1' then + mem(TO_INTEGER(UNSIGNED(waddr))) <= d; + end if; + end if; + end process; + +end RTL; +---------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.STD_LOGIC_UNSIGNED.all; +library WORK; + +entity FIFO is + generic ( + DATA_WIDTH : INTEGER := 12; + ADDR_WIDTH : INTEGER := 2 + ); + port ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + rinc : in STD_LOGIC; + winc : in STD_LOGIC; + datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); + + datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); + fullo : out STD_LOGIC; + emptyo : out STD_LOGIC; + count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0) + ); +end FIFO; + +architecture RTL of FIFO is + + signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0); + signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0); + signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0); + signal rd_en_reg : STD_LOGIC; + signal wr_en_reg : STD_LOGIC; + signal empty_reg : STD_LOGIC; + signal full_reg : STD_LOGIC; + signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); + signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); + signal ramenw : STD_LOGIC; + signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); + signal ramenr : STD_LOGIC; + + constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0'); + constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); + + component RAMF + generic ( + RAMD_W : INTEGER := 12; + RAMA_W : INTEGER := 6 + ); + port ( + d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0); + waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0); + raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0) + ); + end component; +begin + + U_RAMF : RAMF + generic map ( + RAMD_W => DATA_WIDTH, + RAMA_W => ADDR_WIDTH + ) + port map ( + d => ramd, + waddr => ramwaddr, + raddr => ramraddr, + we => ramenw, + clk => clk, + + q => ramq + ); + + ramd <= datai; + + ramwaddr <= waddr_reg; + + ramenw <= wr_en_reg; + + ramraddr <= raddr_reg; + + ramenr <= '1'; + + datao <= ramq; + + emptyo <= empty_reg; + + fullo <= full_reg; + + rd_en_reg <= (rinc and not empty_reg); + + wr_en_reg <= (winc and not full_reg); + + count <= count_reg; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + empty_reg <= '1'; + else + if count_reg = ZEROS_C or + (count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then + empty_reg <= '1'; + else + empty_reg <= '0'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + full_reg <= '0'; + else + if count_reg = 2**ADDR_WIDTH or + (count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then + full_reg <= '1'; + else + full_reg <= '0'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + raddr_reg <= (others => '0'); + else + if rd_en_reg = '1' then + raddr_reg <= raddr_reg + '1'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + waddr_reg <= (others => '0'); + else + if wr_en_reg = '1' then + waddr_reg <= waddr_reg + '1'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + count_reg <= (others => '0'); + else + if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then + if rd_en_reg = '1' then + count_reg <= count_reg - '1'; + else + count_reg <= count_reg + '1'; + end if; + end if; + end if; + end if; + end process; + +end RTL; Index: mkjpeg/branches/16rgb/trunk/design/common/RAMZ.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/common/RAMZ.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/common/RAMZ.VHD (revision 48) @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : RAMZ -- +-- Design : MDCT -- +-- Author : Michal Krepa -- -- -- +-- -- +-------------------------------------------------------------------------------- +-- +-- File : RAMZ.VHD +-- Created : Sat Mar 5 7:37 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : RAM memory simulation model +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.all; + +entity RAMZ is + generic + ( + RAMADDR_W : INTEGER := 6; + RAMDATA_W : INTEGER := 12 + ); + port ( + d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0) + ); +end RAMZ; + +architecture RTL of RAMZ is + type mem_type is array ((2**RAMADDR_W)-1 downto 0) of + STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal mem : mem_type; + signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + +begin + + ------------------------------------------------------------------------------- + q_sg: + ------------------------------------------------------------------------------- + q <= mem(TO_INTEGER(UNSIGNED(read_addr))); + + ------------------------------------------------------------------------------- + read_proc: -- register read address + ------------------------------------------------------------------------------- + process (clk) + begin + if clk = '1' and clk'event then + read_addr <= raddr; + end if; + end process; + + ------------------------------------------------------------------------------- + write_proc: --write access + ------------------------------------------------------------------------------- + process (clk) begin + if clk = '1' and clk'event then + if we = '1' then + mem(TO_INTEGER(UNSIGNED(waddr))) <= d; + end if; + end if; + end process; + +end RTL; \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/rle/RLE.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/rle/RLE.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/rle/RLE.VHD (revision 48) @@ -0,0 +1,315 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : RLE -- +-- Design : MDCT CORE -- +-- Author : Michal Krepa -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- File : RLE.VHD -- +-- Created : Wed Mar 04 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Description : Run Length Encoder -- +-- Baseline Entropy Coding -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.All; + use IEEE.NUMERIC_STD.all; + +library work; + use work.JPEG_PKG.all; + +entity rle is + generic + ( + RAMADDR_W : INTEGER := 6; + RAMDATA_W : INTEGER := 12 + ); + port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + start_pb : in std_logic; + sof : in std_logic; + rle_sm_settings : in T_SM_SETTINGS; + + runlength : out STD_LOGIC_VECTOR(3 downto 0); + size : out STD_LOGIC_VECTOR(3 downto 0); + amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + dovalid : out STD_LOGIC; + rd_addr : out STD_LOGIC_VECTOR(5 downto 0) + ); +end rle; + +architecture rtl of rle is + + + + constant SIZE_REG_C : INTEGER := 4; + constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0'); + + signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0); + signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0); + signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0); + signal acc_reg : SIGNED(RAMDATA_W downto 0); + signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0); + signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0); + signal runlength_reg : UNSIGNED(3 downto 0); + signal dovalid_reg : STD_LOGIC; + signal zero_cnt : unsigned(5 downto 0); + signal wr_cnt_d1 : unsigned(5 downto 0); + signal wr_cnt : unsigned(5 downto 0); + + signal rd_cnt : unsigned(5 downto 0); + signal rd_en : std_logic; + + signal divalid : STD_LOGIC; + signal divalid_en : std_logic; + signal zrl_proc : std_logic; + signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); +begin + + size <= STD_LOGIC_VECTOR(size_reg); + amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0)); + + rd_addr <= STD_LOGIC_VECTOR(rd_cnt); + + ------------------------------------------- + -- MAIN PROCESSING + ------------------------------------------- + process(clk,rst) + begin + if rst = '1' then + wr_cnt_d1 <= (others => '0'); + prev_dc_reg_0 <= (others => '0'); + prev_dc_reg_1 <= (others => '0'); + prev_dc_reg_2 <= (others => '0'); + dovalid_reg <= '0'; + acc_reg <= (others => '0'); + runlength_reg <= (others => '0'); + runlength <= (others => '0'); + dovalid <= '0'; + zero_cnt <= (others => '0'); + zrl_proc <= '0'; + rd_en <= '0'; + rd_cnt <= (others => '0'); + divalid_en <= '0'; + elsif clk = '1' and clk'event then + dovalid_reg <= '0'; + runlength_reg <= (others => '0'); + wr_cnt_d1 <= wr_cnt; + runlength <= std_logic_vector(runlength_reg); + dovalid <= dovalid_reg; + divalid <= rd_en; + + if start_pb = '1' then + rd_cnt <= (others => '0'); + rd_en <= '1'; + divalid_en <= '1'; + end if; + + if divalid = '1' and wr_cnt = 63 then + divalid_en <= '0'; + end if; + + -- input read enable + if rd_en = '1' then + if rd_cnt = 64-1 then + rd_cnt <= (others => '0'); + rd_en <= '0'; + else + rd_cnt <= rd_cnt + 1; + end if; + end if; + + -- input data valid + if divalid = '1' then + wr_cnt <= wr_cnt + 1; + + -- first DCT coefficient received, DC data + if wr_cnt = 0 then + -- differental coding of DC data per component + case rle_sm_settings.cmp_idx is + when "00" => + acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1); + prev_dc_reg_0 <= SIGNED(di); + when "01" => + acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1); + prev_dc_reg_1 <= SIGNED(di); + when "10" => + acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1); + prev_dc_reg_2 <= SIGNED(di); + when others => + null; + end case; + runlength_reg <= (others => '0'); + dovalid_reg <= '1'; + -- AC coefficient + else + -- zero AC + if signed(di) = 0 then + -- EOB + if wr_cnt = 63 then + acc_reg <= (others => '0'); + runlength_reg <= (others => '0'); + dovalid_reg <= '1'; + -- no EOB + else + zero_cnt <= zero_cnt + 1; + end if; + -- non-zero AC + else + -- normal RLE case + if zero_cnt <= 15 then + acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1); + runlength_reg <= zero_cnt(3 downto 0); + zero_cnt <= (others => '0'); + dovalid_reg <= '1'; + -- zero_cnt > 15 + else + -- generate ZRL + acc_reg <= (others => '0'); + runlength_reg <= X"F"; + zero_cnt <= zero_cnt - 16; + dovalid_reg <= '1'; + -- stall input until ZRL is handled + zrl_proc <= '1'; + zrl_di <= di; + divalid <= '0'; + rd_cnt <= rd_cnt; + end if; + end if; + end if; + end if; + + -- ZRL processing + if zrl_proc = '1' then + if zero_cnt <= 15 then + acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1); + runlength_reg <= zero_cnt(3 downto 0); + if signed(zrl_di) = 0 then + zero_cnt <= to_unsigned(1,zero_cnt'length); + else + zero_cnt <= (others => '0'); + end if; + dovalid_reg <= '1'; + divalid <= divalid_en; + -- continue input handling + zrl_proc <= '0'; + -- zero_cnt > 15 + else + -- generate ZRL + acc_reg <= (others => '0'); + runlength_reg <= X"F"; + zero_cnt <= zero_cnt - 16; + dovalid_reg <= '1'; + divalid <= '0'; + rd_cnt <= rd_cnt; + end if; + end if; + + -- start of 8x8 block processing + if start_pb = '1' then + zero_cnt <= (others => '0'); + wr_cnt <= (others => '0'); + end if; + + if sof = '1' then + prev_dc_reg_0 <= (others => '0'); + prev_dc_reg_1 <= (others => '0'); + prev_dc_reg_2 <= (others => '0'); + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- Entropy Coder + ------------------------------------------------------------------- + p_entropy_coder : process(CLK, RST) + begin + if RST = '1' then + ampli_vli_reg <= (others => '0'); + size_reg <= (others => '0'); + elsif CLK'event and CLK = '1' then + -- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude) + -- positive input + if acc_reg >= 0 then + ampli_vli_reg <= acc_reg; + else + ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1); + end if; + + -- compute Symbol-1 Size + if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then + size_reg <= TO_UNSIGNED(1,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(2,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(3,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(4,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(5,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(6,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(7,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(8,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(9,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(10,SIZE_REG_C); + elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(11,SIZE_REG_C); + end if; + + -- compute Symbol-1 Size + -- positive input + if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then + size_reg <= TO_UNSIGNED(1,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(2,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(3,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(4,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(5,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(6,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(7,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(8,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(9,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(10,SIZE_REG_C); + elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then + size_reg <= TO_UNSIGNED(11,SIZE_REG_C); + end if; + + -- DC coefficient amplitude=0 case OR EOB + if acc_reg = 0 then + size_reg <= TO_UNSIGNED(0,SIZE_REG_C); + end if; + end if; + end process; + +end rtl; +-------------------------------------------------------------------------------- + + Index: mkjpeg/branches/16rgb/trunk/design/rle/RLE_TOP.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/rle/RLE_TOP.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/rle/RLE_TOP.VHD (revision 48) @@ -0,0 +1,227 @@ +------------------------------------------------------------------------------- +-- File Name : RLE_TOP.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : RLE_TOP +-- +-- Content : Run Length Encoder top level +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity RLE_TOP is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + rle_sm_settings : in T_SM_SETTINGS; + + -- HUFFMAN + huf_buf_sel : in std_logic; + huf_rden : in std_logic; + huf_runlength : out std_logic_vector(3 downto 0); + huf_size : out std_logic_vector(3 downto 0); + huf_amplitude : out std_logic_vector(11 downto 0); + huf_dval : out std_logic; + huf_fifo_empty : out std_logic; + + -- Quantizer + qua_buf_sel : out std_logic; + qua_rd_addr : out std_logic_vector(5 downto 0); + qua_data : in std_logic_vector(11 downto 0); + + -- HostIF + sof : in std_logic + ); +end entity RLE_TOP; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of RLE_TOP is + + signal dbuf_data : std_logic_vector(19 downto 0); + signal dbuf_q : std_logic_vector(19 downto 0); + signal dbuf_we : std_logic; + + signal rle_runlength : std_logic_vector(3 downto 0); + signal rle_size : std_logic_vector(3 downto 0); + signal rle_amplitude : std_logic_vector(11 downto 0); + signal rle_dovalid : std_logic; + signal rle_di : std_logic_vector(11 downto 0); + signal rle_divalid : std_logic; + + signal qua_buf_sel_s : std_logic; + signal huf_dval_p0 : std_logic; + + signal wr_cnt : unsigned(5 downto 0); + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + huf_runlength <= dbuf_q(19 downto 16); + huf_size <= dbuf_q(15 downto 12); + huf_amplitude <= dbuf_q(11 downto 0); + qua_buf_sel <= qua_buf_sel_s; + + ------------------------------------------------------------------- + -- RLE Core + ------------------------------------------------------------------- + U_rle : entity work.rle + generic map + ( + RAMADDR_W => 6, + RAMDATA_W => 12 + ) + port map + ( + rst => RST, + clk => CLK, + di => rle_di, + start_pb => start_pb, + sof => sof, + rle_sm_settings => rle_sm_settings, + + runlength => rle_runlength, + size => rle_size, + amplitude => rle_amplitude, + dovalid => rle_dovalid, + rd_addr => qua_rd_addr + ); + + rle_di <= qua_data; + + ------------------------------------------------------------------- + -- Double Fifo + ------------------------------------------------------------------- + U_RleDoubleFifo : entity work.RleDoubleFifo + port map + ( + CLK => CLK, + RST => RST, + -- RLE + data_in => dbuf_data, + wren => dbuf_we, + -- HUFFMAN + buf_sel => huf_buf_sel, + rd_req => huf_rden, + fifo_empty => huf_fifo_empty, + data_out => dbuf_q + ); + dbuf_data <= rle_runlength & rle_size & rle_amplitude; + dbuf_we <= rle_dovalid; + + + + + ------------------------------------------------------------------- + -- ready_pb + ------------------------------------------------------------------- + p_ready_pb : process(CLK, RST) + begin + if RST = '1' then + ready_pb <= '0'; + wr_cnt <= (others => '0'); + elsif CLK'event and CLK = '1' then + ready_pb <= '0'; + + if start_pb = '1' then + wr_cnt <= (others => '0'); + end if; + + -- detect EOB (0,0) - end of RLE block + if rle_dovalid = '1' then + + -- ZERO EXTENSION + if unsigned(rle_runlength) = 15 and unsigned(rle_size) = 0 then + wr_cnt <= wr_cnt + 16; + else + wr_cnt <= wr_cnt + 1 + resize(unsigned(rle_runlength), wr_cnt'length); + end if; + + -- EOB can only be on AC! + if dbuf_data = (dbuf_data'range => '0') and wr_cnt /= 0 then + ready_pb <= '1'; + else + if wr_cnt + resize(unsigned(rle_runlength), wr_cnt'length) = 64-1 then + ready_pb <= '1'; + end if; + end if; + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- fdct_buf_sel + ------------------------------------------------------------------- + p_buf_sel : process(CLK, RST) + begin + if RST = '1' then + qua_buf_sel_s <= '0'; + elsif CLK'event and CLK = '1' then + if start_pb = '1' then + qua_buf_sel_s <= not qua_buf_sel_s; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- output data valid + ------------------------------------------------------------------- + p_dval : process(CLK, RST) + begin + if RST = '1' then + huf_dval_p0 <= '0'; + --huf_dval <= '0'; + elsif CLK'event and CLK = '1' then + huf_dval_p0 <= huf_rden; + --huf_dval <= huf_rden; + end if; + end process; + + huf_dval <= huf_rden; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/rle/RleDoubleFifo.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/rle/RleDoubleFifo.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/rle/RleDoubleFifo.vhd (revision 48) @@ -0,0 +1,185 @@ +------------------------------------------------------------------------------- +-- File Name : RleDoubleFifo.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : RleDoubleFifo +-- +-- Content : RleDoubleFifo +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090228: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity RleDoubleFifo is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- HUFFMAN + data_in : in std_logic_vector(19 downto 0); + wren : in std_logic; + -- BYTE STUFFER + buf_sel : in std_logic; + rd_req : in std_logic; + fifo_empty : out std_logic; + data_out : out std_logic_vector(19 downto 0) + ); +end entity RleDoubleFifo; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of RleDoubleFifo is + + signal fifo1_rd : std_logic; + signal fifo1_wr : std_logic; + signal fifo1_q : std_logic_vector(19 downto 0); + signal fifo1_full : std_logic; + signal fifo1_empty : std_logic; + signal fifo1_count : std_logic_vector(6 downto 0); + + signal fifo2_rd : std_logic; + signal fifo2_wr : std_logic; + signal fifo2_q : std_logic_vector(19 downto 0); + signal fifo2_full : std_logic; + signal fifo2_empty : std_logic; + signal fifo2_count : std_logic_vector(6 downto 0); + + signal fifo_data_in : std_logic_vector(19 downto 0); +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- FIFO 1 + ------------------------------------------------------------------- + U_FIFO_1 : entity work.FIFO + generic map + ( + DATA_WIDTH => 20, + ADDR_WIDTH => 6 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo1_rd, + winc => fifo1_wr, + datai => fifo_data_in, + + datao => fifo1_q, + fullo => fifo1_full, + emptyo => fifo1_empty, + count => fifo1_count + ); + + ------------------------------------------------------------------- + -- FIFO 2 + ------------------------------------------------------------------- + U_FIFO_2 : entity work.FIFO + generic map + ( + DATA_WIDTH => 20, + ADDR_WIDTH => 6 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo2_rd, + winc => fifo2_wr, + datai => fifo_data_in, + + datao => fifo2_q, + fullo => fifo2_full, + emptyo => fifo2_empty, + count => fifo2_count + ); + + ------------------------------------------------------------------- + -- mux2 + ------------------------------------------------------------------- + p_mux2 : process(CLK, RST) + begin + if RST = '1' then + fifo1_wr <= '0'; + fifo2_wr <= '0'; + fifo_data_in <= (others => '0'); + elsif CLK'event and CLK = '1' then + if buf_sel = '0' then + fifo1_wr <= wren; + else + fifo2_wr <= wren; + end if; + fifo_data_in <= data_in; + end if; + end process; + + ------------------------------------------------------------------- + -- mux3 + ------------------------------------------------------------------- + p_mux3 : process(CLK, RST) + begin + if RST = '1' then + --data_out <= (others => '0'); + --fifo1_rd <= '0'; + --fifo2_rd <= '0'; + --fifo_empty <= '0'; + elsif CLK'event and CLK = '1' then + if buf_sel = '1' then + --data_out <= fifo1_q; + --fifo1_rd <= rd_req; + --fifo_empty <= fifo1_empty; + else + --data_out <= fifo2_q; + --fifo2_rd <= rd_req; + --fifo_empty <= fifo2_empty; + end if; + end if; + end process; + + fifo1_rd <= rd_req when buf_sel = '1' else '0'; + fifo2_rd <= rd_req when buf_sel = '0' else '0'; + + data_out <= fifo1_q when buf_sel = '1' else fifo2_q; + fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/BufFifo/BUF_FIFO.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/BufFifo/BUF_FIFO.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/BufFifo/BUF_FIFO.vhd (revision 48) @@ -0,0 +1,379 @@ +------------------------------------------------------------------------------- +-- File Name : BUF_FIFO.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : BUF_FIFO +-- +-- Content : Input FIFO Buffer +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090311: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity BUF_FIFO is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- HOST PROG + img_size_x : in std_logic_vector(15 downto 0); + img_size_y : in std_logic_vector(15 downto 0); + sof : in std_logic; + + -- HOST DATA + iram_wren : in std_logic; + iram_wdata : in std_logic_vector(23 downto 0); + fifo_almost_full : out std_logic; + + -- FDCT + fdct_block_cnt : in std_logic_vector(12 downto 0); + fdct_fifo_rd : in std_logic; + fdct_fifo_empty : out std_logic; + fdct_fifo_q : out std_logic_vector(23 downto 0); + fdct_fifo_hf_full : out std_logic + ); +end entity BUF_FIFO; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of BUF_FIFO is + + constant C_NUM_SUBF : integer := C_MAX_LINE_WIDTH/8; + constant C_PIXEL_BITS : integer := 24; + constant C_SUBF_ADDRW : integer := 7-C_MEMORY_OPTIMIZED; + --constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF))); + + type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0); + type T_CNT_ARR is array (0 to C_NUM_SUBF-1) of + std_logic_vector(C_SUBF_ADDRW downto 0); + + type T_FIFO_RAMADDR is array (0 to C_NUM_SUBF-1) of + STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0); + + signal fifo_rd : std_logic_vector(C_NUM_SUBF-1 downto 0); + signal fifo_wr : std_logic_vector(C_NUM_SUBF-1 downto 0); + signal fifo_data : std_logic_vector(23 downto 0); + signal fifo_data_d1 : std_logic_vector(23 downto 0); + signal fifo_full : std_logic_vector(C_NUM_SUBF-1 downto 0); + signal fifo_empty : std_logic_vector(C_NUM_SUBF-1 downto 0); + signal fifo_half_full : std_logic_vector(C_NUM_SUBF-1 downto 0); + signal fifo_count : T_CNT_ARR; + + signal pixel_cnt : unsigned(15 downto 0); + signal wblock_cnt : unsigned(12 downto 0); + signal last_idx : unsigned(12 downto 0); + signal idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0); + signal wr_idx_reg : unsigned(log2(C_NUM_SUBF)-1 downto 0); + + signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0); + signal ramd : STD_LOGIC_VECTOR (C_PIXEL_BITS-1 downto 0); + signal ramwaddr : STD_LOGIC_VECTOR + (log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0); + signal ramwaddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0); + signal ramwaddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0); + signal ramenw : STD_LOGIC; + signal ramenw_m1 : STD_LOGIC; + signal ramenw_m2 : STD_LOGIC; + signal ramraddr : STD_LOGIC_VECTOR + (log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0); + signal ramraddr_base : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0); + signal ramraddr_offset : unsigned(C_SUBF_ADDRW-1 downto 0); + signal ramenr : STD_LOGIC; + + signal fifo_ramwaddr : T_FIFO_RAMADDR; + signal fifo_ramenw : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0); + signal fifo_ramraddr : T_FIFO_RAMADDR; + signal fifo_ramenr : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0); + + signal offset_ramwaddr : STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0); +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- SUB_FIFOs + ------------------------------------------------------------------- + G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate + + U_SUB_FIFO : entity work.SUB_FIFO + generic map + ( + DATA_WIDTH => C_PIXEL_BITS, + ADDR_WIDTH => C_SUBF_ADDRW + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo_rd(i), + winc => fifo_wr(i), + + fullo => fifo_full(i), + emptyo => fifo_empty(i), + count => fifo_count(i), + + ramwaddr => fifo_ramwaddr(i), + ramenw => fifo_ramenw(i), + ramraddr => fifo_ramraddr(i), + ramenr => fifo_ramenr(i) + ); + end generate G_SUB_FIFO; + + ------------------------------------------------------------------- + -- RAM for SUB_FIFOs + ------------------------------------------------------------------- + U_SUB_RAMZ : entity work.SUB_RAMZ + generic map + ( + RAMADDR_W => log2(C_NUM_SUBF)+C_SUBF_ADDRW, + RAMDATA_W => C_PIXEL_BITS + ) + port map + ( + d => ramd, + waddr => ramwaddr, + raddr => ramraddr, + we => ramenw, + clk => clk, + + q => ramq + ); + + ------------------------------------------------------------------- + -- FIFO almost full + ------------------------------------------------------------------- + p_fifo_almost_full : process(CLK, RST) + begin + if RST = '1' then + fifo_almost_full <= '1'; + last_idx <= (others => '0'); + elsif CLK'event and CLK = '1' then + if img_size_x = (img_size_x'range => '0') then + last_idx <= (others => '0'); + else + last_idx <= unsigned(img_size_x(15 downto 3))-1; + end if; + + if C_MEMORY_OPTIMIZED = 0 then + if unsigned(fifo_count(to_integer(wblock_cnt))) > to_unsigned(128-2*8,8) then + fifo_almost_full <= '1'; + else + fifo_almost_full <= '0'; + end if; + else + if unsigned(fifo_count(to_integer(wblock_cnt))) >= to_unsigned(62,8) then + fifo_almost_full <= '1'; + -- due to FIFO full latency next subFIFO is in danger of being + -- overwritten thus its fifo full must be checked ahead + else + -- next=0 when current is last + if wblock_cnt = last_idx then + -- latency from FIFO full till it is recognized by Host is 2T (64-2)=62 + if unsigned(fifo_count(0)) >= to_unsigned(62,8) then + fifo_almost_full <= '1'; + else + fifo_almost_full <= '0'; + end if; + -- next is just current+1 + else + -- latency from FIFO full till it is recognized by Host is 2T (64-2)=62 + if unsigned(fifo_count(to_integer(wblock_cnt)+1)) >= to_unsigned(62,8) then + fifo_almost_full <= '1'; + else + fifo_almost_full <= '0'; + end if; + end if; + end if; + + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- pixel_cnt + ------------------------------------------------------------------- + p_pixel_cnt : process(CLK, RST) + begin + if RST = '1' then + pixel_cnt <= (others => '0'); + elsif CLK'event and CLK = '1' then + if iram_wren = '1' then + if pixel_cnt = unsigned(img_size_x)-1 then + pixel_cnt <= (others => '0'); + else + pixel_cnt <= pixel_cnt + 1; + end if; + end if; + + if sof = '1' then + pixel_cnt <= (others => '0'); + end if; + end if; + end process; + + wblock_cnt <= pixel_cnt(pixel_cnt'high downto 3); + + ------------------------------------------------------------------- + -- FIFO half full + ------------------------------------------------------------------- + p_half_full : process(CLK, RST) + begin + if RST = '1' then + for i in 0 to C_NUM_SUBF-1 loop + fifo_half_full(i) <= '0'; + end loop; + elsif CLK'event and CLK = '1' then + for i in 0 to C_NUM_SUBF-1 loop + if C_MEMORY_OPTIMIZED = 0 then + if unsigned(fifo_count(i)) >= 64 then + fifo_half_full(i) <= '1'; + else + fifo_half_full(i) <= '0'; + end if; + else + fifo_half_full(i) <= fifo_full(i); + end if; + end loop; + end if; + end process; + + ------------------------------------------------------------------- + -- Mux1 + ------------------------------------------------------------------- + p_mux1 : process(CLK, RST) + begin + if RST = '1' then + for i in 0 to C_NUM_SUBF-1 loop + fifo_wr(i) <= '0'; + end loop; + elsif CLK'event and CLK = '1' then + for i in 0 to C_NUM_SUBF-1 loop + if wblock_cnt(log2(C_NUM_SUBF)-1 downto 0) = i then + fifo_wr(i) <= iram_wren; + else + fifo_wr(i) <= '0'; + end if; + end loop; + end if; + end process; + + ------------------------------------------------------------------- + -- Mux2 + ------------------------------------------------------------------- + p_mux2 : process(CLK, RST) + begin + if RST = '1' then + for i in 0 to C_NUM_SUBF-1 loop + fifo_rd(i) <= '0'; + end loop; + fdct_fifo_empty <= '0'; + fdct_fifo_hf_full <= '0'; + idx_reg <= (others => '0'); + elsif CLK'event and CLK = '1' then + idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0)); + + for i in 0 to C_NUM_SUBF-1 loop + if idx_reg = i then + fifo_rd(i) <= fdct_fifo_rd; + else + fifo_rd(i) <= '0'; + end if; + end loop; + + fdct_fifo_empty <= fifo_empty(to_integer(idx_reg)); + fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg)); + end if; + end process; + + fdct_fifo_q <= ramq; + + ------------------------------------------------------------------- + -- Mux3 + ------------------------------------------------------------------- + p_mux3 : process(CLK, RST) + begin + if RST = '1' then + ramwaddr <= (others => '0'); + ramwaddr_offset <= (others => '0'); + ramwaddr_base <= (others => '0'); + ramenw <= '0'; + ramenw_m1 <= '0'; + wr_idx_reg <= (others => '0'); + ramd <= (others => '0'); + fifo_data <= (others => '0'); + fifo_data_d1 <= (others => '0'); + elsif CLK'event and CLK = '1' then + wr_idx_reg <= unsigned(wblock_cnt(log2(C_NUM_SUBF)-1 downto 0)); + + fifo_data <= iram_wdata; + fifo_data_d1 <= fifo_data; + ramd <= fifo_data_d1; + + ramenw_m1 <= fifo_ramenw(to_integer(wr_idx_reg)); + ramenw <= ramenw_m1; + + ramwaddr_offset <= unsigned(fifo_ramwaddr(to_integer(wr_idx_reg))); + ramwaddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) * + wr_idx_reg; + ramwaddr <= std_logic_vector(ramwaddr_base(ramwaddr'range) + + resize(ramwaddr_offset, ramwaddr'length)); + end if; + end process; + + ------------------------------------------------------------------- + -- Mux4 + ------------------------------------------------------------------- + p_mux4 : process(CLK, RST) + begin + if RST = '1' then + ramraddr <= (others => '0'); + ramraddr_base <= (others => '0'); + ramraddr_offset <= (others => '0'); + elsif CLK'event and CLK = '1' then + ramraddr_offset <= unsigned(fifo_ramraddr(to_integer(idx_reg))); + ramraddr_base <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) * + idx_reg; + ramraddr <= std_logic_vector(ramraddr_base(ramraddr'range) + + resize(unsigned(ramraddr_offset), ramraddr'length)); + end if; + end process; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_RAMZ.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_RAMZ.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_RAMZ.VHD (revision 48) @@ -0,0 +1,82 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : SUB_RAMZ -- +-- Design : EV_JPEG_ENC -- +-- Author : Michal Krepa -- -- -- +-- -- +-------------------------------------------------------------------------------- +-- +-- File : SUB_RAMZ.VHD +-- Created : 22/03/2009 +-- +-------------------------------------------------------------------------------- +-- +-- Description : RAM memory simulation model +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.all; + +entity SUB_RAMZ is + generic + ( + RAMADDR_W : INTEGER := 6; + RAMDATA_W : INTEGER := 12 + ); + port ( + d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0) + ); +end SUB_RAMZ; + +architecture RTL of SUB_RAMZ is + type mem_type is array ((2**RAMADDR_W)-1 downto 0) of + STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal mem : mem_type; + signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0); + + --attribute ram_style: string; + --attribute ram_style of mem : signal is "distributed"; + + +begin + + ------------------------------------------------------------------------------- + q_sg: + ------------------------------------------------------------------------------- + q <= mem(TO_INTEGER(UNSIGNED(read_addr))); + + ------------------------------------------------------------------------------- + read_proc: -- register read address + ------------------------------------------------------------------------------- + process (clk) + begin + if clk = '1' and clk'event then + read_addr <= raddr; + end if; + end process; + + ------------------------------------------------------------------------------- + write_proc: --write access + ------------------------------------------------------------------------------- + process (clk) begin + if clk = '1' and clk'event then + if we = '1' then + mem(TO_INTEGER(UNSIGNED(waddr))) <= d; + end if; + end if; + end process; + +end RTL; \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_FIFO.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_FIFO.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/BufFifo/SUB_FIFO.vhd (revision 48) @@ -0,0 +1,131 @@ + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.STD_LOGIC_UNSIGNED.all; +library WORK; + +entity SUB_FIFO is + generic ( + DATA_WIDTH : INTEGER := 12; + ADDR_WIDTH : INTEGER := 2 + ); + port ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + rinc : in STD_LOGIC; + winc : in STD_LOGIC; + + fullo : out STD_LOGIC; + emptyo : out STD_LOGIC; + count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0); + + ramwaddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); + ramenw : out STD_LOGIC; + ramraddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); + ramenr : out STD_LOGIC + ); +end SUB_FIFO; + +architecture RTL of SUB_FIFO is + + signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0); + signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0); + signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0); + signal rd_en_reg : STD_LOGIC; + signal wr_en_reg : STD_LOGIC; + signal empty_reg : STD_LOGIC; + signal full_reg : STD_LOGIC; + + constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0'); + constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); + +begin + + ramwaddr <= waddr_reg; + ramenw <= wr_en_reg; + ramraddr <= raddr_reg; + ramenr <= '1'; + + emptyo <= empty_reg; + fullo <= full_reg; + rd_en_reg <= (rinc and not empty_reg); + wr_en_reg <= (winc and not full_reg); + + count <= count_reg; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + empty_reg <= '1'; + else + if count_reg = ZEROS_C or + (count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then + empty_reg <= '1'; + else + empty_reg <= '0'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + full_reg <= '0'; + else + if count_reg = 2**ADDR_WIDTH or + (count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then + full_reg <= '1'; + else + full_reg <= '0'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + raddr_reg <= (others => '0'); + else + if rd_en_reg = '1' then + raddr_reg <= raddr_reg + '1'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + waddr_reg <= (others => '0'); + else + if wr_en_reg = '1' then + waddr_reg <= waddr_reg + '1'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + count_reg <= (others => '0'); + else + if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then + if rd_en_reg = '1' then + count_reg <= count_reg - '1'; + else + count_reg <= count_reg + '1'; + end if; + end if; + end if; + end if; + end process; + +end RTL; Index: mkjpeg/branches/16rgb/trunk/design/huffman/Huffman.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/Huffman.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/Huffman.vhd (revision 48) @@ -0,0 +1,535 @@ +------------------------------------------------------------------------------- +-- File Name : Huffman.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : Huffman +-- +-- Content : Huffman Encoder +-- +-- Description : Huffman encoder core +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090228: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity Huffman is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + huf_sm_settings : in T_SM_SETTINGS; + + -- HOST IF + sof : in std_logic; + img_size_x : in std_logic_vector(15 downto 0); + img_size_y : in std_logic_vector(15 downto 0); + cmp_max : in std_logic_vector(1 downto 0); + + -- RLE + rle_buf_sel : out std_logic; + rd_en : out std_logic; + runlength : in std_logic_vector(3 downto 0); + VLI_size : in std_logic_vector(3 downto 0); + VLI : in std_logic_vector(11 downto 0); + d_val : in std_logic; + rle_fifo_empty : in std_logic; + + -- Byte Stuffer + bs_buf_sel : in std_logic; + bs_fifo_empty : out std_logic; + bs_rd_req : in std_logic; + bs_packed_byte : out std_logic_vector(7 downto 0) + ); +end entity Huffman; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of Huffman is + + type T_STATE is (IDLE, RUN_VLC, RUN_VLI, PAD); + + constant C_M : integer := 23; + constant BLK_SIZE : integer := 64; + + signal state : T_STATE; + signal rle_buf_sel_s : std_logic; + signal first_rle_word : std_logic; + signal word_reg : unsigned(C_M-1 downto 0); + signal bit_ptr : unsigned(4 downto 0); + signal num_fifo_wrs : unsigned(1 downto 0); + signal VLI_ext : unsigned(15 downto 0); + signal VLI_ext_size : unsigned(4 downto 0); + signal ready_HFW : std_logic; + signal fifo_wbyte : std_logic_vector(7 downto 0); + signal fifo_wrt_cnt : unsigned(1 downto 0); + signal fifo_wren : std_logic; + signal last_block : std_logic; + signal image_area_size : unsigned(33 downto 0); + signal block_cnt : unsigned(27 downto 0); + signal VLC_size : unsigned(4 downto 0); + signal VLC : unsigned(15 downto 0); + signal VLC_DC_size : std_logic_vector(3 downto 0); + signal VLC_DC : unsigned(8 downto 0); + signal VLC_AC_size : unsigned(4 downto 0); + signal VLC_AC : unsigned(15 downto 0); + signal vlc_vld : std_logic; + signal d_val_d1 : std_logic; + signal d_val_d2 : std_logic; + signal d_val_d3 : std_logic; + signal d_val_d4 : std_logic; + signal VLI_size_d : std_logic_vector(3 downto 0); + signal VLI_d : std_logic_vector(11 downto 0); + signal VLI_size_d1 : std_logic_vector(3 downto 0); + signal VLI_d1 : std_logic_vector(11 downto 0); + signal HFW_running : std_logic; + signal runlength_r : std_logic_vector(3 downto 0); + signal VLI_size_r : std_logic_vector(3 downto 0); + signal VLI_r : std_logic_vector(11 downto 0); + signal rd_en_s : std_logic; + signal pad_byte : std_logic_vector(7 downto 0); + signal pad_reg : std_logic; + signal VLC_CR_DC_size : std_logic_vector(3 downto 0); + signal VLC_CR_DC : unsigned(10 downto 0); + signal VLC_CR_AC_size : unsigned(4 downto 0); + signal VLC_CR_AC : unsigned(15 downto 0); + signal start_pb_d1 : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + rle_buf_sel <= rle_buf_sel_s; + + rd_en <= rd_en_s; + vlc_vld <= rd_en_s; + + ------------------------------------------------------------------- + -- latch FIFO Q + ------------------------------------------------------------------- + p_latch_fifo : process(CLK, RST) + begin + if RST = '1' then + VLI_size_r <= (others => '0'); + VLI_r <= (others => '0'); + elsif CLK'event and CLK = '1' then + if d_val = '1' then + VLI_size_r <= VLI_size; + VLI_r <= VLI; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- DC_ROM Luminance + ------------------------------------------------------------------- + U_DC_ROM : entity work.DC_ROM + port map + ( + CLK => CLK, + RST => RST, + VLI_size => VLI_size, + + VLC_DC_size => VLC_DC_size, + VLC_DC => VLC_DC + ); + + ------------------------------------------------------------------- + -- AC_ROM Luminance + ------------------------------------------------------------------- + U_AC_ROM : entity work.AC_ROM + port map + ( + CLK => CLK, + RST => RST, + runlength => runlength, + VLI_size => VLI_size, + + VLC_AC_size => VLC_AC_size, + VLC_AC => VLC_AC + ); + + ------------------------------------------------------------------- + -- DC_ROM Chrominance + ------------------------------------------------------------------- + U_DC_CR_ROM : entity work.DC_CR_ROM + port map + ( + CLK => CLK, + RST => RST, + VLI_size => VLI_size, + + VLC_DC_size => VLC_CR_DC_size, + VLC_DC => VLC_CR_DC + ); + + ------------------------------------------------------------------- + -- AC_ROM Chrominance + ------------------------------------------------------------------- + U_AC_CR_ROM : entity work.AC_CR_ROM + port map + ( + CLK => CLK, + RST => RST, + runlength => runlength, + VLI_size => VLI_size, + + VLC_AC_size => VLC_CR_AC_size, + VLC_AC => VLC_CR_AC + ); + + ------------------------------------------------------------------- + -- Double Fifo + ------------------------------------------------------------------- + U_DoubleFifo : entity work.DoubleFifo + port map + ( + CLK => CLK, + RST => RST, + -- HUFFMAN + data_in => fifo_wbyte, + wren => fifo_wren, + -- BYTE STUFFER + buf_sel => bs_buf_sel, + rd_req => bs_rd_req, + fifo_empty => bs_fifo_empty, + data_out => bs_packed_byte + ); + + ------------------------------------------------------------------- + -- RLE buf_sel + ------------------------------------------------------------------- + p_rle_buf_sel : process(CLK, RST) + begin + if RST = '1' then + rle_buf_sel_s <= '0'; + elsif CLK'event and CLK = '1' then + if start_pb = '1' then + rle_buf_sel_s <= not rle_buf_sel_s; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- mux for DC/AC ROM Luminance/Chrominance + ------------------------------------------------------------------- + p_mux : process(CLK, RST) + begin + if RST = '1' then + VLC_size <= (others => '0'); + VLC <= (others => '0'); + elsif CLK'event and CLK = '1' then + -- DC + if first_rle_word = '1' then + -- luminance + if huf_sm_settings.cmp_idx = 0 then + VLC_size <= unsigned('0' & VLC_DC_size); + VLC <= resize(VLC_DC, VLC'length); + -- chrominance + else + VLC_size <= unsigned('0' & VLC_CR_DC_size); + VLC <= resize(VLC_CR_DC, VLC'length); + end if; + -- AC + else + -- luminance + if huf_sm_settings.cmp_idx = 0 then + VLC_size <= VLC_AC_size; + VLC <= VLC_AC; + -- chrominance + else + VLC_size <= VLC_CR_AC_size; + VLC <= VLC_CR_AC; + end if; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- Block Counter / Last Block detector + ------------------------------------------------------------------- + p_blk_cnt : process(CLK, RST) + begin + if RST = '1' then + image_area_size <= (others => '0'); + last_block <= '0'; + elsif CLK'event and CLK = '1' then + image_area_size <= unsigned(cmp_max)* + unsigned(img_size_x)*unsigned(img_size_y); + + if sof = '1' then + block_cnt <= (others => '0'); + elsif start_pb = '1' then + block_cnt <= block_cnt + 1; + end if; + + if block_cnt = image_area_size(33 downto 6) then + last_block <= '1'; + else + last_block <= '0'; + end if; + + end if; + end process; + + VLI_ext <= unsigned("0000" & VLI_d1); + VLI_ext_size <= unsigned('0' & VLI_size_d1); + + ------------------------------------------------------------------- + -- delay line + ------------------------------------------------------------------- + p_vli_dly : process(CLK, RST) + begin + if RST = '1' then + VLI_d <= (others => '0'); + VLI_size_d <= (others => '0'); + VLI_d1 <= (others => '0'); + VLI_size_d1 <= (others => '0'); + d_val_d1 <= '0'; + d_val_d2 <= '0'; + d_val_d3 <= '0'; + d_val_d4 <= '0'; + elsif CLK'event and CLK = '1' then + VLI_d1 <= VLI_r; + VLI_size_d1 <= VLI_size_r; + + VLI_d <= VLI_d1; + VLI_size_d <= VLI_size_d1; + + d_val_d1 <= d_val; + d_val_d2 <= d_val_d1; + d_val_d3 <= d_val_d2; + d_val_d4 <= d_val_d3; + end if; + end process; + + ------------------------------------------------------------------- + -- HandleFifoWrites + ------------------------------------------------------------------- + p_HandleFifoWrites : process(CLK, RST) + begin + if RST = '1' then + ready_HFW <= '0'; + fifo_wrt_cnt <= (others => '0'); + fifo_wren <= '0'; + fifo_wbyte <= (others => '0'); + rd_en_s <= '0'; + start_pb_d1 <= '0'; + elsif CLK'event and CLK = '1' then + fifo_wren <= '0'; + ready_HFW <= '0'; + rd_en_s <= '0'; + start_pb_d1 <= start_pb; + + if start_pb_d1 = '1' then + rd_en_s <= '1' and not rle_fifo_empty; + end if; + + if HFW_running = '1' and ready_HFW = '0' then + -- there is no at least one integer byte to write this time + if num_fifo_wrs = 0 then + ready_HFW <= '1'; + if state = RUN_VLI then + rd_en_s <= '1' and not rle_fifo_empty; + end if; + -- single byte write to FIFO + else + fifo_wrt_cnt <= fifo_wrt_cnt + 1; + fifo_wren <= '1'; + -- last byte write + if fifo_wrt_cnt + 1 = num_fifo_wrs then + ready_HFW <= '1'; + if state = RUN_VLI then + rd_en_s <= '1' and not rle_fifo_empty; + end if; + fifo_wrt_cnt <= (others => '0'); + end if; + end if; + end if; + + case fifo_wrt_cnt is + when "00" => + fifo_wbyte <= std_logic_vector(word_reg(C_M-1 downto C_M-8)); + when "01" => + fifo_wbyte <= std_logic_vector(word_reg(C_M-8-1 downto C_M-16)); + when others => + fifo_wbyte <= (others => '0'); + end case; + if pad_reg = '1' then + fifo_wbyte <= pad_byte; + end if; + + + end if; + end process; + + -- divide by 8 + num_fifo_wrs <= bit_ptr(4 downto 3); + + ------------------------------------------------------------------- + -- Variable Length Processor FSM + ------------------------------------------------------------------- + p_vlp : process(CLK, RST) + begin + if RST = '1' then + ready_pb <= '0'; + first_rle_word <= '0'; + state <= IDLE; + word_reg <= (others => '0'); + bit_ptr <= (others => '0'); + HFW_running <= '0'; + pad_reg <= '0'; + pad_byte <= (others => '0'); + elsif CLK'event and CLK = '1' then + ready_pb <= '0'; + + case state is + + when IDLE => + if start_pb = '1' then + first_rle_word <= '1'; + state <= RUN_VLC; + end if; + + when RUN_VLC => + -- data valid DC or data valid AC + if (d_val_d1 = '1' and first_rle_word = '1') or + (d_val = '1' and first_rle_word = '0') then + for i in 0 to C_M-1 loop + if i < to_integer(VLC_size) then + word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i); + end if; + end loop; + bit_ptr <= bit_ptr + resize(VLC_size,bit_ptr'length); + + -- HandleFifoWrites + HFW_running <= '1'; + -- HandleFifoWrites completed + elsif HFW_running = '1' and + (num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then + -- shift word reg left to skip bytes already written to FIFO + word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000")); + -- adjust bit pointer after some bytes were written to FIFO + -- modulo 8 operation + bit_ptr <= bit_ptr - (num_fifo_wrs & "000"); + HFW_running <= '0'; + first_rle_word <= '0'; + state <= RUN_VLI; + end if; + + when RUN_VLI => + if HFW_running = '0' then + + for i in 0 to C_M-1 loop + if i < to_integer(VLI_ext_size) then + word_reg(C_M-1-to_integer(bit_ptr)-i) + <= VLI_ext(to_integer(VLI_ext_size)-1-i); + end if; + end loop; + + bit_ptr <= bit_ptr + resize(VLI_ext_size,bit_ptr'length); + + -- HandleFifoWrites + HFW_running <= '1'; + -- HandleFifoWrites completed + elsif HFW_running = '1' and + (num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then + -- shift word reg left to skip bytes already written to FIFO + word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000")); + -- adjust bit pointer after some bytes were written to FIFO + -- modulo 8 operation + bit_ptr <= bit_ptr - (num_fifo_wrs & "000"); + HFW_running <= '0'; + + -- end of block + if rle_fifo_empty = '1' then + -- end of segment + if bit_ptr - (num_fifo_wrs & "000") /= 0 and last_block = '1' then + state <= PAD; + else + ready_pb <= '1'; + state <= IDLE; + end if; + else + state <= RUN_VLC; + end if; + end if; + + -- end of segment which requires bit padding + when PAD => + if HFW_running = '0' then + -- 1's bit padding to integer number of bytes + for i in 0 to 7 loop + if i < bit_ptr then + pad_byte(7-i) <= word_reg(C_M-1-i); + else + pad_byte(7-i) <= '1'; + end if; + end loop; + pad_reg <= '1'; + + bit_ptr <= to_unsigned(8, bit_ptr'length); + + -- HandleFifoWrites + HFW_running <= '1'; + elsif HFW_running = '1' and + (num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then + bit_ptr <= (others => '0'); + HFW_running <= '0'; + pad_reg <= '0'; + + ready_pb <= '1'; + state <= IDLE; + end if; + + when others => + + end case; + + if sof = '1' then + bit_ptr <= (others => '0'); + end if; + + end if; + end process; + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/huffman/AC_CR_ROM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/AC_CR_ROM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/AC_CR_ROM.vhd (revision 48) @@ -0,0 +1,708 @@ +------------------------------------------------------------------------------- +-- File Name : AC_CR_ROM.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : AC_CR_ROM +-- +-- Content : AC_CR_ROM Chrominance +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090329: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity AC_CR_ROM is + port + ( + CLK : in std_logic; + RST : in std_logic; + runlength : in std_logic_vector(3 downto 0); + VLI_size : in std_logic_vector(3 downto 0); + + VLC_AC_size : out unsigned(4 downto 0); + VLC_AC : out unsigned(15 downto 0) + ); +end entity AC_CR_ROM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of AC_CR_ROM is + + signal rom_addr : std_logic_vector(7 downto 0); + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + rom_addr <= runlength & VLI_size; + + ------------------------------------------------------------------- + -- AC-ROM + ------------------------------------------------------------------- + p_AC_CR_ROM : process(CLK, RST) + begin + if RST = '1' then + VLC_AC_size <= (others => '0'); + VLC_AC <= (others => '0'); + elsif CLK'event and CLK = '1' then + case runlength is + when X"0" => + + case VLI_size is + when X"0" => + VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); + VLC_AC <= resize("00", VLC_AC'length); + when X"1" => + VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); + VLC_AC <= resize("01", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); + VLC_AC <= resize("100", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); + VLC_AC <= resize("1010", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111000", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111000", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111110110", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110100", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"1" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); + VLC_AC <= resize("1011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111001", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11110110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110101", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111110110", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110101", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001000", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001001", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001010", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001011", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"2" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111110111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110110", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); + VLC_AC <= resize("111111111000010", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001100", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001101", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001110", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001111", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010000", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"3" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11111000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111000", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"4" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110110", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"5" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111001", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"6" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"7" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111111000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"8" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111000", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111001", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111010", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111011", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111100", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111101", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111110", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111111", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"9" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110111", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000001", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000010", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000011", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000100", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000101", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000110", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000111", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001000", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"A" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111000", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001001", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001010", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001011", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001100", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001101", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001110", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001111", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010000", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010001", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"B" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010010", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010011", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010100", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010101", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010110", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010111", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011000", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011001", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011010", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"C" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011011", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011100", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011101", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011110", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011111", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100000", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100001", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100010", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100011", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"D" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100100", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100101", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100110", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100111", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101000", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101001", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101010", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101011", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101100", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"E" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(14, VLC_AC_size'length); + VLC_AC <= resize("11111111100000", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101101", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"F" => + + case VLI_size is + when X"0" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111010", VLC_AC'length); + when X"1" => + VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); + VLC_AC <= resize("111111111000011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110110", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when others => + VLC_AC_size <= (others => '0'); + VLC_AC <= (others => '0'); + end case; + end if; + end process; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/huffman/DC_CR_ROM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/DC_CR_ROM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/DC_CR_ROM.vhd (revision 48) @@ -0,0 +1,127 @@ +------------------------------------------------------------------------------- +-- File Name : DC_CR_ROM.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : DC_CR_ROM +-- +-- Content : DC_CR_ROM Chrominance +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090329: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity DC_CR_ROM is + port + ( + CLK : in std_logic; + RST : in std_logic; + VLI_size : in std_logic_vector(3 downto 0); + + VLC_DC_size : out std_logic_vector(3 downto 0); + VLC_DC : out unsigned(10 downto 0) + ); +end entity DC_CR_ROM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of DC_CR_ROM is + + + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- DC-ROM + ------------------------------------------------------------------- + p_DC_CR_ROM : process(CLK, RST) + begin + if RST = '1' then + VLC_DC_size <= X"0"; + VLC_DC <= (others => '0'); + elsif CLK'event and CLK = '1' then + case VLI_size is + when X"0" => + VLC_DC_size <= X"2"; + VLC_DC <= resize("00", VLC_DC'length); + when X"1" => + VLC_DC_size <= X"2"; + VLC_DC <= resize("01", VLC_DC'length); + when X"2" => + VLC_DC_size <= X"2"; + VLC_DC <= resize("10", VLC_DC'length); + when X"3" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("110", VLC_DC'length); + when X"4" => + VLC_DC_size <= X"4"; + VLC_DC <= resize("1110", VLC_DC'length); + when X"5" => + VLC_DC_size <= X"5"; + VLC_DC <= resize("11110", VLC_DC'length); + when X"6" => + VLC_DC_size <= X"6"; + VLC_DC <= resize("111110", VLC_DC'length); + when X"7" => + VLC_DC_size <= X"7"; + VLC_DC <= resize("1111110", VLC_DC'length); + when X"8" => + VLC_DC_size <= X"8"; + VLC_DC <= resize("11111110", VLC_DC'length); + when X"9" => + VLC_DC_size <= X"9"; + VLC_DC <= resize("111111110", VLC_DC'length); + when X"A" => + VLC_DC_size <= X"A"; + VLC_DC <= resize("1111111110", VLC_DC'length); + when X"B" => + VLC_DC_size <= X"B"; + VLC_DC <= resize("11111111110", VLC_DC'length); + when others => + VLC_DC_size <= X"0"; + VLC_DC <= (others => '0'); + end case; + end if; + end process; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/huffman/AC_ROM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/AC_ROM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/AC_ROM.vhd (revision 48) @@ -0,0 +1,708 @@ +------------------------------------------------------------------------------- +-- File Name : AC_ROM.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : AC_ROM +-- +-- Content : AC_ROM Luminance +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090228: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity AC_ROM is + port + ( + CLK : in std_logic; + RST : in std_logic; + runlength : in std_logic_vector(3 downto 0); + VLI_size : in std_logic_vector(3 downto 0); + + VLC_AC_size : out unsigned(4 downto 0); + VLC_AC : out unsigned(15 downto 0) + ); +end entity AC_ROM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of AC_ROM is + + signal rom_addr : std_logic_vector(7 downto 0); + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + rom_addr <= runlength & VLI_size; + + ------------------------------------------------------------------- + -- AC-ROM + ------------------------------------------------------------------- + p_AC_ROM : process(CLK, RST) + begin + if RST = '1' then + VLC_AC_size <= (others => '0'); + VLC_AC <= (others => '0'); + elsif CLK'event and CLK = '1' then + case runlength is + when X"0" => + + case VLI_size is + when X"0" => + VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); + VLC_AC <= resize("1010", VLC_AC'length); + when X"1" => + VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); + VLC_AC <= resize("00", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); + VLC_AC <= resize("01", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); + VLC_AC <= resize("100", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); + VLC_AC <= resize("1011", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11010", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111000", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11111000", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111110110", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000010", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000011", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"1" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); + VLC_AC <= resize("1100", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11011", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111001", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110110", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111110110", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000100", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000101", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000110", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110000111", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001000", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"2" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); + VLC_AC <= resize("11100", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11111001", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111110111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110100", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"3" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110101", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110001111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"4" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); + VLC_AC <= resize("111011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110010111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"5" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110011111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"6" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); + VLC_AC <= resize("1111011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110110", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110100111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"7" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); + VLC_AC <= resize("11111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); + VLC_AC <= resize("111111110111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110101111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"8" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111000", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); + VLC_AC <= resize("111111111000000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110110", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110110111", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111000", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111001", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111010", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111011", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111100", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111101", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"9" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111110", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111110111111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"A" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); + VLC_AC <= resize("111111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111000111", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001000", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001001", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001010", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001011", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001100", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001101", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001110", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111001111", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"B" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111001", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010000", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010001", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010010", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010011", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010100", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010101", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010110", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111010111", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011000", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"C" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); + VLC_AC <= resize("1111111010", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011001", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011010", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011011", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011100", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011101", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011110", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111011111", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100000", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100001", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"D" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111111000", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100010", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100011", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100100", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100101", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100110", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111100111", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101000", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101001", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101010", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"E" => + + case VLI_size is + when X"1" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101011", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101100", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101101", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101110", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111101111", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110000", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110001", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110010", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110011", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110100", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when X"F" => + + case VLI_size is + when X"0" => + VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); + VLC_AC <= resize("11111111001", VLC_AC'length); + when X"1" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110101", VLC_AC'length); + when X"2" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110110", VLC_AC'length); + when X"3" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111110111", VLC_AC'length); + when X"4" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111000", VLC_AC'length); + when X"5" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111001", VLC_AC'length); + when X"6" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111010", VLC_AC'length); + when X"7" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111011", VLC_AC'length); + when X"8" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111100", VLC_AC'length); + when X"9" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111101", VLC_AC'length); + when X"A" => + VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); + VLC_AC <= resize("1111111111111110", VLC_AC'length); + when others => + VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); + VLC_AC <= resize("0", VLC_AC'length); + end case; + + when others => + VLC_AC_size <= (others => '0'); + VLC_AC <= (others => '0'); + end case; + end if; + end process; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/huffman/DC_ROM.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/DC_ROM.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/DC_ROM.vhd (revision 48) @@ -0,0 +1,127 @@ +------------------------------------------------------------------------------- +-- File Name : DC_ROM.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : DC_ROM +-- +-- Content : DC_ROM Luminance +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090228: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity DC_ROM is + port + ( + CLK : in std_logic; + RST : in std_logic; + VLI_size : in std_logic_vector(3 downto 0); + + VLC_DC_size : out std_logic_vector(3 downto 0); + VLC_DC : out unsigned(8 downto 0) + ); +end entity DC_ROM; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of DC_ROM is + + + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- DC-ROM + ------------------------------------------------------------------- + p_dc_rom : process(CLK, RST) + begin + if RST = '1' then + VLC_DC_size <= X"0"; + VLC_DC <= (others => '0'); + elsif CLK'event and CLK = '1' then + case VLI_size is + when X"0" => + VLC_DC_size <= X"2"; + VLC_DC <= resize("00", VLC_DC'length); + when X"1" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("010", VLC_DC'length); + when X"2" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("011", VLC_DC'length); + when X"3" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("100", VLC_DC'length); + when X"4" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("101", VLC_DC'length); + when X"5" => + VLC_DC_size <= X"3"; + VLC_DC <= resize("110", VLC_DC'length); + when X"6" => + VLC_DC_size <= X"4"; + VLC_DC <= resize("1110", VLC_DC'length); + when X"7" => + VLC_DC_size <= X"5"; + VLC_DC <= resize("11110", VLC_DC'length); + when X"8" => + VLC_DC_size <= X"6"; + VLC_DC <= resize("111110", VLC_DC'length); + when X"9" => + VLC_DC_size <= X"7"; + VLC_DC <= resize("1111110", VLC_DC'length); + when X"A" => + VLC_DC_size <= X"8"; + VLC_DC <= resize("11111110", VLC_DC'length); + when X"B" => + VLC_DC_size <= X"9"; + VLC_DC <= resize("111111110", VLC_DC'length); + when others => + VLC_DC_size <= X"0"; + VLC_DC <= (others => '0'); + end case; + end if; + end process; + + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/huffman/DoubleFifo.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/huffman/DoubleFifo.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/huffman/DoubleFifo.vhd (revision 48) @@ -0,0 +1,178 @@ +------------------------------------------------------------------------------- +-- File Name : DoubleFifo.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : DoubleFifo +-- +-- Content : DoubleFifo +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090228: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity DoubleFifo is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- HUFFMAN + data_in : in std_logic_vector(7 downto 0); + wren : in std_logic; + -- BYTE STUFFER + buf_sel : in std_logic; + rd_req : in std_logic; + fifo_empty : out std_logic; + data_out : out std_logic_vector(7 downto 0) + ); +end entity DoubleFifo; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of DoubleFifo is + + signal fifo1_rd : std_logic; + signal fifo1_wr : std_logic; + signal fifo1_q : std_logic_vector(7 downto 0); + signal fifo1_full : std_logic; + signal fifo1_empty : std_logic; + signal fifo1_count : std_logic_vector(7 downto 0); + + signal fifo2_rd : std_logic; + signal fifo2_wr : std_logic; + signal fifo2_q : std_logic_vector(7 downto 0); + signal fifo2_full : std_logic; + signal fifo2_empty : std_logic; + signal fifo2_count : std_logic_vector(7 downto 0); + + signal fifo_data_in : std_logic_vector(7 downto 0); +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- FIFO 1 + ------------------------------------------------------------------- + U_FIFO_1 : entity work.FIFO + generic map + ( + DATA_WIDTH => 8, + ADDR_WIDTH => 7 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo1_rd, + winc => fifo1_wr, + datai => fifo_data_in, + + datao => fifo1_q, + fullo => fifo1_full, + emptyo => fifo1_empty, + count => fifo1_count + ); + + ------------------------------------------------------------------- + -- FIFO 2 + ------------------------------------------------------------------- + U_FIFO_2 : entity work.FIFO + generic map + ( + DATA_WIDTH => 8, + ADDR_WIDTH => 7 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo2_rd, + winc => fifo2_wr, + datai => fifo_data_in, + + datao => fifo2_q, + fullo => fifo2_full, + emptyo => fifo2_empty, + count => fifo2_count + ); + + ------------------------------------------------------------------- + -- mux2 + ------------------------------------------------------------------- + p_mux2 : process(CLK, RST) + begin + if RST = '1' then + fifo1_wr <= '0'; + fifo2_wr <= '0'; + fifo_data_in <= (others => '0'); + elsif CLK'event and CLK = '1' then + if buf_sel = '0' then + fifo1_wr <= wren; + else + fifo2_wr <= wren; + end if; + fifo_data_in <= data_in; + end if; + end process; + + ------------------------------------------------------------------- + -- mux3 + ------------------------------------------------------------------- + p_mux3 : process(CLK, RST) + begin + if RST = '1' then + data_out <= (others => '0'); + fifo1_rd <= '0'; + fifo2_rd <= '0'; + fifo_empty <= '0'; + elsif CLK'event and CLK = '1' then + if buf_sel = '1' then + data_out <= fifo1_q; + fifo1_rd <= rd_req; + fifo_empty <= fifo1_empty; + else + data_out <= fifo2_q; + fifo2_rd <= rd_req; + fifo_empty <= fifo2_empty; + end if; + end if; + end process; + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/JFIFGen/JFIFGen.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/JFIFGen/JFIFGen.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/JFIFGen/JFIFGen.vhd (revision 48) @@ -0,0 +1,284 @@ +------------------------------------------------------------------------------- +-- File Name : JFIFGen.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : JFIFGen +-- +-- Content : JFIF Header Generator +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090309: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.JPEG_PKG.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity JFIFGen is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start : in std_logic; + ready : out std_logic; + eoi : in std_logic; + + -- ByteStuffer + num_enc_bytes : in std_logic_vector(23 downto 0); + + -- HOST IF + qwren : in std_logic; + qwaddr : in std_logic_vector(6 downto 0); + qwdata : in std_logic_vector(7 downto 0); + image_size_reg : in std_logic_vector(31 downto 0); + image_size_reg_wr : in std_logic; + + -- OUT RAM + ram_byte : out std_logic_vector(7 downto 0); + ram_wren : out std_logic; + ram_wraddr : out std_logic_vector(23 downto 0) + ); +end entity JFIFGen; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of JFIFGen is + + constant C_SIZE_Y_H : integer := 25; + constant C_SIZE_Y_L : integer := 26; + constant C_SIZE_X_H : integer := 27; + constant C_SIZE_X_L : integer := 28; + + constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9"; + constant C_QLUM_BASE : integer := 44; + constant C_QCHR_BASE : integer := 44+69; + + + signal hr_data : std_logic_vector(7 downto 0); + signal hr_waddr : std_logic_vector(9 downto 0); + signal hr_raddr : std_logic_vector(9 downto 0); + signal hr_we : std_logic; + signal hr_q : std_logic_vector(7 downto 0); + signal size_wr_cnt : unsigned(2 downto 0); + signal size_wr : std_logic; + signal rd_cnt : unsigned(9 downto 0); + signal rd_en : std_logic; + signal rd_en_d1 : std_logic; + signal rd_cnt_d1 : unsigned(rd_cnt'range); + signal rd_cnt_d2 : unsigned(rd_cnt'range); + signal eoi_cnt : unsigned(1 downto 0); + signal eoi_wr : std_logic; + signal eoi_wr_d1 : std_logic; + + component HeaderRam is + port + ( + d : in STD_LOGIC_VECTOR(7 downto 0); + waddr : in STD_LOGIC_VECTOR(9 downto 0); + raddr : in STD_LOGIC_VECTOR(9 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(7 downto 0) + ); + end component; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + ------------------------------------------------------------------- + -- Header RAM + ------------------------------------------------------------------- + U_Header_RAM : HeaderRam + port map + ( + d => hr_data, + waddr => hr_waddr, + raddr => hr_raddr, + we => hr_we, + clk => CLK, + + q => hr_q + ); + + hr_raddr <= std_logic_vector(rd_cnt); + + ------------------------------------------------------------------- + -- Host programming + ------------------------------------------------------------------- + p_host_wr : process(CLK, RST) + begin + if RST = '1' then + size_wr_cnt <= (others => '0'); + size_wr <= '0'; + hr_we <= '0'; + hr_data <= (others => '0'); + hr_waddr <= (others => '0'); + elsif CLK'event and CLK = '1' then + hr_we <= '0'; + + if image_size_reg_wr = '1' then + size_wr_cnt <= (others => '0'); + size_wr <= '1'; + end if; + + -- write image size + if size_wr = '1' then + if size_wr_cnt = 4 then + size_wr_cnt <= (others => '0'); + size_wr <= '0'; + else + size_wr_cnt <= size_wr_cnt + 1; + hr_we <= '1'; + case size_wr_cnt is + -- height H byte + when "000" => + hr_data <= image_size_reg(15 downto 8); + hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length)); + -- height L byte + when "001" => + hr_data <= image_size_reg(7 downto 0); + hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length)); + -- width H byte + when "010" => + hr_data <= image_size_reg(31 downto 24); + hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length)); + -- width L byte + when "011" => + hr_data <= image_size_reg(23 downto 16); + hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length)); + when others => + null; + end case; + end if; + -- write Quantization table + elsif qwren = '1' then + -- luminance table select + if qwaddr(6) = '0' then + hr_waddr <= std_logic_vector + ( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) + + to_unsigned(C_QLUM_BASE,hr_waddr'length)); + else + -- chrominance table select + hr_waddr <= std_logic_vector + ( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) + + to_unsigned(C_QCHR_BASE,hr_waddr'length)); + end if; + hr_we <= '1'; + hr_data <= qwdata; + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- CTRL + ------------------------------------------------------------------- + p_ctrl : process(CLK, RST) + begin + if RST = '1' then + ready <= '0'; + rd_en <= '0'; + rd_cnt <= (others => '0'); + rd_cnt_d1 <= (others => '0'); + rd_cnt_d2 <= (others => '0'); + rd_cnt_d1 <= (others => '0'); + rd_en_d1 <= '0'; + eoi_wr_d1 <= '0'; + eoi_wr <= '0'; + eoi_cnt <= (others => '0'); + ram_wren <= '0'; + ram_byte <= (others => '0'); + ram_wraddr <= (others => '0'); + elsif CLK'event and CLK = '1' then + ready <= '0'; + rd_cnt_d1 <= rd_cnt; + rd_cnt_d2 <= rd_cnt_d1; + rd_en_d1 <= rd_en; + eoi_wr_d1 <= eoi_wr; + + -- defaults: encoded data write + ram_wren <= rd_en_d1; + ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length)); + ram_byte <= hr_q; + + -- start JFIF + if start = '1' and eoi = '0' then + rd_cnt <= (others => '0'); + rd_en <= '1'; + elsif start = '1' and eoi = '1' then + eoi_wr <= '1'; + eoi_cnt <= (others => '0'); + end if; + + -- read JFIF Header + if rd_en = '1' then + if rd_cnt = C_HDR_SIZE-1 then + rd_en <= '0'; + ready <= '1'; + else + rd_cnt <= rd_cnt + 1; + end if; + end if; + + -- EOI MARKER write + if eoi_wr = '1' then + if eoi_cnt = 2 then + eoi_cnt <= (others => '0'); + eoi_wr <= '0'; + ready <= '1'; + else + eoi_cnt <= eoi_cnt + 1; + ram_wren <= '1'; + if eoi_cnt = 0 then + ram_byte <= C_EOI(15 downto 8); + ram_wraddr <= num_enc_bytes; + elsif eoi_cnt = 1 then + ram_byte <= C_EOI(7 downto 0); + ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) + + to_unsigned(1,ram_wraddr'length)); + end if; + end if; + end if; + end if; + end process; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/JFIFGen/header.hex =================================================================== --- mkjpeg/branches/16rgb/trunk/design/JFIFGen/header.hex (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/JFIFGen/header.hex (revision 48) @@ -0,0 +1,623 @@ +FF +D8 +FF +E0 +00 +10 +4A +46 +49 +46 +00 +01 +01 +00 +00 +01 +00 +01 +00 +00 +FF +C0 +00 +11 +08 +01 +20 +01 +60 +03 +01 +11 +00 +02 +11 +01 +03 +11 +01 +FF +DB +00 +43 +00 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +FF +DB +00 +43 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +01 +FF +C4 +00 +1F +00 +00 +01 +05 +01 +01 +01 +01 +01 +01 +00 +00 +00 +00 +00 +00 +00 +00 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +FF +C4 +00 +1F +01 +00 +03 +01 +01 +01 +01 +01 +01 +01 +01 +01 +00 +00 +00 +00 +00 +00 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +FF +C4 +00 +B5 +10 +00 +02 +01 +03 +03 +02 +04 +03 +05 +05 +04 +04 +00 +00 +01 +7D +01 +02 +03 +00 +04 +11 +05 +12 +21 +31 +41 +06 +13 +51 +61 +07 +22 +71 +14 +32 +81 +91 +A1 +08 +23 +42 +B1 +C1 +15 +52 +D1 +F0 +24 +33 +62 +72 +82 +09 +0A +16 +17 +18 +19 +1A +25 +26 +27 +28 +29 +2A +34 +35 +36 +37 +38 +39 +3A +43 +44 +45 +46 +47 +48 +49 +4A +53 +54 +55 +56 +57 +58 +59 +5A +63 +64 +65 +66 +67 +68 +69 +6A +73 +74 +75 +76 +77 +78 +79 +7A +83 +84 +85 +86 +87 +88 +89 +8A +92 +93 +94 +95 +96 +97 +98 +99 +9A +A2 +A3 +A4 +A5 +A6 +A7 +A8 +A9 +AA +B2 +B3 +B4 +B5 +B6 +B7 +B8 +B9 +BA +C2 +C3 +C4 +C5 +C6 +C7 +C8 +C9 +CA +D2 +D3 +D4 +D5 +D6 +D7 +D8 +D9 +DA +E1 +E2 +E3 +E4 +E5 +E6 +E7 +E8 +E9 +EA +F1 +F2 +F3 +F4 +F5 +F6 +F7 +F8 +F9 +FA +FF +C4 +00 +B5 +11 +00 +02 +01 +02 +04 +04 +03 +04 +07 +05 +04 +04 +00 +01 +02 +77 +00 +01 +02 +03 +11 +04 +05 +21 +31 +06 +12 +41 +51 +07 +61 +71 +13 +22 +32 +81 +08 +14 +42 +91 +A1 +B1 +C1 +09 +23 +33 +52 +F0 +15 +62 +72 +D1 +0A +16 +24 +34 +E1 +25 +F1 +17 +18 +19 +1A +26 +27 +28 +29 +2A +35 +36 +37 +38 +39 +3A +43 +44 +45 +46 +47 +48 +49 +4A +53 +54 +55 +56 +57 +58 +59 +5A +63 +64 +65 +66 +67 +68 +69 +6A +73 +74 +75 +76 +77 +78 +79 +7A +82 +83 +84 +85 +86 +87 +88 +89 +8A +92 +93 +94 +95 +96 +97 +98 +99 +9A +A2 +A3 +A4 +A5 +A6 +A7 +A8 +A9 +AA +B2 +B3 +B4 +B5 +B6 +B7 +B8 +B9 +BA +C2 +C3 +C4 +C5 +C6 +C7 +C8 +C9 +CA +D2 +D3 +D4 +D5 +D6 +D7 +D8 +D9 +DA +E2 +E3 +E4 +E5 +E6 +E7 +E8 +E9 +EA +F2 +F3 +F4 +F5 +F6 +F7 +F8 +F9 +FA +FF +DA +00 +0C +03 +01 +00 +02 +11 +03 +11 +00 +3F +00 Index: mkjpeg/branches/16rgb/trunk/design/JFIFGen/HeaderRAM.v =================================================================== --- mkjpeg/branches/16rgb/trunk/design/JFIFGen/HeaderRAM.v (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/JFIFGen/HeaderRAM.v (revision 48) @@ -0,0 +1,21 @@ +module HeaderRam(d, waddr, raddr, we, clk, q); +output [7:0] q; +input [7:0] d; +input[9:0] raddr; +input[9:0] waddr; +input clk, we; + +reg [9:0] read_addr; +reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */; + +initial $readmemh("../design/jfifgen/header.hex", mem); + +assign q = mem[read_addr]; + +always @(posedge clk) begin +if (we) +mem[waddr] <= d; +read_addr <= raddr; +end + +endmodule Index: mkjpeg/branches/16rgb/trunk/design/bytestuffer/ByteStuffer.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/bytestuffer/ByteStuffer.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/bytestuffer/ByteStuffer.vhd (revision 48) @@ -0,0 +1,220 @@ +------------------------------------------------------------------------------- +-- File Name : ByteStuffer.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : ByteStuffer +-- +-- Content : ByteStuffer +-- +-- Description : ByteStuffer core +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity ByteStuffer is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + + -- HOST IF + sof : in std_logic; + num_enc_bytes : out std_logic_vector(23 downto 0); + outram_base_addr : in std_logic_vector(9 downto 0); + + -- Huffman + huf_buf_sel : out std_logic; + huf_fifo_empty : in std_logic; + huf_rd_req : out std_logic; + huf_packed_byte : in std_logic_vector(7 downto 0); + + -- OUT RAM + ram_byte : out std_logic_vector(7 downto 0); + ram_wren : out std_logic; + ram_wraddr : out std_logic_vector(23 downto 0) + ); +end entity ByteStuffer; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of ByteStuffer is + + signal huf_data_val : std_logic_vector(3 downto 0); + signal wdata_reg : std_logic_vector(15 downto 0); + signal wraddr : unsigned(23 downto 0); + signal wr_n_cnt : unsigned(1 downto 0); + signal huf_buf_sel_s : std_logic; + signal rd_en : std_logic; + signal rd_en_d1 : std_logic; + signal huf_rd_req_s : std_logic; + signal latch_byte : std_logic_vector(7 downto 0); + signal data_valid : std_logic; + signal wait_for_ndata : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + huf_buf_sel <= huf_buf_sel_s; + huf_rd_req <= huf_rd_req_s; + + ------------------------------------------------------------------- + -- CTRL_SM + ------------------------------------------------------------------- + p_ctrl_sm : process(CLK, RST) + begin + if RST = '1' then + wr_n_cnt <= (others => '0'); + ready_pb <= '0'; + huf_rd_req_s <= '0'; + huf_data_val <= (others => '0'); + rd_en <= '0'; + rd_en_d1 <= '0'; + wdata_reg <= (others => '0'); + ram_wren <= '0'; + wraddr <= (others => '0'); + ram_wraddr <= (others => '0'); + ram_byte <= (others => '0'); + latch_byte <= (others => '0'); + wait_for_ndata <= '0'; + data_valid <= '0'; + elsif CLK'event and CLK = '1' then + huf_rd_req_s <= '0'; + ready_pb <= '0'; + huf_data_val <= huf_data_val(huf_data_val'length-2 downto 0) & huf_rd_req_s; + rd_en_d1 <= rd_en; + ram_wren <= '0'; + data_valid <= '0'; + + if start_pb = '1' then + rd_en <= '1'; + end if; + + -- read FIFO until it becomes empty. wait until last byte read is + -- serviced + if rd_en_d1 = '1' and wait_for_ndata = '0' then + -- FIFO empty + if huf_fifo_empty = '1' then + rd_en <= '0'; + rd_en_d1 <= '0'; + ready_pb <= '1'; + else + huf_rd_req_s <= '1'; + wait_for_ndata <= '1'; + end if; + end if; + + -- show ahead FIFO, capture data early + if huf_rd_req_s = '1' then + latch_byte <= huf_packed_byte; + data_valid <= '1'; + end if; + + if huf_data_val(1) = '1' then + wait_for_ndata <= '0'; + end if; + + -- data from FIFO is valid + if data_valid = '1' then + -- stuffing necessary + if latch_byte = X"FF" then + -- two writes are necessary for byte stuffing + wr_n_cnt <= "10"; + wdata_reg <= X"FF00"; + -- no stuffing + else + wr_n_cnt <= "01"; + wdata_reg <= X"00" & latch_byte; + end if; + end if; + + if wr_n_cnt > 0 then + wr_n_cnt <= wr_n_cnt - 1; + ram_wren <= '1'; + wraddr <= wraddr + 1; + end if; + -- delayed to make address post-increment + ram_wraddr <= std_logic_vector(wraddr); + + -- stuffing + if wr_n_cnt = 2 then + ram_byte <= wdata_reg(15 downto 8); + elsif wr_n_cnt = 1 then + ram_byte <= wdata_reg(7 downto 0); + end if; + + if sof = '1' then + wraddr <= to_unsigned(C_HDR_SIZE,wraddr'length); + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- HUFFMAN buf_sel + ------------------------------------------------------------------- + p_huf_buf_sel : process(CLK, RST) + begin + if RST = '1' then + huf_buf_sel_s <= '0'; + elsif CLK'event and CLK = '1' then + if start_pb = '1' then + huf_buf_sel_s <= not huf_buf_sel_s; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- num_enc_bytes + ------------------------------------------------------------------- + p_num_enc_bytes : process(CLK, RST) + begin + if RST = '1' then + num_enc_bytes <= (others => '0'); + elsif CLK'event and CLK = '1' then + -- plus 2 for EOI marker last bytes + num_enc_bytes <= std_logic_vector(wraddr + 2); + end if; + end process; + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/quantizer/QUANT_TOP.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/QUANT_TOP.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/QUANT_TOP.VHD (revision 48) @@ -0,0 +1,233 @@ +------------------------------------------------------------------------------- +-- File Name : QUANT_TOP.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : QUANT_TOP +-- +-- Content : Quantizer Top level +-- +-- Description : Quantizer Top level +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090328: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity QUANT_TOP is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + qua_sm_settings : in T_SM_SETTINGS; + + -- RLE + rle_buf_sel : in std_logic; + rle_rdaddr : in std_logic_vector(5 downto 0); + rle_data : out std_logic_vector(11 downto 0); + + -- ZIGZAG + zig_buf_sel : out std_logic; + zig_rd_addr : out std_logic_vector(5 downto 0); + zig_data : in std_logic_vector(11 downto 0); + + -- HOST + qdata : in std_logic_vector(7 downto 0); + qaddr : in std_logic_vector(6 downto 0); + qwren : in std_logic + ); +end entity QUANT_TOP; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of QUANT_TOP is + + signal dbuf_data : std_logic_vector(11 downto 0); + signal dbuf_q : std_logic_vector(11 downto 0); + signal dbuf_we : std_logic; + signal dbuf_waddr : std_logic_vector(6 downto 0); + signal dbuf_raddr : std_logic_vector(6 downto 0); + signal zigzag_di : std_logic_vector(11 downto 0); + signal zigzag_divalid : std_logic; + signal quant_dout : std_logic_vector(11 downto 0); + signal quant_dovalid : std_logic; + signal wr_cnt : unsigned(5 downto 0); + signal rd_cnt : unsigned(5 downto 0); + signal rd_en_d : std_logic_vector(5 downto 0); + signal rd_en : std_logic; + signal zig_buf_sel_s : std_logic; + signal zz_rd_addr : std_logic_vector(5 downto 0); + signal fifo_empty : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + zig_rd_addr <= std_logic_vector(rd_cnt); + rle_data <= dbuf_q; + zig_buf_sel <= zig_buf_sel_s; + + zigzag_di <= zig_data; + zigzag_divalid <= rd_en_d(0); + + ------------------------------------------------------------------- + -- Quantizer + ------------------------------------------------------------------- + U_quantizer : entity work.quantizer + generic map + ( + SIZE_C => 12, + RAMQADDR_W => 7, + RAMQDATA_W => 8 + ) + port map + ( + rst => RST, + clk => CLK, + di => zigzag_di, + divalid => zigzag_divalid, + qdata => qdata, + qwaddr => qaddr, + qwren => qwren, + cmp_idx => qua_sm_settings.cmp_idx, + + do => quant_dout, + dovalid => quant_dovalid + ); + + ------------------------------------------------------------------- + -- DBUF + ------------------------------------------------------------------- + U_RAMZ : entity work.RAMZ + generic map + ( + RAMADDR_W => 7, + RAMDATA_W => 12 + ) + port map + ( + d => dbuf_data, + waddr => dbuf_waddr, + raddr => dbuf_raddr, + we => dbuf_we, + clk => CLK, + + q => dbuf_q + ); + + dbuf_data <= quant_dout; + dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt); + dbuf_we <= quant_dovalid; + dbuf_raddr <= rle_buf_sel & rle_rdaddr; + + ------------------------------------------------------------------- + -- Counter1 + ------------------------------------------------------------------- + p_counter1 : process(CLK, RST) + begin + if RST = '1' then + rd_en <= '0'; + rd_en_d <= (others => '0'); + rd_cnt <= (others => '0'); + elsif CLK'event and CLK = '1' then + rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en; + + if start_pb = '1' then + rd_cnt <= (others => '0'); + rd_en <= '1'; + end if; + + if rd_en = '1' then + if rd_cnt = 64-1 then + rd_cnt <= (others => '0'); + rd_en <= '0'; + else + rd_cnt <= rd_cnt + 1; + end if; + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- wr_cnt + ------------------------------------------------------------------- + p_wr_cnt : process(CLK, RST) + begin + if RST = '1' then + wr_cnt <= (others => '0'); + ready_pb <= '0'; + elsif CLK'event and CLK = '1' then + ready_pb <= '0'; + + if start_pb = '1' then + wr_cnt <= (others => '0'); + end if; + + if quant_dovalid = '1' then + if wr_cnt = 64-1 then + wr_cnt <= (others => '0'); + else + wr_cnt <=wr_cnt + 1; + end if; + + -- give ready ahead to save cycles! + if wr_cnt = 64-1-3 then + ready_pb <= '1'; + end if; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- zig_buf_sel + ------------------------------------------------------------------- + p_buf_sel : process(CLK, RST) + begin + if RST = '1' then + zig_buf_sel_s <= '0'; + elsif CLK'event and CLK = '1' then + if start_pb = '1' then + zig_buf_sel_s <= not zig_buf_sel_s; + end if; + end if; + end process; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/quantizer/QUANTIZER.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/QUANTIZER.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/QUANTIZER.vhd (revision 48) @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006-2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : DIVIDER -- +-- Design : DCT QUANTIZER -- +-- Author : Michal Krepa -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- File : QUANTIZER.VHD -- +-- Created : Sun Aug 27 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.All; + use IEEE.NUMERIC_STD.all; + +entity quantizer is + generic + ( + SIZE_C : INTEGER := 12; + RAMQADDR_W : INTEGER := 7; + RAMQDATA_W : INTEGER := 8 + ); + port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + divalid : in STD_LOGIC; + qdata : in std_logic_vector(7 downto 0); + qwaddr : in std_logic_vector(6 downto 0); + qwren : in std_logic; + cmp_idx : in unsigned(1 downto 0); + + do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + dovalid : out STD_LOGIC + ); +end quantizer; + +architecture rtl of quantizer is + + constant INTERN_PIPE_C : INTEGER := 3; + + signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0); + signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0); + signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0); + signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal round_s : STD_LOGIC; + signal di_d1 : std_logic_vector(SIZE_C-1 downto 0); + + signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0); + signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0); + signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal table_select : std_logic; + +begin + + ---------------------------- + -- RAMQ + ---------------------------- + U_RAMQ : entity work.RAMZ + generic map + ( + RAMADDR_W => RAMQADDR_W, + RAMDATA_W => RAMQDATA_W + ) + port map + ( + d => qdata, + waddr => qwaddr, + raddr => slv_romaddr_s, + we => qwren, + clk => CLK, + + q => romdatao_s + ); + + + + divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s; + divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0'); + + r_divider : entity work.r_divider + port map + ( + rst => rst, + clk => clk, + a => di_d1, + d => romdatao_s, + + q => do_s + ) ; + do <= do_s; + slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s); + + ------------------------------ + -- Quantization sub table select + ------------------------------ + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + table_select <= '0'; + else + -- luminance table select + if cmp_idx = 0 then + table_select <= '0'; + -- chrominance table select + else + table_select <= '1'; + end if; + end if; + end if; + end process; + + ---------------------------- + -- address incrementer + ---------------------------- + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + romaddr_s <= (others => '0'); + pipeline_reg <= (OTHERS => '0'); + di_d1 <= (OTHERS => '0'); + sign_bit_pipe <= (others => '0'); + else + if divalid = '1' then + romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length); + end if; + + pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid; + + di_d1 <= di; + + sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1); + end if; + end if; + end process; + + dovalid <= pipeline_reg(pipeline_reg'high); + +end rtl; +-------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/quantizer/ROMR.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/ROMR.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/ROMR.vhd (revision 48) @@ -0,0 +1,322 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : ROMR +-- Design : EV_JPEG_ENC +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : ROMR.VHD +-- Created : Wed Mar 19 21:09 2009 +-- +-------------------------------------------------------------------------------- +-- +-- Description : Reciprocal of 1/X where X is 1..255 +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use ieee.numeric_std.all; + +entity ROMR is + generic + ( + ROMADDR_W : INTEGER := 8; + ROMDATA_W : INTEGER := 16 + ); + port( + addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; + + datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) + ); + +end ROMR; + +architecture RTL of ROMR is + + constant CK : integer := 256*256; + type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1) + of INTEGER range 0 to 2**ROMDATA_W-1; + + constant rom : ROMQ_TYPE := + ( + 0, + 65535, + 32768, + 21845, + 16384, + 13107, + 10923, + 9362, + 8192, + 7282, + 6554, + 5958, + 5461, + 5041, + 4681, + 4369, + 4096, + 3855, + 3641, + 3449, + 3277, + 3121, + 2979, + 2849, + 2731, + 2621, + 2521, + 2427, + 2341, + 2260, + 2185, + 2114, + 2048, + 1986, + 1928, + 1872, + 1820, + 1771, + 1725, + 1680, + 1638, + 1598, + 1560, + 1524, + 1489, + 1456, + 1425, + 1394, + 1365, + 1337, + 1311, + 1285, + 1260, + 1237, + 1214, + 1192, + 1170, + 1150, + 1130, + 1111, + 1092, + 1074, + 1057, + 1040, + 1024, + 1008, + 993, + 978, + 964, + 950, + 936, + 923, + 910, + 898, + 886, + 874, + 862, + 851, + 840, + 830, + 819, + 809, + 799, + 790, + 780, + 771, + 762, + 753, + 745, + 736, + 728, + 720, + 712, + 705, + 697, + 690, + 683, + 676, + 669, + 662, + 655, + 649, + 643, + 636, + 630, + 624, + 618, + 612, + 607, + 601, + 596, + 590, + 585, + 580, + 575, + 570, + 565, + 560, + 555, + 551, + 546, + 542, + 537, + 533, + 529, + 524, + 520, + 516, + 512, + 508, + 504, + 500, + 496, + 493, + 489, + 485, + 482, + 478, + 475, + 471, + 468, + 465, + 462, + 458, + 455, + 452, + 449, + 446, + 443, + 440, + 437, + 434, + 431, + 428, + 426, + 423, + 420, + 417, + 415, + 412, + 410, + 407, + 405, + 402, + 400, + 397, + 395, + 392, + 390, + 388, + 386, + 383, + 381, + 379, + 377, + 374, + 372, + 370, + 368, + 366, + 364, + 362, + 360, + 358, + 356, + 354, + 352, + 350, + 349, + 347, + 345, + 343, + 341, + 340, + 338, + 336, + 334, + 333, + 331, + 329, + 328, + 326, + 324, + 323, + 321, + 320, + 318, + 317, + 315, + 314, + 312, + 311, + 309, + 308, + 306, + 305, + 303, + 302, + 301, + 299, + 298, + 297, + 295, + 294, + 293, + 291, + 290, + 289, + 287, + 286, + 285, + 284, + 282, + 281, + 280, + 279, + 278, + 277, + 275, + 274, + 273, + 272, + 271, + 270, + 269, + 267, + 266, + 265, + 264, + 263, + 262, + 261, + 260, + 259, + 258, + 257 + ); + + + + signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); +begin + + datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W)); + + process(clk) + begin + if clk = '1' and clk'event then + addr_reg <= addr; + end if; + end process; + +end RTL; Index: mkjpeg/branches/16rgb/trunk/design/quantizer/r_divider.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/r_divider.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/r_divider.vhd (revision 48) @@ -0,0 +1,124 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : DIVIDER -- +-- Design : Divider using reciprocal table -- +-- Author : Michal Krepa -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- File : R_DIVIDER.VHD -- +-- Created : Wed 18-03-2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- MAIN DIVIDER top level +-------------------------------------------------------------------------------- +library IEEE; + use IEEE.STD_LOGIC_1164.All; + use IEEE.NUMERIC_STD.all; + +entity r_divider is + port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + a : in STD_LOGIC_VECTOR(11 downto 0); + d : in STD_LOGIC_VECTOR(7 downto 0); + + q : out STD_LOGIC_VECTOR(11 downto 0) + ) ; +end r_divider ; + +architecture rtl of r_divider is + + signal romr_datao : std_logic_vector(15 downto 0); + signal romr_addr : std_logic_vector(7 downto 0); + signal dividend : signed(11 downto 0); + signal dividend_d1 : unsigned(11 downto 0); + signal reciprocal : unsigned(15 downto 0); + signal mult_out : unsigned(27 downto 0); + signal mult_out_s : signed(11 downto 0); + signal signbit : std_logic; + signal signbit_d1 : std_logic; + signal signbit_d2 : std_logic; + signal signbit_d3 : std_logic; + signal round : std_logic; + +begin + + U_ROMR : entity work.ROMR + generic map + ( + ROMADDR_W => 8, + ROMDATA_W => 16 + ) + port map + ( + addr => romr_addr, + clk => CLK, + datao => romr_datao + ); + + romr_addr <= d; + reciprocal <= unsigned(romr_datao); + + dividend <= signed(a); + signbit <= dividend(dividend'high); + + rdiv : process(clk,rst) + begin + if rst = '1' then + mult_out <= (others => '0'); + mult_out_s <= (others => '0'); + dividend_d1 <= (others => '0'); + q <= (others => '0'); + signbit_d1 <= '0'; + signbit_d2 <= '0'; + signbit_d3 <= '0'; + round <= '0'; + elsif clk = '1' and clk'event then + signbit_d1 <= signbit; + signbit_d2 <= signbit_d1; + signbit_d3 <= signbit_d2; + if signbit = '1' then + dividend_d1 <= unsigned(0-dividend); + else + dividend_d1 <= unsigned(dividend); + end if; + + mult_out <= dividend_d1 * reciprocal; + + if signbit_d2 = '0' then + mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length); + else + mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length); + end if; + round <= mult_out(15); + + if signbit_d3 = '0' then + if round = '1' then + q <= std_logic_vector(mult_out_s + 1); + else + q <= std_logic_vector(mult_out_s); + end if; + else + if round = '1' then + q <= std_logic_vector(mult_out_s - 1); + else + q <= std_logic_vector(mult_out_s); + end if; + end if; + end if; + end process; + +end rtl; + + Index: mkjpeg/branches/16rgb/trunk/design/quantizer/s_divider.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/s_divider.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/s_divider.vhd (revision 48) @@ -0,0 +1,170 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006-2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : DIVIDER -- +-- Design : Signed Pipelined Divider core -- +-- Author : Michal Krepa -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- File : S_DIVIDER.VHD -- +-- Created : Sat Aug 26 2006 -- +-- Modified : Thu Mar 12 2009 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Description : Signed Pipelined Divider -- +-- -- +-- dividend allowable range of -2**SIZE_C to 2**SIZE_C-1 [SIGNED number] -- +-- divisor allowable range of 1 to (2**SIZE_C)/2-1 [UNSIGNED number] -- +-- pipeline latency is 2*SIZE_C+2 (time from latching input to result ready) -- +-- when pipeline is full new result is generated every clock cycle -- +-- Non-Restoring division algorithm -- +-- Use SIZE_C constant in divider entity to adjust bit width -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- MAIN DIVIDER top level +-------------------------------------------------------------------------------- +library IEEE; + use IEEE.STD_LOGIC_1164.All; + use IEEE.NUMERIC_STD.all; + +entity s_divider is + generic + ( + SIZE_C : INTEGER := 32 + ) ; -- SIZE_C: Number of bits + port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + a : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ; + d : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ; + + q : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ; + r : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ; + round : out STD_LOGIC + ) ; +end s_divider ; + +architecture str of s_divider is + + type S_ARRAY is array(0 to SIZE_C+3) of unsigned(SIZE_C-1 downto 0); + type S2_ARRAY is array(0 to SIZE_C+1) of unsigned(2*SIZE_C-1 downto 0); + + signal d_s : S_ARRAY; + signal q_s : S_ARRAY; + signal r_s : S2_ARRAY; + signal diff : S_ARRAY; + signal qu_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal ru_s : unsigned(SIZE_C-1 downto 0); + signal qu_s2 : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal ru_s2 : unsigned(SIZE_C-1 downto 0); + signal d_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + signal pipeline_reg : STD_LOGIC_VECTOR(SIZE_C+3-1 downto 0); + signal r_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0); + +begin + + pipeline : process(clk,rst) + begin + if rst = '1' then + for k in 0 to SIZE_C loop + r_s(k) <= (others => '0'); + q_s(k) <= (others => '0'); + d_s(k) <= (others => '0'); + end loop; + pipeline_reg <= (others => '0'); + elsif clk = '1' and clk'event then + + -- negative number + if a(SIZE_C-1) = '1' then + -- negate negative number to create positive + r_s(0) <= unsigned(resize(unsigned(not(SIGNED(a)) + TO_SIGNED(1,SIZE_C)),2*SIZE_C)); + -- left shift + pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '1'; + else + r_s(0) <= resize(unsigned(a),2*SIZE_C); + -- left shift + pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '0'; + end if; + d_s(0) <= unsigned(d); + q_s(0) <= (others => '0'); + + -- pipeline + for k in 0 to SIZE_C loop + -- test remainder if positive/negative + if r_s(k)(2*SIZE_C-1) = '0' then + -- shift r_tmp one bit left and subtract d_tmp from upper part of r_tmp + r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) - d_s(k); + else + r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) + d_s(k); + end if; + -- shift r_tmp one bit left (lower part) + r_s(k+1)(SIZE_C-1 downto 0) <= r_s(k)(SIZE_C-2 downto 0) & '0'; + + if diff(k)(SIZE_C-1) = '0' then + q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '1'; + else + q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '0'; + end if; + + d_s(k+1) <= d_s(k); + end loop; + end if; + end process; + + G_DIFF: for x in 0 to SIZE_C generate + diff(x) <= r_s(x)(2*SIZE_C-2 downto SIZE_C-1) - d_s(x) when r_s(x)(2*SIZE_C-1) = '0' + else r_s(x)(2*SIZE_C-2 downto SIZE_C-1) + d_s(x); + end generate G_DIFF; + + qu_s <= STD_LOGIC_VECTOR( q_s(SIZE_C) ); + ru_s <= r_s(SIZE_C)(2*SIZE_C-1 downto SIZE_C); + + process(clk,rst) + begin + if rst = '1' then + q <= (others => '0'); + r_reg <= (others => '0'); + round <= '0'; + elsif clk = '1' and clk'event then + + + if ru_s(SIZE_C-1) = '0' then + ru_s2 <= (ru_s); + else + ru_s2 <= (unsigned(ru_s) + d_s(SIZE_C)); + end if; + qu_s2 <= qu_s; + + -- negative number + if pipeline_reg(SIZE_C+1) = '1' then + -- negate positive number to create negative + q <= STD_LOGIC_VECTOR(not(SIGNED(qu_s2)) + TO_SIGNED(1,SIZE_C)); + r_reg <= STD_LOGIC_VECTOR(not(SIGNED(ru_s2)) + TO_SIGNED(1,SIZE_C)); + else + q <= STD_LOGIC_VECTOR(qu_s2); + r_reg <= STD_LOGIC_VECTOR(ru_s2); + end if; + + -- if 2*remainder >= divisor then add 1 to round to nearest integer + if (ru_s2(SIZE_C-2 downto 0) & '0') >= d_s(SIZE_C+1) then + round <= '1'; + else + round <= '0'; + end if; + end if; + end process; + + -- remainder + r <= r_reg; + +end str; + + Index: mkjpeg/branches/16rgb/trunk/design/quantizer/ROMQ.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/quantizer/ROMQ.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/quantizer/ROMQ.vhd (revision 48) @@ -0,0 +1,92 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : ROMQ.VHD +-- Created : Sun Aug 27 18:09 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : ROM for DCT quantizer matrix +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use ieee.numeric_std.all; + +entity ROMQ is + generic + ( + ROMADDR_W : INTEGER := 6; + ROMDATA_W : INTEGER := 8 + ); + port( + addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; + + datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) + ); + +end ROMQ; + +architecture RTL of ROMQ is + + type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1) + of INTEGER range 0 to 2**ROMDATA_W-1; + + constant rom : ROMQ_TYPE := + -- ( + -- 16,11,10,16,24,40,51,61, + -- 12,12,14,19,26,58,60,55, + -- 14,13,16,24,40,57,69,56, + -- 14,17,22,29,51,87,80,62, + -- 18,22,37,56,68,109,103,77, + -- 24,35,55,64,81,104,113,92, + -- 49,64,78,87,103,121,120,101, + -- 72,92,95,98,112,100,103,99); + ( + --8,6,6,7,6,5,8, + --7,7,7,9,9,8,10,12, + --20,13,12,11,11,12,25,18,19,15,20,29, + --26,31,30,29,26,28,28,32,36,46,39,32, + --34,44,35,28,28,40,55,41,44,48,49,52,52,52, + --31,39,57,61,56,50,60,46,51,52,50 + + + + + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1 + ); + + + + signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); +begin + + datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W)); + + process(clk) + begin + if clk = '1' and clk'event then + addr_reg <= addr; + end if; + end process; + +end RTL; Index: mkjpeg/branches/16rgb/trunk/design/zigzag/ZZ_TOP.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/zigzag/ZZ_TOP.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/zigzag/ZZ_TOP.VHD (revision 48) @@ -0,0 +1,247 @@ +------------------------------------------------------------------------------- +-- File Name : ZZ_TOP.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : ZZ_TOP +-- +-- Content : ZigZag Top level +-- +-- Description : Zig Zag scan +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity ZZ_TOP is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + zig_sm_settings : in T_SM_SETTINGS; + + -- Quantizer + qua_buf_sel : in std_logic; + qua_rdaddr : in std_logic_vector(5 downto 0); + qua_data : out std_logic_vector(11 downto 0); + + -- FDCT + fdct_buf_sel : out std_logic; + fdct_rd_addr : out std_logic_vector(5 downto 0); + fdct_data : in std_logic_vector(11 downto 0); + fdct_rden : out std_logic + ); +end entity ZZ_TOP; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of ZZ_TOP is + + signal dbuf_data : std_logic_vector(11 downto 0); + signal dbuf_q : std_logic_vector(11 downto 0); + signal dbuf_we : std_logic; + signal dbuf_waddr : std_logic_vector(6 downto 0); + signal dbuf_raddr : std_logic_vector(6 downto 0); + signal zigzag_di : std_logic_vector(11 downto 0); + signal zigzag_divalid : std_logic; + signal zigzag_dout : std_logic_vector(11 downto 0); + signal zigzag_dovalid : std_logic; + signal wr_cnt : unsigned(5 downto 0); + signal rd_cnt : unsigned(5 downto 0); + signal rd_en_d : std_logic_vector(5 downto 0); + signal rd_en : std_logic; + signal fdct_buf_sel_s : std_logic; + signal zz_rd_addr : std_logic_vector(5 downto 0); + signal fifo_empty : std_logic; + signal fifo_rden : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + fdct_rd_addr <= std_logic_vector(zz_rd_addr); + qua_data <= dbuf_q; + fdct_buf_sel <= fdct_buf_sel_s; + fdct_rden <= rd_en; + + ------------------------------------------------------------------- + -- ZigZag Core + ------------------------------------------------------------------- + U_zigzag : entity work.zigzag + generic map + ( + RAMADDR_W => 6, + RAMDATA_W => 12 + ) + port map + ( + rst => RST, + clk => CLK, + di => zigzag_di, + divalid => zigzag_divalid, + rd_addr => rd_cnt, + fifo_rden => fifo_rden, + + fifo_empty => fifo_empty, + dout => zigzag_dout, + dovalid => zigzag_dovalid, + zz_rd_addr => zz_rd_addr + ); + + zigzag_di <= fdct_data; + zigzag_divalid <= rd_en_d(1); + + ------------------------------------------------------------------- + -- DBUF + ------------------------------------------------------------------- + U_RAMZ : entity work.RAMZ + generic map + ( + RAMADDR_W => 7, + RAMDATA_W => 12 + ) + port map + ( + d => dbuf_data, + waddr => dbuf_waddr, + raddr => dbuf_raddr, + we => dbuf_we, + clk => CLK, + + q => dbuf_q + ); + + dbuf_data <= zigzag_dout; + dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt); + dbuf_we <= zigzag_dovalid; + dbuf_raddr <= qua_buf_sel & qua_rdaddr; + + ------------------------------------------------------------------- + -- FIFO Ctrl + ------------------------------------------------------------------- + p_fifo_ctrl : process(CLK, RST) + begin + if RST = '1' then + fifo_rden <= '0'; + elsif CLK'event and CLK = '1' then + if fifo_empty = '0' then + fifo_rden <= '1'; + else + fifo_rden <= '0'; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- Counter1 + ------------------------------------------------------------------- + p_counter1 : process(CLK, RST) + begin + if RST = '1' then + rd_en <= '0'; + rd_en_d <= (others => '0'); + rd_cnt <= (others => '0'); + elsif CLK'event and CLK = '1' then + rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en; + + if start_pb = '1' then + rd_cnt <= (others => '0'); + rd_en <= '1'; + end if; + + if rd_en = '1' then + if rd_cnt = 64-1 then + rd_cnt <= (others => '0'); + rd_en <= '0'; + else + rd_cnt <= rd_cnt + 1; + end if; + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- wr_cnt + ------------------------------------------------------------------- + p_wr_cnt : process(CLK, RST) + begin + if RST = '1' then + wr_cnt <= (others => '0'); + ready_pb <= '0'; + elsif CLK'event and CLK = '1' then + ready_pb <= '0'; + + if start_pb = '1' then + wr_cnt <= (others => '0'); + end if; + + if zigzag_dovalid = '1' then + if wr_cnt = 64-1 then + wr_cnt <= (others => '0'); + else + wr_cnt <=wr_cnt + 1; + end if; + + -- give ready ahead to save cycles! + if wr_cnt = 64-1-3 then + ready_pb <= '1'; + end if; + + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- fdct_buf_sel + ------------------------------------------------------------------- + p_buf_sel : process(CLK, RST) + begin + if RST = '1' then + fdct_buf_sel_s <= '0'; + elsif CLK'event and CLK = '1' then + if start_pb = '1' then + fdct_buf_sel_s <= not fdct_buf_sel_s; + end if; + end if; + end process; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/zigzag/ZIGZAG.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/zigzag/ZIGZAG.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/zigzag/ZIGZAG.VHD (revision 48) @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : ZIGZAG -- +-- Design : MDCT CORE -- +-- Author : Michal Krepa -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- File : ZIGZAG.VHD -- +-- Created : Sun Sep 3 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Description : Zig-Zag scan -- +-- -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.All; + use IEEE.NUMERIC_STD.all; + +entity zigzag is + generic + ( + RAMADDR_W : INTEGER := 6; + RAMDATA_W : INTEGER := 12 + ); + port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + divalid : in STD_LOGIC; + rd_addr : in unsigned(5 downto 0); + fifo_rden : in std_logic; + + fifo_empty : out std_logic; + dout : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + dovalid : out std_logic; + zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0) + ); +end zigzag; + +architecture rtl of zigzag is + + type ZIGZAG_TYPE is array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1; + constant ZIGZAG_ARRAY : ZIGZAG_TYPE := + ( + 0,1,8,16,9,2,3,10, + 17,24,32,25,18,11,4,5, + 12,19,26,33,40,48,41,34, + 27,20,13,6,7,14,21,28, + 35,42,49,56,57,50,43,36, + 29,22,15,23,30,37,44,51, + 58,59,52,45,38,31,39,46, + 53,60,61,54,47,55,62,63 + ); + + signal fifo_wr : std_logic; + signal fifo_q : std_logic_vector(11 downto 0); + signal fifo_full : std_logic; + signal fifo_count : std_logic_vector(6 downto 0); + signal fifo_data_in : std_logic_vector(11 downto 0); + signal fifo_empty_s : std_logic; + + +begin + + dout <= fifo_q; + fifo_empty <= fifo_empty_s; + + ------------------------------------------------------------------- + -- FIFO (show ahead) + ------------------------------------------------------------------- + U_FIFO : entity work.FIFO + generic map + ( + DATA_WIDTH => 12, + ADDR_WIDTH => 6 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo_rden, + winc => fifo_wr, + datai => fifo_data_in, + + datao => fifo_q, + fullo => fifo_full, + emptyo => fifo_empty_s, + count => fifo_count + ); + + fifo_wr <= divalid; + fifo_data_in <= di; + + + process(clk) + begin + if clk = '1' and clk'event then + if rst = '1' then + zz_rd_addr <= (others => '0'); + dovalid <= '0'; + else + zz_rd_addr <= std_logic_vector( + to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6)); + + dovalid <= fifo_rden and not fifo_empty_s; + end if; + end if; + end process; + + +end rtl; +-------------------------------------------------------------------------------- Index: mkjpeg/branches/16rgb/trunk/design/hostif/HostIF.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/hostif/HostIF.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/hostif/HostIF.vhd (revision 48) @@ -0,0 +1,274 @@ +------------------------------------------------------------------------------- +-- File Name : HostIF.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : HostIF +-- +-- Content : Host Interface (Xilinx OPB v2.1) +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity HostIF is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- OPB + OPB_ABus : in std_logic_vector(31 downto 0); + OPB_BE : in std_logic_vector(3 downto 0); + OPB_DBus_in : in std_logic_vector(31 downto 0); + OPB_RNW : in std_logic; + OPB_select : in std_logic; + OPB_DBus_out : out std_logic_vector(31 downto 0); + OPB_XferAck : out std_logic; + OPB_retry : out std_logic; + OPB_toutSup : out std_logic; + OPB_errAck : out std_logic; + + -- Quantizer RAM + qdata : out std_logic_vector(7 downto 0); + qaddr : out std_logic_vector(6 downto 0); + qwren : out std_logic; + + -- CTRL + jpeg_ready : in std_logic; + jpeg_busy : in std_logic; + + -- ByteStuffer + outram_base_addr : out std_logic_vector(9 downto 0); + num_enc_bytes : in std_logic_vector(23 downto 0); + + -- others + img_size_x : out std_logic_vector(15 downto 0); + img_size_y : out std_logic_vector(15 downto 0); + img_size_wr : out std_logic; + sof : out std_logic; + cmp_max : out std_logic_vector(1 downto 0) + + ); +end entity HostIF; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of HostIF is + + constant C_ENC_START_REG : std_logic_vector(31 downto 0) := X"0000_0000"; + constant C_IMAGE_SIZE_REG : std_logic_vector(31 downto 0) := X"0000_0004"; + constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008"; + constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C"; + constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010"; + constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014"; + constant C_QUANTIZER_RAM_LUM : std_logic_vector(31 downto 0) := + X"0000_01" & "------00"; + constant C_QUANTIZER_RAM_CHR : std_logic_vector(31 downto 0) := + X"0000_02" & "------00"; + constant C_IMAGE_RAM : std_logic_vector(31 downto 0) := + X"001" & "------------------00"; + + constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000"; + + signal enc_start_reg : std_logic_vector(31 downto 0); + signal image_size_reg : std_logic_vector(31 downto 0); + signal image_ram_access_reg : std_logic_vector(31 downto 0); + signal enc_sts_reg : std_logic_vector(31 downto 0); + signal cod_data_addr_reg : std_logic_vector(31 downto 0); + signal enc_length_reg : std_logic_vector(31 downto 0); + + signal rd_dval : std_logic; + signal data_read : std_logic_vector(31 downto 0); + signal write_done : std_logic; + signal OPB_select_d : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + OPB_retry <= '0'; + OPB_toutSup <= '0'; + OPB_errAck <= '0'; + + img_size_x <= image_size_reg(31 downto 16); + img_size_y <= image_size_reg(15 downto 0); + + outram_base_addr <= cod_data_addr_reg(outram_base_addr'range); + + cmp_max <= enc_start_reg(2 downto 1); + + ------------------------------------------------------------------- + -- OPB read + ------------------------------------------------------------------- + p_read : process(CLK, RST) + begin + if RST = '1' then + OPB_DBus_out <= (others => '0'); + rd_dval <= '0'; + data_read <= (others => '0'); + elsif CLK'event and CLK = '1' then + rd_dval <= '0'; + + OPB_DBus_out <= data_read; + + if OPB_select = '1' and OPB_select_d = '0' then + -- only double word transactions are be supported + if OPB_RNW = '1' and OPB_BE = X"F" then + case OPB_ABus is + when C_ENC_START_REG => + data_read <= enc_start_reg; + rd_dval <= '1'; + + when C_IMAGE_SIZE_REG => + data_read <= image_size_reg; + rd_dval <= '1'; + + when C_IMAGE_RAM_ACCESS_REG => + data_read <= image_ram_access_reg; + rd_dval <= '1'; + + when C_ENC_STS_REG => + data_read <= enc_sts_reg; + rd_dval <= '1'; + + when C_COD_DATA_ADDR_REG => + data_read <= cod_data_addr_reg; + rd_dval <= '1'; + + when C_ENC_LENGTH_REG => + data_read <= enc_length_reg; + rd_dval <= '1'; + + when others => + data_read <= (others => '0'); + end case; + + end if; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- OPB write + ------------------------------------------------------------------- + p_write : process(CLK, RST) + begin + if RST = '1' then + qwren <= '0'; + write_done <= '0'; + enc_start_reg <= (others => '0'); + image_size_reg <= (others => '0'); + image_ram_access_reg <= (others => '0'); + enc_sts_reg <= (others => '0'); + cod_data_addr_reg <= (others => '0'); + enc_length_reg <= (others => '0'); + qdata <= (others => '0'); + qaddr <= (others => '0'); + OPB_select_d <= '0'; + sof <= '0'; + img_size_wr <= '0'; + elsif CLK'event and CLK = '1' then + qwren <= '0'; + write_done <= '0'; + sof <= '0'; + img_size_wr <= '0'; + OPB_select_d <= OPB_select; + + if OPB_select = '1' and OPB_select_d = '0' then + -- only double word transactions are be supported + if OPB_RNW = '0' and OPB_BE = X"F" then + case OPB_ABus is + when C_ENC_START_REG => + enc_start_reg <= OPB_DBus_in; + write_done <= '1'; + if OPB_DBus_in(0) = '1' then + sof <= '1'; + end if; + + when C_IMAGE_SIZE_REG => + image_size_reg <= OPB_DBus_in; + img_size_wr <= '1'; + write_done <= '1'; + + when C_IMAGE_RAM_ACCESS_REG => + image_ram_access_reg <= OPB_DBus_in; + write_done <= '1'; + + when C_ENC_STS_REG => + enc_sts_reg <= (others => '0'); + write_done <= '1'; + + when C_COD_DATA_ADDR_REG => + cod_data_addr_reg <= OPB_DBus_in; + write_done <= '1'; + + when C_ENC_LENGTH_REG => + --enc_length_reg <= OPB_DBus_in; + write_done <= '1'; + + when others => + null; + end case; + + if std_match(OPB_ABus, C_QUANTIZER_RAM_LUM) then + qdata <= OPB_DBus_in(qdata'range); + qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2); + qwren <= '1'; + write_done <= '1'; + end if; + + if std_match(OPB_ABus, C_QUANTIZER_RAM_CHR) then + qdata <= OPB_DBus_in(qdata'range); + qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2); + qwren <= '1'; + write_done <= '1'; + end if; + + end if; + end if; + + -- special handling of status reg + if jpeg_ready = '1' then + -- set jpeg done flag + enc_sts_reg(1) <= '1'; + end if; + enc_sts_reg(0) <= jpeg_busy; + + enc_length_reg <= (others => '0'); + enc_length_reg(num_enc_bytes'range) <= num_enc_bytes; + + end if; + end process; + + ------------------------------------------------------------------- + -- transfer ACK + ------------------------------------------------------------------- + p_ack : process(CLK, RST) + begin + if RST = '1' then + OPB_XferAck <= '0'; + elsif CLK'event and CLK = '1' then + OPB_XferAck <= rd_dval or write_done; + end if; + end process; + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/mdct/FDCT.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/FDCT.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/FDCT.vhd (revision 48) @@ -0,0 +1,555 @@ +------------------------------------------------------------------------------- +-- File Name : FDCT.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : FDCT +-- +-- Content : FDCT +-- +-- Description : 2D Discrete Cosine Transform +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity FDCT is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + start_pb : in std_logic; + ready_pb : out std_logic; + fdct_sm_settings : in T_SM_SETTINGS; + + -- BUF_FIFO + bf_block_cnt : out std_logic_vector(12 downto 0); + bf_fifo_rd : out std_logic; + bf_fifo_empty : in std_logic; + bf_fifo_q : in std_logic_vector(23 downto 0); + bf_fifo_hf_full : in std_logic; + + -- ZIG ZAG + zz_buf_sel : in std_logic; + zz_rd_addr : in std_logic_vector(5 downto 0); + zz_data : out std_logic_vector(11 downto 0); + zz_rden : in std_logic; + + -- HOST + img_size_x : in std_logic_vector(15 downto 0); + img_size_y : in std_logic_vector(15 downto 0); + sof : in std_logic + ); +end entity FDCT; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of FDCT is + + constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15); + constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15); + constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15); + constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15); + constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15); + constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15); + constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15); + constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15); + constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15); + + + signal mdct_data_in : std_logic_vector(7 downto 0); + signal mdct_idval : std_logic; + signal mdct_odval : std_logic; + signal mdct_data_out : std_logic_vector(11 downto 0); + signal odv1 : std_logic; + signal dcto1 : std_logic_vector(11 downto 0); + signal x_block_cnt : unsigned(15 downto 0); + signal y_block_cnt : unsigned(15 downto 0); + signal x_block_cnt_cur : unsigned(15 downto 0); + signal y_block_cnt_cur : unsigned(15 downto 0); + signal rd_addr : std_logic_vector(31 downto 0); + signal input_rd_cnt : unsigned(5 downto 0); + signal rd_en : std_logic; + signal rd_en_d1 : std_logic; + signal rdaddr : unsigned(31 downto 0); + signal bf_dval : std_logic_vector(3 downto 0); + signal wr_cnt : unsigned(5 downto 0); + signal dbuf_data : std_logic_vector(11 downto 0); + signal dbuf_q : std_logic_vector(11 downto 0); + signal dbuf_we : std_logic; + signal dbuf_waddr : std_logic_vector(6 downto 0); + signal dbuf_raddr : std_logic_vector(6 downto 0); + signal xw_cnt : unsigned(2 downto 0); + signal yw_cnt : unsigned(2 downto 0); + + signal dbuf_q_z1 : std_logic_vector(11 downto 0); + constant C_SIMA_ASZ : integer := 9; + signal sim_rd_addr : unsigned(C_SIMA_ASZ-1 downto 0); + signal Y_reg_1 : signed(23 downto 0); + signal Y_reg_2 : signed(23 downto 0); + signal Y_reg_3 : signed(23 downto 0); + signal Cb_reg_1 : signed(23 downto 0); + signal Cb_reg_2 : signed(23 downto 0); + signal Cb_reg_3 : signed(23 downto 0); + signal Cr_reg_1 : signed(23 downto 0); + signal Cr_reg_2 : signed(23 downto 0); + signal Cr_reg_3 : signed(23 downto 0); + signal Y_reg : signed(23 downto 0); + signal Cb_reg : signed(23 downto 0); + signal Cr_reg : signed(23 downto 0); + signal R_s : signed(8 downto 0); + signal G_s : signed(8 downto 0); + signal B_s : signed(8 downto 0); + signal Y_8bit : unsigned(7 downto 0); + signal Cb_8bit : unsigned(7 downto 0); + signal Cr_8bit : unsigned(7 downto 0); + signal cmp_idx : unsigned(1 downto 0); + signal cur_cmp_idx : unsigned(1 downto 0); + signal cur_cmp_idx_d1 : unsigned(1 downto 0); + signal cur_cmp_idx_d2 : unsigned(1 downto 0); + signal cur_cmp_idx_d3 : unsigned(1 downto 0); + signal cur_cmp_idx_d4 : unsigned(1 downto 0); + signal cur_cmp_idx_d5 : unsigned(1 downto 0); + signal cur_cmp_idx_d6 : unsigned(1 downto 0); + signal cur_cmp_idx_d7 : unsigned(1 downto 0); + signal cur_cmp_idx_d8 : unsigned(1 downto 0); + signal cur_cmp_idx_d9 : unsigned(1 downto 0); + signal fifo1_rd : std_logic; + signal fifo1_wr : std_logic; + signal fifo1_q : std_logic_vector(11 downto 0); + signal fifo1_full : std_logic; + signal fifo1_empty : std_logic; + signal fifo1_count : std_logic_vector(8 downto 0); + signal fifo1_rd_cnt : unsigned(5 downto 0); + signal fifo1_q_dval : std_logic; + signal fifo_data_in : std_logic_vector(11 downto 0); + signal fifo_rd_arm : std_logic; + + signal eoi_fdct : std_logic; + signal bf_fifo_rd_s : std_logic; + signal start_int : std_logic; + + signal fram1_data : std_logic_vector(23 downto 0); + signal fram1_q : std_logic_vector(23 downto 0); + signal fram1_we : std_logic; + signal fram1_waddr : std_logic_vector(5 downto 0); + signal fram1_raddr : std_logic_vector(5 downto 0); + signal fram1_rd_d : std_logic_vector(8 downto 0); + signal fram1_rd : std_logic; + signal bf_fifo_empty_d1 : std_logic; + signal rd_started : std_logic; + signal writing_en : std_logic; + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + zz_data <= dbuf_q; + + bf_fifo_rd <= bf_fifo_rd_s; + bf_block_cnt <= std_logic_vector(x_block_cnt_cur(15 downto 3)); + + ------------------------------------------------------------------- + -- FRAM1 + ------------------------------------------------------------------- + U_FRAM1 : entity work.RAMZ + generic map + ( + RAMADDR_W => 6, + RAMDATA_W => 24 + ) + port map + ( + d => fram1_data, + waddr => fram1_waddr, + raddr => fram1_raddr, + we => fram1_we, + clk => CLK, + + q => fram1_q + ); + + fram1_we <= bf_dval(bf_dval'high); + fram1_data <= bf_fifo_q; + + ------------------------------------------------------------------- + -- FRAM1 process + ------------------------------------------------------------------- + p_fram1_acc : process(CLK, RST) + begin + if RST = '1' then + fram1_waddr <= (others => '0'); + elsif CLK'event and CLK = '1' then + if fram1_we = '1' then + fram1_waddr <= std_logic_vector(unsigned(fram1_waddr) + 1); + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- IRAM read process + ------------------------------------------------------------------- + p_counter1 : process(CLK, RST) + begin + if RST = '1' then + rd_en <= '0'; + rd_en_d1 <= '0'; + x_block_cnt <= (others => '0'); + y_block_cnt <= (others => '0'); + input_rd_cnt <= (others => '0'); + cmp_idx <= (others => '0'); + cur_cmp_idx <= (others => '0'); + cur_cmp_idx_d1 <= (others => '0'); + cur_cmp_idx_d2 <= (others => '0'); + cur_cmp_idx_d3 <= (others => '0'); + cur_cmp_idx_d4 <= (others => '0'); + cur_cmp_idx_d5 <= (others => '0'); + cur_cmp_idx_d6 <= (others => '0'); + cur_cmp_idx_d7 <= (others => '0'); + cur_cmp_idx_d8 <= (others => '0'); + cur_cmp_idx_d9 <= (others => '0'); + eoi_fdct <= '0'; + x_block_cnt_cur <= (others => '0'); + y_block_cnt_cur <= (others => '0'); + start_int <= '0'; + bf_fifo_rd_s <= '0'; + bf_dval <= (others => '0'); + fram1_rd <= '0'; + fram1_rd_d <= (others => '0'); + fram1_raddr <= (others => '0'); + elsif CLK'event and CLK = '1' then + rd_en_d1 <= rd_en; + cur_cmp_idx_d1 <= cur_cmp_idx; + cur_cmp_idx_d2 <= cur_cmp_idx_d1; + cur_cmp_idx_d3 <= cur_cmp_idx_d2; + cur_cmp_idx_d4 <= cur_cmp_idx_d3; + cur_cmp_idx_d5 <= cur_cmp_idx_d4; + cur_cmp_idx_d6 <= cur_cmp_idx_d5; + cur_cmp_idx_d7 <= cur_cmp_idx_d6; + cur_cmp_idx_d8 <= cur_cmp_idx_d7; + cur_cmp_idx_d9 <= cur_cmp_idx_d8; + start_int <= '0'; + + bf_dval <= bf_dval(bf_dval'length-2 downto 0) & bf_fifo_rd_s; + fram1_rd_d <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd; + + -- SOF or internal self-start + if (sof = '1' or start_int = '1') then + input_rd_cnt <= (others => '0'); + -- enable BUF_FIFO/FRAM1 reading + rd_started <= '1'; + + -- component index + if cmp_idx = 3-1 then + cmp_idx <= (others => '0'); + -- horizontal block counter + if x_block_cnt = unsigned(img_size_x)-8 then + x_block_cnt <= (others => '0'); + -- vertical block counter + if y_block_cnt = unsigned(img_size_y)-8 then + y_block_cnt <= (others => '0'); + eoi_fdct <= '1'; + else + y_block_cnt <= y_block_cnt + 8; + end if; + else + x_block_cnt <= x_block_cnt + 8; + end if; + else + cmp_idx <=cmp_idx + 1; + end if; + + x_block_cnt_cur <= x_block_cnt; + y_block_cnt_cur <= y_block_cnt; + cur_cmp_idx <= cmp_idx; + end if; + + -- wait until FIFO becomes half full + if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx /= 0) then + rd_en <= '1'; + rd_started <= '0'; + end if; + + bf_fifo_rd_s <= '0'; + fram1_rd <= '0'; + -- stall reading from input FIFO and writing to output FIFO + -- when output FIFO is almost full + if rd_en = '1' and unsigned(fifo1_count) < 256-64 then + -- read request goes to BUF_FIFO only for component 0. + if cur_cmp_idx = 0 then + bf_fifo_rd_s <= '1'; + end if; + + -- count number of samples read from input in one run + if input_rd_cnt = 64-1 then + rd_en <= '0'; + start_int <= '1' and not eoi_fdct; + eoi_fdct <= '0'; + else + input_rd_cnt <= input_rd_cnt + 1; + end if; + -- FRAM read enable + fram1_rd <= '1'; + end if; + + -- increment FRAM1 read address + if fram1_rd_d(4) = '1' then + fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1); + end if; + + end if; + end process; + + ------------------------------------------------------------------- + -- FDCT with input level shift + ------------------------------------------------------------------- + U_MDCT : entity work.MDCT + port map + ( + clk => CLK, + rst => RST, + dcti => mdct_data_in, + idv => mdct_idval, + odv => mdct_odval, + dcto => mdct_data_out, + odv1 => odv1, + dcto1 => dcto1 + ); + + mdct_idval <= fram1_rd_d(8); + + R_s <= signed('0' & fram1_q(7 downto 0)); + G_s <= signed('0' & fram1_q(15 downto 8)); + B_s <= signed('0' & fram1_q(23 downto 16)); + + ------------------------------------------------------------------- + -- Mux1 + ------------------------------------------------------------------- + p_mux1 : process(CLK, RST) + begin + if RST = '1' then + mdct_data_in <= (others => '0'); + elsif CLK'event and CLK = '1' then + case cur_cmp_idx_d9 is + when "00" => + mdct_data_in <= std_logic_vector(Y_8bit); + when "01" => + mdct_data_in <= std_logic_vector(Cb_8bit); + when "10" => + mdct_data_in <= std_logic_vector(Cr_8bit); + when others => + null; + end case; + end if; + end process; + + + ------------------------------------------------------------------- + -- FIFO1 + ------------------------------------------------------------------- + U_FIFO1 : entity work.FIFO + generic map + ( + DATA_WIDTH => 12, + ADDR_WIDTH => 8 + ) + port map + ( + rst => RST, + clk => CLK, + rinc => fifo1_rd, + winc => fifo1_wr, + datai => fifo_data_in, + + datao => fifo1_q, + fullo => fifo1_full, + emptyo => fifo1_empty, + count => fifo1_count + ); + + fifo1_wr <= mdct_odval; + fifo_data_in <= mdct_data_out; + + + + ------------------------------------------------------------------- + -- FIFO rd controller + ------------------------------------------------------------------- + p_fifo_rd_ctrl : process(CLK, RST) + begin + if RST = '1' then + fifo1_rd <= '0'; + fifo_rd_arm <= '0'; + fifo1_rd_cnt <= (others => '0'); + fifo1_q_dval <= '0'; + elsif CLK'event and CLK = '1' then + fifo1_rd <= '0'; + + fifo1_q_dval <= fifo1_rd; + + if start_pb = '1' then + fifo_rd_arm <= '1'; + fifo1_rd_cnt <= (others => '0'); + end if; + + if fifo_rd_arm = '1' then + + if fifo1_rd_cnt = 64-1 then + fifo_rd_arm <= '0'; + fifo1_rd <= '1'; + elsif fifo1_empty = '0' then + fifo1_rd <= '1'; + fifo1_rd_cnt <= fifo1_rd_cnt + 1; + end if; + + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- write counter + ------------------------------------------------------------------- + p_wr_cnt : process(CLK, RST) + begin + if RST = '1' then + wr_cnt <= (others => '0'); + ready_pb <= '0'; + xw_cnt <= (others => '0'); + yw_cnt <= (others => '0'); + writing_en <= '0'; + elsif CLK'event and CLK = '1' then + ready_pb <= '0'; + + if start_pb = '1' then + wr_cnt <= (others => '0'); + xw_cnt <= (others => '0'); + yw_cnt <= (others => '0'); + writing_en <= '1'; + end if; + + if writing_en = '1' then + if fifo1_q_dval = '1' then + if wr_cnt = 64-1 then + wr_cnt <= (others => '0'); + ready_pb <= '1'; + writing_en <= '0'; + else + wr_cnt <= wr_cnt + 1; + end if; + + if yw_cnt = 8-1 then + yw_cnt <= (others => '0'); + xw_cnt <= xw_cnt+1; + else + yw_cnt <= yw_cnt+1; + end if; + end if; + end if; + end if; + end process; + + ------------------------------------------------------------------- + -- RGB to YCbCr conversion + ------------------------------------------------------------------- + p_rgb2ycbcr : process(CLK, RST) + begin + if RST = '1' then + Y_Reg_1 <= (others => '0'); + Y_Reg_2 <= (others => '0'); + Y_Reg_3 <= (others => '0'); + Cb_Reg_1 <= (others => '0'); + Cb_Reg_2 <= (others => '0'); + Cb_Reg_3 <= (others => '0'); + Cr_Reg_1 <= (others => '0'); + Cr_Reg_2 <= (others => '0'); + Cr_Reg_3 <= (others => '0'); + Y_Reg <= (others => '0'); + Cb_Reg <= (others => '0'); + Cr_Reg <= (others => '0'); + elsif CLK'event and CLK = '1' then + Y_Reg_1 <= R_s*C_Y_1; + Y_Reg_2 <= G_s*C_Y_2; + Y_Reg_3 <= B_s*C_Y_3; + + Cb_Reg_1 <= R_s*C_Cb_1; + Cb_Reg_2 <= G_s*C_Cb_2; + Cb_Reg_3 <= B_s*C_Cb_3; + + Cr_Reg_1 <= R_s*C_Cr_1; + Cr_Reg_2 <= G_s*C_Cr_2; + Cr_Reg_3 <= B_s*C_Cr_3; + + Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3; + Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length); + Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length); + + end if; + end process; + + Y_8bit <= unsigned(Y_Reg(21 downto 14)); + Cb_8bit <= unsigned(Cb_Reg(21 downto 14)); + Cr_8bit <= unsigned(Cr_Reg(21 downto 14)); + + + ------------------------------------------------------------------- + -- DBUF + ------------------------------------------------------------------- + U_RAMZ : entity work.RAMZ + generic map + ( + RAMADDR_W => 7, + RAMDATA_W => 12 + ) + port map + ( + d => dbuf_data, + waddr => dbuf_waddr, + raddr => dbuf_raddr, + we => dbuf_we, + clk => CLK, + + q => dbuf_q + ); + + dbuf_data <= fifo1_q; + dbuf_we <= fifo1_q_dval; + dbuf_waddr <= (not zz_buf_sel) & std_logic_vector(yw_cnt & xw_cnt); + dbuf_raddr <= zz_buf_sel & zz_rd_addr; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/mdct/DCT1D.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/DCT1D.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/DCT1D.vhd (revision 48) @@ -0,0 +1,334 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT1D +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : DCT1D.VHD +-- Created : Sat Mar 5 7:37 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : 1D Discrete Cosine Transform (1st stage) +-- +-------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.all; + +library WORK; + use WORK.MDCT_PKG.all; + +-------------------------------------------------------------------------------- +-- ENTITY +-------------------------------------------------------------------------------- +entity DCT1D is + port( + clk : in STD_LOGIC; + rst : in std_logic; + dcti : in std_logic_vector(IP_W-1 downto 0); + idv : in STD_LOGIC; + romedatao : in T_ROM1DATAO; + romodatao : in T_ROM1DATAO; + + odv : out STD_LOGIC; + dcto : out std_logic_vector(OP_W-1 downto 0); + romeaddro : out T_ROM1ADDRO; + romoaddro : out T_ROM1ADDRO; + ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + ramwe : out STD_LOGIC; + wmemsel : out STD_LOGIC + ); +end DCT1D; + +-------------------------------------------------------------------------------- +-- ARCHITECTURE +-------------------------------------------------------------------------------- +architecture RTL of DCT1D is + + type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0); + + signal databuf_reg : INPUT_DATA; + signal latchbuf_reg : INPUT_DATA; + signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal ramwe_s : STD_LOGIC; + signal wmemsel_reg : STD_LOGIC; + signal stage2_reg : STD_LOGIC; + signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0); + signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + + signal even_not_odd : std_logic; + signal even_not_odd_d1 : std_logic; + signal even_not_odd_d2 : std_logic; + signal even_not_odd_d3 : std_logic; + signal ramwe_d1 : STD_LOGIC; + signal ramwe_d2 : STD_LOGIC; + signal ramwe_d3 : STD_LOGIC; + signal ramwe_d4 : STD_LOGIC; + signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal wmemsel_d1 : STD_LOGIC; + signal wmemsel_d2 : STD_LOGIC; + signal wmemsel_d3 : STD_LOGIC; + signal wmemsel_d4 : STD_LOGIC; + signal romedatao_d1 : T_ROM1DATAO; + signal romodatao_d1 : T_ROM1DATAO; + signal romedatao_d2 : T_ROM1DATAO; + signal romodatao_d2 : T_ROM1DATAO; + signal romedatao_d3 : T_ROM1DATAO; + signal romodatao_d3 : T_ROM1DATAO; + signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0); + signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0); + signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0); + signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0); + +begin + + ramwaddro <= ramwaddro_d4; + ramwe <= ramwe_d4; + ramdatai <= dcto_4(DA_W-1 downto 12); + wmemsel <= wmemsel_d4; + + process(clk,rst) + begin + if rst = '1' then + inpcnt_reg <= (others => '0'); + latchbuf_reg <= (others => (others => '0')); + databuf_reg <= (others => (others => '0')); + stage2_reg <= '0'; + stage2_cnt_reg <= (others => '1'); + ramwe_s <= '0'; + ramwaddro_s <= (others => '0'); + col_reg <= (others => '0'); + row_reg <= (others => '0'); + wmemsel_reg <= '0'; + col_2_reg <= (others => '0'); + elsif clk = '1' and clk'event then + stage2_reg <= '0'; + ramwe_s <= '0'; + + -------------------------------- + -- 1st stage + -------------------------------- + if idv = '1' then + + inpcnt_reg <= inpcnt_reg + 1; + + -- right shift input data + latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1); + latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT; + + if inpcnt_reg = N-1 then + -- after this sum databuf_reg is in range of -256 to 254 (min to max) + databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT); + databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7); + databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6); + databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5); + databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT); + databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7); + databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6); + databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5); + stage2_reg <= '1'; + end if; + end if; + -------------------------------- + + -------------------------------- + -- 2nd stage + -------------------------------- + if stage2_cnt_reg < N then + + stage2_cnt_reg <= stage2_cnt_reg + 1; + + -- write RAM + ramwe_s <= '1'; + -- reverse col/row order for transposition purpose + ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg); + -- increment column counter + col_reg <= col_reg + 1; + col_2_reg <= col_2_reg + 1; + + -- finished processing one input row + if col_reg = 0 then + row_reg <= row_reg + 1; + -- switch to 2nd memory + if row_reg = N - 1 then + wmemsel_reg <= not wmemsel_reg; + col_reg <= (others => '0'); + end if; + end if; + + end if; + + if stage2_reg = '1' then + stage2_cnt_reg <= (others => '0'); + col_reg <= (0=>'1',others => '0'); + col_2_reg <= (others => '0'); + end if; + ---------------------------------- + + + end if; + end process; + + -- output data pipeline + p_data_out_pipe : process(CLK, RST) + begin + if RST = '1' then + even_not_odd <= '0'; + even_not_odd_d1 <= '0'; + even_not_odd_d2 <= '0'; + even_not_odd_d3 <= '0'; + ramwe_d1 <= '0'; + ramwe_d2 <= '0'; + ramwe_d3 <= '0'; + ramwe_d4 <= '0'; + ramwaddro_d1 <= (others => '0'); + ramwaddro_d2 <= (others => '0'); + ramwaddro_d3 <= (others => '0'); + ramwaddro_d4 <= (others => '0'); + wmemsel_d1 <= '0'; + wmemsel_d2 <= '0'; + wmemsel_d3 <= '0'; + wmemsel_d4 <= '0'; + dcto_1 <= (others => '0'); + dcto_2 <= (others => '0'); + dcto_3 <= (others => '0'); + dcto_4 <= (others => '0'); + elsif CLK'event and CLK = '1' then + even_not_odd <= stage2_cnt_reg(0); + even_not_odd_d1 <= even_not_odd; + even_not_odd_d2 <= even_not_odd_d1; + even_not_odd_d3 <= even_not_odd_d2; + ramwe_d1 <= ramwe_s; + ramwe_d2 <= ramwe_d1; + ramwe_d3 <= ramwe_d2; + ramwe_d4 <= ramwe_d3; + ramwaddro_d1 <= ramwaddro_s; + ramwaddro_d2 <= ramwaddro_d1; + ramwaddro_d3 <= ramwaddro_d2; + ramwaddro_d4 <= ramwaddro_d3; + wmemsel_d1 <= wmemsel_reg; + wmemsel_d2 <= wmemsel_d1; + wmemsel_d3 <= wmemsel_d2; + wmemsel_d4 <= wmemsel_d3; + + if even_not_odd = '0' then + dcto_1 <= STD_LOGIC_VECTOR(RESIZE + (RESIZE(SIGNED(romedatao(0)),DA_W) + + (RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') + + (RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"), + DA_W)); + else + dcto_1 <= STD_LOGIC_VECTOR(RESIZE + (RESIZE(SIGNED(romodatao(0)),DA_W) + + (RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') + + (RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"), + DA_W)); + end if; + + if even_not_odd_d1 = '0' then + dcto_2 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_1) + + (RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") + + (RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"), + DA_W)); + else + dcto_2 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_1) + + (RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") + + (RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"), + DA_W)); + end if; + + if even_not_odd_d2 = '0' then + dcto_3 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_2) + + (RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") + + (RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"), + DA_W)); + else + dcto_3 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_2) + + (RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") + + (RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"), + DA_W)); + end if; + + if even_not_odd_d3 = '0' then + dcto_4 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_3) + + (RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") - + (RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"), + DA_W)); + else + dcto_4 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_3) + + (RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") - + (RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"), + DA_W)); + end if; + end if; + end process; + + -- read precomputed MAC results from LUT + p_romaddr : process(CLK, RST) + begin + if RST = '1' then + romeaddro <= (others => (others => '0')); + romoaddro <= (others => (others => '0')); + elsif CLK'event and CLK = '1' then + for i in 0 to 8 loop + -- even + romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & + databuf_reg(0)(i) & + databuf_reg(1)(i) & + databuf_reg(2)(i) & + databuf_reg(3)(i); + -- odd + romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & + databuf_reg(4)(i) & + databuf_reg(5)(i) & + databuf_reg(6)(i) & + databuf_reg(7)(i); + end loop; + end if; + end process; + + p_romdatao_d1 : process(CLK, RST) + begin + if RST = '1' then + romedatao_d1 <= (others => (others => '0')); + romodatao_d1 <= (others => (others => '0')); + romedatao_d2 <= (others => (others => '0')); + romodatao_d2 <= (others => (others => '0')); + romedatao_d3 <= (others => (others => '0')); + romodatao_d3 <= (others => (others => '0')); + elsif CLK'event and CLK = '1' then + romedatao_d1 <= romedatao; + romodatao_d1 <= romodatao; + romedatao_d2 <= romedatao_d1; + romodatao_d2 <= romodatao_d1; + romedatao_d3 <= romedatao_d2; + romodatao_d3 <= romodatao_d2; + end if; + end process; + +end RTL; +-------------------------------------------------------------------------------- Index: mkjpeg/branches/16rgb/trunk/design/mdct/RAM.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/RAM.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/RAM.VHD (revision 48) @@ -0,0 +1,79 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- -- +-- Title : RAM -- +-- Design : MDCT -- +-- Author : Michal Krepa -- -- -- +-- -- +-------------------------------------------------------------------------------- +-- +-- File : RAM.VHD +-- Created : Sat Mar 5 7:37 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : RAM memory simulation model +-- +-------------------------------------------------------------------------------- + +-- 5:3 row select +-- 2:0 col select + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.all; + +library WORK; + use WORK.MDCT_PKG.all; + +entity RAM is + port ( + d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + waddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + we : in STD_LOGIC; + clk : in STD_LOGIC; + + q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0) + ); +end RAM; + +architecture RTL of RAM is + type mem_type is array ((2**RAMADRR_W)-1 downto 0) of + STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal mem : mem_type; + signal read_addr : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + +begin + + ------------------------------------------------------------------------------- + q_sg: + ------------------------------------------------------------------------------- + q <= mem(TO_INTEGER(UNSIGNED(read_addr))); + + ------------------------------------------------------------------------------- + read_proc: -- register read address + ------------------------------------------------------------------------------- + process (clk) + begin + if clk = '1' and clk'event then + read_addr <= raddr; + end if; + end process; + + ------------------------------------------------------------------------------- + write_proc: --write access + ------------------------------------------------------------------------------- + process (clk) begin + if clk = '1' and clk'event then + if we = '1' then + mem(TO_INTEGER(UNSIGNED(waddr))) <= d; + end if; + end if; + end process; + +end RTL; \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/mdct/DCT2D.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/DCT2D.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/DCT2D.VHD (revision 48) @@ -0,0 +1,357 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT2D +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : DCT2D.VHD +-- Created : Sat Mar 28 22:32 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : 1D Discrete Cosine Transform (second stage) +-- +-------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use ieee.numeric_std.all; + +library WORK; + use WORK.MDCT_PKG.all; + +entity DCT2D is + port( + clk : in STD_LOGIC; + rst : in std_logic; + romedatao : in T_ROM2DATAO; + romodatao : in T_ROM2DATAO; + ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + dataready : in STD_LOGIC; + + odv : out STD_LOGIC; + dcto : out std_logic_vector(OP_W-1 downto 0); + romeaddro : out T_ROM2ADDRO; + romoaddro : out T_ROM2ADDRO; + ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + rmemsel : out STD_LOGIC; + datareadyack : out STD_LOGIC + + ); +end DCT2D; + +architecture RTL of DCT2D is + + type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0); + + signal databuf_reg : input_data2; + signal latchbuf_reg : input_data2; + signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rmemsel_reg : STD_LOGIC; + signal stage1_reg : STD_LOGIC; + signal stage2_reg : STD_LOGIC; + signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0); + signal dataready_2_reg : STD_LOGIC; + signal even_not_odd : std_logic; + signal even_not_odd_d1 : std_logic; + signal even_not_odd_d2 : std_logic; + signal even_not_odd_d3 : std_logic; + signal even_not_odd_d4 : std_logic; + signal odv_d0 : std_logic; + signal odv_d1 : std_logic; + signal odv_d2 : std_logic; + signal odv_d3 : std_logic; + signal odv_d4 : std_logic; + signal odv_d5 : std_logic; + signal dcto_1 : std_logic_vector(DA2_W-1 downto 0); + signal dcto_2 : std_logic_vector(DA2_W-1 downto 0); + signal dcto_3 : std_logic_vector(DA2_W-1 downto 0); + signal dcto_4 : std_logic_vector(DA2_W-1 downto 0); + signal dcto_5 : std_logic_vector(DA2_W-1 downto 0); + signal romedatao_d1 : T_ROM2DATAO; + signal romodatao_d1 : T_ROM2DATAO; + signal romedatao_d2 : T_ROM2DATAO; + signal romodatao_d2 : T_ROM2DATAO; + signal romedatao_d3 : T_ROM2DATAO; + signal romodatao_d3 : T_ROM2DATAO; + signal romedatao_d4 : T_ROM2DATAO; + signal romodatao_d4 : T_ROM2DATAO; +begin + + ramraddro_sg: + ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg); + + rmemsel_sg: + rmemsel <= rmemsel_reg; + + process(clk,rst) + begin + if rst = '1' then + stage2_cnt_reg <= (others => '1'); + rmemsel_reg <= '0'; + stage1_reg <= '0'; + stage2_reg <= '0'; + colram_reg <= (others => '0'); + rowram_reg <= (others => '0'); + col_reg <= (others => '0'); + row_reg <= (others => '0'); + latchbuf_reg <= (others => (others => '0')); + databuf_reg <= (others => (others => '0')); + odv_d0 <= '0'; + colr_reg <= (others => '0'); + rowr_reg <= (others => '0'); + dataready_2_reg <= '0'; + elsif clk='1' and clk'event then + stage2_reg <= '0'; + odv_d0 <= '0'; + datareadyack <= '0'; + dataready_2_reg <= dataready; + + ---------------------------------- + -- read DCT 1D to barrel shifer + ---------------------------------- + if stage1_reg = '1' then + + -- right shift input data + latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1); + latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1); + + colram_reg <= colram_reg + 1; + colr_reg <= colr_reg + 1; + + if colram_reg = N-2 then + rowr_reg <= rowr_reg + 1; + end if; + + if colram_reg = N-1 then + rowram_reg <= rowram_reg + 1; + if rowram_reg = N-1 then + stage1_reg <= '0'; + colr_reg <= (others => '0'); + -- release memory + rmemsel_reg <= not rmemsel_reg; + end if; + + -- after this sum databuf_reg is in range of -256 to 254 (min to max) + databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1); + databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7); + databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6); + databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5); + databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1); + databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7); + databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6); + databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5); + + -- 8 point input latched + stage2_reg <= '1'; + end if; + end if; + + -------------------------------- + -- 2nd stage + -------------------------------- + if stage2_cnt_reg < N then + stage2_cnt_reg <= stage2_cnt_reg + 1; + + -- output data valid + odv_d0 <= '1'; + + -- increment column counter + col_reg <= col_reg + 1; + + -- finished processing one input row + if col_reg = N - 1 then + row_reg <= row_reg + 1; + end if; + end if; + + if stage2_reg = '1' then + stage2_cnt_reg <= (others => '0'); + col_reg <= (0=>'1',others => '0'); + end if; + -------------------------------- + + ---------------------------------- + -- wait for new data + ---------------------------------- + -- one of ram buffers has new data, process it + if dataready = '1' and dataready_2_reg = '0' then + stage1_reg <= '1'; + -- to account for 1T RAM delay, increment RAM address counter + colram_reg <= (others => '0'); + colr_reg <= (0=>'1',others => '0'); + datareadyack <= '1'; + end if; + ---------------------------------- + + + end if; + end process; + + p_data_pipe : process(CLK, RST) + begin + if RST = '1' then + even_not_odd <= '0'; + even_not_odd_d1 <= '0'; + even_not_odd_d2 <= '0'; + even_not_odd_d3 <= '0'; + even_not_odd_d4 <= '0'; + odv_d1 <= '0'; + odv_d2 <= '0'; + odv_d3 <= '0'; + odv_d4 <= '0'; + odv_d5 <= '0'; + dcto_1 <= (others => '0'); + dcto_2 <= (others => '0'); + dcto_3 <= (others => '0'); + dcto_4 <= (others => '0'); + dcto_5 <= (others => '0'); + elsif CLK'event and CLK = '1' then + even_not_odd <= stage2_cnt_reg(0); + even_not_odd_d1 <= even_not_odd; + even_not_odd_d2 <= even_not_odd_d1; + even_not_odd_d3 <= even_not_odd_d2; + even_not_odd_d4 <= even_not_odd_d3; + odv_d1 <= odv_d0; + odv_d2 <= odv_d1; + odv_d3 <= odv_d2; + odv_d4 <= odv_d3; + odv_d5 <= odv_d4; + + if even_not_odd = '0' then + dcto_1 <= STD_LOGIC_VECTOR(RESIZE + (RESIZE(SIGNED(romedatao(0)),DA2_W) + + (RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') + + (RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"), + DA2_W)); + else + dcto_1 <= STD_LOGIC_VECTOR(RESIZE + (RESIZE(SIGNED(romodatao(0)),DA2_W) + + (RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') + + (RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"), + DA2_W)); + end if; + + if even_not_odd_d1 = '0' then + dcto_2 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_1) + + (RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") + + (RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"), + DA2_W)); + else + dcto_2 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_1) + + (RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") + + (RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"), + DA2_W)); + end if; + + if even_not_odd_d2 = '0' then + dcto_3 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_2) + + (RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") + + (RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"), + DA2_W)); + else + dcto_3 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_2) + + (RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") + + (RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"), + DA2_W)); + end if; + + if even_not_odd_d3 = '0' then + dcto_4 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_3) + + (RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") + + (RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"), + DA2_W)); + else + dcto_4 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_3) + + (RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") + + (RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"), + DA2_W)); + end if; + + if even_not_odd_d4 = '0' then + dcto_5 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_4) + + (RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") - + (RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"), + DA2_W)); + else + dcto_5 <= STD_LOGIC_VECTOR(RESIZE + (signed(dcto_4) + + (RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") - + (RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"), + DA2_W)); + end if; + end if; + end process; + + dcto <= dcto_5(DA2_W-1 downto 12); + odv <= odv_d5; + + p_romaddr : process(CLK, RST) + begin + if RST = '1' then + romeaddro <= (others => (others => '0')); + romoaddro <= (others => (others => '0')); + elsif CLK'event and CLK = '1' then + for i in 0 to 10 loop + -- read precomputed MAC results from LUT + romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & + databuf_reg(0)(i) & + databuf_reg(1)(i) & + databuf_reg(2)(i) & + databuf_reg(3)(i); + -- odd + romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & + databuf_reg(4)(i) & + databuf_reg(5)(i) & + databuf_reg(6)(i) & + databuf_reg(7)(i); + end loop; + end if; + end process; + + p_romdatao_dly : process(CLK, RST) + begin + if RST = '1' then + romedatao_d1 <= (others => (others => '0')); + romodatao_d1 <= (others => (others => '0')); + romedatao_d2 <= (others => (others => '0')); + romodatao_d2 <= (others => (others => '0')); + romedatao_d3 <= (others => (others => '0')); + romodatao_d3 <= (others => (others => '0')); + romedatao_d4 <= (others => (others => '0')); + romodatao_d4 <= (others => (others => '0')); + elsif CLK'event and CLK = '1' then + romedatao_d1 <= romedatao; + romodatao_d1 <= romodatao; + romedatao_d2 <= romedatao_d1; + romodatao_d2 <= romodatao_d1; + romedatao_d3 <= romedatao_d2; + romodatao_d3 <= romodatao_d2; + romedatao_d4 <= romedatao_d3; + romodatao_d4 <= romodatao_d3; + end if; + end process; + +end RTL; +-------------------------------------------------------------------------------- + Index: mkjpeg/branches/16rgb/trunk/design/mdct/ROME.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/ROME.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/ROME.VHD (revision 48) @@ -0,0 +1,133 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : ROME.VHD +-- Created : Sat Mar 5 7:37 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : ROM for DCT matrix constant cosine coefficients (even part) +-- +-------------------------------------------------------------------------------- + +-- 5:0 +-- 5:4 = select matrix row (1 out of 4) +-- 3:0 = select precomputed MAC ( 1 out of 16) + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.STD_LOGIC_arith.all; + use WORK.MDCT_PKG.all; + +entity ROME is + port( + addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; + + datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) + ); + +end ROME; + +architecture RTL of ROME is + + type ROM_TYPE is array (0 to (2**ROMADDR_W)-1) + of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); + constant rom : ROM_TYPE := + ( + (others => '0'), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP+AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ), + + + (others => '0'), + conv_std_logic_vector( BM,ROMDATA_W ), + conv_std_logic_vector( CM,ROMDATA_W ), + conv_std_logic_vector( CM+BM,ROMDATA_W ), + conv_std_logic_vector( CP,ROMDATA_W ), + conv_std_logic_vector( CP+BM,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( BM,ROMDATA_W ), + conv_std_logic_vector( BP,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( BP+CM,ROMDATA_W ), + conv_std_logic_vector( CM,ROMDATA_W ), + conv_std_logic_vector( BP+CP,ROMDATA_W ), + conv_std_logic_vector( CP,ROMDATA_W ), + conv_std_logic_vector( BP,ROMDATA_W ), + (others => '0'), + + + (others => '0'), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AM,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( AM,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( AM+AM,ROMDATA_W ), + conv_std_logic_vector( AM,ROMDATA_W ), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AP+AP,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( AP,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( AP,ROMDATA_W ), + conv_std_logic_vector( AM,ROMDATA_W ), + (others => '0'), + + + (others => '0'), + conv_std_logic_vector( CM,ROMDATA_W ), + conv_std_logic_vector( BP,ROMDATA_W ), + conv_std_logic_vector( BP+CM,ROMDATA_W ), + conv_std_logic_vector( BM,ROMDATA_W ), + conv_std_logic_vector( BM+CM,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( CM,ROMDATA_W ), + conv_std_logic_vector( CP,ROMDATA_W ), + (others => '0'), + conv_std_logic_vector( CP+BP,ROMDATA_W ), + conv_std_logic_vector( BP,ROMDATA_W ), + conv_std_logic_vector( CP+BM,ROMDATA_W ), + conv_std_logic_vector( BM,ROMDATA_W ), + conv_std_logic_vector( CP,ROMDATA_W ), + (others => '0') + ); + +begin + + + process(clk) + begin + if clk = '1' and clk'event then + datao <= rom(CONV_INTEGER(UNSIGNED(addr)) ); + end if; + end process; + +end RTL; + + + Index: mkjpeg/branches/16rgb/trunk/design/mdct/DBUFCTL.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/DBUFCTL.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/DBUFCTL.VHD (revision 48) @@ -0,0 +1,73 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DBUFCTL +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : DBUFCTL.VHD +-- Created : Thu Mar 30 22:19 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : Double buffer memory controller +-- +-------------------------------------------------------------------------------- +library IEEE; + use IEEE.STD_LOGIC_1164.all; + +library WORK; + use WORK.MDCT_PKG.all; + +entity DBUFCTL is + port( + clk : in STD_LOGIC; + rst : in STD_LOGIC; + wmemsel : in STD_LOGIC; + rmemsel : in STD_LOGIC; + datareadyack : in STD_LOGIC; + + memswitchwr : out STD_LOGIC; + memswitchrd : out STD_LOGIC; + dataready : out STD_LOGIC + ); +end DBUFCTL; + +architecture RTL of DBUFCTL is + + signal memswitchwr_reg : STD_LOGIC; + signal memswitchrd_reg : STD_LOGIC; + +begin + + memswitchwr <= memswitchwr_reg; + memswitchrd <= memswitchrd_reg; + + memswitchrd_reg <= rmemsel; + + MEM_SWITCH : process(clk,rst) + begin + if rst = '1' then + memswitchwr_reg <= '0'; -- initially mem 1 is selected + dataready <= '0'; + elsif clk = '1' and clk'event then + memswitchwr_reg <= wmemsel; + + if wmemsel /= memswitchwr_reg then + dataready <= '1'; + end if; + + if datareadyack = '1' then + dataready <= '0'; + end if; + end if; + end process; + +end RTL; +-------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/mdct/MDCT.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/MDCT.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/MDCT.VHD (revision 48) @@ -0,0 +1,219 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006-2009 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT +-- Design : MDCT Core +-- Author : Michal Krepa +-- Company : None +-- +-------------------------------------------------------------------------------- +-- +-- File : MDCT.VHD +-- Created : Sat Feb 25 16:12 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : Discrete Cosine Transform - chip top level (w/ memories) +-- +-------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + +library WORK; + use WORK.MDCT_PKG.all; + + +entity MDCT is + port( + clk : in STD_LOGIC; + rst : in std_logic; + dcti : in std_logic_vector(IP_W-1 downto 0); + idv : in STD_LOGIC; + + odv : out STD_LOGIC; + dcto : out std_logic_vector(COE_W-1 downto 0); + -- debug + odv1 : out STD_LOGIC; + dcto1 : out std_logic_vector(OP_W-1 downto 0) + + ); +end MDCT; + +architecture RTL of MDCT is + + signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); + signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal ramwe_s : STD_LOGIC; + + signal romedatao_s : T_ROM1DATAO; + signal romodatao_s : T_ROM1DATAO; + signal romeaddro_s : T_ROM1ADDRO; + signal romoaddro_s : T_ROM1ADDRO; + + signal rome2datao_s : T_ROM2DATAO; + signal romo2datao_s : T_ROM2DATAO; + signal rome2addro_s : T_ROM2ADDRO; + signal romo2addro_s : T_ROM2ADDRO; + + signal odv2_s : STD_LOGIC; + signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0); + signal trigger2_s : STD_LOGIC; + signal trigger1_s : STD_LOGIC; + signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); + signal ramwe1_s : STD_LOGIC; + signal ramwe2_s : STD_LOGIC; + signal memswitchrd_s : STD_LOGIC; + signal memswitchwr_s : STD_LOGIC; + signal wmemsel_s : STD_LOGIC; + signal rmemsel_s : STD_LOGIC; + signal dataready_s : STD_LOGIC; + signal datareadyack_s : STD_LOGIC; + +begin + +------------------------------ +-- 1D DCT port map +------------------------------ +U_DCT1D : entity work.DCT1D + port map( + clk => clk, + rst => rst, + dcti => dcti, + idv => idv, + romedatao => romedatao_s, + romodatao => romodatao_s, + + odv => odv1, + dcto => dcto1, + romeaddro => romeaddro_s, + romoaddro => romoaddro_s, + ramwaddro => ramwaddro_s, + ramdatai => ramdatai_s, + ramwe => ramwe_s, + wmemsel => wmemsel_s + ); + +------------------------------ +-- 1D DCT port map +------------------------------ +U_DCT2D : entity work.DCT2D + port map( + clk => clk, + rst => rst, + romedatao => rome2datao_s, + romodatao => romo2datao_s, + ramdatao => ramdatao_s, + dataready => dataready_s, + + odv => odv, + dcto => dcto, + romeaddro => rome2addro_s, + romoaddro => romo2addro_s, + ramraddro => ramraddro_s, + rmemsel => rmemsel_s, + datareadyack => datareadyack_s + ); + +------------------------------ +-- RAM1 port map +------------------------------ +U1_RAM : entity work.RAM + port map ( + d => ramdatai_s, + waddr => ramwaddro_s, + raddr => ramraddro_s, + we => ramwe1_s, + clk => clk, + + q => ramdatao1_s + ); + +------------------------------ +-- RAM2 port map +------------------------------ +U2_RAM : entity work.RAM + port map ( + d => ramdatai_s, + waddr => ramwaddro_s, + raddr => ramraddro_s, + we => ramwe2_s, + clk => clk, + + q => ramdatao2_s + ); + +-- double buffer switch +ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0'; +ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0'; +ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s; + +------------------------------ +-- DBUFCTL +------------------------------ +U_DBUFCTL : entity work.DBUFCTL + port map( + clk => clk, + rst => rst, + wmemsel => wmemsel_s, + rmemsel => rmemsel_s, + datareadyack => datareadyack_s, + + memswitchwr => memswitchwr_s, + memswitchrd => memswitchrd_s, + dataready => dataready_s + ); + +------------------------------ +-- 1st stage ROMs +------------------------------ + +G_ROM_ST1 : for i in 0 to 8 generate + U1_ROME : entity work.ROME + port map( + addr => romeaddro_s(i), + clk => clk, + + datao => romedatao_s(i) + ); + + U1_ROMO : entity work.ROMO + port map( + addr => romoaddro_s(i), + clk => clk, + + datao => romodatao_s(i) + ); +end generate G_ROM_ST1; + +------------------------------ +-- 2nd stage ROMs +------------------------------ +G_ROM_ST2 : for i in 0 to 10 generate + U2_ROME : entity work.ROME + port map( + addr => rome2addro_s(i), + clk => clk, + + datao => rome2datao_s(i) + ); + + U2_ROMO : entity work.ROMO + port map( + addr => romo2addro_s(i), + clk => clk, + + datao => romo2datao_s(i) + ); + +end generate G_ROM_ST2; + +end RTL; Index: mkjpeg/branches/16rgb/trunk/design/mdct/MDCT_PKG.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/MDCT_PKG.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/MDCT_PKG.vhd (revision 48) @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : MDCT_PKG +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : MDCT_PKG.VHD +-- Created : Sat Mar 5 2006 +-- +-------------------------------------------------------------------------------- +-- +-- Description : Package for MDCT core +-- +-------------------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use ieee.numeric_std.all; + +package MDCT_PKG is + + constant IP_W : INTEGER := 8; + constant OP_W : INTEGER := 12; + constant N : INTEGER := 8; + constant COE_W : INTEGER := 12; + constant ROMDATA_W : INTEGER := COE_W+2; + constant ROMADDR_W : INTEGER := 6; + constant RAMDATA_W : INTEGER := 10; + constant RAMADRR_W : INTEGER := 6; + constant COL_MAX : INTEGER := N-1; + constant ROW_MAX : INTEGER := N-1; + constant LEVEL_SHIFT : INTEGER := 128; + constant DA_W : INTEGER := ROMDATA_W+IP_W; + constant DA2_W : INTEGER := DA_W+2; + -- 2's complement numbers + + constant AP : INTEGER := 1448; + constant BP : INTEGER := 1892; + constant CP : INTEGER := 784; + constant DP : INTEGER := 2009; + constant EP : INTEGER := 1703; + constant FP : INTEGER := 1138; + constant GP : INTEGER := 400; + constant AM : INTEGER := -1448; + constant BM : INTEGER := -1892; + constant CM : INTEGER := -784; + constant DM : INTEGER := -2009; + constant EM : INTEGER := -1703; + constant FM : INTEGER := -1138; + constant GM : INTEGER := -400; + + type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); + type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + + type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); + type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + + +end MDCT_PKG; \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/mdct/ROMO.VHD =================================================================== --- mkjpeg/branches/16rgb/trunk/design/mdct/ROMO.VHD (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/mdct/ROMO.VHD (revision 48) @@ -0,0 +1,132 @@ +-------------------------------------------------------------------------------- +-- -- +-- V H D L F I L E -- +-- COPYRIGHT (C) 2006 -- +-- -- +-------------------------------------------------------------------------------- +-- +-- Title : DCT +-- Design : MDCT Core +-- Author : Michal Krepa +-- +-------------------------------------------------------------------------------- +-- +-- File : ROMO.VHD +-- Created : Sat Mar 5 7:37 2006 +-- Modified : Dez. 30 2008 - Andreas Bergmann +-- Libs and Typeconversion fixed due Xilinx Synthesis errors +-- +-------------------------------------------------------------------------------- +-- +-- Description : ROM for DCT matrix constant cosine coefficients (odd part) +-- +-------------------------------------------------------------------------------- + +-- 5:0 +-- 5:4 = select matrix row (1 out of 4) +-- 3:0 = select precomputed MAC ( 1 out of 16) + +library IEEE; + use IEEE.STD_LOGIC_1164.all; +-- use ieee.STD_LOGIC_signed.all; + use IEEE.STD_LOGIC_arith.all; + use WORK.MDCT_PKG.all; + +entity ROMO is + port( + addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); + clk : in STD_LOGIC; + + datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0) + ); + +end ROMO; + +architecture RTL of ROMO is + type ROM_TYPE is array (0 to 2**ROMADDR_W-1) + of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); + constant rom : ROM_TYPE := + ( + (others => '0'), + conv_std_logic_vector( GP,ROMDATA_W ), + conv_std_logic_vector( FP,ROMDATA_W ), + conv_std_logic_vector( FP+GP,ROMDATA_W ), + conv_std_logic_vector( EP,ROMDATA_W ), + conv_std_logic_vector( EP+GP,ROMDATA_W ), + conv_std_logic_vector( EP+FP,ROMDATA_W ), + conv_std_logic_vector( EP+FP+GP,ROMDATA_W ), + conv_std_logic_vector( DP,ROMDATA_W ), + conv_std_logic_vector( DP+GP,ROMDATA_W ), + conv_std_logic_vector( DP+FP,ROMDATA_W ), + conv_std_logic_vector( DP+FP+GP,ROMDATA_W ), + conv_std_logic_vector( DP+EP,ROMDATA_W ), + conv_std_logic_vector( DP+EP+GP,ROMDATA_W ), + conv_std_logic_vector( DP+EP+FP,ROMDATA_W ), + conv_std_logic_vector( DP+EP+FP+GP,ROMDATA_W ), + + (others => '0'), + conv_std_logic_vector( FM,ROMDATA_W ), + conv_std_logic_vector( DM,ROMDATA_W ), + conv_std_logic_vector( DM+FM,ROMDATA_W ), + conv_std_logic_vector( GM,ROMDATA_W ), + conv_std_logic_vector( GM+FM,ROMDATA_W ), + conv_std_logic_vector( GM+DM,ROMDATA_W ), + conv_std_logic_vector( GM+DM+FM,ROMDATA_W ), + conv_std_logic_vector( EP,ROMDATA_W ), + conv_std_logic_vector( EP+FM,ROMDATA_W ), + conv_std_logic_vector( EP+DM,ROMDATA_W ), + conv_std_logic_vector( EP+DM+FM,ROMDATA_W ), + conv_std_logic_vector( EP+GM,ROMDATA_W ), + conv_std_logic_vector( EP+GM+FM,ROMDATA_W ), + conv_std_logic_vector( EP+GM+DM,ROMDATA_W ), + conv_std_logic_vector( EP+GM+DM+FM,ROMDATA_W ), + + (others => '0'), + conv_std_logic_vector( EP,ROMDATA_W ), + conv_std_logic_vector( GP,ROMDATA_W ), + conv_std_logic_vector( EP+GP,ROMDATA_W ), + conv_std_logic_vector( DM,ROMDATA_W ), + conv_std_logic_vector( DM+EP,ROMDATA_W ), + conv_std_logic_vector( DM+GP,ROMDATA_W ), + conv_std_logic_vector( DM+GP+EP,ROMDATA_W ), + conv_std_logic_vector( FP,ROMDATA_W ), + conv_std_logic_vector( FP+EP,ROMDATA_W ), + conv_std_logic_vector( FP+GP,ROMDATA_W ), + conv_std_logic_vector( FP+GP+EP,ROMDATA_W ), + conv_std_logic_vector( FP+DM,ROMDATA_W ), + conv_std_logic_vector( FP+DM+EP,ROMDATA_W ), + conv_std_logic_vector( FP+DM+GP,ROMDATA_W ), + conv_std_logic_vector( FP+DM+GP+EP,ROMDATA_W ), + + (others => '0'), + conv_std_logic_vector( DM,ROMDATA_W ), + conv_std_logic_vector( EP,ROMDATA_W ), + conv_std_logic_vector( EP+DM,ROMDATA_W ), + conv_std_logic_vector( FM,ROMDATA_W ), + conv_std_logic_vector( FM+DM,ROMDATA_W ), + conv_std_logic_vector( FM+EP,ROMDATA_W ), + conv_std_logic_vector( FM+EP+DM,ROMDATA_W ), + conv_std_logic_vector( GP,ROMDATA_W ), + conv_std_logic_vector( GP+DM,ROMDATA_W ), + conv_std_logic_vector( GP+EP,ROMDATA_W ), + conv_std_logic_vector( GP+EP+DM,ROMDATA_W ), + conv_std_logic_vector( GP+FM,ROMDATA_W ), + conv_std_logic_vector( GP+FM+DM,ROMDATA_W ), + conv_std_logic_vector( GP+FM+EP,ROMDATA_W ), + conv_std_logic_vector( GP+FM+EP+DM,ROMDATA_W ) + ); + +begin + + process(clk) + begin + if clk = '1' and clk'event then + datao <= rom( CONV_INTEGER(UNSIGNED(addr)) ); + end if; + end process; + +end RTL; + + + + Index: mkjpeg/branches/16rgb/trunk/design/outmux/OutMux.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/outmux/OutMux.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/outmux/OutMux.vhd (revision 48) @@ -0,0 +1,110 @@ +------------------------------------------------------------------------------- +-- File Name : OutMux.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : OutMux +-- +-- Content : Output Multiplexer +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090308: (MK): Initial Creation. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- LIBRARY/PACKAGE --------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- generic packages/libraries: +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- user packages/libraries: +------------------------------------------------------------------------------- +library work; + use work.JPEG_PKG.all; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ENTITY ------------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +entity OutMux is + port + ( + CLK : in std_logic; + RST : in std_logic; + -- CTRL + out_mux_ctrl : in std_logic; + + -- ByteStuffer + bs_ram_byte : in std_logic_vector(7 downto 0); + bs_ram_wren : in std_logic; + bs_ram_wraddr : in std_logic_vector(23 downto 0); + + -- JFIFGen + jfif_ram_byte : in std_logic_vector(7 downto 0); + jfif_ram_wren : in std_logic; + jfif_ram_wraddr : in std_logic_vector(23 downto 0); + + -- OUT RAM + ram_byte : out std_logic_vector(7 downto 0); + ram_wren : out std_logic; + ram_wraddr : out std_logic_vector(23 downto 0) + ); +end entity OutMux; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of OutMux is + + + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + + ------------------------------------------------------------------- + -- Mux + ------------------------------------------------------------------- + p_ctrl : process(CLK, RST) + begin + if RST = '1' then + ram_byte <= (others => '0'); + ram_wren <= '0'; + ram_wraddr <= (others => '0'); + elsif CLK'event and CLK = '1' then + if out_mux_ctrl = '0' then + ram_byte <= jfif_ram_byte; + ram_wren <= jfif_ram_wren; + ram_wraddr <= std_logic_vector(jfif_ram_wraddr); + else + ram_byte <= bs_ram_byte; + ram_wren <= bs_ram_wren; + ram_wraddr <= bs_ram_wraddr; + end if; + end if; + end process; + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/design/iramif/IRAMIF.vhd =================================================================== --- mkjpeg/branches/16rgb/trunk/design/iramif/IRAMIF.vhd (nonexistent) +++ mkjpeg/branches/16rgb/trunk/design/iramif/IRAMIF.vhd (revision 48) @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------- +-- File Name : IRamIF.vhd +-- +-- Project : JPEG_ENC +-- +-- Module : IRamIF +-- +-- Content : IMAGE RAM Interface +-- +-- Description : +-- +-- Spec. : +-- +-- Author : Michal Krepa +-- +------------------------------------------------------------------------------- +-- History : +-- 20090301: (MK): Initial Creation. +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity IRamIF is + port + ( + CLK : in std_logic; + RST : in std_logic; + + -- IMAGE RAM + iram_addr : out std_logic_vector(19 downto 0); + iram_rdata : in std_logic_vector(23 downto 0); + + -- FDCT + jpg_iram_rden : in std_logic; + jpg_iram_rdaddr : in std_logic_vector(31 downto 0); + jpg_iram_data : out std_logic_vector(23 downto 0) + ); +end entity IRamIF; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +----------------------------------- ARCHITECTURE ------------------------------ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +architecture RTL of IRamIF is + + +------------------------------------------------------------------------------- +-- Architecture: begin +------------------------------------------------------------------------------- +begin + + jpg_iram_data <= iram_rdata; + + ------------------------------------------------------------------- + -- + ------------------------------------------------------------------- + p_if : process(CLK, RST) + begin + if RST = '1' then + iram_addr <= (others => '0'); + elsif CLK'event and CLK = '1' then + -- host has access + iram_addr <= jpg_iram_rdaddr(iram_addr'range); + end if; + end process; + + +end architecture RTL; +------------------------------------------------------------------------------- +-- Architecture: end +------------------------------------------------------------------------------- \ No newline at end of file Index: mkjpeg/branches/16rgb/trunk/doc/JPEG.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: mkjpeg/branches/16rgb/trunk/doc/JPEG.doc =================================================================== --- mkjpeg/branches/16rgb/trunk/doc/JPEG.doc (nonexistent) +++ mkjpeg/branches/16rgb/trunk/doc/JPEG.doc (revision 48)

mkjpeg/branches/16rgb/trunk/doc/JPEG.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: mkjpeg/branches/16rgb/trunk/license-lgpl-3.0.txt =================================================================== --- mkjpeg/branches/16rgb/trunk/license-lgpl-3.0.txt (nonexistent) +++ mkjpeg/branches/16rgb/trunk/license-lgpl-3.0.txt (revision 48) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. Index: mkjpeg/branches/16rgb/trunk =================================================================== --- mkjpeg/branches/16rgb/trunk (nonexistent) +++ mkjpeg/branches/16rgb/trunk (revision 48)

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