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    /mkjpeg/branches/16rgb/trunk/design/common
    from Rev 42 to Rev 48
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Rev 42 → Rev 48

/JPEG_PKG.vhd
0,0 → 1,73
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_PKG
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_PKG.VHD
-- Created : Sat Mar 7 2009
--
--------------------------------------------------------------------------------
--
-- Description : Package for JPEG core
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package JPEG_PKG is
 
-- do not change, constant
constant C_HDR_SIZE : integer := 623;
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 1280;
 
-- 0=highest clock per pixel performance
-- 1=memory used by BUF_FIFO halved, speed performance reduced by circa 18%
constant C_MEMORY_OPTIMIZED : integer := 0;
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
y_cnt : unsigned(15 downto 0);
cmp_idx : unsigned(1 downto 0);
end record;
constant C_SM_SETTINGS : T_SM_SETTINGS :=
(
(others => '0'),
(others => '0'),
(others => '0')
);
function log2(n : natural) return natural;
end package JPEG_PKG;
 
package body JPEG_PKG is
 
-----------------------------------------------------------------------------
function log2(n : natural)
return natural is
begin
for i in 0 to 31 loop
if (2**i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
-----------------------------------------------------------------------------
 
end package body JPEG_PKG;
/SingleSM.vhd
0,0 → 1,125
-------------------------------------------------------------------------------
-- File Name : SingleSM.vhd
--
-- Project :
--
-- Module :
--
-- Content :
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
-------------------------------------------------------------------------------
-- History :
-- 20080301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity SingleSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- from/to SM(m)
start_i : in std_logic;
idle_o : out std_logic;
-- from/to SM(m+1)
idle_i : in std_logic;
start_o : out std_logic;
-- from/to processing block
pb_rdy_i : in std_logic;
pb_start_o : out std_logic;
-- state debug
fsm_o : out std_logic_vector(1 downto 0)
);
end entity SingleSM;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture SingleSM_rtl of SingleSM is
 
 
-------------------------------------------------------------------------------
-- Architecture: Signal definition.
-------------------------------------------------------------------------------
type T_STATE is (IDLE, WAIT_FOR_BLK_RDY, WAIT_FOR_BLK_IDLE);
signal state : T_STATE;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
fsm_o <= "00" when state = IDLE else
"01" when state = WAIT_FOR_BLK_RDY else
"10" when state = WAIT_FOR_BLK_IDLE else
"11";
 
------------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------------
p_fsm : process(CLK, RST)
begin
if RST = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
elsif CLK'event and CLK = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
case state is
when IDLE =>
idle_o <= '1';
-- this fsm is started
if start_i = '1' then
state <= WAIT_FOR_BLK_RDY;
-- start processing block associated with this FSM
pb_start_o <= '1';
idle_o <= '0';
end if;
when WAIT_FOR_BLK_RDY =>
-- wait until processing block completes
if pb_rdy_i = '1' then
-- wait until next FSM is idle before starting it
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
else
state <= WAIT_FOR_BLK_IDLE;
end if;
end if;
when WAIT_FOR_BLK_IDLE =>
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
end if;
when others =>
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
end case;
end if;
end process;
 
end architecture SingleSM_rtl;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
/FIFO.vhd
0,0 → 1,230
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMF is
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end RAMF;
 
architecture RTL of RAMF is
type mem_type is array ((2**RAMA_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
entity FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
);
end FIFO;
 
architecture RTL of FIFO is
 
signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenr : STD_LOGIC;
 
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
 
component RAMF
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end component;
begin
 
U_RAMF : RAMF
generic map (
RAMD_W => DATA_WIDTH,
RAMA_W => ADDR_WIDTH
)
port map (
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
we => ramenw,
clk => clk,
q => ramq
);
ramd <= datai;
ramwaddr <= waddr_reg;
ramenw <= wr_en_reg;
ramraddr <= raddr_reg;
 
ramenr <= '1';
datao <= ramq;
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= count_reg;
 
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = ZEROS_C or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + '1';
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + '1';
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - '1';
else
count_reg <= count_reg + '1';
end if;
end if;
end if;
end if;
end process;
 
end RTL;
/RAMZ.VHD
0,0 → 1,78
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RAMZ --
-- Design : MDCT --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : RAMZ.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMZ is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end RAMZ;
 
architecture RTL of RAMZ is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;

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