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/JPEG_TB.VHD
0,0 → 1,227
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_TB
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_TB.VHD
-- Created : Sun Mar 1 2009
--
--------------------------------------------------------------------------------
--
-- Description : Testbench top-level
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
library work;
use work.GPL_V2_Image_Pkg.ALL;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
 
entity JPEG_TB is
end JPEG_TB;
 
--**************************************************************************--
 
architecture TB of JPEG_TB is
type char_file is file of character;
 
file f_capture : text;
file f_capture_bin : char_file;
constant CAPTURE_ORAM : string := "OUT_RAM.txt";
constant CAPTURE_BIN : string := "test_out.jpg";
 
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal ram_rdaddr : std_logic_vector(23 downto 0);
signal ram_q : std_logic_vector(7 downto 0);
signal ram_byte : std_logic_vector(7 downto 0);
signal ram_wren : std_logic;
signal ram_wraddr : std_logic_vector(23 downto 0);
signal OPB_ABus : std_logic_vector(31 downto 0);
signal OPB_BE : std_logic_vector(3 downto 0);
signal OPB_DBus_in : std_logic_vector(31 downto 0);
signal OPB_RNW : std_logic;
signal OPB_select : std_logic;
signal OPB_DBus_out : std_logic_vector(31 downto 0);
signal OPB_XferAck : std_logic;
signal OPB_retry : std_logic;
signal OPB_toutSup : std_logic;
signal OPB_errAck : std_logic;
signal iram_waddr : std_logic_vector(19 downto 0);
signal iram_raddr : std_logic_vector(19 downto 0);
signal iram_wdata : std_logic_vector(23 downto 0);
signal iram_rdata : std_logic_vector(23 downto 0);
signal iram_wren : std_logic;
signal iram_rden : std_logic;
signal sim_done : std_logic;
signal iram_fifo_afull : std_logic;
signal outif_almost_full : std_logic;
signal count1 : unsigned(15 downto 0);
------------------------------
-- architecture begin
------------------------------
begin
 
 
 
 
------------------------------
-- CLKGEN map
------------------------------
U_ClkGen : entity work.ClkGen
port map
(
CLK => CLK,
RST => RST
);
------------------------------
-- HOST Bus Functional Model
------------------------------
U_HostBFM : entity work.HostBFM
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- IRAM
iram_wdata => iram_wdata,
iram_wren => iram_wren,
fifo_almost_full => iram_fifo_afull,
sim_done => sim_done
);
------------------------------
-- JPEG ENCODER
------------------------------
U_JpegEnc : entity work.JpegEnc
port map
(
CLK => CLK,
RST => RST,
 
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
 
-- IMAGE RAM
iram_wdata => iram_wdata,
iram_wren => iram_wren,
iram_fifo_afull => iram_fifo_afull,
 
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr,
outif_almost_full => outif_almost_full
);
-------------------------------------------------------------------
-- OUT RAM
-------------------------------------------------------------------
U_OUT_RAM : entity work.RAMSIM
generic map
(
RAMADDR_W => 18,
RAMDATA_W => 8
)
port map
(
d => ram_byte,
waddr => ram_wraddr(17 downto 0),
raddr => ram_rdaddr(17 downto 0),
we => ram_wren,
clk => CLK,
q => ram_q
);
p_capture : process
variable fLine : line;
variable fLine_bin : line;
begin
file_open(f_capture, CAPTURE_ORAM, write_mode);
file_open(f_capture_bin, CAPTURE_BIN, write_mode);
while sim_done /= '1' loop
wait until rising_edge(CLK);
if ram_wren = '1' then
hwrite(fLine, ram_byte);
write(fLine, string'(" "));
write(f_capture_bin, CHARACTER'VAL(to_integer(unsigned(ram_byte))));
end if;
end loop;
writeline(f_capture, fLine);
--writeline(f_capture_bin, fLine_bin);
file_close(f_capture);
file_close(f_capture_bin);
wait;
end process;
 
backpressure : process(CLK, RST)
begin
if RST = '1' then
outif_almost_full <= '0';
count1 <= (others => '0');
elsif CLK'event and CLK = '1' then
if count1 = 10000 then
count1 <= (others => '0');
outif_almost_full <= not outif_almost_full;
else
count1 <= count1 + 1;
end if;
end if;
end process;
 
end TB;
-----------------------------------
 
 
--**************************************************************************--
/HostBFM.vhd
0,0 → 1,453
-------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
library work;
use work.GPL_V2_Image_Pkg.ALL;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
use work.JPEG_PKG.all;
entity HostBFM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : out std_logic_vector(31 downto 0);
OPB_BE : out std_logic_vector(3 downto 0);
OPB_DBus_in : out std_logic_vector(31 downto 0);
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_DBus_out : in std_logic_vector(31 downto 0);
OPB_XferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_errAck : in std_logic;
-- HOST DATA
iram_wdata : out std_logic_vector(23 downto 0);
iram_wren : out std_logic;
fifo_almost_full : in std_logic;
sim_done : out std_logic
);
end entity HostBFM;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostBFM is
 
signal num_comps : integer;
signal addr_inc : integer := 0;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- code
-------------------------------------------------------------------
p_code : process
-----------------------------------------------------------------
-- HOST WRITE
-----------------------------------------------------------------
procedure host_write
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
constant C_WDATA : in unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_in : out std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
) is
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= std_logic_vector(C_WDATA);
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
severity note;
wait until rising_edge(clk);
end procedure host_write;
-----------------------------------------------------------------
-- HOST READ
-----------------------------------------------------------------
procedure host_read
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
variable RDATA : out unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_out : in std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
)
is
variable data_r : std_logic_vector(31 downto 0);
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '1';
OPB_BE <= X"F";
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
RDATA := unsigned(OPB_DBus_out);
data_r := OPB_DBus_out;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
severity note;
 
wait until rising_edge(clk);
end procedure host_read;
--------------------------------------
-- read text image data
--------------------------------------
procedure read_image is
file infile : TEXT open read_mode is "test.txt";
constant N : integer := 8;
constant MAX_COMPS : integer := 3;
variable inline : LINE;
variable tmp_int : INTEGER := 0;
variable y_size : INTEGER := 0;
variable x_size : INTEGER := 0;
variable matrix : I_MATRIX_TYPE;
variable x_blk_cnt : INTEGER := 0;
variable y_blk_cnt : INTEGER := 0;
variable n_lines_arr : N_LINES_TYPE;
variable line_n : INTEGER := 0;
variable pix_n : INTEGER := 0;
variable x_n : INTEGER := 0;
variable y_n : INTEGER := 0;
variable data_word : unsigned(31 downto 0);
variable image_line : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
variable x_cnt : integer;
variable data_word2 : unsigned(31 downto 0);
variable num_comps_v : integer;
begin
READLINE(infile,inline);
READ(inline,num_comps_v);
READLINE(infile,inline);
READ(inline,y_size);
READLINE(infile,inline);
READ(inline,x_size);
num_comps <= num_comps_v;
if y_size rem N > 0 then
assert false
report "ERROR: Image height dimension is not multiply of 8!"
severity Failure;
end if;
if x_size rem N > 0 then
assert false
report "ERROR: Image width dimension is not multiply of 8!"
severity Failure;
end if;
if x_size > C_MAX_LINE_WIDTH then
assert false
report "ERROR: Image width bigger than C_MAX_LINE_WIDTH in JPEG_PKG.VHD! " &
"Increase C_MAX_LINE_WIDTH accordingly"
severity Failure;
end if;
addr_inc <= 0;
-- image size
host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
iram_wren <= '0';
for y_n in 0 to y_size-1 loop
READLINE(infile,inline);
HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
x_cnt := 0;
for x_n in 0 to x_size-1 loop
data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
data_word2(7 downto 0) := data_word(23 downto 16);
data_word2(15 downto 8) := data_word(15 downto 8);
data_word2(23 downto 16) := data_word(7 downto 0);
iram_wren <= '0';
iram_wdata <= (others => 'X');
while(fifo_almost_full = '1') loop
wait until rising_edge(clk);
end loop;
--for i in 0 to 10 loop
-- wait until rising_edge(clk);
--end loop;
iram_wren <= '1';
iram_wdata <= std_logic_vector(data_word2(23 downto 0));
wait until rising_edge(clk);
x_cnt := x_cnt + num_comps*IP_W;
addr_inc <= addr_inc + 1;
end loop;
end loop;
iram_wren <= '0';
end read_image;
------------------
type ROMQ_TYPE is array (0 to 64-1)
of unsigned(7 downto 0);
constant qrom_lum : ROMQ_TYPE :=
(
-- 100%
--others => X"01"
-- 85%
--X"05", X"03", X"04", X"04",
--X"04", X"03", X"05", X"04",
--X"04", X"04", X"05", X"05",
--X"05", X"06", X"07", X"0C",
--X"08", X"07", X"07", X"07",
--X"07", X"0F", X"0B", X"0B",
--X"09", X"0C", X"11", X"0F",
--X"12", X"12", X"11", X"0F",
--X"11", X"11", X"13", X"16",
--X"1C", X"17", X"13", X"14",
--X"1A", X"15", X"11", X"11",
--X"18", X"21", X"18", X"1A",
--X"1D", X"1D", X"1F", X"1F",
--X"1F", X"13", X"17", X"22",
--X"24", X"22", X"1E", X"24",
--X"1C", X"1E", X"1F", X"1E"
-- others => X"01"
-- 75%
X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- 15 %
--X"35", X"25", X"28", X"2F",
--X"28", X"21", X"35", X"2F",
--X"2B", X"2F", X"3C", X"39",
--X"35", X"3F", X"50", X"85",
--X"57", X"50", X"49", X"49",
--X"50", X"A3", X"75", X"7B",
--X"61", X"85", X"C1", X"AA",
--X"CB", X"C8", X"BE", X"AA",
--X"BA", X"B7", X"D5", X"F0",
--X"FF", X"FF", X"D5", X"E2",
--X"FF", X"E6", X"B7", X"BA",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"CE", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF"
-- 50%
--X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
--X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
--X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
--X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
--X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
--X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
--X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
--X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
(
-- 50% for chrominance
--X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A",
--X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
--X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
-- 75% chrominance
X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32"
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- others => X"01"
);
variable data_read : unsigned(31 downto 0);
variable data_write : unsigned(31 downto 0);
variable addr : unsigned(31 downto 0);
 
------------------------------------------------------------------------------
-- BEGIN
------------------------------------------------------------------------------
begin
sim_done <= '0';
iram_wren <= '0';
while RST /= '0' loop
wait until rising_edge(clk);
end loop;
for i in 0 to 100 loop
wait until rising_edge(clk);
end loop;
host_read(CLK, X"0000_0000", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
host_read(CLK, X"0000_0004", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
-- write luminance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_lum(i);
addr := X"0000_0100" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
-- write chrominance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_chr(i);
addr := X"0000_0200" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
-- SOF & num_comps
host_write(CLK, X"0000_0000", data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
 
-- write BUF_FIFO with bitmap
read_image;
-- wait until JPEG encoding is done
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
while data_read /= 2 loop
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
sim_done <= '1';
wait;
end process;
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
/ClkGen.vhd
0,0 → 1,75
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ClkGen is
port (
CLK : out std_logic;
RST : out std_logic
);
end entity ClkGen;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture ClkGen_rtl of ClkGen is
 
 
constant CLOCK_PERIOD : time := 10 ns;
 
signal clk_s : std_logic := '0';
signal rst_s : std_logic := '0';
 
begin
 
-- Clock generator (50% duty cycle)
clk_gen: process
begin
clk_s <= '0';
wait for CLOCK_PERIOD/2;
clk_s <= '1';
wait for CLOCK_PERIOD/2;
end process clk_gen;
CLK <= clk_s;
 
reset_gen: process
begin
wait until rising_edge(clk_s);
rst_s <= '0';
wait until rising_edge(clk_s);
rst_s <= '1';
wait until rising_edge(clk_s);
rst_s <= '0';
wait;
end process reset_gen;
 
RST <= rst_s;
 
 
end architecture ClkGen_rtl;
/RAMSIM.VHD
0,0 → 1,77
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RAMZ --
-- Design : MDCT --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : RAMZ.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMSIM is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end RAMSIM;
 
architecture RTL of RAMSIM is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
begin
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk)
variable mem : mem_type;
begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) := d;
end if;
q <= mem(TO_INTEGER(UNSIGNED(raddr)));
end if;
end process;
end RTL;
/DCT_TROM.vhd
0,0 → 1,143
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT_TROM.VHD
-- Created : Sun Aug 27 18:09 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT quantizer matrix
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
entity DCT_TROM is
generic
(
ROMADDR_W : INTEGER := 9;
ROMDATA_W : INTEGER := 8
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end DCT_TROM;
 
architecture RTL of DCT_TROM is
 
type DCT_TROM_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER;
constant rom : DCT_TROM_TYPE :=
-- (
-- 16,11,10,16,24,40,51,61,
-- 12,12,14,19,26,58,60,55,
-- 14,13,16,24,40,57,69,56,
-- 14,17,22,29,51,87,80,62,
-- 18,22,37,56,68,109,103,77,
-- 24,35,55,64,81,104,113,92,
-- 49,64,78,87,103,121,120,101,
-- 72,92,95,98,112,100,103,99);
(
-280, 48, -20, 16, -26, 46, -42, 27,
45, 12, -34, -31, 11, -1, 16, -44,
-5, -63, -34, 36, 24, -27, 6, 1,
-12, 12, -8, 34, 5, 2, -12, 5,
22, -18, 15, 9, 12, -5, 1, -11,
1, 10, 6, 12, -15, -11, -5, -10,
5, -16, -4, 10, -1, -11, -5, -11,
-9, 11, 5, -3, -14, 4, 0, 0,
-213, -110, -78, 38, 32, 2, -1, -9,
28, 62, -7, -7, 22, -11, 5, 7,
85, -21, 33, -28, -37, 36, -11, 5,
-34, -18, 2, -24, 8, -12, -11, -8,
-13, 8, 39, -63, 27, 0, 1, -4,
-32, -4, -8, 24, -22, 11, 20, -4,
-12, 8, 43, 41, -16, -12, 4, -10,
-11, 14, 15, 7, -11, 9, -32, 0,
-225, 10, 25, 18, -30, 18, -14, 7,
44, -13, -93, -7, 20, -7, 5, -11,
-88, -53, 6, 36, 2, 1, 22, 2,
-46, -10, 17, 23, 16, 32, -7, 8,
66, 46, -10, -3, -17, 4, -5, -5,
-51, -18, -9, 6, 37, 15, 23, -4,
-21, 22, 44, 49, 25, 21, 1, -12,
25, 12, -5, -2, -19, -8, -15, 0,
390, -97, -41, -15, 20, 6, 0, 12,
4, -62, 21, -5, -31, -7, -3, -20,
-352, 44, 27, 36, 35, 6, 5, 10,
33, 48, 48, 14, -8, 14, 10, -9,
-95, 108, 5, 1, -11, -23, -20, 1,
54, -7, -43, -32, -15, 3, 9, 3,
-42, 57, -32, -19, -4, 6, 5, -3,
23, -31, -22, -1, 19, 24, 22, 1,
-14, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0,
-317, -9, 63, 17, 10, -26, 1, -11,
159, -41, -29, 42, -3, 21, 11, 1,
-6, -13, -18, 9, -19, 5, 15, 7,
-8, -9, -11, 16, -4, -1, -12, -3,
1, 15, -1, 3, -13, -8, 5, -1,
-9, 3, 2, 5, 7, -6, 12, -11,
-3, 1, -6, 1, -5, -4, 9, 6,
3, 7, 7, 3, -3, -5, -2, 0,
 
 
-404, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0,
-404, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0
 
 
);
 
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_SIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
/GPL_V2_Image_pkg.vhd
0,0 → 1,304
-----------------------------------------------------------------
-- Copyright (c) 1997 Ben Cohen. All rights reserved.
-- email: vhdlcohen@aol.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation; either version 2 of the License,
-- or (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
 
 
-- UPDATE: 8/22/02
-- Add to HexImage the supply of hex 'Z'
-- in the case statement when a binary set of 4 bits = "ZZZZ"
 
---------------------------------------------------------------
 
-- Note: 2006.08.11: (FB): modified package name to fit the structure of the
-- project and to highlight the license.
 
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_TextIO.all;
use ieee.numeric_std.all;
-- use IEEE.Std_Logic_Arith.all;
 
library Std;
use STD.TextIO.all;
 
--package Image_Pkg is
package GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String;
function Image(In_Image : Bit) return String;
function Image(In_Image : Bit_Vector) return String;
function Image(In_Image : Integer) return String;
function Image(In_Image : Real) return String;
function Image(In_Image : Std_uLogic) return String;
function Image(In_Image : Std_uLogic_Vector) return String;
function Image(In_Image : Std_Logic_Vector) return String;
function Image(In_Image : Signed) return String;
function Image(In_Image : UnSigned) return String;
 
function HexImage(InStrg : String) return String;
function HexImage(In_Image : Bit_Vector) return String;
function HexImage(In_Image : Std_uLogic_Vector) return String;
function HexImage(In_Image : Std_Logic_Vector) return String;
function HexImage(In_Image : Signed) return String;
function HexImage(In_Image : UnSigned) return String;
 
function DecImage(In_Image : Bit_Vector) return String;
function DecImage(In_Image : Std_uLogic_Vector) return String;
function DecImage(In_Image : Std_Logic_Vector) return String;
function DecImage(In_Image : Signed) return String;
function DecImage(In_Image : UnSigned) return String;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
 
--package body Image_Pkg is
package body GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String is
variable L : Line; -- access type
variable W : String(1 to 14) := (others => ' ');
-- Long enough to hold a time string
begin
-- the WRITE procedure creates an object with "NEW".
-- L is passed as an output of the procedure.
Std.TextIO.WRITE(L, in_image);
-- Copy L.all onto W
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Bit) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Bit_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Integer) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Real) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Std_uLogic) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Std_uLogic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Std_Logic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
 
function Image(In_Image : Signed) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
 
function Image(In_Image : UnSigned) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
 
function HexImage(InStrg : String) return String is
subtype Int03_Typ is Integer range 0 to 3;
variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
(others => '0');
variable StrTo4 : string(1 to Result'length * 4) :=
(others => '0');
variable MTspace : Int03_Typ; -- Empty space to fill in
variable Str4 : String(1 to 4);
variable Group_v : Natural := 0;
begin
MTspace := Result'length * 4 - InStrg'length;
StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
Cnvrt_Lbl : for I in Result'range loop
Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
case Str4 is
when "0000" => Result(I) := '0';
when "0001" => Result(I) := '1';
when "0010" => Result(I) := '2';
when "0011" => Result(I) := '3';
when "0100" => Result(I) := '4';
when "0101" => Result(I) := '5';
when "0110" => Result(I) := '6';
when "0111" => Result(I) := '7';
when "1000" => Result(I) := '8';
when "1001" => Result(I) := '9';
when "1010" => Result(I) := 'A';
when "1011" => Result(I) := 'B';
when "1100" => Result(I) := 'C';
when "1101" => Result(I) := 'D';
when "1110" => Result(I) := 'E';
when "1111" => Result(I) := 'F';
when "ZZZZ" => Result(I) := 'Z'; -- added 8/23/02
when others => Result(I) := 'X';
end case; -- Str4
end loop Cnvrt_Lbl;
 
return Result;
end HexImage;
 
 
function HexImage(In_Image : Bit_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
 
function HexImage(In_Image : Std_uLogic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_Logic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Signed) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : UnSigned) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
 
function DecImage(In_Image : Bit_Vector) return String is
variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer
(Unsigned(To_StdLogicVector
(In_Image_v(31 downto 1)))));
else
return Image(To_integer(Unsigned(To_StdLogicVector(In_Image))));
end if;
end DecImage;
function DecImage(In_Image : Std_uLogic_Vector) return String is
variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Std_Logic_Vector) return String is
variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Signed) return String is
variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
function DecImage(In_Image : UnSigned) return String is
variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
 
 
 
 
 
 
 
 
/MDCTTB_PKG.vhd
0,0 → 1,468
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCTTB_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCTTB_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for testbench simulation
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
-- use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
 
library STD;
use STD.TEXTIO.all;
library WORK;
use WORK.MDCT_PKG.all;
 
package MDCTTB_PKG is
----------------------------------------------
-- constant section 1
----------------------------------------------
constant MAX_IMAGE_SIZE_X : INTEGER := 1280;
constant MAX_IMAGE_SIZE_Y : INTEGER := 1280;
----------------------------------------------
-- type section
----------------------------------------------
type MATRIX_TYPE is array (0 to N-1,0 TO N-1) of REAL;
type I_MATRIX_TYPE is array (0 to N-1,0 TO N-1) of INTEGER;
type COEM_TYPE is array (0 to N/2-1, 0 to N/2-1)
of SIGNED(ROMDATA_W-1 downto 0);
type VECTOR4 is array (0 to N/2-1) of REAL;
type N_LINES_TYPE is array (0 to N-1)
of STD_LOGIC_VECTOR(0 to MAX_IMAGE_SIZE_X*IP_W-1);
type IMAGE_TYPE is array (0 to MAX_IMAGE_SIZE_Y-1,
0 to MAX_IMAGE_SIZE_X-1) of INTEGER;
----------------------------------------------
-- function section
----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER);
function STR(int: INTEGER; base: INTEGER) return STRING;
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN
) return I_MATRIX_TYPE;
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE) return I_MATRIX_TYPE;
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL;
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL;
----------------------------------------------
-- constant section 2
----------------------------------------------
-- set below to true to enable quantization in testbench
constant CLK_FREQ_C : INTEGER := 50;
constant HOLD_TIME : TIME := 1 ns;
constant ENABLE_QUANTIZATION_C : BOOLEAN := FALSE;
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant RUN_FULL_IMAGE : BOOLEAN := FALSE;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant FILEERROR_NAME_C : STRING := "SOURCE\TESTBENCH\imagee.txt";
constant FILEIMAGEO_NAME_C : STRING := "SOURCE\TESTBENCH\imageo.txt";
constant MAX_ERROR_1D : INTEGER := 1;
constant MAX_ERROR_2D : INTEGER := 4;
constant MAX_PIX_VAL : INTEGER := 2**IP_W-1;
constant null_data_r : MATRIX_TYPE :=
(
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0)
);
constant input_data0 : I_MATRIX_TYPE :=
(
(139,144,149,153,155,155,155,155),
(144,151,153,156,159,156,156,156),
(150,155,160,163,158,156,156,156),
(159,161,162,160,160,159,159,159),
(159,160,161,162,162,155,155,155),
(161,161,161,161,160,157,157,157),
(162,162,161,163,162,157,157,157),
(162,162,161,161,163,158,158,158)
);
constant input_data1 : I_MATRIX_TYPE :=
(
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000)
);
constant input_data2 : I_MATRIX_TYPE :=
(
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000)
);
constant input_data3 : I_MATRIX_TYPE :=
(
(55,89,0,2,35,34,100,255),
(144,151,153,151,159,156,156,156),
(150,155,165,163,158,126,156,156),
(254,000,255,255,000,245,254,255),
(159,199,161,162,162,133,155,165),
(231,000,255,235,000,255,254,253),
(162,162,161,163,162,157,157,157),
(11,12,167,165,166,167,101,108)
);
constant input_data4 : I_MATRIX_TYPE :=
(
(135,14,145,15,155,15,155,15),
(140,15,151,15,152,15,153,15),
(154,15,165,16,156,15,157,15),
(158,16,168,16,169,15,150,15),
(15,161,16,162,16,153,15,154),
(165,16,166,16,167,15,158,15),
(16,169,16,160,16,152,15,153),
(164,16,165,16,165,15,156,15)
);
-- from JPEG standard (but not in standard itself!)
constant Q_JPEG_STD : I_MATRIX_TYPE :=
(
(16,11,10,16,24,40,51,61),
(12,12,14,19,26,58,60,55),
(14,13,16,24,40,57,69,56),
(14,17,22,29,51,87,80,62),
(18,22,37,56,68,109,103,77),
(24,35,55,64,81,104,113,92),
(49,64,78,87,103,121,120,101),
(72,92,95,98,112,100,103,99)
);
-- CANON EOS10D super fine quality
constant Q_CANON10D : I_MATRIX_TYPE :=
(
(1, 1, 1, 1, 1, 1, 2, 2),
(1, 1, 1, 1, 1, 2, 4, 4),
(1, 1, 1, 1, 1, 3, 3, 5),
(1, 1, 1, 2, 3, 3, 5, 5),
(1, 1, 3, 3, 4, 4, 5, 5),
(1, 3, 3, 3, 4, 5, 6, 6),
(2, 3, 3, 5, 3, 6, 5, 5),
(3, 3, 4, 3, 6, 4, 5, 5)
);
-- quantization matrix used in testbench
constant Q_MATRIX_USED : I_MATRIX_TYPE := Q_CANON10D;
constant Ce : COEM_TYPE :=
(
(CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W)),
(CONV_SIGNED(BP,ROMDATA_W),CONV_SIGNED(CP,ROMDATA_W),CONV_SIGNED(CM,ROMDATA_W),CONV_SIGNED(BM,ROMDATA_W)),
(CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AM,ROMDATA_W),CONV_SIGNED(AM,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W)),
(CONV_SIGNED(CP,ROMDATA_W),CONV_SIGNED(BM,ROMDATA_W),CONV_SIGNED(BP,ROMDATA_W),CONV_SIGNED(CM,ROMDATA_W))
);
constant Co : COEM_TYPE :=
(
(CONV_SIGNED(DP,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(FP,ROMDATA_W),CONV_SIGNED(GP,ROMDATA_W)),
(CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(GM,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W),CONV_SIGNED(FM,ROMDATA_W)),
(CONV_SIGNED(FP,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W),CONV_SIGNED(GP,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W)),
(CONV_SIGNED(GP,ROMDATA_W),CONV_SIGNED(FM,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W))
);
end MDCTTB_PKG;
 
--------------------------------------------------
-- PACKAGE BODY
--------------------------------------------------
package body MDCTTB_PKG is
--------------------------------------------------------------------------
-- converts an INTEGER into a CHARACTER
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the CHARACTERs A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
--------------------------------------------------------------------------
function CHR(int: INTEGER) return CHARACTER is
variable c: CHARACTER;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end CHR;
 
 
--------------------------------------------------------------------------
-- convert INTEGER to STRING using specified base
--------------------------------------------------------------------------
function STR(int: INTEGER; base: INTEGER) return STRING is
variable temp: STRING(1 to 10);
variable num: INTEGER;
variable abs_int: INTEGER;
variable len: INTEGER := 1;
variable power: INTEGER := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop
len := len + 1;
num := num / base;
end loop ;
for i in len downto 1 loop
temp(i) := chr(abs_int/power mod base);
power := power * base;
end loop ;
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end STR;
------------------------------------------------
-- computes DCT1D
------------------------------------------------
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN)
return I_MATRIX_TYPE is
variable fXm : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fXs : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYe : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYo : VECTOR4 := (0.0,0.0,0.0,0.0);
variable ref_dct_matrix : I_MATRIX_TYPE;
variable norma_input : MATRIX_TYPE;
begin
-- compute reference coefficients
for x in 0 to N-1 loop
for s in 0 to 7 loop
if shift = TRUE then
norma_input(x,s) := (REAL(input_matrix(x,s))- REAL(LEVEL_SHIFT))/2.0;
else
norma_input(x,s) := REAL(input_matrix(x,s))/2.0;
end if;
end loop;
fXs(0) := norma_input(x,0)+norma_input(x,7);
fXs(1) := norma_input(x,1)+norma_input(x,6);
fXs(2) := norma_input(x,2)+norma_input(x,5);
fXs(3) := norma_input(x,3)+norma_input(x,4);
fXm(0) := norma_input(x,0)-norma_input(x,7);
fXm(1) := norma_input(x,1)-norma_input(x,6);
fXm(2) := norma_input(x,2)-norma_input(x,5);
fXm(3) := norma_input(x,3)-norma_input(x,4);
for k in 0 to N/2-1 loop
fYe(k) := REAL(CONV_INTEGER(Ce(k,0)))*fXs(0) +
REAL(CONV_INTEGER(Ce(k,1)))*fXs(1) +
REAL(CONV_INTEGER(Ce(k,2)))*fXs(2) +
REAL(CONV_INTEGER(Ce(k,3)))*fXs(3);
fYo(k) := REAL(CONV_INTEGER(Co(k,0)))*fXm(0) +
REAL(CONV_INTEGER(Co(k,1)))*fXm(1) +
REAL(CONV_INTEGER(Co(k,2)))*fXm(2) +
REAL(CONV_INTEGER(Co(k,3)))*fXm(3);
end loop;
-- transpose matrix by writing in row order
ref_dct_matrix(0,x) := INTEGER(fYe(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(1,x) := INTEGER(fYo(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(2,x) := INTEGER(fYe(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(3,x) := INTEGER(fYo(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(4,x) := INTEGER(fYe(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(5,x) := INTEGER(fYo(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(6,x) := INTEGER(fYe(3)/REAL((2**(COE_W-1))));
ref_dct_matrix(7,x) := INTEGER(fYo(3)/REAL((2**(COE_W-1))));
end loop;
return ref_dct_matrix;
end COMPUTE_REF_DCT1D;
-----------------------------------------------
-- compares NxN matrices, logs failure if difference
-- greater than maximum error specified
-----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER
) is
variable error_matrix_v : I_MATRIX_TYPE;
begin
for a in 0 to N - 1 loop
for b in 0 to N - 1 loop
error_matrix_v(a,b) := ref_matrix(a,b) - dcto_matrix(a,b);
if abs(error_matrix_v(a,b)) > max_error then
error_cnt := error_cnt + 1;
assert false
report "E01: DCT max error violated!"
severity Error;
end if;
end loop;
end loop;
error_matrix := error_matrix_v;
end CMP_MATRIX;
------------------------------------------------
-- computes IDCT on NxN matrix
------------------------------------------------
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE)
return I_MATRIX_TYPE is
variable i : INTEGER := 0;
variable j : INTEGER := 0;
variable u : INTEGER := 0;
variable v : INTEGER := 0;
variable Cu : REAL;
variable Cv : REAL;
variable xi : MATRIX_TYPE := null_data_r;
variable xr : I_MATRIX_TYPE;
begin
-- idct
for i in 0 to N-1 loop
for j in 0 to N-1 loop
for u in 0 to N-1 loop
if u = 0 then
Cu := 1.0/sqrt(2.0);
else
Cu := 1.0;
end if;
for v in 0 to N-1 loop
if v = 0 then
Cv := 1.0/sqrt(2.0);
else
Cv := 1.0;
end if;
xi(i,j) := xi(i,j) +
2.0/REAL(N)*Cu*Cv*REAL(X(u,v))*
cos( ( (2.0*REAL(i)+1.0)*REAL(u)*MATH_PI ) / (2.0*REAL(N)) )*
cos( ( (2.0*REAL(j)+1.0)*REAL(v)*MATH_PI ) / (2.0*REAL(N)) );
xr(i,j) := INTEGER(ROUND(xi(i,j)))+LEVEL_SHIFT;
end loop;
end loop;
end loop;
end loop;
return xr;
end COMPUTE_REF_IDCT;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL is
variable psnr_tmp : REAL := 0.0;
begin
for i in 0 to N-1 loop
for j in 0 to N-1 loop
psnr_tmp := psnr_tmp + (REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(N)*REAL(N));
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL is
variable psnr_tmp : REAL := 0.0;
variable lineb : LINE;
begin
for i in 0 to ysize-1 loop
for j in 0 to xsize-1 loop
psnr_tmp := psnr_tmp +
(REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(ysize)*REAL(xsize));
--WRITE(lineb,STRING'("MSE Mean Squared Error is "));
--WRITE(lineb,psnr_tmp);
--assert false
-- report lineb.all
-- severity Note;
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
end MDCTTB_PKG;

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