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URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

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  • This comparison shows the changes necessary to convert path 
    /mkjpeg/trunk
    from Rev 66 to Rev 67
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  •

Rev 66 → Rev 67

/design/BufFifo/BUF_FIFO.vhd
28,7 → 28,7
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
71,17 → 71,39
architecture RTL of BUF_FIFO is
 
constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;
 
--constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;
-- No Exstra Lines
constant C_NUM_LINES : integer := 8;
signal pixel_cnt : unsigned(15 downto 0);
signal line_cnt : unsigned(15 downto 0);
 
signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
--signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal q : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ram_data : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal wr_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal ram_write : STD_LOGIC;
signal rd_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal wr_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal we : STD_LOGIC;
signal rd_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal data_out : STD_LOGIC_VECTOR(15 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal data_in : unsigned(15 downto 0);
signal wr_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal we2 : STD_LOGIC;
signal rd_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
signal data_out2 : STD_LOGIC_VECTOR(15 downto 0);
--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal data_in2 : unsigned(15 downto 0);
signal pix_inblk_cnt : unsigned(3 downto 0);
signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
signal line_inblk_cnt : unsigned(2 downto 0);
93,7 → 115,7
signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_tmp : unsigned(15 downto 0);
signal ramwaddr_d1 : unsigned(ramwaddr'range);
--signal ramwaddr_d1 : unsigned(ramwaddr'range);
signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);
107,8 → 129,34
signal image_write_end : std_logic;
signal result :std_logic_vector(31 downto 0);
signal threshold :std_logic_vector(31 downto 0);
signal wr_counter : unsigned(15 downto 0);
signal rd_counter : unsigned(15 downto 0);
signal wr_mod : unsigned(15 downto 0);
signal rd_mod : unsigned(15 downto 0);
signal wr_counter_total : unsigned(31 downto 0);
signal rd_counter_total : unsigned(31 downto 0);
signal counter : unsigned(31 downto 0);
signal counter2 : unsigned(31 downto 0);
signal init_table_wr : std_logic;
signal init_table_rd : std_logic;
signal do1 : unsigned(15 downto 0);
signal do2 : unsigned(15 downto 0);
signal data_temp : unsigned(15 downto 0);
signal data_temp2 : unsigned(15 downto 0);
signal temp :std_logic_vector(23 downto 0);
signal fifo_almost_full_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
116,6 → 164,8
-------------------------------------------------------------------
-- RAM for SUB_FIFOs
-------------------------------------------------------------------
fifo_almost_full <= fifo_almost_full_i;
U_SUB_RAMZ : entity work.SUB_RAMZ
generic map
(
124,198 → 174,320
)
port map
(
d => ramd,
waddr => std_logic_vector(ramwaddr_d1),
raddr => std_logic_vector(ramraddr),
we => ramenw,
d => ram_data,
waddr => std_logic_vector(wr_ptr),
raddr => std_logic_vector(rd_ptr),
we => ram_write,
clk => clk,
q => ramq
q => q
);
-------------------------------------------------------------------
-- register RAM data input
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
ramenw <= '0';
ramd <= (others => '0');
elsif CLK'event and CLK = '1' then
ramd <= iram_wdata;
ramenw <= iram_wren;
end if;
end process;
MULTIPLIER : entity work.multiplier
PORT MAP(
CLK => CLK,
RST => RST,
img_size_x => img_size_x,
img_size_y => img_size_y,
result => result,
threshold => threshold
);
U_SUB_RAMZ_WR_ADRESS_LUT : entity work.SUB_RAMZ_LUT
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
RAMDATA_W => 16
)
port map
(
d => std_logic_vector(data_in),
waddr => std_logic_vector(wr_addr),
raddr => std_logic_vector(rd_addr),
we => we,
clk => CLK,
q => data_out
);
-------------------------------------------------------------------
-- resolve RAM write address
-------------------------------------------------------------------
p_pixel_cnt : process(CLK, RST)
U_SUB_RAMZ_RD_ADRESS_LUT : entity work.SUB_RAMZ_LUT
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
RAMDATA_W => 16
)
port map
(
d => std_logic_vector(data_in2),
waddr => std_logic_vector(wr_addr2),
raddr => std_logic_vector(rd_addr2),
we => we2,
clk => CLK,
q => data_out2
);
process (CLK, RST)
begin
if RST = '1' then
pixel_cnt <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
ramwaddr <= (others => '0');
ramwaddr_d1 <= (others => '0');
image_write_end <= '0';
elsif CLK'event and CLK = '1' then
ramwaddr_d1 <= ramwaddr;
if iram_wren = '1' then
-- end of line
if pixel_cnt = unsigned(img_size_x)-1 then
pixel_cnt <= (others => '0');
-- absolute write line index
wr_line_idx <= wr_line_idx + 1;
if wr_line_idx = unsigned(img_size_y)-1 then
image_write_end <= '1';
end if;
-- memory line index
if memwr_line_cnt = C_NUM_LINES-1 then
memwr_line_cnt <= (others => '0');
ramwaddr <= (others => '0');
else
memwr_line_cnt <= memwr_line_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
else
pixel_cnt <= pixel_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
end if;
if (RST = '1') then
wr_counter <= (others => '0');
wr_counter_total <= (others => '0');
wr_mod <= (others => '0');
wr_ptr <= (others => '0');
ram_write <= '0';
init_table_wr <= '0';
do1 <= (others => '0');
data_temp <= (others => '0');
wr_addr <= (others => '0');
rd_addr <= (others => '0');
we <= '0';
counter <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (init_table_wr = '0') then
if (iram_wren = '1') then
if (wr_mod /= 0 and wr_counter mod 8 = "000") then
wr_ptr <= resize(do1(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do1(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
data_temp <= resize(do1(5 downto 3) * unsigned(img_size_x), 16) + resize(do1(15 downto 6) * 8, 16);
--wr_ptr <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;
--data_temp <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;
else
if (wr_counter = 0) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
if (wr_mod /= 0 and wr_counter mod 8 = "011") then
if (wr_counter = unsigned(img_size_x) * 8 - 5) then
rd_addr <= (others => '0');
else
rd_addr <= resize((wr_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
end if;
end if;
if (wr_mod /= 0 and wr_counter mod 8 = "101") then
do1 <= unsigned(data_out);
we <= '1';
if (wr_mod = unsigned(img_size_y) / 8 - 1) then
wr_addr <= resize(counter, log2(C_MAX_LINE_WIDTH));
data_in <= resize(counter * 8, 16);
counter <= counter + 1;
else
data_in <= data_temp;
if (wr_counter = unsigned(img_size_x) * 8 - 3) then
wr_addr <= (others => '0');
else
wr_addr <= resize((wr_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
end if;
end if;
else
we <= '0';
end if;
ram_write <= '1';
ram_data <= iram_wdata;
wr_counter_total <= wr_counter_total + 1;
if (wr_counter_total = unsigned(result) - 1) then
init_table_wr <= '1';
counter <= (others => '0');
end if;
if (wr_counter = unsigned(img_size_x) * 8 - 1) then
wr_counter <= (others => '0');
wr_mod <= wr_mod + 1;
else
wr_counter <= wr_counter + 1;
end if;
else
ram_write <= '0';
end if;
if sof = '1' then
pixel_cnt <= (others => '0');
ramwaddr <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
image_write_end <= '0';
wr_counter <= (others => '0');
wr_counter_total <= (others => '0');
wr_mod <= (others => '0');
wr_ptr <= (others => '0');
ram_write <= '0';
init_table_wr <= '0';
do1 <= (others => '0');
data_temp <= (others => '0');
wr_addr <= (others => '0');
rd_addr <= (others => '0');
we <= '0';
counter <= (others => '0');
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- FIFO half full / almost full flag generation
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
fdct_fifo_hf_full <= '0';
fifo_almost_full <= '0';
elsif CLK'event and CLK = '1' then
process (CLK, RST)
begin
if (RST = '1') then
fifo_almost_full_i <= '0';
fdct_fifo_hf_full <= '0';
elsif (CLK'event and CLK = '1') then
if (fifo_almost_full_i = '0' and wr_counter_total = rd_counter_total + unsigned(img_size_x)*8-2) then
fifo_almost_full_i <= '1';
end if;
if (fifo_almost_full_i = '1' and wr_counter_total < rd_counter_total + unsigned(threshold) ) then
fifo_almost_full_i <= '0';
end if;
if (wr_counter = unsigned(img_size_x) * 8 - 1) then
fdct_fifo_hf_full <= '1';
end if;
if (rd_counter = unsigned(img_size_x) * 8 - 1) then
fdct_fifo_hf_full <= '0';
fifo_almost_full_i <= '0';
end if;
if rd_line_idx + 8 <= wr_line_idx then
fdct_fifo_hf_full <= '1';
else
fdct_fifo_hf_full <= '0';
end if;
fifo_almost_full <= '0';
if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
if pixel_cnt >= unsigned(img_size_x)-1-1 then
fifo_almost_full <= '1';
if sof = '1' then
fifo_almost_full_i <= '0';
fdct_fifo_hf_full <= '0';
end if;
elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
fifo_almost_full <= '1';
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
fdct_fifo_q <= (others => '0');
temp <= (others => '0');
rd_counter <= (others => '0');
rd_counter_total <= (others => '0');
rd_mod <= x"0001";
rd_ptr <= (others => '0');
init_table_rd <= '0';
do2 <= (others => '0');
data_temp2 <= (others => '0');
wr_addr2 <= (others => '0');
rd_addr2 <= (others => '0');
we2 <= '0';
counter2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (init_table_rd = '0') then
if (fdct_fifo_rd = '1') then
if (rd_counter mod 8 = "000") then
--rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
--data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, 16);
rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do2(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x), 16) + resize(do2(15 downto 6) * 8, 16);
else
rd_ptr <= rd_ptr + 1;
end if;
if (rd_counter mod 8 = "011") then
if (rd_counter = unsigned(img_size_x) * 8 - 5) then
rd_addr2 <= (others => '0');
else
rd_addr2 <= resize(unsigned(rd_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
end if;
end if;
if (rd_counter mod 8 = "101") then
do2 <= unsigned(data_out2);
we2 <= '1';
if (rd_mod = unsigned(img_size_y) / 8) then
data_in2 <= resize(counter2 * 8, 16);
wr_addr2 <= resize(counter2, log2(C_MAX_LINE_WIDTH));
counter2 <= counter2 + 1;
else
data_in2 <= data_temp2;
if (rd_counter = unsigned(img_size_x) * 8 - 3) then
wr_addr2 <= (others => '0');
else
wr_addr2 <= resize(unsigned(rd_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
end if;
end if;
else
we2 <= '0';
end if;
rd_counter_total <= rd_counter_total + 1;
if (rd_counter_total = unsigned(result) - 1) then
init_table_rd <= '1';
counter2 <= (others => '0');
end if;
if (rd_counter = unsigned(img_size_x) * 8 - 1) then
rd_counter <= (others => '0');
rd_mod <= rd_mod + 1;
else
rd_counter <= rd_counter + 1;
end if;
end if;
if sof = '1' then
fdct_fifo_q <= (others => '0');
temp <= (others => '0');
rd_counter <= (others => '0');
rd_counter_total <= (others => '0');
rd_mod <= x"0001";
rd_ptr <= (others => '0');
init_table_rd <= '0';
do2 <= (others => '0');
data_temp2 <= (others => '0');
wr_addr2 <= (others => '0');
rd_addr2 <= (others => '0');
we2 <= '0';
counter2 <= (others => '0');
end if;
-- fdct_fifo_q <= (temp(15 downto 11) & "000" &
-- temp(10 downto 5) & "00" &
-- temp(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
-- std_logic_vector(resize(unsigned(temp), 24));
end if;
temp <= q;
if (C_PIXEL_BITS = 16) then
fdct_fifo_q <= (temp(15 downto 11) & "000" &
temp(10 downto 5) & "00" &
temp(4 downto 0) & "000");
else
fdct_fifo_q <= temp;
end if;
 
end if;
end process;
end if;
end process;
-------------------------------------------------------------------
-- read side
-------------------------------------------------------------------
p_mux5 : process(CLK, RST)
begin
if RST = '1' then
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
pix_inblk_cnt_d1 <= (others => '0');
read_block_cnt_d1 <= (others => '0');
elsif CLK'event and CLK = '1' then
pix_inblk_cnt_d1 <= pix_inblk_cnt;
read_block_cnt_d1 <= read_block_cnt;
-- BUF FIFO read
if fdct_fifo_rd = '1' then
-- last pixel in block
if pix_inblk_cnt = 8-1 then
pix_inblk_cnt <= (others => '0');
 
-- last line in 8
if line_inblk_cnt = 8-1 then
line_inblk_cnt <= (others => '0');
 
-- last block in last line
if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
read_block_cnt <= (others => '0');
rd_line_idx <= rd_line_idx + 8;
if memrd_offs_cnt + 8 > C_NUM_LINES-1 then
memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;
else
memrd_offs_cnt <= memrd_offs_cnt + 8;
end if;
else
read_block_cnt <= read_block_cnt + 1;
end if;
else
line_inblk_cnt <= line_inblk_cnt + 1;
end if;
else
pix_inblk_cnt <= pix_inblk_cnt + 1;
end if;
end if;
if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);
else
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);
end if;
if sof = '1' then
memrd_line <= (others => '0');
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
end if;
end if;
end process;
-- generate RAM data output based on 16 or 24 bit mode selection
fdct_fifo_q <= (ramq(15 downto 11) & "000" &
ramq(10 downto 5) & "00" &
ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
std_logic_vector(resize(unsigned(ramq), 24));
ramraddr <= ramraddr_int(ramraddr'range);
-------------------------------------------------------------------
-- resolve RAM read address
-------------------------------------------------------------------
p_mux4 : process(CLK, RST)
begin
if RST = '1' then
ramraddr_int <= (others => '0');
elsif CLK'event and CLK = '1' then
raddr_base_line <= (memrd_line) * unsigned(img_size_x);
raddr_tmp <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;
ramraddr_int <= raddr_tmp + raddr_base_line;
end if;
end process;
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
/design/BufFifo/counter_8.txt
0,0 → 1,8192
0000
0008
0010
0018
0020
0028
0030
0038
0040
0048
0050
0058
0060
0068
0070
0078
0080
0088
0090
0098
00a0
00a8
00b0
00b8
00c0
00c8
00d0
00d8
00e0
00e8
00f0
00f8
0100
0108
0110
0118
0120
0128
0130
0138
0140
0148
0150
0158
0160
0168
0170
0178
0180
0188
0190
0198
01a0
01a8
01b0
01b8
01c0
01c8
01d0
01d8
01e0
01e8
01f0
01f8
0200
0208
0210
0218
0220
0228
0230
0238
0240
0248
0250
0258
0260
0268
0270
0278
0280
0288
0290
0298
02a0
02a8
02b0
02b8
02c0
02c8
02d0
02d8
02e0
02e8
02f0
02f8
0300
0308
0310
0318
0320
0328
0330
0338
0340
0348
0350
0358
0360
0368
0370
0378
0380
0388
0390
0398
03a0
03a8
03b0
03b8
03c0
03c8
03d0
03d8
03e0
03e8
03f0
03f8
0400
0408
0410
0418
0420
0428
0430
0438
0440
0448
0450
0458
0460
0468
0470
0478
0480
0488
0490
0498
04a0
04a8
04b0
04b8
04c0
04c8
04d0
04d8
04e0
04e8
04f0
04f8
0500
0508
0510
0518
0520
0528
0530
0538
0540
0548
0550
0558
0560
0568
0570
0578
0580
0588
0590
0598
05a0
05a8
05b0
05b8
05c0
05c8
05d0
05d8
05e0
05e8
05f0
05f8
0600
0608
0610
0618
0620
0628
0630
0638
0640
0648
0650
0658
0660
0668
0670
0678
0680
0688
0690
0698
06a0
06a8
06b0
06b8
06c0
06c8
06d0
06d8
06e0
06e8
06f0
06f8
0700
0708
0710
0718
0720
0728
0730
0738
0740
0748
0750
0758
0760
0768
0770
0778
0780
0788
0790
0798
07a0
07a8
07b0
07b8
07c0
07c8
07d0
07d8
07e0
07e8
07f0
07f8
0800
0808
0810
0818
0820
0828
0830
0838
0840
0848
0850
0858
0860
0868
0870
0878
0880
0888
0890
0898
08a0
08a8
08b0
08b8
08c0
08c8
08d0
08d8
08e0
08e8
08f0
08f8
0900
0908
0910
0918
0920
0928
0930
0938
0940
0948
0950
0958
0960
0968
0970
0978
0980
0988
0990
0998
09a0
09a8
09b0
09b8
09c0
09c8
09d0
09d8
09e0
09e8
09f0
09f8
0a00
0a08
0a10
0a18
0a20
0a28
0a30
0a38
0a40
0a48
0a50
0a58
0a60
0a68
0a70
0a78
0a80
0a88
0a90
0a98
0aa0
0aa8
0ab0
0ab8
0ac0
0ac8
0ad0
0ad8
0ae0
0ae8
0af0
0af8
0b00
0b08
0b10
0b18
0b20
0b28
0b30
0b38
0b40
0b48
0b50
0b58
0b60
0b68
0b70
0b78
0b80
0b88
0b90
0b98
0ba0
0ba8
0bb0
0bb8
0bc0
0bc8
0bd0
0bd8
0be0
0be8
0bf0
0bf8
0c00
0c08
0c10
0c18
0c20
0c28
0c30
0c38
0c40
0c48
0c50
0c58
0c60
0c68
0c70
0c78
0c80
0c88
0c90
0c98
0ca0
0ca8
0cb0
0cb8
0cc0
0cc8
0cd0
0cd8
0ce0
0ce8
0cf0
0cf8
0d00
0d08
0d10
0d18
0d20
0d28
0d30
0d38
0d40
0d48
0d50
0d58
0d60
0d68
0d70
0d78
0d80
0d88
0d90
0d98
0da0
0da8
0db0
0db8
0dc0
0dc8
0dd0
0dd8
0de0
0de8
0df0
0df8
0e00
0e08
0e10
0e18
0e20
0e28
0e30
0e38
0e40
0e48
0e50
0e58
0e60
0e68
0e70
0e78
0e80
0e88
0e90
0e98
0ea0
0ea8
0eb0
0eb8
0ec0
0ec8
0ed0
0ed8
0ee0
0ee8
0ef0
0ef8
0f00
0f08
0f10
0f18
0f20
0f28
0f30
0f38
0f40
0f48
0f50
0f58
0f60
0f68
0f70
0f78
0f80
0f88
0f90
0f98
0fa0
0fa8
0fb0
0fb8
0fc0
0fc8
0fd0
0fd8
0fe0
0fe8
0ff0
0ff8
1000
1008
1010
1018
1020
1028
1030
1038
1040
1048
1050
1058
1060
1068
1070
1078
1080
1088
1090
1098
10a0
10a8
10b0
10b8
10c0
10c8
10d0
10d8
10e0
10e8
10f0
10f8
1100
1108
1110
1118
1120
1128
1130
1138
1140
1148
1150
1158
1160
1168
1170
1178
1180
1188
1190
1198
11a0
11a8
11b0
11b8
11c0
11c8
11d0
11d8
11e0
11e8
11f0
11f8
1200
1208
1210
1218
1220
1228
1230
1238
1240
1248
1250
1258
1260
1268
1270
1278
1280
1288
1290
1298
12a0
12a8
12b0
12b8
12c0
12c8
12d0
12d8
12e0
12e8
12f0
12f8
1300
1308
1310
1318
1320
1328
1330
1338
1340
1348
1350
1358
1360
1368
1370
1378
1380
1388
1390
1398
13a0
13a8
13b0
13b8
13c0
13c8
13d0
13d8
13e0
13e8
13f0
13f8
1400
1408
1410
1418
1420
1428
1430
1438
1440
1448
1450
1458
1460
1468
1470
1478
1480
1488
1490
1498
14a0
14a8
14b0
14b8
14c0
14c8
14d0
14d8
14e0
14e8
14f0
14f8
1500
1508
1510
1518
1520
1528
1530
1538
1540
1548
1550
1558
1560
1568
1570
1578
1580
1588
1590
1598
15a0
15a8
15b0
15b8
15c0
15c8
15d0
15d8
15e0
15e8
15f0
15f8
1600
1608
1610
1618
1620
1628
1630
1638
1640
1648
1650
1658
1660
1668
1670
1678
1680
1688
1690
1698
16a0
16a8
16b0
16b8
16c0
16c8
16d0
16d8
16e0
16e8
16f0
16f8
1700
1708
1710
1718
1720
1728
1730
1738
1740
1748
1750
1758
1760
1768
1770
1778
1780
1788
1790
1798
17a0
17a8
17b0
17b8
17c0
17c8
17d0
17d8
17e0
17e8
17f0
17f8
1800
1808
1810
1818
1820
1828
1830
1838
1840
1848
1850
1858
1860
1868
1870
1878
1880
1888
1890
1898
18a0
18a8
18b0
18b8
18c0
18c8
18d0
18d8
18e0
18e8
18f0
18f8
1900
1908
1910
1918
1920
1928
1930
1938
1940
1948
1950
1958
1960
1968
1970
1978
1980
1988
1990
1998
19a0
19a8
19b0
19b8
19c0
19c8
19d0
19d8
19e0
19e8
19f0
19f8
1a00
1a08
1a10
1a18
1a20
1a28
1a30
1a38
1a40
1a48
1a50
1a58
1a60
1a68
1a70
1a78
1a80
1a88
1a90
1a98
1aa0
1aa8
1ab0
1ab8
1ac0
1ac8
1ad0
1ad8
1ae0
1ae8
1af0
1af8
1b00
1b08
1b10
1b18
1b20
1b28
1b30
1b38
1b40
1b48
1b50
1b58
1b60
1b68
1b70
1b78
1b80
1b88
1b90
1b98
1ba0
1ba8
1bb0
1bb8
1bc0
1bc8
1bd0
1bd8
1be0
1be8
1bf0
1bf8
1c00
1c08
1c10
1c18
1c20
1c28
1c30
1c38
1c40
1c48
1c50
1c58
1c60
1c68
1c70
1c78
1c80
1c88
1c90
1c98
1ca0
1ca8
1cb0
1cb8
1cc0
1cc8
1cd0
1cd8
1ce0
1ce8
1cf0
1cf8
1d00
1d08
1d10
1d18
1d20
1d28
1d30
1d38
1d40
1d48
1d50
1d58
1d60
1d68
1d70
1d78
1d80
1d88
1d90
1d98
1da0
1da8
1db0
1db8
1dc0
1dc8
1dd0
1dd8
1de0
1de8
1df0
1df8
1e00
1e08
1e10
1e18
1e20
1e28
1e30
1e38
1e40
1e48
1e50
1e58
1e60
1e68
1e70
1e78
1e80
1e88
1e90
1e98
1ea0
1ea8
1eb0
1eb8
1ec0
1ec8
1ed0
1ed8
1ee0
1ee8
1ef0
1ef8
1f00
1f08
1f10
1f18
1f20
1f28
1f30
1f38
1f40
1f48
1f50
1f58
1f60
1f68
1f70
1f78
1f80
1f88
1f90
1f98
1fa0
1fa8
1fb0
1fb8
1fc0
1fc8
1fd0
1fd8
1fe0
1fe8
1ff0
1ff8
2000
2008
2010
2018
2020
2028
2030
2038
2040
2048
2050
2058
2060
2068
2070
2078
2080
2088
2090
2098
20a0
20a8
20b0
20b8
20c0
20c8
20d0
20d8
20e0
20e8
20f0
20f8
2100
2108
2110
2118
2120
2128
2130
2138
2140
2148
2150
2158
2160
2168
2170
2178
2180
2188
2190
2198
21a0
21a8
21b0
21b8
21c0
21c8
21d0
21d8
21e0
21e8
21f0
21f8
2200
2208
2210
2218
2220
2228
2230
2238
2240
2248
2250
2258
2260
2268
2270
2278
2280
2288
2290
2298
22a0
22a8
22b0
22b8
22c0
22c8
22d0
22d8
22e0
22e8
22f0
22f8
2300
2308
2310
2318
2320
2328
2330
2338
2340
2348
2350
2358
2360
2368
2370
2378
2380
2388
2390
2398
23a0
23a8
23b0
23b8
23c0
23c8
23d0
23d8
23e0
23e8
23f0
23f8
2400
2408
2410
2418
2420
2428
2430
2438
2440
2448
2450
2458
2460
2468
2470
2478
2480
2488
2490
2498
24a0
24a8
24b0
24b8
24c0
24c8
24d0
24d8
24e0
24e8
24f0
24f8
2500
2508
2510
2518
2520
2528
2530
2538
2540
2548
2550
2558
2560
2568
2570
2578
2580
2588
2590
2598
25a0
25a8
25b0
25b8
25c0
25c8
25d0
25d8
25e0
25e8
25f0
25f8
2600
2608
2610
2618
2620
2628
2630
2638
2640
2648
2650
2658
2660
2668
2670
2678
2680
2688
2690
2698
26a0
26a8
26b0
26b8
26c0
26c8
26d0
26d8
26e0
26e8
26f0
26f8
2700
2708
2710
2718
2720
2728
2730
2738
2740
2748
2750
2758
2760
2768
2770
2778
2780
2788
2790
2798
27a0
27a8
27b0
27b8
27c0
27c8
27d0
27d8
27e0
27e8
27f0
27f8
2800
2808
2810
2818
2820
2828
2830
2838
2840
2848
2850
2858
2860
2868
2870
2878
2880
2888
2890
2898
28a0
28a8
28b0
28b8
28c0
28c8
28d0
28d8
28e0
28e8
28f0
28f8
2900
2908
2910
2918
2920
2928
2930
2938
2940
2948
2950
2958
2960
2968
2970
2978
2980
2988
2990
2998
29a0
29a8
29b0
29b8
29c0
29c8
29d0
29d8
29e0
29e8
29f0
29f8
2a00
2a08
2a10
2a18
2a20
2a28
2a30
2a38
2a40
2a48
2a50
2a58
2a60
2a68
2a70
2a78
2a80
2a88
2a90
2a98
2aa0
2aa8
2ab0
2ab8
2ac0
2ac8
2ad0
2ad8
2ae0
2ae8
2af0
2af8
2b00
2b08
2b10
2b18
2b20
2b28
2b30
2b38
2b40
2b48
2b50
2b58
2b60
2b68
2b70
2b78
2b80
2b88
2b90
2b98
2ba0
2ba8
2bb0
2bb8
2bc0
2bc8
2bd0
2bd8
2be0
2be8
2bf0
2bf8
2c00
2c08
2c10
2c18
2c20
2c28
2c30
2c38
2c40
2c48
2c50
2c58
2c60
2c68
2c70
2c78
2c80
2c88
2c90
2c98
2ca0
2ca8
2cb0
2cb8
2cc0
2cc8
2cd0
2cd8
2ce0
2ce8
2cf0
2cf8
2d00
2d08
2d10
2d18
2d20
2d28
2d30
2d38
2d40
2d48
2d50
2d58
2d60
2d68
2d70
2d78
2d80
2d88
2d90
2d98
2da0
2da8
2db0
2db8
2dc0
2dc8
2dd0
2dd8
2de0
2de8
2df0
2df8
2e00
2e08
2e10
2e18
2e20
2e28
2e30
2e38
2e40
2e48
2e50
2e58
2e60
2e68
2e70
2e78
2e80
2e88
2e90
2e98
2ea0
2ea8
2eb0
2eb8
2ec0
2ec8
2ed0
2ed8
2ee0
2ee8
2ef0
2ef8
2f00
2f08
2f10
2f18
2f20
2f28
2f30
2f38
2f40
2f48
2f50
2f58
2f60
2f68
2f70
2f78
2f80
2f88
2f90
2f98
2fa0
2fa8
2fb0
2fb8
2fc0
2fc8
2fd0
2fd8
2fe0
2fe8
2ff0
2ff8
3000
3008
3010
3018
3020
3028
3030
3038
3040
3048
3050
3058
3060
3068
3070
3078
3080
3088
3090
3098
30a0
30a8
30b0
30b8
30c0
30c8
30d0
30d8
30e0
30e8
30f0
30f8
3100
3108
3110
3118
3120
3128
3130
3138
3140
3148
3150
3158
3160
3168
3170
3178
3180
3188
3190
3198
31a0
31a8
31b0
31b8
31c0
31c8
31d0
31d8
31e0
31e8
31f0
31f8
3200
3208
3210
3218
3220
3228
3230
3238
3240
3248
3250
3258
3260
3268
3270
3278
3280
3288
3290
3298
32a0
32a8
32b0
32b8
32c0
32c8
32d0
32d8
32e0
32e8
32f0
32f8
3300
3308
3310
3318
3320
3328
3330
3338
3340
3348
3350
3358
3360
3368
3370
3378
3380
3388
3390
3398
33a0
33a8
33b0
33b8
33c0
33c8
33d0
33d8
33e0
33e8
33f0
33f8
3400
3408
3410
3418
3420
3428
3430
3438
3440
3448
3450
3458
3460
3468
3470
3478
3480
3488
3490
3498
34a0
34a8
34b0
34b8
34c0
34c8
34d0
34d8
34e0
34e8
34f0
34f8
3500
3508
3510
3518
3520
3528
3530
3538
3540
3548
3550
3558
3560
3568
3570
3578
3580
3588
3590
3598
35a0
35a8
35b0
35b8
35c0
35c8
35d0
35d8
35e0
35e8
35f0
35f8
3600
3608
3610
3618
3620
3628
3630
3638
3640
3648
3650
3658
3660
3668
3670
3678
3680
3688
3690
3698
36a0
36a8
36b0
36b8
36c0
36c8
36d0
36d8
36e0
36e8
36f0
36f8
3700
3708
3710
3718
3720
3728
3730
3738
3740
3748
3750
3758
3760
3768
3770
3778
3780
3788
3790
3798
37a0
37a8
37b0
37b8
37c0
37c8
37d0
37d8
37e0
37e8
37f0
37f8
3800
3808
3810
3818
3820
3828
3830
3838
3840
3848
3850
3858
3860
3868
3870
3878
3880
3888
3890
3898
38a0
38a8
38b0
38b8
38c0
38c8
38d0
38d8
38e0
38e8
38f0
38f8
3900
3908
3910
3918
3920
3928
3930
3938
3940
3948
3950
3958
3960
3968
3970
3978
3980
3988
3990
3998
39a0
39a8
39b0
39b8
39c0
39c8
39d0
39d8
39e0
39e8
39f0
39f8
3a00
3a08
3a10
3a18
3a20
3a28
3a30
3a38
3a40
3a48
3a50
3a58
3a60
3a68
3a70
3a78
3a80
3a88
3a90
3a98
3aa0
3aa8
3ab0
3ab8
3ac0
3ac8
3ad0
3ad8
3ae0
3ae8
3af0
3af8
3b00
3b08
3b10
3b18
3b20
3b28
3b30
3b38
3b40
3b48
3b50
3b58
3b60
3b68
3b70
3b78
3b80
3b88
3b90
3b98
3ba0
3ba8
3bb0
3bb8
3bc0
3bc8
3bd0
3bd8
3be0
3be8
3bf0
3bf8
3c00
3c08
3c10
3c18
3c20
3c28
3c30
3c38
3c40
3c48
3c50
3c58
3c60
3c68
3c70
3c78
3c80
3c88
3c90
3c98
3ca0
3ca8
3cb0
3cb8
3cc0
3cc8
3cd0
3cd8
3ce0
3ce8
3cf0
3cf8
3d00
3d08
3d10
3d18
3d20
3d28
3d30
3d38
3d40
3d48
3d50
3d58
3d60
3d68
3d70
3d78
3d80
3d88
3d90
3d98
3da0
3da8
3db0
3db8
3dc0
3dc8
3dd0
3dd8
3de0
3de8
3df0
3df8
3e00
3e08
3e10
3e18
3e20
3e28
3e30
3e38
3e40
3e48
3e50
3e58
3e60
3e68
3e70
3e78
3e80
3e88
3e90
3e98
3ea0
3ea8
3eb0
3eb8
3ec0
3ec8
3ed0
3ed8
3ee0
3ee8
3ef0
3ef8
3f00
3f08
3f10
3f18
3f20
3f28
3f30
3f38
3f40
3f48
3f50
3f58
3f60
3f68
3f70
3f78
3f80
3f88
3f90
3f98
3fa0
3fa8
3fb0
3fb8
3fc0
3fc8
3fd0
3fd8
3fe0
3fe8
3ff0
3ff8
4000
4008
4010
4018
4020
4028
4030
4038
4040
4048
4050
4058
4060
4068
4070
4078
4080
4088
4090
4098
40a0
40a8
40b0
40b8
40c0
40c8
40d0
40d8
40e0
40e8
40f0
40f8
4100
4108
4110
4118
4120
4128
4130
4138
4140
4148
4150
4158
4160
4168
4170
4178
4180
4188
4190
4198
41a0
41a8
41b0
41b8
41c0
41c8
41d0
41d8
41e0
41e8
41f0
41f8
4200
4208
4210
4218
4220
4228
4230
4238
4240
4248
4250
4258
4260
4268
4270
4278
4280
4288
4290
4298
42a0
42a8
42b0
42b8
42c0
42c8
42d0
42d8
42e0
42e8
42f0
42f8
4300
4308
4310
4318
4320
4328
4330
4338
4340
4348
4350
4358
4360
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/design/BufFifo/SUB_RAMZ_LUT.vhd
0,0 → 1,109
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : SUB_RAMZ --
-- Design : EV_JPEG_ENC --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : SUB_RAMZ.VHD
-- Created : 22/03/2009
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all;
 
library std;
use std.textio.all;
entity SUB_RAMZ_LUT is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end SUB_RAMZ_LUT;
 
architecture RTL of SUB_RAMZ_LUT is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
--type mem_type is array (( 1296*8)-1 downto 0) of --/*1296*8*/
-- STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
impure function InitRamFromFile (RamFileName : in string) return mem_type is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : mem_type;
begin
for I in 0 to (2**RAMADDR_W)-1 loop
readline (RamFile, RamFileLine);
--Write (RamFileLine, I * 8);
hread(RamFileLine, RAM(I));
--write( (I * 8),RamFileLine );
--read (RamFileLine, RAM(I), LEFT, 10);
end loop;
return RAM;
end function;
signal mem : mem_type := InitRamFromFile("../design/BufFifo/counter_8.txt") ;
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
--attribute ram_style: string;
--attribute ram_style of mem : signal is "distributed";
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
/design/BufFifo/multiplier.vhd
0,0 → 1,80
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:18:01 03/12/2011
-- Design Name:
-- Module Name: multiplier - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity multiplier is
port (
CLK : in std_logic;
RST : in std_logic;
--
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
--
result : out std_logic_vector(31 downto 0);
threshold : out std_logic_vector(31 downto 0)
);
end multiplier;
 
architecture Behavioral of multiplier is
 
signal prev_x : std_logic_vector(15 downto 0);
signal prev_y : std_logic_vector(15 downto 0);
 
begin
process(CLK, RST)
begin
if (RST = '1') then
result <= x"00000000";
threshold <= x"00000000";
prev_x <= x"0000";
prev_y <= x"0000";
elsif (CLK'event and CLK = '1') then
if (prev_x /= img_size_x or prev_y /= img_size_y) then
result <= img_size_x * img_size_y;
threshold <= img_size_x * x"0007";
end if;
prev_x <= img_size_x;
prev_y <= img_size_y;
end if;
end process;
 
end Behavioral;
 
/design/mdct/DCT1D.vhd
1,334 → 1,386
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
library WORK;
use WORK.MDCT_PKG.all;
 
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
 
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
 
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
begin
 
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
library WORK;
use WORK.MDCT_PKG.all;
 
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
 
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
 
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal ramwe_d1 : STD_LOGIC;
signal ramwe_d2 : STD_LOGIC;
signal ramwe_d3 : STD_LOGIC;
signal ramwe_d4 : STD_LOGIC;
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d5 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_d6 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal wmemsel_d1 : STD_LOGIC;
signal wmemsel_d2 : STD_LOGIC;
signal wmemsel_d3 : STD_LOGIC;
signal wmemsel_d4 : STD_LOGIC;
signal wmemsel_d5 : STD_LOGIC;
signal wmemsel_d6 : STD_LOGIC;
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal fpr_out : STD_LOGIC_VECTOR(DA_W-12-1 downto 0);
 
component FinitePrecRndNrst is
generic
(
C_IN_SZ : natural := 37;
C_OUT_SZ : natural := 16;
C_FRAC_SZ : natural := 15
);
port (
CLK : in std_logic;
RST : in std_logic;
datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
dataval : in std_logic;
dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
clip_inc : out std_logic;
dval_out : out std_logic
);
end component;
begin
 
ramwaddro <= ramwaddro_d6;
--ramwe <= ramwe_d4;
--ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
odv <= ramwe_d4;
dcto <= STD_LOGIC_VECTOR(RESIZE(SIGNED(fpr_out),12));
ramdatai <= fpr_out;
U_FinitePrecRndNrst : FinitePrecRndNrst
generic map(
C_IN_SZ => DA_W,
C_OUT_SZ => DA_W-12,
C_FRAC_SZ => 12
)
port map(
CLK => clk,
RST => rst,
 
datain => dcto_4,
dataval => ramwe_d4,
dataout => fpr_out,
 
clip_inc => open,
dval_out => ramwe
);
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif clk = '1' and clk'event then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
 
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
ramwaddro_d5 <= ramwaddro_d4;
ramwaddro_d6 <= ramwaddro_d5;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
wmemsel_d5 <= wmemsel_d4;
wmemsel_d6 <= wmemsel_d5;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
/design/mdct/DCT2D.VHD
1,357 → 1,398
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
library WORK;
use WORK.MDCT_PKG.all;
 
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
 
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
begin
 
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_5(DA2_W-1 downto 12);
odv <= odv_d5;
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
 
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
library WORK;
use WORK.MDCT_PKG.all;
 
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
 
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
signal odv_s : std_logic;
signal dcto_s : std_logic_vector(OP_W-1 downto 0);
 
component FinitePrecRndNrst is
generic
(
C_IN_SZ : natural := 37;
C_OUT_SZ : natural := 16;
C_FRAC_SZ : natural := 15
);
port (
CLK : in std_logic;
RST : in std_logic;
datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
dataval : in std_logic;
dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
clip_inc : out std_logic;
dval_out : out std_logic
);
end component;
 
begin
 
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
 
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_s;
odv <= odv_s;
U_FinitePrecRndNrst : FinitePrecRndNrst
generic map(
C_IN_SZ => DA2_W,
C_OUT_SZ => DA2_W-12,
C_FRAC_SZ => 12
)
port map(
CLK => clk,
RST => rst,
 
datain => dcto_5,
dataval => odv_d5,
dataout => dcto_s,
 
clip_inc => open,
dval_out => odv_s
);
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
 
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
 
/design/mdct/FinitePrecRndNrst.v
0,0 → 1,111
//-----------------------------------------------------------------------------
// Title : Finite Precision Symmetric Reduction module
 
// Introduces 2 clock cycles of latency
 
`timescale 1 ns / 100 ps
 
module FinitePrecRndNrst
#(
parameter C_IN_SZ=37,
C_OUT_SZ=16,
C_FRAC_SZ=15
)
( input wire CLK,
input wire RST,
input wire signed [C_IN_SZ-1:0] datain,
input wire dataval,
output wire signed [C_OUT_SZ-1:0] dataout,
output reg clip_inc,
output reg dval_out
);
wire sign;
wire signed [C_IN_SZ-1:0] rc_val;
reg signed [C_IN_SZ-1:0] data_round_f;
wire signed [C_IN_SZ-C_FRAC_SZ-1:0] data_round;
reg signed [C_OUT_SZ-1:0] data_rs;
reg dataval_d1;
reg sign_d1;
assign sign = datain[C_IN_SZ-1];
assign rc_val = { {(C_IN_SZ-C_FRAC_SZ){1'b0}}, 1'b1, {(C_FRAC_SZ-1){1'b0}} };
 
always @(posedge CLK or posedge RST)
if(RST)
begin
data_round_f <= 'b0;
dataval_d1 <= 1'b0;
sign_d1 <= 1'b0;
dval_out <= 1'b0;
end
else
begin
data_round_f <= datain + rc_val;
dataval_d1 <= dataval;
dval_out <= dataval_d1;
sign_d1 <= sign;
end
assign data_round = data_round_f[C_IN_SZ-1:C_FRAC_SZ];
// saturation / clipping
always @(posedge CLK or posedge RST)
if(RST)
begin
data_rs <= 'b0;
clip_inc <= 1'b0;
end
else
begin
clip_inc <= 1'b0;
// clipping condition
if(
(
(C_IN_SZ-C_FRAC_SZ != C_OUT_SZ) &&
(~(&data_round[C_IN_SZ-C_FRAC_SZ-1 : C_OUT_SZ-1])) ==
(|(data_round[C_IN_SZ-C_FRAC_SZ-1 : C_OUT_SZ-1]))
)
|| // special case
(
(C_IN_SZ-C_FRAC_SZ == C_OUT_SZ) &&
(data_round[C_IN_SZ-C_FRAC_SZ-1] != sign_d1) &&
data_round != {C_OUT_SZ{1'b0}}
)
)
begin
// clipping counter
if(dataval_d1)
clip_inc <= 1'b1;
if(sign_d1)
// do saturation
data_rs <= -(2**(C_OUT_SZ)/2)+1;
else
// do saturation
data_rs <= (2**(C_OUT_SZ)/2)-1;
end
else
data_rs <= data_round[C_OUT_SZ-1:0];
end
assign dataout = data_rs;
//always @(posedge CLK or posedge RST)
// if(RST)
// begin
// dataout <= 0;
// end
// else
// begin
// dataout <= data_rs;
// end
 
 
endmodule
 
/design/common/JPEG_PKG.vhd
32,12 → 32,12
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 2048;
constant C_MAX_LINE_WIDTH : integer := 640;
-- memory/performance tradeoff
-- 8 extra lines highest performance
-- 0 extra lines lowest area
constant C_EXTRA_LINES : integer := 8; -- from 0 to 8
--constant C_EXTRA_LINES : integer := 0; -- from 0 to 8
 
-- 24 bit format RGB/YCbCr 888 bits

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