URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

Subversion Repositories mod_mult_exp

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```
/mod_mult_exp
```
from Rev 4 to Rev 5
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Compare Path: Rev

With Path: Rev

Rev 4 → Rev 5

/trunk/bench/vhdl/mod_exp/ModExp32bitTB.vhd

0,0 → 1,229

/trunk/bench/vhdl/mod_exp/ModExp512bitTB.vhd

0,0 → 1,235

/trunk/bench/vhdl/mod_exp/ModExp64bitTB.vhd

0,0 → 1,229

/trunk/rtl/vhdl/commons/properties_32bit.vhd

62,45 → 62,35

/trunk/rtl/vhdl/commons/properties_64bit.vhd

62,45 → 62,35

/trunk/rtl/vhdl/commons/properties.vhd

61,45 → 61,35

/trunk/rtl/vhdl/commons/Reg.vhd

0,0 → 1,84

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_xmdf.tcl

0,0 → 1,263

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.ucf

0,0 → 1,57

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_prod.vhd

0,0 → 1,270

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.xdc

0,0 → 1,54

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design/blockMemory_exdes.vhd

0,0 → 1,166

/trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/example_design Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/random.vhd (revision 5) @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_ncsim.sv (revision 5) @@ -0,0 +1,21 @@ + + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_ncsim.sh (revision 5) @@ -0,0 +1,70 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + + +mkdir work +echo "Compiling Core VHDL UNISIM/Behavioral model" +ncvhdl -v93 -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Elaborating Design" +ncelab -access +rwc work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_vcs.sh (revision 5) @@ -0,0 +1,69 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../../blockMemory.vhd +vhdlan ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + +echo "Elaborating Design" +vcs +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_isim.bat (revision 5) @@ -0,0 +1,68 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\..\blockMemory.vhd +vhpcomp -work work ..\..\example_design\blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + +fuse work.blockMemory_tb -L unisims -L xilinxcorelib -o blockMemory_tb.exe + + +.\blockMemory_tb.exe -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional/simulate_mti.do (revision 5) @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + +vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/functional Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/data_gen.vhd (revision 5) @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/addr_gen.vhd (revision 5) @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/checker.vhd (revision 5) @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG Generator v8.4 Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- + +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_ncsim.sv (revision 5) @@ -0,0 +1,20 @@ + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_ncsim.sh (revision 5) @@ -0,0 +1,78 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +mkdir work + + +ncvhdl -v93 -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :blockMemory_synth_inst:BMG_PORT,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + + +echo "Elaborating Design" +ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_vcs.sh (revision 5) @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh + +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + + +echo "Elaborating Design" +vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_isim.bat (revision 5) @@ -0,0 +1,67 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\implement\results\routed.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + + + fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe + +.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing/simulate_mti.do (revision 5) @@ -0,0 +1,75 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + + vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=../../implement/results/routed.sdf $work.blockMemory_tb -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/timing Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_synth.vhd (revision 5) @@ -0,0 +1,289 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY blockMemory_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS + + +COMPONENT blockMemory_exdes + PORT ( + --Inputs - Port A + RSTA : IN STD_LOGIC; --opt port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 32, + READ_WIDTH => 32 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_EN_R, + DATA_IN => DOUTA, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLK => clk_in_i, + RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + WEA => WEA, + CHECK_DATA => CHECKER_EN + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: blockMemory_exdes PORT MAP ( + --Port A + RSTA => RSTA, + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + DOUTA => DOUTA, + CLKA => CLKA + + ); +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/blockMemory_tb.vhd (revision 5) @@ -0,0 +1,129 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: blockMemory_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY blockMemory_tb IS +END ENTITY; + + +ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "Simulation Complete" + SEVERITY FAILURE; + END IF; +END PROCESS; + + blockMemory_synth_inst:ENTITY work.blockMemory_synth + PORT MAP( + CLK_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_stim_gen.vhd (revision 5) @@ -0,0 +1,243 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Stimulus Generator For Single Port Ram +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SRAM +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; + +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC_SRAM IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC_SRAM; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS + SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + + CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32); + SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_WRITE : STD_LOGIC := '0'; + SIGNAL DO_READ : STD_LOGIC := '0'; + SIGNAL COUNT_NO : INTEGER :=0; + SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); +BEGIN + WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0); + READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0); + ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ; + DINA <= DINA_INT ; + + CHECK_DATA <= DO_READ; + +RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + +WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + +WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 32, + DOUT_WIDTH => 32, + DATA_PART_CNT => DATA_PART_CNT_A, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + +WR_RD_PROCESS: PROCESS (CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + ELSIF(COUNT_NO < 4) THEN + DO_WRITE <= '1'; + DO_READ <= '0'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO< 8) THEN + DO_WRITE <= '0'; + DO_READ <= '1'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO=8) THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + END IF; + END IF; +END PROCESS; + +BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(0), + CLK => CLK, + RST => RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG; + + WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ; + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation/bmg_tb_pkg.vhd (revision 5) @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/simulation Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (revision 5) @@ -0,0 +1,237 @@ + + +blk_mem_gen_v7_1_vinfo + + + +










    +                Core name: Xilinx LogiCORE Block Memory Generator








    +                Version: 7.1








    +                Release: ISE 14.1 / Vivado 2012.1








    +                Release Date: April 24, 2012








    +








    +








    +================================================================================








    +








    +This document contains the following sections:








    +








    +This document contains the following sections:








    +








    +1. Introduction








    +2. New Features








    +  2.1 ISE








    +  2.2 Vivado








    +3. Supported Devices








    +  3.1 ISE








    +  3.2 Vivado








    +4. Resolved Issues








    +  4.1 ISE








    +  4.2 Vivado








    +5. Known Issues








    +  5.1 ISE








    +  5.2 Vivado








    +6. Technical Support








    +7. Core Release History








    +8. Legal Disclaimer








    +








    +================================================================================








    +








    +








    +1. INTRODUCTION








    +








    +For installation instructions for this release, please go to:








    +








    +  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm








    +








    +For system requirements:








    +








    +   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm








    +








    +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1








    +solution. For the latest core updates, see the product page at:








    +








    + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm








    +








    +








    +................................................................................








    +2. NEW FEATURES








    +








    +








    +  2.1 ISE








    +








    +    - ISE 14.1 software support








    +    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,








    +      and Automotive Zynq device support








    +








    +








    +  2.2 Vivado








    +








    +    - 2012.1 software support








    +    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,








    +      and Automotive Zynq device support








    +








    +








    +................................................................................








    +3. SUPPORTED DEVICES








    +








    +








    +  3.1 ISE








    +








    +  The following device families are supported by the core for this release.








    +








    +  All 7 Series devices








    +  Zynq-7000 devices








    +  All Virtex-6 devices








    +  All Spartan-6 devices








    +  All Virtex-5 devices








    +  All Spartan-3 devices








    +  All Virtex-4 devices








    +








    +








    +  3.2 Vivado








    +  All 7 Series devices








    +  Zynq-7000 devices








    +








    +








    +................................................................................








    +4. RESOLVED ISSUES








    +








    +








    +The following issues are resolved in Block Memory Generator v7.1:








    +








    +  4.1 ISE








    +








    +








    +  4.2 Vivado








    +








    +








    +................................................................................








    +5. KNOWN ISSUES








    +








    +








    +  5.1 ISE








    +








    +    The following are known issues for v7.1 of this core at time of release:








    +








    +    1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)








    +      Work around: The user must review the possible scenarios that causes the collission and revise








    +       their design to avoid those situations.








    +      - CR588505








    +








    +      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with








    +            Write Mode = Read First in conjunction with asynchronous clocking








    +








    +    2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.








    +








    +    3. Core does not generate for large memories. Depending on the








    +       machine the ISE CORE Generator software runs on, the maximum size of the memory that








    +       can be generated will vary.  For example, a Dual Pentium-4 server








    +       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes








    +      - CR 415768








    +      - AR 24034








    +








    +








    +  5.2 Vivado








    +








    +  The most recent information, including known issues, workarounds, and resolutions for








    +  this version is provided in the IP Release Notes User Guide located at








    +








    +         www.xilinx.com/support/documentation/user_guides/xtp025.pdf








    +








    +








    +








    +................................................................................








    +6. TECHNICAL SUPPORT








    +








    +To obtain technical support, create a WebCase at www.xilinx.com/support.








    +Questions are routed to a team with expertise using this product.








    +








    +Xilinx provides technical support for use of this product when used








    +according to the guidelines described in the core documentation, and








    +cannot guarantee timing, functionality, or support of this product for








    +designs that do not follow specified guidelines.








    +








    +








    +








    +7. CORE RELEASE HISTORY








    +








    +Date        By            Version      Description








    +================================================================================








    +04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support








    +01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support








    +06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;








    +03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support








    +09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support








    +07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support








    +04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support








    +03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue








    +12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power








    +                                       Device support; Automotive Spartan 3A








    +                                       DSP device support








    +09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3








    +06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2








    +04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1








    +09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8








    +03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7








    +10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6








    +07/2007     Xilinx, Inc.  2.5          Revised to v2.5








    +04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1








    +02/2007     Xilinx, Inc.  2.4          Revised to v2.4








    +11/2006     Xilinx, Inc.  2.3          Revised to v2.3








    +09/2006     Xilinx, Inc.  2.2          Revised to v2.2








    +06/2006     Xilinx, Inc.  2.1          Revised to v2.1








    +01/2006     Xilinx, Inc.  1.1          Initial release








    +================================================================================








    +








    +8. Legal Disclaimer








    +








    + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.








    +








    + This file contains confidential and proprietary information








    + of Xilinx, Inc. and is protected under U.S. and








    + international copyright and other intellectual property








    + laws.








    +








    + DISCLAIMER








    + This disclaimer is not a license and does not grant any








    + rights to the materials distributed herewith. Except as








    + otherwise provided in a valid license issued to you by








    + Xilinx, and to the maximum extent permitted by applicable








    + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND








    + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES








    + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING








    + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-








    + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and








    + (2) Xilinx shall not be liable (whether in contract or tort,








    + including negligence, or under any other theory of








    + liability) for any loss or damage of any kind or nature








    + related to, arising under or in connection with these








    + materials, including for any direct, or any indirect,








    + special, incidental, or consequential loss or damage








    + (including loss of data, profits, goodwill, or any type of








    + loss or damage suffered as a result of any action brought








    + by a third party) even if such damage or loss was








    + reasonably foreseeable or Xilinx had been advised of the








    + possibility of the same.








    +








    + CRITICAL APPLICATIONS








    + Xilinx products are not designed or intended to be fail-








    + safe, or for use in any application requiring fail-safe








    + performance, such as life-support or safety devices or








    + systems, Class III medical devices, nuclear facilities,








    + applications related to the deployment of airbags, or any








    + other applications that could lead to death, personal








    + injury, or severe property or environmental damage








    + (individually and collectively, "Critical








    + Applications"). Customer assumes the sole risk and








    + liability of any use of Xilinx products in Critical








    + Applications, subject only to applicable laws and








    + regulations governing limitations on product liability.








    +








    + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS








    + PART OF THIS FILE AT ALL TIMES.








    +








    +








    +

+ + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc/blk_mem_gen_ds512.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/blk_mem_gen_v7_1_readme.txt (revision 5) @@ -0,0 +1,226 @@ + Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.bat (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy blockMemory_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\blockMemory.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\blockMemory_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/implement.sh (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp blockMemory_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../blockMemory.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/blockMemory_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.scr (revision 5) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent blockMemory_exdes +-p xc3s500e-fg320-5 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn blockMemory_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/xst.prj (revision 5) @@ -0,0 +1 @@ +work ../example_design/blockMemory_exdes.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_rdn.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement/planAhead_ise.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory/implement Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.v (revision 5) @@ -0,0 +1,180 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module blockMemory( + clka, + rsta, + wea, + addra, + dina, + douta +); + +input clka; +input rsta; +input [0 : 0] wea; +input [3 : 0] addra; +input [511 : 0] dina; +output [511 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V7_1 #( + .C_ADDRA_WIDTH(4), + .C_ADDRB_WIDTH(4), + .C_ALGORITHM(0), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(1), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(0), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(6), + .C_READ_DEPTH_A(16), + .C_READ_DEPTH_B(16), + .C_READ_WIDTH_A(512), + .C_READ_WIDTH_B(512), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(16), + .C_WRITE_DEPTH_B(16), + .C_WRITE_MODE_A("READ_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(512), + .C_WRITE_WIDTH_B(512), + .C_XDEVICEFAMILY("spartan3e") + ) + inst ( + .CLKA(clka), + .RSTA(rsta), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .ENA(), + .REGCEA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ncf =================================================================== Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.ngc (revision 5) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ + +

+ + + + + + + + +

trunk/rtl/vhdl/mod_exp/blockMemory32/xlnx_auto_0_xdb Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/gen_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator regen command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_regen "blockMemory" xc3s500e-5fg320 VHDL CURRENT ] + +if { $result == 0 } { + puts "Core Generator regen command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator regen command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator regen cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs/cg.xmsgs (revision 5) @@ -0,0 +1,30 @@ + + + +Generating IP... + + +A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten. + + +A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten. + + +Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis + + +Pre-processing HDL files for 'blockMemory'... + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/blockMemory.lso (revision 5) @@ -0,0 +1 @@ +work Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs/xst.xmsgs (revision 5) @@ -0,0 +1,412 @@ + + + +Message file "usenglish/ip.msg" wasn't found. + + +0: (0,0) : 72x256 u:32 + + +0: (0,0) : 72x256 u:32 + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 370: Net <doutb_i[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <doutb> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +Input <S_AXI_AWID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WDATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEA<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'dina_pad<71:67>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<62:58>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<53:49>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<44:40>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<35:31>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<26:22>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<17:13>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dina_pad<8:4>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<71:67>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<62:58>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<53:49>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<44:40>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<35:31>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<26:22>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<17:13>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal 'dinb_pad<8:4>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (00000). + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <DOUTB_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RDADDRECC_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + +You have chosen to run a version of XST which is not the default solution +for the specified device family. You are free to use it in order to take +advantage of its enhanced HDL parsing/elaboration capabilities. However, +please be aware that you may be impacted by language support differences. +This version may also result in circuit performance and device utilization +differences for your particular design. You can always revert back to the +default XST solution by setting the "use_new_parser" option to value "no" +on the XST command line or in the XST process properties panel. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/tmp/_cg Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/tmp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/tmp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/tmp (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32/tmp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_flist.txt (revision 5) @@ -0,0 +1,60 @@ +# Output products list for +_xmsgs\pn_parser.xmsgs +blockMemory.asy +blockMemory.gise +blockMemory.ngc +blockMemory.sym +blockMemory.vhd +blockMemory.vho +blockMemory.xco +blockMemory.xise +blockMemory\blk_mem_gen_v7_1_readme.txt +blockMemory\doc\blk_mem_gen_ds512.pdf +blockMemory\doc\blk_mem_gen_v7_1_vinfo.html +blockMemory\example_design\blockMemory_exdes.ucf +blockMemory\example_design\blockMemory_exdes.vhd +blockMemory\example_design\blockMemory_exdes.xdc +blockMemory\example_design\blockMemory_prod.vhd +blockMemory\implement\implement.bat +blockMemory\implement\implement.sh +blockMemory\implement\planAhead_ise.bat +blockMemory\implement\planAhead_ise.sh +blockMemory\implement\planAhead_ise.tcl +blockMemory\implement\planAhead_rdn.bat +blockMemory\implement\planAhead_rdn.sh +blockMemory\implement\planAhead_rdn.tcl +blockMemory\implement\xst.prj +blockMemory\implement\xst.scr +blockMemory\simulation\addr_gen.vhd +blockMemory\simulation\blockMemory_synth.vhd +blockMemory\simulation\blockMemory_tb.vhd +blockMemory\simulation\bmg_stim_gen.vhd +blockMemory\simulation\bmg_tb_pkg.vhd +blockMemory\simulation\checker.vhd +blockMemory\simulation\data_gen.vhd +blockMemory\simulation\functional\simcmds.tcl +blockMemory\simulation\functional\simulate_isim.bat +blockMemory\simulation\functional\simulate_mti.bat +blockMemory\simulation\functional\simulate_mti.do +blockMemory\simulation\functional\simulate_mti.sh +blockMemory\simulation\functional\simulate_ncsim.sh +blockMemory\simulation\functional\simulate_vcs.sh +blockMemory\simulation\functional\ucli_commands.key +blockMemory\simulation\functional\vcs_session.tcl +blockMemory\simulation\functional\wave_mti.do +blockMemory\simulation\functional\wave_ncsim.sv +blockMemory\simulation\random.vhd +blockMemory\simulation\timing\simcmds.tcl +blockMemory\simulation\timing\simulate_isim.bat +blockMemory\simulation\timing\simulate_mti.bat +blockMemory\simulation\timing\simulate_mti.do +blockMemory\simulation\timing\simulate_mti.sh +blockMemory\simulation\timing\simulate_ncsim.sh +blockMemory\simulation\timing\simulate_vcs.sh +blockMemory\simulation\timing\ucli_commands.key +blockMemory\simulation\timing\vcs_session.tcl +blockMemory\simulation\timing\wave_mti.do +blockMemory\simulation\timing\wave_ncsim.sv +blockMemory_flist.txt +blockMemory_xmdf.tcl +summary.log Index: trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.log (revision 5) @@ -0,0 +1,63 @@ +INFO:sim:172 - Generating IP... +Applying current project options... +Finished applying current project options. +WARNING:sim - A core named 'blockMemory' already exists in the project. Output + products for this core may be overwritten. +Resolving generics for 'blockMemory'... +WARNING:sim - A core named 'blockMemory' already exists in the project. Output + products for this core may be overwritten. +Applying external generics to 'blockMemory'... +Delivering associated files for 'blockMemory'... +WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for + VHDL synthesis +Delivering EJava files for 'blockMemory'... +Generating implementation netlist for 'blockMemory'... +INFO:sim - Pre-processing HDL files for 'blockMemory'... +Running synthesis for 'blockMemory' +Running ngcbuild... +Writing VHO instantiation template for 'blockMemory'... +Writing VHDL behavioral simulation model for 'blockMemory'... +Generating ASY schematic symbol... +INFO:sim:949 - Finished generation of ASY schematic symbol. +Generating SYM schematic symbol for 'blockMemory'... +Generating metadata file... +Generating ISE project... +XCO file found: blockMemory.xco +XMDF file found: blockMemory_xmdf.tcl +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.asy -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc -view all -origin_type created +Checking file "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" for project device match ... +File "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" device information matches project device. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.sym -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vhd -view all -origin_type created +INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i + praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp + /_cg/blockMemory.vhd" into library work +INFO:ProjectMgmt - Parsing design hierarchy completed successfully. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vho -view all -origin_type imported +INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. + Please set the new top explicitly by running the "project set top" command. + To re-calculate the new top automatically, set the "Auto Implementation Top" + property to true. +Top level has been set to "/blockMemory" +Generating README file... +Generating FLIST file... +INFO:sim:948 - Finished FLIST file generation. +Launching README viewer... +Moving files to output directory... +Finished moving files to output directory +Wrote CGP file for project 'blockMemory'. Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd (revision 5) @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY blockMemory IS + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END blockMemory; + +ARCHITECTURE blockMemory_a OF blockMemory IS +-- synthesis translate_off +COMPONENT wrapped_blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_blockMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_1(behavioral) + GENERIC MAP ( + c_addra_width => 4, + c_addrb_width => 4, + c_algorithm => 0, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 1, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 0, + c_mux_pipeline_stages => 0, + c_prim_type => 6, + c_read_depth_a => 16, + c_read_depth_b => 16, + c_read_width_a => 32, + c_read_width_b => 32, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 16, + c_write_depth_b => 16, + c_write_mode_a => "READ_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 32, + c_write_width_b => 32, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- synthesis translate_on + +END blockMemory_a; Index: trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/edit_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "blockMemory" xc3s500e-5fg320 VHDL ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.gise (revision 5) @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory_beh.cgp (revision 5) @@ -0,0 +1,22 @@ +# Date: Sat Dec 22 01:24:09 2012 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +SET workingdirectory = .\tmp\ + +# CRC: 46f7aa00 Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.veo (revision 5) @@ -0,0 +1,70 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 * +* * +* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * +* Block Memory and Single Port Block Memory LogiCOREs, but is not a * +* direct drop-in replacement. It should be used in all new Xilinx * +* designs. The core supports RAM and ROM functions over a wide range of * +* widths and depths. Use this core to generate block memories with * +* symmetric or asymmetric read and write port widths, as well as cores * +* which can perform simultaneous write operations to separate * +* locations, and simultaneous read operations from the same location. * +* For more information on differences in interface and feature support * +* between this core and the Dual Port Block Memory and Single Port * +* Block Memory LogiCOREs, please consult the data sheet. * +*******************************************************************************/ + +// Interfaces: +// AXI_SLAVE_S_AXI +// AXI_SLAVE +// AXILite_SLAVE_S_AXI +// AXILite_SLAVE + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +blockMemory your_instance_name ( + .clka(clka), // input clka + .rsta(rsta), // input rsta + .wea(wea), // input [0 : 0] wea + .addra(addra), // input [3 : 0] addra + .dina(dina), // input [511 : 0] dina + .douta(douta) // output [511 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.xco (revision 5) @@ -0,0 +1,106 @@ +############################################################## +# +# Xilinx Core Generator version 14.2 +# Date: Sun Feb 01 11:31:51 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Fixed_Primitives +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=blockMemory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Single_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=256x72 +CSET read_width_a=32 +CSET read_width_b=32 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=true +CSET use_rstb_pin=false +CSET write_depth_a=16 +CSET write_width_a=32 +CSET write_width_b=32 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-01T17:17:26Z +# END Extra information +GENERATE +# CRC: 442de25c Index: trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/summary.log (revision 5) @@ -0,0 +1,18 @@ + +User Configuration +------------------------------------- +Algorithm : Fixed_Primitives +Memory Type : Single_Port_RAM +Port A Read Width : 32 +Port A Write Width : 32 +Memory Depth : 16 +-------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : 1 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 8.073006 mW +---------------------------------------------------------- Index: trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/coregen.cgc (revision 5) @@ -0,0 +1,725 @@ + + + xilinx.com + project + coregen + 1.0 + + + blockMemory + + + blockMemory + Native + AXI4_Full + Memory_Slave + false + 4 + Single_Port_RAM + false + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Fixed_Primitives + 256x72 + false + 64 + 16 + 64 + READ_FIRST + Always_Enabled + 64 + 64 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + false + no_coe_file_loaded + false + 0 + true + false + CE + 0 + false + false + CE + 0 + SYNC + false + 100 + 50 + 100 + 50 + 100 + 100 + ALL + false + false + spartan3 + spartan3e + E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_cg/ + 0 + 1 + 0 + 0 + 4 + 0 + 9 + 0 + 6 + 0 + no_coe_file_loaded + 0 + 0 + SYNC + 1 + CE + 0 + 0 + 0 + 0 + 0 + 1 + READ_FIRST + 64 + 64 + 16 + 16 + 4 + 0 + CE + 0 + 0 + 0 + 0 + 0 + 1 + WRITE_FIRST + 64 + 64 + 16 + 16 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ALL + 0 + 0 + 0 + 0 + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2012-05-01+17:17 + + + + + customization_generator + + ./summary.log + unknown + Sun Feb 01 11:01:05 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + model_parameter_resolution_generator + + ./summary.log + unknown + Sun Feb 01 11:01:18 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + ip_xco_generator + + ./blockMemory.xco + xco + Sun Feb 01 11:01:19 GMT 2015 + 0xB3588484 + generationID_4013899584 + + + + associated_files_generator + + ./blockMemory/blk_mem_gen_v7_1_readme.txt + ignore + txt + Sat Jul 21 06:09:39 GMT 2012 + 0xD29D9619 + generationID_4013899584 + + + ./blockMemory/doc/blk_mem_gen_ds512.pdf + ignore + pdf + Sat Jul 21 06:09:39 GMT 2012 + 0xC67523A8 + generationID_4013899584 + + + ./blockMemory/doc/blk_mem_gen_v7_1_vinfo.html + ignore + unknown + Sat Jul 21 06:09:39 GMT 2012 + 0x19E371FD + generationID_4013899584 + + + + ejava_generator + + ./blockMemory/example_design/blockMemory_exdes.ucf + ignore + ucf + Sun Feb 01 11:01:22 GMT 2015 + 0xC44C6B6D + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_exdes.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xC531B9D3 + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_exdes.xdc + ignore + xdc + Sun Feb 01 11:01:22 GMT 2015 + 0x7684D6D4 + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_prod.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xBCC35C04 + generationID_4013899584 + + + ./blockMemory/implement/implement.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x73DC98D0 + generationID_4013899584 + + + ./blockMemory/implement/implement.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xDA8C5F63 + generationID_4013899584 + + + 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01 11:01:22 GMT 2015 + 0x0ACE6523 + generationID_4013899584 + + + ./blockMemory/simulation/addr_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xC4BD0686 + generationID_4013899584 + + + ./blockMemory/simulation/blockMemory_synth.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x242B5734 + generationID_4013899584 + + + ./blockMemory/simulation/blockMemory_tb.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x403EDE43 + generationID_4013899584 + + + ./blockMemory/simulation/bmg_stim_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xB51AD3DA + generationID_4013899584 + + + ./blockMemory/simulation/bmg_tb_pkg.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x888E222F + generationID_4013899584 + + + ./blockMemory/simulation/checker.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x165912E8 + generationID_4013899584 + + + ./blockMemory/simulation/data_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xAAF37274 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simcmds.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x32EA978C + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_isim.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x5732BCC0 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFFDC1F87 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_ncsim.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x7DAF5A7C + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_vcs.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x0377E85E + generationID_4013899584 + + + ./blockMemory/simulation/functional/ucli_commands.key + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x124DD850 + generationID_4013899584 + + + ./blockMemory/simulation/functional/vcs_session.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x65C492A4 + generationID_4013899584 + + + ./blockMemory/simulation/functional/wave_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xD1AE9DBA + generationID_4013899584 + + + ./blockMemory/simulation/functional/wave_ncsim.sv + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFA4242CF + generationID_4013899584 + + + ./blockMemory/simulation/random.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x63A1BAB3 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simcmds.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x32EA978C + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_isim.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x4934A6A9 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x73AA9BB8 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_ncsim.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFBC651DC + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_vcs.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x4D9140C3 + generationID_4013899584 + + + ./blockMemory/simulation/timing/ucli_commands.key + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x124DD850 + generationID_4013899584 + + + ./blockMemory/simulation/timing/vcs_session.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0xB2A5A6F2 + generationID_4013899584 + + + ./blockMemory/simulation/timing/wave_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x9F72A3C7 + generationID_4013899584 + + + ./blockMemory/simulation/timing/wave_ncsim.sv + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x3E2BD0E3 + generationID_4013899584 + + + + ngc_netlist_generator + + ./blockMemory.ngc + ngc + Sun Feb 01 11:03:12 GMT 2015 + 0xB01C4161 + generationID_4013899584 + + + + obfuscate_netlist_generator + + + padded_implementation_netlist_generator + + + instantiation_template_generator + + ./blockMemory.vho + vho + Sun Feb 01 11:03:15 GMT 2015 + 0x533BD793 + generationID_4013899584 + + + + structural_simulation_model_generator + + ./blockMemory.vhd + vhdl + Sun Feb 01 11:03:16 GMT 2015 + 0x4F617396 + generationID_4013899584 + + + + asy_generator + + ./blockMemory.asy + asy + Sun Feb 01 11:03:25 GMT 2015 + 0xD23467E4 + generationID_4013899584 + + + ./summary.log + unknown + Sun Feb 01 11:03:25 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + xmdf_generator + + ./blockMemory_xmdf.tcl + tclXmdf + tcl + Sun Feb 01 11:03:25 GMT 2015 + 0x0F84EBAC + generationID_4013899584 + + + + ise_generator + + ./_xmsgs/pn_parser.xmsgs + ignore + unknown + Sun Feb 01 11:03:38 GMT 2015 + 0x8B9E9C83 + generationID_4013899584 + + + ./blockMemory.gise + ignore + gise + Sun Feb 01 11:03:38 GMT 2015 + 0x12517467 + generationID_4013899584 + + + ./blockMemory.xise + ignore + xise + Sun Feb 01 11:03:38 GMT 2015 + 0xBEBA0475 + generationID_4013899584 + + + + deliver_readme_generator + + + flist_generator + + ./blockMemory_flist.txt + ignore + txtFlist + txt + Sun Feb 01 11:03:39 GMT 2015 + 0x56F501F4 + generationID_4013899584 + + + + view_readme_generator + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.asy (revision 5) @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 blockMemory +RECTANGLE Normal 32 32 544 1376 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[3:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[31:0] +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rsta +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[31:0] +PINATTR Polarity OUT + Index: trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32/blockMemory.vho (revision 5) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 -- +-- -- +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port -- +-- Block Memory and Single Port Block Memory LogiCOREs, but is not a -- +-- direct drop-in replacement. It should be used in all new Xilinx -- +-- designs. The core supports RAM and ROM functions over a wide range of -- +-- widths and depths. Use this core to generate block memories with -- +-- symmetric or asymmetric read and write port widths, as well as cores -- +-- which can perform simultaneous write operations to separate -- +-- locations, and simultaneous read operations from the same location. -- +-- For more information on differences in interface and feature support -- +-- between this core and the Dual Port Block Memory and Single Port -- +-- Block Memory LogiCOREs, please consult the data sheet. -- +-------------------------------------------------------------------------------- + +-- Interfaces: +-- AXI_SLAVE_S_AXI +-- AXI_SLAVE +-- AXILite_SLAVE_S_AXI +-- AXILite_SLAVE +-- BRAM_PORTA +-- BRAM_PORTA +-- BRAM_PORTB +-- BRAM_PORTB + +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory32 =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory32 (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory32 (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory32 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_xmdf.tcl (revision 5) @@ -0,0 +1,263 @@ +# The package naming convention is _xmdf +package provide blockMemory_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::blockMemory_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::blockMemory_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name blockMemory +} +# ::blockMemory_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::blockMemory_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/blk_mem_gen_v7_1_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_v7_1_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_prod.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/addr_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_stim_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_tb_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/checker.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/data_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/random.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blockMemory +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_prod.vhd (revision 5) @@ -0,0 +1,270 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_prod.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan3e +-- C_XDEVICEFAMILY : spartan3e +-- C_INTERFACE_TYPE : 0 +-- C_ENABLE_32BIT_ADDRESS : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 0 +-- C_BYTE_SIZE : 9 +-- C_ALGORITHM : 0 +-- C_PRIM_TYPE : 6 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 1 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 0 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 0 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : READ_FIRST +-- C_WRITE_WIDTH_A : 512 +-- C_READ_WIDTH_A : 512 +-- C_WRITE_DEPTH_A : 16 +-- C_READ_DEPTH_A : 16 +-- C_ADDRA_WIDTH : 4 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 0 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 0 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 512 +-- C_READ_WIDTH_B : 512 +-- C_WRITE_DEPTH_B : 16 +-- C_READ_DEPTH_B : 16 +-- C_ADDRB_WIDTH : 4 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY blockMemory_prod IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END blockMemory_prod; + + +ARCHITECTURE xilinx OF blockMemory_prod IS + + COMPONENT blockMemory_exdes IS + PORT ( + --Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + + CLKA : IN STD_LOGIC + + + + + ); + END COMPONENT; + +BEGIN + + bmg0 : blockMemory_exdes + PORT MAP ( + --Port A + RSTA => RSTA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + DOUTA => DOUTA, + + CLKA => CLKA + + + + ); +END xilinx; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.ucf (revision 5) @@ -0,0 +1,57 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +################################################################################ Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.xdc (revision 5) @@ -0,0 +1,54 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] +################################################################################ Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design/blockMemory_exdes.vhd (revision 5) @@ -0,0 +1,166 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY blockMemory_exdes IS + PORT ( + --Inputs - Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END blockMemory_exdes; + + +ARCHITECTURE xilinx OF blockMemory_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT blockMemory IS + PORT ( + --Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + + CLKA : IN STD_LOGIC + + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + + + bmg0 : blockMemory + PORT MAP ( + --Port A + RSTA => RSTA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + DOUTA => DOUTA, + + CLKA => CLKA_buf + + + ); + +END xilinx; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/example_design Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/random.vhd (revision 5) @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_ncsim.sv (revision 5) @@ -0,0 +1,21 @@ + + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_ncsim.sh (revision 5) @@ -0,0 +1,70 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + + +mkdir work +echo "Compiling Core VHDL UNISIM/Behavioral model" +ncvhdl -v93 -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Elaborating Design" +ncelab -access +rwc work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_vcs.sh (revision 5) @@ -0,0 +1,69 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../../blockMemory.vhd +vhdlan ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + +echo "Elaborating Design" +vcs +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_isim.bat (revision 5) @@ -0,0 +1,68 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\..\blockMemory.vhd +vhpcomp -work work ..\..\example_design\blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + +fuse work.blockMemory_tb -L unisims -L xilinxcorelib -o blockMemory_tb.exe + + +.\blockMemory_tb.exe -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional/simulate_mti.do (revision 5) @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + +vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/functional Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/data_gen.vhd (revision 5) @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/addr_gen.vhd (revision 5) @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/checker.vhd (revision 5) @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG Generator v8.4 Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- + +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_ncsim.sv (revision 5) @@ -0,0 +1,20 @@ + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_ncsim.sh (revision 5) @@ -0,0 +1,78 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +mkdir work + + +ncvhdl -v93 -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :blockMemory_synth_inst:BMG_PORT,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + + +echo "Elaborating Design" +ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_vcs.sh (revision 5) @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh + +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + + +echo "Elaborating Design" +vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_isim.bat (revision 5) @@ -0,0 +1,67 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\implement\results\routed.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + + + fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe + +.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing/simulate_mti.do (revision 5) @@ -0,0 +1,75 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + + vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=../../implement/results/routed.sdf $work.blockMemory_tb -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/timing Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_tb.vhd (revision 5) @@ -0,0 +1,129 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: blockMemory_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY blockMemory_tb IS +END ENTITY; + + +ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "Simulation Complete" + SEVERITY FAILURE; + END IF; +END PROCESS; + + blockMemory_synth_inst:ENTITY work.blockMemory_synth + PORT MAP( + CLK_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/blockMemory_synth.vhd (revision 5) @@ -0,0 +1,289 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY blockMemory_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS + + +COMPONENT blockMemory_exdes + PORT ( + --Inputs - Port A + RSTA : IN STD_LOGIC; --opt port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTA: STD_LOGIC_VECTOR(511 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 512, + READ_WIDTH => 512 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_EN_R, + DATA_IN => DOUTA, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLK => clk_in_i, + RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + WEA => WEA, + CHECK_DATA => CHECKER_EN + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: blockMemory_exdes PORT MAP ( + --Port A + RSTA => RSTA, + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + DOUTA => DOUTA, + CLKA => CLKA + + ); +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_stim_gen.vhd (revision 5) @@ -0,0 +1,243 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Stimulus Generator For Single Port Ram +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SRAM +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; + +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC_SRAM IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC_SRAM; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS + SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0'); + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + + CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(512,512); + SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_INT : STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_WRITE : STD_LOGIC := '0'; + SIGNAL DO_READ : STD_LOGIC := '0'; + SIGNAL COUNT_NO : INTEGER :=0; + SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); +BEGIN + WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0); + READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0); + ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ; + DINA <= DINA_INT ; + + CHECK_DATA <= DO_READ; + +RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + +WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + +WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 512, + DOUT_WIDTH => 512, + DATA_PART_CNT => DATA_PART_CNT_A, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + +WR_RD_PROCESS: PROCESS (CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + ELSIF(COUNT_NO < 4) THEN + DO_WRITE <= '1'; + DO_READ <= '0'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO< 8) THEN + DO_WRITE <= '0'; + DO_READ <= '1'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO=8) THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + END IF; + END IF; +END PROCESS; + +BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(0), + CLK => CLK, + RST => RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG; + + WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ; + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation/bmg_tb_pkg.vhd (revision 5) @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/simulation Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (revision 5) @@ -0,0 +1,237 @@ + + +blk_mem_gen_v7_1_vinfo + + + +










    +                Core name: Xilinx LogiCORE Block Memory Generator








    +                Version: 7.1








    +                Release: ISE 14.1 / Vivado 2012.1








    +                Release Date: April 24, 2012








    +








    +








    +================================================================================








    +








    +This document contains the following sections:








    +








    +This document contains the following sections:








    +








    +1. Introduction








    +2. New Features








    +  2.1 ISE








    +  2.2 Vivado








    +3. Supported Devices








    +  3.1 ISE








    +  3.2 Vivado








    +4. Resolved Issues








    +  4.1 ISE








    +  4.2 Vivado








    +5. Known Issues








    +  5.1 ISE








    +  5.2 Vivado








    +6. Technical Support








    +7. Core Release History








    +8. Legal Disclaimer








    +








    +================================================================================








    +








    +








    +1. INTRODUCTION








    +








    +For installation instructions for this release, please go to:








    +








    +  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm








    +








    +For system requirements:








    +








    +   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm








    +








    +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1








    +solution. For the latest core updates, see the product page at:








    +








    + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm








    +








    +








    +................................................................................








    +2. NEW FEATURES








    +








    +








    +  2.1 ISE








    +








    +    - ISE 14.1 software support








    +    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,








    +      and Automotive Zynq device support








    +








    +








    +  2.2 Vivado








    +








    +    - 2012.1 software support








    +    - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL,








    +      and Automotive Zynq device support








    +








    +








    +................................................................................








    +3. SUPPORTED DEVICES








    +








    +








    +  3.1 ISE








    +








    +  The following device families are supported by the core for this release.








    +








    +  All 7 Series devices








    +  Zynq-7000 devices








    +  All Virtex-6 devices








    +  All Spartan-6 devices








    +  All Virtex-5 devices








    +  All Spartan-3 devices








    +  All Virtex-4 devices








    +








    +








    +  3.2 Vivado








    +  All 7 Series devices








    +  Zynq-7000 devices








    +








    +








    +................................................................................








    +4. RESOLVED ISSUES








    +








    +








    +The following issues are resolved in Block Memory Generator v7.1:








    +








    +  4.1 ISE








    +








    +








    +  4.2 Vivado








    +








    +








    +................................................................................








    +5. KNOWN ISSUES








    +








    +








    +  5.1 ISE








    +








    +    The following are known issues for v7.1 of this core at time of release:








    +








    +    1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)








    +      Work around: The user must review the possible scenarios that causes the collission and revise








    +       their design to avoid those situations.








    +      - CR588505








    +








    +      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with








    +            Write Mode = Read First in conjunction with asynchronous clocking








    +








    +    2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.








    +








    +    3. Core does not generate for large memories. Depending on the








    +       machine the ISE CORE Generator software runs on, the maximum size of the memory that








    +       can be generated will vary.  For example, a Dual Pentium-4 server








    +       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes








    +      - CR 415768








    +      - AR 24034








    +








    +








    +  5.2 Vivado








    +








    +  The most recent information, including known issues, workarounds, and resolutions for








    +  this version is provided in the IP Release Notes User Guide located at








    +








    +         www.xilinx.com/support/documentation/user_guides/xtp025.pdf








    +








    +








    +








    +................................................................................








    +6. TECHNICAL SUPPORT








    +








    +To obtain technical support, create a WebCase at www.xilinx.com/support.








    +Questions are routed to a team with expertise using this product.








    +








    +Xilinx provides technical support for use of this product when used








    +according to the guidelines described in the core documentation, and








    +cannot guarantee timing, functionality, or support of this product for








    +designs that do not follow specified guidelines.








    +








    +








    +








    +7. CORE RELEASE HISTORY








    +








    +Date        By            Version      Description








    +================================================================================








    +04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support








    +01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support








    +06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;








    +03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support








    +09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support








    +07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support








    +04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support








    +03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue








    +12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power








    +                                       Device support; Automotive Spartan 3A








    +                                       DSP device support








    +09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3








    +06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2








    +04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1








    +09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8








    +03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7








    +10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6








    +07/2007     Xilinx, Inc.  2.5          Revised to v2.5








    +04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1








    +02/2007     Xilinx, Inc.  2.4          Revised to v2.4








    +11/2006     Xilinx, Inc.  2.3          Revised to v2.3








    +09/2006     Xilinx, Inc.  2.2          Revised to v2.2








    +06/2006     Xilinx, Inc.  2.1          Revised to v2.1








    +01/2006     Xilinx, Inc.  1.1          Initial release








    +================================================================================








    +








    +8. Legal Disclaimer








    +








    + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved.








    +








    + This file contains confidential and proprietary information








    + of Xilinx, Inc. and is protected under U.S. and








    + international copyright and other intellectual property








    + laws.








    +








    + DISCLAIMER








    + This disclaimer is not a license and does not grant any








    + rights to the materials distributed herewith. Except as








    + otherwise provided in a valid license issued to you by








    + Xilinx, and to the maximum extent permitted by applicable








    + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND








    + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES








    + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING








    + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-








    + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and








    + (2) Xilinx shall not be liable (whether in contract or tort,








    + including negligence, or under any other theory of








    + liability) for any loss or damage of any kind or nature








    + related to, arising under or in connection with these








    + materials, including for any direct, or any indirect,








    + special, incidental, or consequential loss or damage








    + (including loss of data, profits, goodwill, or any type of








    + loss or damage suffered as a result of any action brought








    + by a third party) even if such damage or loss was








    + reasonably foreseeable or Xilinx had been advised of the








    + possibility of the same.








    +








    + CRITICAL APPLICATIONS








    + Xilinx products are not designed or intended to be fail-








    + safe, or for use in any application requiring fail-safe








    + performance, such as life-support or safety devices or








    + systems, Class III medical devices, nuclear facilities,








    + applications related to the deployment of airbags, or any








    + other applications that could lead to death, personal








    + injury, or severe property or environmental damage








    + (individually and collectively, "Critical








    + Applications"). Customer assumes the sole risk and








    + liability of any use of Xilinx products in Critical








    + Applications, subject only to applicable laws and








    + regulations governing limitations on product liability.








    +








    + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS








    + PART OF THIS FILE AT ALL TIMES.








    +








    +








    +

+ + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc/blk_mem_gen_ds512.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/blk_mem_gen_v7_1_readme.txt (revision 5) @@ -0,0 +1,226 @@ + Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.bat (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy blockMemory_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\blockMemory.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\blockMemory_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/implement.sh (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp blockMemory_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../blockMemory.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/blockMemory_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.scr (revision 5) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent blockMemory_exdes +-p xc3s500e-fg320-5 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn blockMemory_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/xst.prj (revision 5) @@ -0,0 +1 @@ +work ../example_design/blockMemory_exdes.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_rdn.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement/planAhead_ise.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory/implement Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.v (revision 5) @@ -0,0 +1,180 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module blockMemory( + clka, + rsta, + wea, + addra, + dina, + douta +); + +input clka; +input rsta; +input [0 : 0] wea; +input [3 : 0] addra; +input [511 : 0] dina; +output [511 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V7_1 #( + .C_ADDRA_WIDTH(4), + .C_ADDRB_WIDTH(4), + .C_ALGORITHM(0), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(1), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(0), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(6), + .C_READ_DEPTH_A(16), + .C_READ_DEPTH_B(16), + .C_READ_WIDTH_A(512), + .C_READ_WIDTH_B(512), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(16), + .C_WRITE_DEPTH_B(16), + .C_WRITE_MODE_A("READ_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(512), + .C_WRITE_WIDTH_B(512), + .C_XDEVICEFAMILY("spartan3e") + ) + inst ( + .CLKA(clka), + .RSTA(rsta), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .ENA(), + .REGCEA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ncf =================================================================== Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.ngc (revision 5) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xise =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xise (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xise (revision 5) @@ -0,0 +1,386 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.sym =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.sym (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.sym (revision 5) @@ -0,0 +1,27 @@ + + + BLOCK + 2015-2-1T10:47:44 + + + + + + + + blockMemory + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.cgp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.cgp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.cgp (revision 5) @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET package = fg320 +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false Index: trunk/rtl/vhdl/mod_exp/blockMemory512/gen_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/gen_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/gen_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator regen command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_regen "blockMemory" xc3s500e-5fg320 VHDL CURRENT ] + +if { $result == 0 } { + puts "Core Generator regen command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator regen command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator regen cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory512/xlnx_auto_0_xdb =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/xlnx_auto_0_xdb (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/xlnx_auto_0_xdb (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/xlnx_auto_0_xdb Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/cg.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/cg.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs/cg.xmsgs (revision 5) @@ -0,0 +1,27 @@ + + + +Generating IP... + + +A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten. + + +Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis + + +Pre-processing HDL files for 'blockMemory'... + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/blockMemory.lso =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/blockMemory.lso (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/blockMemory.lso (revision 5) @@ -0,0 +1 @@ +work Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/xst.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/xst.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs/xst.xmsgs (revision 5) @@ -0,0 +1,748 @@ + + + +Message file "usenglish/ip.msg" wasn't found. + + +0: (0,0) : 72x256 u:72 + + +1: (72,0) : 72x256 u:72 + + +2: (144,0) : 72x256 u:72 + + +3: (216,0) : 72x256 u:72 + + +4: (288,0) : 72x256 u:72 + + +5: (360,0) : 72x256 u:72 + + +6: (432,0) : 72x256 u:72 + + +7: (504,0) : 72x256 u:8 + + +0: (0,0) : 72x256 u:72 + + +1: (72,0) : 72x256 u:72 + + +2: (144,0) : 72x256 u:72 + + +3: (216,0) : 72x256 u:72 + + +4: (288,0) : 72x256 u:72 + + +5: (360,0) : 72x256 u:72 + + +6: (432,0) : 72x256 u:72 + + +7: (504,0) : 72x256 u:8 + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 370: Net <doutb_i[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <doutb> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +Input <S_AXI_AWID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WDATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEA<56:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB<56:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[2].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[2].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[3].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[3].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[4].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[4].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[5].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[5].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[6].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[6].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[7].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[7].ram.r> is unconnected or connected to loadless signal. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_1', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_2', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_3', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_4', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_5', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_6', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_7', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'dina_pad<71:64>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<62:55>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<53:46>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<44:37>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<35:28>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<26:19>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<17:10>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dina_pad<8:1>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<71:64>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<62:55>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<53:46>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<44:37>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<35:28>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<26:19>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<17:10>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal 'dinb_pad<8:1>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (00000000). + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3_8', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <DOUTB_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RDADDRECC_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + +You have chosen to run a version of XST which is not the default solution +for the specified device family. You are free to use it in order to take +advantage of its enhanced HDL parsing/elaboration capabilities. However, +please be aware that you may be impacted by language support differences. +This version may also result in circuit performance and device utilization +differences for your particular design. You can always revert back to the +default XST solution by setting the "use_new_parser" option to value "no" +on the XST command line or in the XST process properties panel. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_cg =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_cg (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_cg (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/tmp/_cg Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/tmp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/tmp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/tmp (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512/tmp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_flist.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_flist.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_flist.txt (revision 5) @@ -0,0 +1,60 @@ +# Output products list for +_xmsgs\pn_parser.xmsgs +blockMemory.asy +blockMemory.gise +blockMemory.ngc +blockMemory.sym +blockMemory.vhd +blockMemory.vho +blockMemory.xco +blockMemory.xise +blockMemory\blk_mem_gen_v7_1_readme.txt +blockMemory\doc\blk_mem_gen_ds512.pdf +blockMemory\doc\blk_mem_gen_v7_1_vinfo.html +blockMemory\example_design\blockMemory_exdes.ucf +blockMemory\example_design\blockMemory_exdes.vhd +blockMemory\example_design\blockMemory_exdes.xdc +blockMemory\example_design\blockMemory_prod.vhd +blockMemory\implement\implement.bat +blockMemory\implement\implement.sh +blockMemory\implement\planAhead_ise.bat +blockMemory\implement\planAhead_ise.sh +blockMemory\implement\planAhead_ise.tcl +blockMemory\implement\planAhead_rdn.bat +blockMemory\implement\planAhead_rdn.sh +blockMemory\implement\planAhead_rdn.tcl +blockMemory\implement\xst.prj +blockMemory\implement\xst.scr +blockMemory\simulation\addr_gen.vhd +blockMemory\simulation\blockMemory_synth.vhd +blockMemory\simulation\blockMemory_tb.vhd +blockMemory\simulation\bmg_stim_gen.vhd +blockMemory\simulation\bmg_tb_pkg.vhd +blockMemory\simulation\checker.vhd +blockMemory\simulation\data_gen.vhd +blockMemory\simulation\functional\simcmds.tcl +blockMemory\simulation\functional\simulate_isim.bat +blockMemory\simulation\functional\simulate_mti.bat +blockMemory\simulation\functional\simulate_mti.do +blockMemory\simulation\functional\simulate_mti.sh +blockMemory\simulation\functional\simulate_ncsim.sh +blockMemory\simulation\functional\simulate_vcs.sh +blockMemory\simulation\functional\ucli_commands.key +blockMemory\simulation\functional\vcs_session.tcl +blockMemory\simulation\functional\wave_mti.do +blockMemory\simulation\functional\wave_ncsim.sv +blockMemory\simulation\random.vhd +blockMemory\simulation\timing\simcmds.tcl +blockMemory\simulation\timing\simulate_isim.bat +blockMemory\simulation\timing\simulate_mti.bat +blockMemory\simulation\timing\simulate_mti.do +blockMemory\simulation\timing\simulate_mti.sh +blockMemory\simulation\timing\simulate_ncsim.sh +blockMemory\simulation\timing\simulate_vcs.sh +blockMemory\simulation\timing\ucli_commands.key +blockMemory\simulation\timing\vcs_session.tcl +blockMemory\simulation\timing\wave_mti.do +blockMemory\simulation\timing\wave_ncsim.sv +blockMemory_flist.txt +blockMemory_xmdf.tcl +summary.log Index: trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/coregen.log (revision 5) @@ -0,0 +1,60 @@ +INFO:sim:172 - Generating IP... +Applying current project options... +Finished applying current project options. +Resolving generics for 'blockMemory'... +WARNING:sim - A core named 'blockMemory' already exists in the project. Output + products for this core may be overwritten. +Applying external generics to 'blockMemory'... +Delivering associated files for 'blockMemory'... +WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for + VHDL synthesis +Delivering EJava files for 'blockMemory'... +Generating implementation netlist for 'blockMemory'... +INFO:sim - Pre-processing HDL files for 'blockMemory'... +Running synthesis for 'blockMemory' +Running ngcbuild... +Writing VHO instantiation template for 'blockMemory'... +Writing VHDL behavioral simulation model for 'blockMemory'... +Generating ASY schematic symbol... +INFO:sim:949 - Finished generation of ASY schematic symbol. +Generating SYM schematic symbol for 'blockMemory'... +Generating metadata file... +Generating ISE project... +XCO file found: blockMemory.xco +XMDF file found: blockMemory_xmdf.tcl +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.asy -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc -view all -origin_type created +Checking file "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" for project device match ... +File "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" device information matches project device. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.sym -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vhd -view all -origin_type created +INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i + praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp + /_cg/blockMemory.vhd" into library work +INFO:ProjectMgmt - Parsing design hierarchy completed successfully. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vho -view all -origin_type imported +INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. + Please set the new top explicitly by running the "project set top" command. + To re-calculate the new top automatically, set the "Auto Implementation Top" + property to true. +Top level has been set to "/blockMemory" +Generating README file... +Generating FLIST file... +INFO:sim:948 - Finished FLIST file generation. +Moving files to output directory... +Finished moving files to output directory +Wrote CGP file for project 'blockMemory'. Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd (revision 5) @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY blockMemory IS + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(511 DOWNTO 0) + ); +END blockMemory; + +ARCHITECTURE blockMemory_a OF blockMemory IS +-- synthesis translate_off +COMPONENT wrapped_blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(511 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_blockMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_1(behavioral) + GENERIC MAP ( + c_addra_width => 4, + c_addrb_width => 4, + c_algorithm => 0, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 1, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 0, + c_mux_pipeline_stages => 0, + c_prim_type => 6, + c_read_depth_a => 16, + c_read_depth_b => 16, + c_read_width_a => 512, + c_read_width_b => 512, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 16, + c_write_depth_b => 16, + c_write_mode_a => "READ_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 512, + c_write_width_b => 512, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- synthesis translate_on + +END blockMemory_a; Index: trunk/rtl/vhdl/mod_exp/blockMemory512/edit_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/edit_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/edit_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "blockMemory" xc3s500e-5fg320 VHDL ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_beh.cgp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_beh.cgp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory_beh.cgp (revision 5) @@ -0,0 +1,22 @@ +# Date: Sat Dec 22 01:24:09 2012 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +SET workingdirectory = .\tmp\ + +# CRC: 46f7aa00 Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.gise =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.gise (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.gise (revision 5) @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.veo =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.veo (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.veo (revision 5) @@ -0,0 +1,70 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 * +* * +* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * +* Block Memory and Single Port Block Memory LogiCOREs, but is not a * +* direct drop-in replacement. It should be used in all new Xilinx * +* designs. The core supports RAM and ROM functions over a wide range of * +* widths and depths. Use this core to generate block memories with * +* symmetric or asymmetric read and write port widths, as well as cores * +* which can perform simultaneous write operations to separate * +* locations, and simultaneous read operations from the same location. * +* For more information on differences in interface and feature support * +* between this core and the Dual Port Block Memory and Single Port * +* Block Memory LogiCOREs, please consult the data sheet. * +*******************************************************************************/ + +// Interfaces: +// AXI_SLAVE_S_AXI +// AXI_SLAVE +// AXILite_SLAVE_S_AXI +// AXILite_SLAVE + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +blockMemory your_instance_name ( + .clka(clka), // input clka + .rsta(rsta), // input rsta + .wea(wea), // input [0 : 0] wea + .addra(addra), // input [3 : 0] addra + .dina(dina), // input [511 : 0] dina + .douta(douta) // output [511 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xco =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xco (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.xco (revision 5) @@ -0,0 +1,106 @@ +############################################################## +# +# Xilinx Core Generator version 14.2 +# Date: Sun Feb 01 10:45:16 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Fixed_Primitives +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=blockMemory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Single_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=256x72 +CSET read_width_a=512 +CSET read_width_b=512 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=true +CSET use_rstb_pin=false +CSET write_depth_a=16 +CSET write_width_a=512 +CSET write_width_b=512 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-01T17:17:26Z +# END Extra information +GENERATE +# CRC: 7654b1f0 Index: trunk/rtl/vhdl/mod_exp/blockMemory512/summary.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/summary.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/summary.log (revision 5) @@ -0,0 +1,18 @@ + +User Configuration +------------------------------------- +Algorithm : Fixed_Primitives +Memory Type : Single_Port_RAM +Port A Read Width : 512 +Port A Write Width : 512 +Memory Depth : 16 +-------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : 8 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 75.800499 mW +---------------------------------------------------------- Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.asy =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.asy (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.asy (revision 5) @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 blockMemory +RECTANGLE Normal 32 32 544 1376 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[3:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[511:0] +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rsta +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[511:0] +PINATTR Polarity OUT + Index: trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vho =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vho (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512/blockMemory.vho (revision 5) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 -- +-- -- +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port -- +-- Block Memory and Single Port Block Memory LogiCOREs, but is not a -- +-- direct drop-in replacement. It should be used in all new Xilinx -- +-- designs. The core supports RAM and ROM functions over a wide range of -- +-- widths and depths. Use this core to generate block memories with -- +-- symmetric or asymmetric read and write port widths, as well as cores -- +-- which can perform simultaneous write operations to separate -- +-- locations, and simultaneous read operations from the same location. -- +-- For more information on differences in interface and feature support -- +-- between this core and the Dual Port Block Memory and Single Port -- +-- Block Memory LogiCOREs, please consult the data sheet. -- +-------------------------------------------------------------------------------- + +-- Interfaces: +-- AXI_SLAVE_S_AXI +-- AXI_SLAVE +-- AXILite_SLAVE_S_AXI +-- AXILite_SLAVE +-- BRAM_PORTA +-- BRAM_PORTA +-- BRAM_PORTB +-- BRAM_PORTB + +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(511 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory512 =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory512 (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory512 (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory512 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/ModExpSM.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/ModExpSM.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/ModExpSM.vhd (revision 5) @@ -0,0 +1,528 @@ +----------------------------------------------------------------------- +---- ---- +---- Montgomery modular multiplier and exponentiator ---- +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator project ---- +---- http://opencores.org/project,mod_mult_exp ---- +---- ---- +---- Description: ---- +---- This is state machine of the Montgomery modular ---- +---- exponentiator. It controls all the registers, block memory ---- +---- and the exponentiation process. ---- +---- ---- +---- To Do: ---- +---- Description ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use work.properties.ALL; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ModExpSM is + generic( + word_size : integer := WORD_LENGTH; + word_binary : integer := WORD_INTEGER + ); + port ( + data_in_ready : in STD_LOGIC; + clk : in STD_LOGIC; + exp_ctrl : in STD_LOGIC_VECTOR(2 downto 0); + reset : in STD_LOGIC; + in_mux_control : out STD_LOGIC_VECTOR(1 downto 0); + -- finalizer end status + ready : out STD_LOGIC; + -- control for multiplier + modMultStart : out STD_LOGIC; + modMultReady : in STD_LOGIC; + -- control for memory and registers + addr_dataA : out STD_LOGIC_VECTOR(3 downto 0); + addr_dataB : out STD_LOGIC_VECTOR(3 downto 0); + regData_EnA : out STD_LOGIC_vector(0 downto 0); + regData_EnB : out STD_LOGIC_vector(0 downto 0); + regData_EnC : out STD_LOGIC; + regData_EnExponent : out STD_LOGIC; + ExponentData : in STD_LOGIC_VECTOR(word_size - 1 downto 0); + memory_reset : out std_logic + ); +end ModExpSM; + +architecture Behavioral of ModExpSM is + +-- Enable signals for registers and block memory +signal regDataEnA : STD_LOGIC_vector(0 downto 0); +signal regDataEnB : STD_LOGIC_vector(0 downto 0); +signal regDataEnC : STD_LOGIC; +signal regDataEnD2 : STD_LOGIC; + +-- states data +signal state : exponentiator_states; +signal next_state : exponentiator_states; + +-- addres data for block memory ''registers'' +signal addr_reg_A : STD_LOGIC_VECTOR(3 downto 0); +signal addr_reg_B : STD_LOGIC_VECTOR(3 downto 0); + +-- signal informing about first exponentiation in given word +signal first_exp : STD_LOGIC; + +-- signal for counting the iterations during exponentiation +signal position_counter : std_logic_vector(word_binary downto 0); + +begin + -- signals assigment + regData_EnA <= regDataEnA; + regData_EnB <= regDataEnB; + regData_EnC <= regDataEnC; + regData_EnExponent <= regDataEnD2; + addr_dataA <= addr_reg_A; + addr_dataB <= addr_reg_B; + + -- State machine process + SM : process(data_in_ready, exp_ctrl, modMultReady, state, position_counter) + begin + case state is + when FIRST_RUN => + -- Preparing the core before the exponentiation + in_mux_control <= "10"; + ready <= '0'; + modMultStart <= '0'; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + addr_reg_A <= addr_unused; + addr_reg_B <= addr_unused; + first_exp <= '1'; + next_state <= NOP; + -- ''No operation'' during waiting for the command and suitable data + when NOP => + in_mux_control <= "11"; + ready <= '0'; + modMultStart <= '0'; + first_exp <= '1'; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + -- Read base + if (exp_ctrl = mn_read_base) and (data_in_ready = '1') then + addr_reg_A <= addr_base; + addr_reg_B <= addr_base; + next_state <= READ_DATA_BASE; + -- Read modulus + elsif (exp_ctrl = mn_read_modulus) and (data_in_ready = '1') then + regDataEnC <= '1'; + addr_reg_A <= addr_modulus; + addr_reg_B <= addr_modulus; + next_state <= READ_DATA_MODULUS; + -- Read exponent + elsif (exp_ctrl = mn_read_exponent) and (data_in_ready = '1') then + regDataEnD2 <= '1'; + addr_reg_A <= addr_exponent; + addr_reg_B <= addr_exponent; + next_state <= READ_DATA_EXPONENT; + -- Read residuum + elsif (exp_ctrl = mn_read_residuum) and (data_in_ready = '1') then + addr_reg_A <= addr_residuum; + addr_reg_B <= addr_residuum; + next_state <= READ_DATA_RESIDUUM; + -- Read power + elsif (exp_ctrl = mn_count_power) then + in_mux_control <= "01"; + addr_reg_A <= addr_one; + addr_reg_B <= addr_one; + next_state <= COUNT_POWER; + -- Prepare the exponentiator for the new data + -- i.e. wrong data was readed first. More important + -- prepare is after the exponentiation (SHOW_RESULT) + elsif (exp_ctrl = mn_prepare_for_data) then + addr_reg_A <= addr_unused; + addr_reg_B <= addr_unused; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= FIRST_RUN; + -- in case of unpredicted ''command'' appear + else + addr_reg_A <= addr_unused; + addr_reg_B <= addr_unused; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= NOP; + end if; + -- ''READ'' states differs only by the addres under + -- which the data are written. + -- State for reading base of the exponentiation + when READ_DATA_BASE => + in_mux_control <= "11"; + ready <= '0'; + modMultStart <= '0'; + addr_reg_A <= addr_base; + addr_reg_B <= addr_base; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= NOP; + first_exp <= '1'; + -- State for reading the modulus + when READ_DATA_MODULUS => + in_mux_control <= "11"; + ready <= '0'; + modMultStart <= '0'; + addr_reg_A <= addr_modulus; + addr_reg_B <= addr_modulus; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '1'; + regDataEnD2 <= '0'; + next_state <= NOP; + first_exp <= '1'; + -- State for reading the exponent + when READ_DATA_EXPONENT => + in_mux_control <= "11"; + ready <= '0'; + modMultStart <= '0'; + addr_reg_A <= addr_exponent; + addr_reg_B <= addr_exponent; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '1'; + next_state <= NOP; + first_exp <= '1'; + -- State for reading the residuum + when READ_DATA_RESIDUUM => + in_mux_control <= "11"; + ready <= '0'; + modMultStart <= '0'; + addr_reg_A <= addr_residuum; + addr_reg_B <= addr_residuum; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= NOP; + first_exp <= '1'; + -- State for preparing the system for the exponentiation + -- First pre computed value ''Z'' - prepare data + when COUNT_POWER => + in_mux_control <= "10"; + ready <= '0'; + modMultStart <= '0'; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + addr_reg_A <= addr_one; + addr_reg_B <= addr_residuum; + first_exp <= '1'; + next_state <= EXP_Z; + -- ''Z'' multiplying - in case if it is first computation or no + -- system behaves a little bit different + when EXP_Z => + regDataEnC <= '0'; + regDataEnD2 <= '0'; + regDataEnD2 <= '0'; + ready <= '0'; + in_mux_control <= "10"; + modMultStart <= '1'; + -- If end of multiplying + if (modMultReady = '1') then + addr_reg_A <= addr_z; + addr_reg_B <= addr_z; + regDataEnA <= "1"; + regDataEnB <= "1"; + if (first_exp = '1') then + first_exp <= '1'; + else + first_exp <= '0'; + end if; + next_state <= SAVE_EXP_Z; + else + -- During first exponentiation it is ''Z precomputing'' + if (first_exp = '1') then + first_exp <= '1'; + addr_reg_A <= addr_one; + addr_reg_B <= addr_residuum; + -- in another case computing related with the algorithm + else + first_exp <= '0'; + if (ExponentData(conv_integer(position_counter)) = '1') then + addr_reg_A <= addr_z; + addr_reg_B <= addr_p; + else + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + end if; + end if; + regDataEnA <= "0"; + regDataEnB <= "0"; + next_state <= EXP_Z; + end if; + -- Svaing the ''Z'' calculation result + when SAVE_EXP_Z => + modMultStart <= '0'; + ready <= '0'; + in_mux_control <= "10"; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + -- Preparing for the ''P'' precalculation in case first + -- calculation of the exponentiation + if (first_exp = '1') then + first_exp <= '1'; + addr_reg_A <= addr_base; + addr_reg_B <= addr_residuum; + next_state <= EXP_P; + -- In another case ''P'' square is performed + else + first_exp <= '0'; + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + next_state <= EXP_P; + end if; + -- ''P'' multiplying - in case if it is first computation or no + -- system behaves a little bit different + when EXP_P => + modMultStart <= '1'; + ready <= '0'; + in_mux_control <= "10"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + -- If end of multiplying + if (modMultReady = '1') then + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + regDataEnA <= "1"; + regDataEnB <= "1"; + if (first_exp = '1') then + first_exp <= '1'; + else + first_exp <= '0'; + end if; + next_state <= SAVE_EXP_P; + else + -- During first exponentiation it is ''P precomputing'' + if (first_exp = '1') then + first_exp <= '1'; + addr_reg_A <= addr_base; + addr_reg_B <= addr_residuum; + -- in another case computing related with the algorithm + else + first_exp <= '0'; + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + end if; + regDataEnA <= "0"; + regDataEnB <= "0"; + next_state <= EXP_P; + end if; + -- Svaing the ''P'' calculation result + when SAVE_EXP_P => + ready <= '0'; + modMultStart <= '0'; + in_mux_control <= "10"; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + first_exp <= '0'; + next_state <= EXP_CONTROL; + -- State controlling the exponentiation process + -- related to compute ''Z'' or ''P'' element + when EXP_CONTROL => + ready <= '0'; + modMultStart <= '0'; + in_mux_control <= "10"; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + -- Checking if it was last exponentiation (if yes + -- post computing stage is performed) + -- modify for change key size by properties + -- (historical remark) + if (position_counter(word_binary - 1) = '1') then + addr_reg_A <= addr_one; + addr_reg_B <= addr_z; + next_state <= EXP_END; + -- in another case algorithm 'stage' checking is made + else + if (ExponentData(conv_integer(position_counter)) = '1') then + addr_reg_A <= addr_z; + addr_reg_B <= addr_p; + next_state <= EXP_Z; + else + addr_reg_A <= addr_p; + addr_reg_B <= addr_p; + next_state <= EXP_P; + end if; + end if; + first_exp <= '0'; + -- Algorithm ''post computing'' + when EXP_END => + modMultStart <= '1'; + ready <= '0'; + in_mux_control <= "10"; + addr_reg_A <= addr_one; + addr_reg_B <= addr_z; + -- if end of ''post computing'' multiplying + -- save result + if (modMultReady = '1') then + addr_reg_A <= addr_power; + addr_reg_B <= addr_power; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= SAVE_EXP_MULT; + -- in another case ''wait'' for the end + else + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + next_state <= EXP_END; + end if; + first_exp <= '0'; + -- save step + when SAVE_EXP_MULT => + in_mux_control <= "10"; + modMultStart <= '0'; + ready <= '0'; + addr_reg_A <= addr_power; + addr_reg_B <= addr_power; + regDataEnA <= "1"; + regDataEnB <= "1"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + first_exp <= '1'; + next_state <= INFO_RESULT; + -- Stage informing ''the world'' about end of + -- exponentiation + when INFO_RESULT => + modMultStart <= '0'; + in_mux_control <= "10"; + ready <= '1'; + addr_reg_A <= addr_power; + addr_reg_B <= addr_power; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + if (exp_ctrl = mn_show_result) then + next_state <= SHOW_RESULT; + else + next_state <= INFO_RESULT; + end if; + first_exp <= '1'; + -- Show result + when SHOW_RESULT => + ready <= '1'; + in_mux_control <= "10"; + modMultStart <= '0'; + addr_reg_A <= addr_power; + addr_reg_B <= addr_power; + regDataEnA <= "0"; + regDataEnB <= "0"; + regDataEnC <= '0'; + regDataEnD2 <= '0'; + -- Here we are waiting until ''prepare data'' command + -- appears + if (exp_ctrl = mn_prepare_for_data) then + next_state <= FIRST_RUN; + else + next_state <= SHOW_RESULT; + end if; + first_exp <= '1'; + end case; + end process SM; + + -- Process resetting the block memory and registers before each exponentiation + memory_reset_proc : process(clk, reset, state) + begin + if (reset = '1') then + memory_reset <= '1'; + elsif (clk = '1' and clk'Event) then + if (state = FIRST_RUN) then + memory_reset <= '1'; + else + memory_reset <= '0'; + end if; + end if; + end process memory_reset_proc; + + -- State change process + state_modifier : process (clk, reset) + begin + if (reset = '1') then + state <= FIRST_RUN; + elsif (clk = '1' and clk'Event) then + state <= next_state; + end if; + end process state_modifier; + + -- Counter process for the control of the exponentiation number iteration + counter_modifier : process (state, clk, reset) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + position_counter <= (others => '1'); + elsif (state = SAVE_EXP_P) then + position_counter <= position_counter + 1; + elsif (state = EXP_END) then + position_counter <= (others => '1'); + else + position_counter <= position_counter; + end if; + end if; + end process counter_modifier; + +end Behavioral; \ No newline at end of file Index: trunk/rtl/vhdl/mod_exp/ModExp.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/ModExp.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/ModExp.vhd (revision 5) @@ -0,0 +1,287 @@ +----------------------------------------------------------------------- +---- ---- +---- Montgomery modular multiplier and exponentiator ---- +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator project ---- +---- http://opencores.org/project,mod_mult_exp ---- +---- ---- +---- Description: ---- +---- Montgomery modular exponentiator main module. It combines ---- +---- all subomponents. It takes four numbers as the input: ---- +---- base, power, modulus and Montgomery residuum ---- +---- (2^(2*word_length) mod N) and results the modular ---- +---- exponentiation A^B mod M. ---- +---- In fact input data are read through one input controlled by ---- +---- the ctrl input. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use work.properties.ALL; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ModExp is + generic ( + word_size : integer := WORD_LENGTH; + word_binary : integer := WORD_INTEGER + ); + Port ( + input : in STD_LOGIC_VECTOR(word_size - 1 downto 0); + ctrl : in STD_LOGIC_VECTOR(2 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + data_in_ready : in STD_LOGIC; + ready : out STD_LOGIC; + output : out STD_LOGIC_VECTOR(word_size - 1 downto 0) + ); +end ModExp; + +architecture Behavioral of ModExp is + +-- Montgomery modular multiplier component +component ModularMultiplierIterative is + generic ( + word_size : integer := WORD_LENGTH + ); + port ( + A : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplicand + B : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplier + M : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- modulus + start : in STD_LOGIC; + product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product + ready : out STD_LOGIC; + clk : in STD_LOGIC + ); +end component ModularMultiplierIterative; + +-- Block memory component generated through ISE +-- It is used like multiple cell register +COMPONENT blockMemory + PORT ( + clka : in STD_LOGIC; + rsta : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : in STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : in STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0); + douta : out STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0) + ); +END COMPONENT; + +-- Register +component Reg is + generic( + word_size : integer := WORD_LENGTH + ); + port( + input : in STD_LOGIC_VECTOR(word_size - 1 downto 0); + output : out STD_LOGIC_VECTOR(word_size - 1 downto 0); + enable : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end component Reg; + +-- Multiplexer +component MontMult4inMux is + generic ( + word_size : integer := WORD_LENGTH - 1 + ); + port ( + ctrl : in STD_LOGIC_VECTOR(1 downto 0); + zero : in STD_LOGIC_VECTOR(word_size downto 0); + M : in STD_LOGIC_VECTOR(word_size downto 0); + Y : in STD_LOGIC_VECTOR(word_size downto 0); + YplusM : in STD_LOGIC_VECTOR(word_size downto 0); + output : out STD_LOGIC_VECTOR(word_size downto 0) + ); +end component MontMult4inMux; + +-- State machine +component ModExpSM is + generic( + word_size : integer := WORD_LENGTH; + word_binary : integer := WORD_INTEGER + ); + port ( + data_in_ready : in STD_LOGIC; + clk : in STD_LOGIC; + exp_ctrl : in STD_LOGIC_VECTOR(2 downto 0); + reset : in STD_LOGIC; + in_mux_control : out STD_LOGIC_VECTOR(1 downto 0); + -- finalizer end status + ready : out STD_LOGIC; + -- control for multiplier + modMultStart : out STD_LOGIC; + modMultReady : in STD_LOGIC; + -- control for memory and registers + addr_dataA : out STD_LOGIC_VECTOR(3 downto 0); + addr_dataB : out STD_LOGIC_VECTOR(3 downto 0); + regData_EnA : out STD_LOGIC_VECTOR(0 downto 0); + regData_EnB : out STD_LOGIC_VECTOR(0 downto 0); + regData_EnC : out STD_LOGIC; + regData_EnExponent : out STD_LOGIC; + ExponentData : in STD_LOGIC_VECTOR(word_size - 1 downto 0); + memory_reset : out STD_LOGIC + ); +end component ModExpSM; + +-- data registers signals +signal addr_dataA : STD_LOGIC_VECTOR(3 downto 0); +signal addr_dataB : STD_LOGIC_VECTOR(3 downto 0); + +signal memDataLoadA : STD_LOGIC_VECTOR(0 downto 0); +signal memDataLoadB : STD_LOGIC_VECTOR(0 downto 0); +signal memDataLoadC : STD_LOGIC; +signal memDataLoadExponent : STD_LOGIC; + +signal memDataA : STD_LOGIC_VECTOR(word_size - 1 downto 0); +signal memDataB : STD_LOGIC_VECTOR(word_size - 1 downto 0); +signal memDataC : STD_LOGIC_VECTOR(word_size - 1 downto 0); +signal memDataExponent : STD_LOGIC_VECTOR(word_size - 1 downto 0); +signal memoryIn : STD_LOGIC_VECTOR(word_size - 1 downto 0); + +signal in_mux_control : STD_LOGIC_VECTOR(1 downto 0); + +-- signal for multiplier +signal multStart : STD_LOGIC; +signal multReady : STD_LOGIC; +signal modMultToBuffer : STD_LOGIC_VECTOR(word_size - 1 downto 0); + +signal zero : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0'); +signal one : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (0 => '1', others => '0'); + +signal memory_reset : STD_LOGIC; + +begin + -- connections between components + zero <= (others => '0'); + one <= (0 => '1', others => '0'); + + -- Montgomery modular multiplier component + modMult : ModularMultiplierIterative + port map ( + A => memDataA, + B => memDataB, + M => memDataC, + start => multStart, + product => modMultToBuffer, + ready => multReady, + clk => clk + ); + + -- Multiplexer + mux : MontMult4inMux + port map ( + ctrl => in_mux_control, + zero => zero, + M => one, + Y => modMultToBuffer, + YplusM => input, + output => memoryIn + ); + + -- Block memory for the first input of the multiplier + memoryA : blockMemory + port map ( + clka => clk, + rsta => memory_reset, + wea => memDataLoadA, + addra => addr_dataA, + dina => memoryIn, + douta => memDataA + ); + + -- Block memory for the second input of the multiplier + memoryB : blockMemory + port map ( + clka => clk, + rsta => memory_reset, + wea => memDataLoadB, + addra => addr_dataB, + dina => memoryIn, + douta => memDataB + ); + + -- Register for the modulus for the multiplier + memoryModulus : Reg + port map ( + input => memoryIn, + output => memDataC, + enable => memDataLoadC, + clk => clk, + reset => memory_reset + ); + + -- Register for the exponent - it feeds also the state machine for the control of the exponentiation process + memoryExponent : Reg + port map ( + input => memoryIn, + output => memDataExponent, + enable => memDataLoadExponent, + clk => clk, + reset => memory_reset + ); + + -- State machine of the Montgomery modular exponentiator + stateMachine : ModExpSM + port map( + data_in_ready => data_in_ready, + clk => clk, + exp_ctrl => ctrl, + reset => reset, + in_mux_control => in_mux_control, + ready => ready, + modMultStart => multStart, + modMultReady => multReady, + addr_dataA => addr_dataA, + addr_dataB => addr_dataB, + regData_EnA => memDataLoadA, + regData_EnB => memDataLoadB, + regData_EnC => memDataLoadC, + regData_EnExponent => memDataLoadExponent, + ExponentData => memDataExponent, + memory_reset => memory_reset + ); + + output <= memDataA; + +end Behavioral; \ No newline at end of file Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_xmdf.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_xmdf.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_xmdf.tcl (revision 5) @@ -0,0 +1,259 @@ +# The package naming convention is _xmdf +package provide blockMemory_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::blockMemory_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::blockMemory_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name blockMemory +} +# ::blockMemory_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::blockMemory_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/blk_mem_gen_v7_1_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/doc/blk_mem_gen_v7_1_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_exdes.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/example_design/blockMemory_prod.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/planAhead_rdn.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/addr_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/blockMemory_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_stim_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/bmg_tb_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/checker.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/data_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/random.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blockMemory_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blockMemory +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.ucf =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.ucf (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.ucf (revision 5) @@ -0,0 +1,57 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +################################################################################ Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_prod.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_prod.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_prod.vhd (revision 5) @@ -0,0 +1,270 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_prod.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan3e +-- C_XDEVICEFAMILY : spartan3e +-- C_INTERFACE_TYPE : 0 +-- C_ENABLE_32BIT_ADDRESS : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 0 +-- C_BYTE_SIZE : 9 +-- C_ALGORITHM : 0 +-- C_PRIM_TYPE : 6 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 1 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 0 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 0 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : READ_FIRST +-- C_WRITE_WIDTH_A : 64 +-- C_READ_WIDTH_A : 64 +-- C_WRITE_DEPTH_A : 16 +-- C_READ_DEPTH_A : 16 +-- C_ADDRA_WIDTH : 4 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 0 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 0 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 64 +-- C_READ_WIDTH_B : 64 +-- C_WRITE_DEPTH_B : 16 +-- C_READ_DEPTH_B : 16 +-- C_ADDRB_WIDTH : 4 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY blockMemory_prod IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END blockMemory_prod; + + +ARCHITECTURE xilinx OF blockMemory_prod IS + + COMPONENT blockMemory_exdes IS + PORT ( + --Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + CLKA : IN STD_LOGIC + + + + + ); + END COMPONENT; + +BEGIN + + bmg0 : blockMemory_exdes + PORT MAP ( + --Port A + RSTA => RSTA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + DOUTA => DOUTA, + + CLKA => CLKA + + + + ); +END xilinx; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.xdc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.xdc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.xdc (revision 5) @@ -0,0 +1,54 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] +################################################################################ Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design/blockMemory_exdes.vhd (revision 5) @@ -0,0 +1,166 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY blockMemory_exdes IS + PORT ( + --Inputs - Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END blockMemory_exdes; + + +ARCHITECTURE xilinx OF blockMemory_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT blockMemory IS + PORT ( + --Port A + RSTA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + + DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + CLKA : IN STD_LOGIC + + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + + + bmg0 : blockMemory + PORT MAP ( + --Port A + RSTA => RSTA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + DOUTA => DOUTA, + + CLKA => CLKA_buf + + + ); + +END xilinx; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/example_design Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/random.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/random.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/random.vhd (revision 5) @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_ncsim.sv (revision 5) @@ -0,0 +1,21 @@ + + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_ncsim.sh (revision 5) @@ -0,0 +1,70 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + + +mkdir work +echo "Compiling Core VHDL UNISIM/Behavioral model" +ncvhdl -v93 -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Elaborating Design" +ncelab -access +rwc work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_vcs.sh (revision 5) @@ -0,0 +1,69 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../../blockMemory.vhd +vhdlan ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + +echo "Elaborating Design" +vcs +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_isim.bat (revision 5) @@ -0,0 +1,68 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\..\blockMemory.vhd +vhpcomp -work work ..\..\example_design\blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + +fuse work.blockMemory_tb -L unisims -L xilinxcorelib -o blockMemory_tb.exe + + +.\blockMemory_tb.exe -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional/simulate_mti.do (revision 5) @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../../blockMemory.vhd \ + ../../example_design/blockMemory_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + +vsim -novopt -t ps -L XilinxCoreLib -L unisim work.blockMemory_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/functional Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/data_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/data_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/data_gen.vhd (revision 5) @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/addr_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/addr_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/addr_gen.vhd (revision 5) @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/checker.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/checker.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/checker.vhd (revision 5) @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/vcs_session.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/vcs_session.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/vcs_session.tcl (revision 5) @@ -0,0 +1,83 @@ + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG Generator v8.4 Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- + +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create blockMemory_Group +gui_list_add_group -id Wave.1 {blockMemory_Group} + + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/status + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + gui_sg_addsignal -group blockMemory_Group /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA + +gui_zoom -window Wave.1 -full Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simcmds.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simcmds.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simcmds.tcl (revision 5) @@ -0,0 +1,63 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /blockMemory_tb/status + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA + wave add /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA +run all +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.bat (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_ncsim.sv =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_ncsim.sv (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_ncsim.sv (revision 5) @@ -0,0 +1,20 @@ + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + + waveform add -signals /blockMemory_tb/status + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + waveform add -signals /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +console submit -using simulator -wait no "run" Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/ucli_commands.key =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/ucli_commands.key (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/ucli_commands.key (revision 5) @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add blockMemory_tb +run +quit Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.sh (revision 5) @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_ncsim.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_ncsim.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_ncsim.sh (revision 5) @@ -0,0 +1,78 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +mkdir work + + +ncvhdl -v93 -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../blockMemory_synth.vhd +ncvhdl -v93 -work work ../blockMemory_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :blockMemory_synth_inst:BMG_PORT,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + + +echo "Elaborating Design" +ncelab -access +rwc -sdf_cmd_file sdf.cmd $work.blockMemory_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.blockMemory_tb Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_vcs.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_vcs.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_vcs.sh (revision 5) @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh + +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhdlan ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../blockMemory_synth.vhd +vhdlan ../blockMemory_tb.vhd + + +echo "Elaborating Design" +vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_isim.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_isim.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_isim.bat (revision 5) @@ -0,0 +1,67 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vhpcomp -work work ..\..\implement\results\routed.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\blockMemory_synth.vhd +vhpcomp -work work ..\blockMemory_tb.vhd + + + fuse -L simprim work.blockMemory_tb -o blockMemory_tb.exe + +.\blockMemory_tb.exe -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/wave_mti.do (revision 5) @@ -0,0 +1,36 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + + add wave -noupdate /blockMemory_tb/status + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/RSTA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/CLKA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/ADDRA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DINA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/WEA + add wave -noupdate /blockMemory_tb/blockMemory_synth_inst/bmg_port/DOUTA +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.do =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.do (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing/simulate_mti.do (revision 5) @@ -0,0 +1,75 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core VHDL UNISIM/Behavioral model" +vcom -work work ../../implement/results/routed.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../blockMemory_synth.vhd +vcom -work work ../blockMemory_tb.vhd + + vsim -novopt -t ps -L simprim +transport_int_delays -sdftyp /blockMemory_tb/blockMemory_synth_inst/bmg_port=../../implement/results/routed.sdf $work.blockMemory_tb -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/timing Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_tb.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_tb.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_tb.vhd (revision 5) @@ -0,0 +1,129 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: blockMemory_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY blockMemory_tb IS +END ENTITY; + + +ARCHITECTURE blockMemory_tb_ARCH OF blockMemory_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "Simulation Complete" + SEVERITY FAILURE; + END IF; +END PROCESS; + + blockMemory_synth_inst:ENTITY work.blockMemory_synth + PORT MAP( + CLK_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_synth.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_synth.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/blockMemory_synth.vhd (revision 5) @@ -0,0 +1,289 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: blockMemory_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY blockMemory_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE blockMemory_synth_ARCH OF blockMemory_synth IS + + +COMPONENT blockMemory_exdes + PORT ( + --Inputs - Port A + RSTA : IN STD_LOGIC; --opt port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + CLKA : IN STD_LOGIC + + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTA: STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 64, + READ_WIDTH => 64 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_EN_R, + DATA_IN => DOUTA, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLK => clk_in_i, + RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + WEA => WEA, + CHECK_DATA => CHECKER_EN + ); + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: blockMemory_exdes PORT MAP ( + --Port A + RSTA => RSTA, + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + DOUTA => DOUTA, + CLKA => CLKA + + ); +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_stim_gen.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_stim_gen.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_stim_gen.vhd (revision 5) @@ -0,0 +1,243 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Stimulus Generator For Single Port Ram +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SRAM +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; + +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC_SRAM IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC_SRAM; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS + SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + + CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(64,64); + SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_WRITE : STD_LOGIC := '0'; + SIGNAL DO_READ : STD_LOGIC := '0'; + SIGNAL COUNT_NO : INTEGER :=0; + SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); +BEGIN + WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0); + READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0); + ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ; + DINA <= DINA_INT ; + + CHECK_DATA <= DO_READ; + +RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + +WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 16 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + +WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 64, + DOUT_WIDTH => 64, + DATA_PART_CNT => DATA_PART_CNT_A, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + +WR_RD_PROCESS: PROCESS (CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + ELSIF(COUNT_NO < 4) THEN + DO_WRITE <= '1'; + DO_READ <= '0'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO< 8) THEN + DO_WRITE <= '0'; + DO_READ <= '1'; + COUNT_NO <= COUNT_NO + 1; + ELSIF(COUNT_NO=8) THEN + DO_WRITE <= '0'; + DO_READ <= '0'; + COUNT_NO <= 0 ; + END IF; + END IF; +END PROCESS; + +BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(0), + CLK => CLK, + RST => RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM + PORT MAP( + Q => DO_READ_REG(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG; + + WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ; + +END ARCHITECTURE; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_tb_pkg.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_tb_pkg.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation/bmg_tb_pkg.vhd (revision 5) @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_1 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/simulation Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_v7_1_vinfo.html (revision 5) @@ -0,0 +1,237 @@ + + +blk_mem_gen_v7_1_vinfo + + + +
+ Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + + +
+ + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_ds512.pdf =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_ds512.pdf (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_ds512.pdf (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc/blk_mem_gen_ds512.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/doc Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/blk_mem_gen_v7_1_readme.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/blk_mem_gen_v7_1_readme.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/blk_mem_gen_v7_1_readme.txt (revision 5) @@ -0,0 +1,226 @@ + Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.1 + Release: ISE 14.1 / Vivado 2012.1 + Release Date: April 24, 2012 + + +================================================================================ + +This document contains the following sections: + +This document contains the following sections: + +1. Introduction +2. New Features + 2.1 ISE + 2.2 Vivado +3. Supported Devices + 3.1 ISE + 3.2 Vivado +4. Resolved Issues + 4.1 ISE + 4.2 Vivado +5. Known Issues + 5.1 ISE + 5.2 Vivado +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ +2. NEW FEATURES + + + 2.1 ISE + + - ISE 14.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + + 2.2 Vivado + + - 2012.1 software support + - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, + and Automotive Zynq device support + + +................................................................................ +3. SUPPORTED DEVICES + + + 3.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 3.2 Vivado + All 7 Series devices + Zynq-7000 devices + + +................................................................................ +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.1: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ +5. KNOWN ISSUES + + + 5.1 ISE + + The following are known issues for v7.1 of this core at time of release: + + 1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First) + Work around: The user must review the possible scenarios that causes the collission and revise + their design to avoid those situations. + - CR588505 + + Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with + Write Mode = Read First in conjunction with asynchronous clocking + + 2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + + +................................................................................ +6. TECHNICAL SUPPORT + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2006 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.bat (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy blockMemory_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\blockMemory.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\blockMemory_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/implement.sh (revision 5) @@ -0,0 +1,48 @@ + + + + + + + + +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp blockMemory_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../blockMemory.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/blockMemory_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes + +echo 'Running map' +map blockMemory_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.scr =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.scr (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.scr (revision 5) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent blockMemory_exdes +-p xc3s500e-fg320-5 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn blockMemory_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.bat =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.bat (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.bat (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\blockMemory.ngc . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.prj =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.prj (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/xst.prj (revision 5) @@ -0,0 +1 @@ +work ../example_design/blockMemory_exdes.vhd Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.sh =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.sh (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_rdn.sh (revision 5) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../blockMemory.ngc . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement/planAhead_ise.tcl (revision 5) @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc3s500efg320-5 +set projName blockMemory +set design blockMemory +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blockMemory_exdes +add_files -norecurse {../../example_design/blockMemory_exdes.vhd} +add_files -norecurse {./blockMemory.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blockMemory_exdes.xdc} +set_property top blockMemory_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module blockMemory_exdes -file routed.sdf +write_vhdl -mode sim routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory/implement Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.v =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.v (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.v (revision 5) @@ -0,0 +1,180 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module blockMemory( + clka, + rsta, + wea, + addra, + dina, + douta +); + +input clka; +input rsta; +input [0 : 0] wea; +input [3 : 0] addra; +input [511 : 0] dina; +output [511 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V7_1 #( + .C_ADDRA_WIDTH(4), + .C_ADDRB_WIDTH(4), + .C_ALGORITHM(0), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(1), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(0), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(6), + .C_READ_DEPTH_A(16), + .C_READ_DEPTH_B(16), + .C_READ_WIDTH_A(512), + .C_READ_WIDTH_B(512), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(16), + .C_WRITE_DEPTH_B(16), + .C_WRITE_MODE_A("READ_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(512), + .C_WRITE_WIDTH_B(512), + .C_XDEVICEFAMILY("spartan3e") + ) + inst ( + .CLKA(clka), + .RSTA(rsta), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .ENA(), + .REGCEA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.ncf =================================================================== Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.ngc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.ngc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.ngc (revision 5) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ + BLOCK + 2015-2-1T10:47:44 + + + + + + + + blockMemory + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xise =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xise (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xise (revision 5) @@ -0,0 +1,386 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/xlnx_auto_0_xdb =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/xlnx_auto_0_xdb (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/xlnx_auto_0_xdb (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/xlnx_auto_0_xdb Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/gen_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/gen_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/gen_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator regen command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_regen "blockMemory" xc3s500e-5fg320 VHDL CURRENT ] + +if { $result == 0 } { + puts "Core Generator regen command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator regen command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator regen cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/cg.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/cg.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/cg.xmsgs (revision 5) @@ -0,0 +1,27 @@ + + + +Generating IP... + + +A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten. + + +Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis + + +Pre-processing HDL files for 'blockMemory'... + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/blockMemory.lso =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/blockMemory.lso (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/blockMemory.lso (revision 5) @@ -0,0 +1 @@ +work Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/pn_parser.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/pn_parser.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/pn_parser.xmsgs (revision 5) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/blockMemory.vhd" into library work + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/xst.xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/xst.xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs/xst.xmsgs (revision 5) @@ -0,0 +1,412 @@ + + + +Message file "usenglish/ip.msg" wasn't found. + + +0: (0,0) : 72x256 u:64 + + +0: (0,0) : 72x256 u:64 + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4199: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4206: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Range is empty (null range) + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 4213: Assignment ignored + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_wrapper_s3.vhd" Line 370: Net <doutb_i[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[71]> does not have a driver. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns FALSE. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <doutb> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blockMemory.vhd" line 161: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +Input <S_AXI_AWID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WDATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARADDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARLEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARSIZE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARBURST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v7_1_xst', is tied to its initial value (0000). + + +Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEA<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"E:\spent i praca\OpenCores\ModMultExp_opencores_edition\rtl\vhdl\mod_exp\blockMemory\tmp\_cg\_dbg\blk_mem_gen_v7_1\blk_mem_gen_generic_cstr.vhd" line 1343: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'dina_pad<71>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<62>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<53>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<44>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<71>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<62>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<53>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<44>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <ADDRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'doutb_i', unconnected in block 'blk_mem_gen_prim_wrapper_s3', is tied to its initial value (000000000000000000000000000000000000000000000000000000000000000000000000). + + +Input <DOUTB_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RDADDRECC_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + +You have chosen to run a version of XST which is not the default solution +for the specified device family. You are free to use it in order to take +advantage of its enhanced HDL parsing/elaboration capabilities. However, +please be aware that you may be impacted by language support differences. +This version may also result in circuit performance and device utilization +differences for your particular design. You can always revert back to the +default XST solution by setting the "use_new_parser" option to value "no" +on the XST command line or in the XST process properties panel. + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_cg =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_cg (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_cg (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/tmp/_cg Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/tmp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/tmp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/tmp (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64/tmp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_flist.txt =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_flist.txt (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_flist.txt (revision 5) @@ -0,0 +1,59 @@ +# Output products list for +_xmsgs\pn_parser.xmsgs +blockMemory.asy +blockMemory.gise +blockMemory.ngc +blockMemory.vhd +blockMemory.vho +blockMemory.xco +blockMemory.xise +blockMemory\blk_mem_gen_v7_1_readme.txt +blockMemory\doc\blk_mem_gen_ds512.pdf +blockMemory\doc\blk_mem_gen_v7_1_vinfo.html +blockMemory\example_design\blockMemory_exdes.ucf +blockMemory\example_design\blockMemory_exdes.vhd +blockMemory\example_design\blockMemory_exdes.xdc +blockMemory\example_design\blockMemory_prod.vhd +blockMemory\implement\implement.bat +blockMemory\implement\implement.sh +blockMemory\implement\planAhead_ise.bat +blockMemory\implement\planAhead_ise.sh +blockMemory\implement\planAhead_ise.tcl +blockMemory\implement\planAhead_rdn.bat +blockMemory\implement\planAhead_rdn.sh +blockMemory\implement\planAhead_rdn.tcl +blockMemory\implement\xst.prj +blockMemory\implement\xst.scr +blockMemory\simulation\addr_gen.vhd +blockMemory\simulation\blockMemory_synth.vhd +blockMemory\simulation\blockMemory_tb.vhd +blockMemory\simulation\bmg_stim_gen.vhd +blockMemory\simulation\bmg_tb_pkg.vhd +blockMemory\simulation\checker.vhd +blockMemory\simulation\data_gen.vhd +blockMemory\simulation\functional\simcmds.tcl +blockMemory\simulation\functional\simulate_isim.bat +blockMemory\simulation\functional\simulate_mti.bat +blockMemory\simulation\functional\simulate_mti.do +blockMemory\simulation\functional\simulate_mti.sh +blockMemory\simulation\functional\simulate_ncsim.sh +blockMemory\simulation\functional\simulate_vcs.sh +blockMemory\simulation\functional\ucli_commands.key +blockMemory\simulation\functional\vcs_session.tcl +blockMemory\simulation\functional\wave_mti.do +blockMemory\simulation\functional\wave_ncsim.sv +blockMemory\simulation\random.vhd +blockMemory\simulation\timing\simcmds.tcl +blockMemory\simulation\timing\simulate_isim.bat +blockMemory\simulation\timing\simulate_mti.bat +blockMemory\simulation\timing\simulate_mti.do +blockMemory\simulation\timing\simulate_mti.sh +blockMemory\simulation\timing\simulate_ncsim.sh +blockMemory\simulation\timing\simulate_vcs.sh +blockMemory\simulation\timing\ucli_commands.key +blockMemory\simulation\timing\vcs_session.tcl +blockMemory\simulation\timing\wave_mti.do +blockMemory\simulation\timing\wave_ncsim.sv +blockMemory_flist.txt +blockMemory_xmdf.tcl +summary.log Index: trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.log (revision 5) @@ -0,0 +1,60 @@ +INFO:sim:172 - Generating IP... +Applying current project options... +Finished applying current project options. +Resolving generics for 'blockMemory'... +WARNING:sim - A core named 'blockMemory' already exists in the project. Output + products for this core may be overwritten. +Applying external generics to 'blockMemory'... +Delivering associated files for 'blockMemory'... +WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for + VHDL synthesis +Delivering EJava files for 'blockMemory'... +Generating implementation netlist for 'blockMemory'... +INFO:sim - Pre-processing HDL files for 'blockMemory'... +Running synthesis for 'blockMemory' +Running ngcbuild... +Writing VHO instantiation template for 'blockMemory'... +Writing VHDL behavioral simulation model for 'blockMemory'... +Generating ASY schematic symbol... +INFO:sim:949 - Finished generation of ASY schematic symbol. +Generating SYM schematic symbol for 'blockMemory'... +Generating metadata file... +Generating ISE project... +XCO file found: blockMemory.xco +XMDF file found: blockMemory_xmdf.tcl +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.asy -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc -view all -origin_type created +Checking file "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" for project device match ... +File "E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.ngc" device information matches project device. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.sym -view all -origin_type imported +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vhd -view all -origin_type created +INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i + praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp + /_cg/blockMemory.vhd" into library work +INFO:ProjectMgmt - Parsing design hierarchy completed successfully. +Adding E:/spent i +praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c +g/blockMemory.vho -view all -origin_type imported +INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. + Please set the new top explicitly by running the "project set top" command. + To re-calculate the new top automatically, set the "Auto Implementation Top" + property to true. +Top level has been set to "/blockMemory" +Generating README file... +Generating FLIST file... +INFO:sim:948 - Finished FLIST file generation. +Moving files to output directory... +Finished moving files to output directory +Wrote CGP file for project 'blockMemory'. Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd (revision 5) @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY blockMemory IS + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END blockMemory; + +ARCHITECTURE blockMemory_a OF blockMemory IS +-- synthesis translate_off +COMPONENT wrapped_blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_blockMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_1(behavioral) + GENERIC MAP ( + c_addra_width => 4, + c_addrb_width => 4, + c_algorithm => 0, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 1, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 0, + c_mux_pipeline_stages => 0, + c_prim_type => 6, + c_read_depth_a => 16, + c_read_depth_b => 16, + c_read_width_a => 64, + c_read_width_b => 64, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 16, + c_write_depth_b => 16, + c_write_mode_a => "READ_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 64, + c_write_width_b => 64, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- synthesis translate_on + +END blockMemory_a; Index: trunk/rtl/vhdl/mod_exp/blockMemory64/edit_blockMemory.tcl =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/edit_blockMemory.tcl (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/edit_blockMemory.tcl (revision 5) @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "blockMemory" xc3s500e-5fg320 VHDL ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.gise =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.gise (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.gise (revision 5) @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_beh.cgp =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_beh.cgp (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory_beh.cgp (revision 5) @@ -0,0 +1,22 @@ +# Date: Sat Dec 22 01:24:09 2012 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +SET workingdirectory = .\tmp\ + +# CRC: 46f7aa00 Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xco =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xco (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.xco (revision 5) @@ -0,0 +1,106 @@ +############################################################## +# +# Xilinx Core Generator version 14.2 +# Date: Sun Feb 01 11:01:19 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s500e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg320 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Fixed_Primitives +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=blockMemory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Single_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=256x72 +CSET read_width_a=64 +CSET read_width_b=64 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=true +CSET use_rstb_pin=false +CSET write_depth_a=16 +CSET write_width_a=64 +CSET write_width_b=64 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-01T17:17:26Z +# END Extra information +GENERATE +# CRC: b6414ecb Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.veo =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.veo (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.veo (revision 5) @@ -0,0 +1,70 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 * +* * +* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * +* Block Memory and Single Port Block Memory LogiCOREs, but is not a * +* direct drop-in replacement. It should be used in all new Xilinx * +* designs. The core supports RAM and ROM functions over a wide range of * +* widths and depths. Use this core to generate block memories with * +* symmetric or asymmetric read and write port widths, as well as cores * +* which can perform simultaneous write operations to separate * +* locations, and simultaneous read operations from the same location. * +* For more information on differences in interface and feature support * +* between this core and the Dual Port Block Memory and Single Port * +* Block Memory LogiCOREs, please consult the data sheet. * +*******************************************************************************/ + +// Interfaces: +// AXI_SLAVE_S_AXI +// AXI_SLAVE +// AXILite_SLAVE_S_AXI +// AXILite_SLAVE + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +blockMemory your_instance_name ( + .clka(clka), // input clka + .rsta(rsta), // input rsta + .wea(wea), // input [0 : 0] wea + .addra(addra), // input [3 : 0] addra + .dina(dina), // input [511 : 0] dina + .douta(douta) // output [511 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file blockMemory.v when simulating +// the core, blockMemory. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/summary.log =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/summary.log (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/summary.log (revision 5) @@ -0,0 +1,18 @@ + +User Configuration +------------------------------------- +Algorithm : Fixed_Primitives +Memory Type : Single_Port_RAM +Port A Read Width : 64 +Port A Write Width : 64 +Memory Depth : 16 +-------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : 1 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 9.504473 mW +---------------------------------------------------------- Index: trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.cgc =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.cgc (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/coregen.cgc (revision 5) @@ -0,0 +1,725 @@ + + + xilinx.com + project + coregen + 1.0 + + + blockMemory + + + blockMemory + Native + AXI4_Full + Memory_Slave + false + 4 + Single_Port_RAM + false + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Fixed_Primitives + 256x72 + false + 64 + 16 + 64 + READ_FIRST + Always_Enabled + 64 + 64 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + false + no_coe_file_loaded + false + 0 + true + false + CE + 0 + false + false + CE + 0 + SYNC + false + 100 + 50 + 100 + 50 + 100 + 100 + ALL + false + false + spartan3 + spartan3e + E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_cg/ + 0 + 1 + 0 + 0 + 4 + 0 + 9 + 0 + 6 + 0 + no_coe_file_loaded + 0 + 0 + SYNC + 1 + CE + 0 + 0 + 0 + 0 + 0 + 1 + READ_FIRST + 64 + 64 + 16 + 16 + 4 + 0 + CE + 0 + 0 + 0 + 0 + 0 + 1 + WRITE_FIRST + 64 + 64 + 16 + 16 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ALL + 0 + 0 + 0 + 0 + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2012-05-01+17:17 + + + + + customization_generator + + ./summary.log + unknown + Sun Feb 01 11:01:05 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + model_parameter_resolution_generator + + ./summary.log + unknown + Sun Feb 01 11:01:18 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + ip_xco_generator + + ./blockMemory.xco + xco + Sun Feb 01 11:01:19 GMT 2015 + 0xB3588484 + generationID_4013899584 + + + + associated_files_generator + + ./blockMemory/blk_mem_gen_v7_1_readme.txt + ignore + txt + Sat Jul 21 06:09:39 GMT 2012 + 0xD29D9619 + generationID_4013899584 + + + ./blockMemory/doc/blk_mem_gen_ds512.pdf + ignore + pdf + Sat Jul 21 06:09:39 GMT 2012 + 0xC67523A8 + generationID_4013899584 + + + ./blockMemory/doc/blk_mem_gen_v7_1_vinfo.html + ignore + unknown + Sat Jul 21 06:09:39 GMT 2012 + 0x19E371FD + generationID_4013899584 + + + + ejava_generator + + ./blockMemory/example_design/blockMemory_exdes.ucf + ignore + ucf + Sun Feb 01 11:01:22 GMT 2015 + 0xC44C6B6D + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_exdes.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xC531B9D3 + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_exdes.xdc + ignore + xdc + Sun Feb 01 11:01:22 GMT 2015 + 0x7684D6D4 + generationID_4013899584 + + + ./blockMemory/example_design/blockMemory_prod.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xBCC35C04 + generationID_4013899584 + + + ./blockMemory/implement/implement.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x73DC98D0 + generationID_4013899584 + + + ./blockMemory/implement/implement.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xDA8C5F63 + generationID_4013899584 + + + ./blockMemory/implement/planAhead_ise.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xAB675294 + generationID_4013899584 + + + ./blockMemory/implement/planAhead_ise.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x2CC3322B + generationID_4013899584 + + + ./blockMemory/implement/planAhead_ise.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0xE0D499D8 + generationID_4013899584 + + + ./blockMemory/implement/planAhead_rdn.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xF18BE2F0 + generationID_4013899584 + + + ./blockMemory/implement/planAhead_rdn.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x762F824F + generationID_4013899584 + + + ./blockMemory/implement/planAhead_rdn.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0xE0D499D8 + generationID_4013899584 + + + ./blockMemory/implement/xst.prj + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x49531A1B + generationID_4013899584 + + + ./blockMemory/implement/xst.scr + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x0ACE6523 + generationID_4013899584 + + + ./blockMemory/simulation/addr_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xC4BD0686 + generationID_4013899584 + + + ./blockMemory/simulation/blockMemory_synth.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x242B5734 + generationID_4013899584 + + + ./blockMemory/simulation/blockMemory_tb.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x403EDE43 + generationID_4013899584 + + + ./blockMemory/simulation/bmg_stim_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xB51AD3DA + generationID_4013899584 + + + ./blockMemory/simulation/bmg_tb_pkg.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x888E222F + generationID_4013899584 + + + ./blockMemory/simulation/checker.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x165912E8 + generationID_4013899584 + + + ./blockMemory/simulation/data_gen.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0xAAF37274 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simcmds.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x32EA978C + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_isim.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x5732BCC0 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFFDC1F87 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_mti.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_ncsim.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x7DAF5A7C + generationID_4013899584 + + + ./blockMemory/simulation/functional/simulate_vcs.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x0377E85E + generationID_4013899584 + + + ./blockMemory/simulation/functional/ucli_commands.key + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x124DD850 + generationID_4013899584 + + + ./blockMemory/simulation/functional/vcs_session.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x65C492A4 + generationID_4013899584 + + + ./blockMemory/simulation/functional/wave_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xD1AE9DBA + generationID_4013899584 + + + ./blockMemory/simulation/functional/wave_ncsim.sv + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFA4242CF + generationID_4013899584 + + + ./blockMemory/simulation/random.vhd + ignore + vhdl + Sun Feb 01 11:01:22 GMT 2015 + 0x63A1BAB3 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simcmds.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0x32EA978C + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_isim.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x4934A6A9 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.bat + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x73AA9BB8 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_mti.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x86EA5D67 + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_ncsim.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0xFBC651DC + generationID_4013899584 + + + ./blockMemory/simulation/timing/simulate_vcs.sh + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x4D9140C3 + generationID_4013899584 + + + ./blockMemory/simulation/timing/ucli_commands.key + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x124DD850 + generationID_4013899584 + + + ./blockMemory/simulation/timing/vcs_session.tcl + ignore + tcl + Sun Feb 01 11:01:22 GMT 2015 + 0xB2A5A6F2 + generationID_4013899584 + + + ./blockMemory/simulation/timing/wave_mti.do + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x9F72A3C7 + generationID_4013899584 + + + ./blockMemory/simulation/timing/wave_ncsim.sv + ignore + unknown + Sun Feb 01 11:01:22 GMT 2015 + 0x3E2BD0E3 + generationID_4013899584 + + + + ngc_netlist_generator + + ./blockMemory.ngc + ngc + Sun Feb 01 11:03:12 GMT 2015 + 0xB01C4161 + generationID_4013899584 + + + + obfuscate_netlist_generator + + + padded_implementation_netlist_generator + + + instantiation_template_generator + + ./blockMemory.vho + vho + Sun Feb 01 11:03:15 GMT 2015 + 0x533BD793 + generationID_4013899584 + + + + structural_simulation_model_generator + + ./blockMemory.vhd + vhdl + Sun Feb 01 11:03:16 GMT 2015 + 0x4F617396 + generationID_4013899584 + + + + asy_generator + + ./blockMemory.asy + asy + Sun Feb 01 11:03:25 GMT 2015 + 0xD23467E4 + generationID_4013899584 + + + ./summary.log + unknown + Sun Feb 01 11:03:25 GMT 2015 + 0x276B8704 + generationID_4013899584 + + + + xmdf_generator + + ./blockMemory_xmdf.tcl + tclXmdf + tcl + Sun Feb 01 11:03:25 GMT 2015 + 0x0F84EBAC + generationID_4013899584 + + + + ise_generator + + ./_xmsgs/pn_parser.xmsgs + ignore + unknown + Sun Feb 01 11:03:38 GMT 2015 + 0x8B9E9C83 + generationID_4013899584 + + + ./blockMemory.gise + ignore + gise + Sun Feb 01 11:03:38 GMT 2015 + 0x12517467 + generationID_4013899584 + + + ./blockMemory.xise + ignore + xise + Sun Feb 01 11:03:38 GMT 2015 + 0xBEBA0475 + generationID_4013899584 + + + + deliver_readme_generator + + + flist_generator + + ./blockMemory_flist.txt + ignore + txtFlist + txt + Sun Feb 01 11:03:39 GMT 2015 + 0x56F501F4 + generationID_4013899584 + + + + view_readme_generator + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s500e + spartan3e + fg320 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vho =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vho (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.vho (revision 5) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2015 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.1 -- +-- -- +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port -- +-- Block Memory and Single Port Block Memory LogiCOREs, but is not a -- +-- direct drop-in replacement. It should be used in all new Xilinx -- +-- designs. The core supports RAM and ROM functions over a wide range of -- +-- widths and depths. Use this core to generate block memories with -- +-- symmetric or asymmetric read and write port widths, as well as cores -- +-- which can perform simultaneous write operations to separate -- +-- locations, and simultaneous read operations from the same location. -- +-- For more information on differences in interface and feature support -- +-- between this core and the Dual Port Block Memory and Single Port -- +-- Block Memory LogiCOREs, please consult the data sheet. -- +-------------------------------------------------------------------------------- + +-- Interfaces: +-- AXI_SLAVE_S_AXI +-- AXI_SLAVE +-- AXILite_SLAVE_S_AXI +-- AXILite_SLAVE +-- BRAM_PORTA +-- BRAM_PORTA +-- BRAM_PORTB +-- BRAM_PORTB + +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT blockMemory + PORT ( + clka : IN STD_LOGIC; + rsta : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : blockMemory + PORT MAP ( + clka => clka, + rsta => rsta, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file blockMemory.vhd when simulating +-- the core, blockMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + Index: trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.asy =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.asy (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64/blockMemory.asy (revision 5) @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 blockMemory +RECTANGLE Normal 32 32 544 1376 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[3:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[63:0] +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rsta +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[63:0] +PINATTR Polarity OUT + Index: trunk/rtl/vhdl/mod_exp/blockMemory64 =================================================================== --- trunk/rtl/vhdl/mod_exp/blockMemory64 (nonexistent) +++ trunk/rtl/vhdl/mod_exp/blockMemory64 (revision 5)

trunk/rtl/vhdl/mod_exp/blockMemory64 Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/sim/rtl_sim/bin/ModExp512bitTB_stx_beh.prj =================================================================== --- trunk/sim/rtl_sim/bin/ModExp512bitTB_stx_beh.prj (nonexistent) +++ trunk/sim/rtl_sim/bin/ModExp512bitTB_stx_beh.prj (revision 5) @@ -0,0 +1,9 @@ +vhdl isim_temp "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/properties.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/MontMult4inMux.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/Reg.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExp.vhd" +vhdl isim_temp "../../../bench/vhdl/mod_exp/ModExp512bitTB.vhd" Index: trunk/sim/rtl_sim/bin/ModExp64bitTB_stx_beh.prj =================================================================== --- trunk/sim/rtl_sim/bin/ModExp64bitTB_stx_beh.prj (nonexistent) +++ trunk/sim/rtl_sim/bin/ModExp64bitTB_stx_beh.prj (revision 5) @@ -0,0 +1,9 @@ +vhdl isim_temp "../../../rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/properties_64bit.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/MontMult4inMux.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/Reg.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExp.vhd" +vhdl isim_temp "../../../bench/vhdl/mod_exp/ModExp64bitTB.vhd" Index: trunk/sim/rtl_sim/bin/ModExp512bitTB_beh.prj =================================================================== --- trunk/sim/rtl_sim/bin/ModExp512bitTB_beh.prj (nonexistent) +++ trunk/sim/rtl_sim/bin/ModExp512bitTB_beh.prj (revision 5) @@ -0,0 +1,9 @@ +vhdl work "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd" +vhdl work "../../../rtl/vhdl/commons/properties.vhd" +vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" +vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd" +vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" +vhdl work "../../../rtl/vhdl/commons/Reg.vhd" +vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" +vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd" +vhdl work "../../../bench/vhdl/mod_exp/ModExp512bitTB.vhd" Index: trunk/sim/rtl_sim/bin/ModExp64bitTB_beh.prj =================================================================== --- trunk/sim/rtl_sim/bin/ModExp64bitTB_beh.prj (nonexistent) +++ trunk/sim/rtl_sim/bin/ModExp64bitTB_beh.prj (revision 5) @@ -0,0 +1,9 @@ +vhdl work "../../../rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd" +vhdl work "../../../rtl/vhdl/commons/properties_64bit.vhd" +vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" +vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd" +vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" +vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" +vhdl work "../../../rtl/vhdl/commons/Reg.vhd" +vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd" +vhdl work "../../../bench/vhdl/mod_exp/ModExp64bitTB.vhd" Index: trunk/sim/rtl_sim/bin/ModExp32bitTB_stx_beh.prj =================================================================== --- trunk/sim/rtl_sim/bin/ModExp32bitTB_stx_beh.prj (nonexistent) +++ trunk/sim/rtl_sim/bin/ModExp32bitTB_stx_beh.prj (revision 5) @@ -0,0 +1,9 @@ +vhdl isim_temp "../../../rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/properties_32bit.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/MontMult4inMux.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExpSM.vhd" +vhdl isim_temp "../../../rtl/vhdl/commons/Reg.vhd" +vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExp.vhd" +vhdl isim_temp "../../../bench/vhdl/mod_exp/ModExp32bitTB.vhd" Index: trunk/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/sim/rtl_sim/bin/Makefile (revision 4) +++ trunk/sim/rtl_sim/bin/Makefile (revision 5) @@ -16,6 +16,7 @@ $(RM) *.xmsgs $(RM) ./fuseRelaunch.cmd $(RM) *.exe + $(RM) *.wdb exports: export DISPLAY=:0 @@ -24,7 +25,7 @@ export PATH=${XILINX}/bin/${SYSOP} export LD_LIBRARY_PATH=${XILINX}/lib/${SYSOP} -ModMult32: +ModMult32: exports $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ModularMultiplierIterative32bitTB_stx_beh.prj $(FUSE) -intstyle ise -incremental -o ModularMultiplierIterative32bitTB_isim_beh.exe -prj ./ModularMultiplierIterative32bitTB_beh.prj work.ModularMultiplierIterative32bitTB @@ -31,14 +32,35 @@ run_ModMult32: exports ModMult32 "./ModularMultiplierIterative32bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModularMultiplierIterative32bitTB_isim_beh.wdb" -ModMult64: +ModMult64: exports $(FUSE) -intstyle ise -incremental -o ModularMultiplierIterative64bitTB_isim_beh.exe -prj ./ModularMultiplierIterative64bitTB_beh.prj work.ModularMultiplierIterative64bitTB run_ModMult64: exports ModMult64 "./ModularMultiplierIterative64bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "ModularMultiplierIterative64bitTB_isim_beh.wdb" -ModMult512: +ModMult512: exports $(FUSE) -intstyle ise -incremental -o ModularMultiplierIterative512bitTB_isim_beh.exe -prj ./ModularMultiplierIterative512bitTB_beh.prj work.ModularMultiplierIterative512bitTB run_ModMult512: exports ModMult512 - "./ModularMultiplierIterative512bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "ModularMultiplierIterative512bitTB_isim_beh.wdb" \ No newline at end of file + "./ModularMultiplierIterative512bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "ModularMultiplierIterative512bitTB_isim_beh.wdb" + +ModExp32: exports + $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ModExp32bitTB_stx_beh.prj + $(FUSE) -intstyle ise -incremental -o ModExp32bitTB_isim_beh.exe -prj ./ModExp32bitTB_beh.prj work.ModExp32bitTB + +run_ModExp32: exports ModExp32 + "./ModExp32bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModExp32bitTB_isim_beh.wdb" + +ModExp64: exports + $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ModExp64bitTB_stx_beh.prj + $(FUSE) -intstyle ise -incremental -o ModExp64bitTB_isim_beh.exe -prj ./ModExp64bitTB_beh.prj work.ModExp64bitTB + +run_ModExp64: exports ModExp64 + "./ModExp64bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModExp64bitTB_isim_beh.wdb" + +ModExp512: exports + $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ModExp512bitTB_stx_beh.prj + $(FUSE) -intstyle ise -incremental -o ModExp512bitTB_isim_beh.exe -prj ./ModExp512bitTB_beh.prj work.ModExp512bitTB + +run_ModExp512: exports ModExp512 + "./ModExp512bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModExp512bitTB_isim_beh.wdb"

/trunk/sim/rtl_sim/bin/ModExp32bitTB_beh.prj
0,0 → 1,9

vhdl work "../../../rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd"

vhdl work "../../../rtl/vhdl/commons/properties_32bit.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"

vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"

vhdl work "../../../rtl/vhdl/commons/Reg.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"

vhdl work "../../../bench/vhdl/mod_exp/ModExp32bitTB.vhd"

/trunk/syn/XC3ES500/mod_exp/ModExp64.prj
0,0 → 1,8

vhdl work "../../../rtl/vhdl/mod_exp/blockMemory64/blockMemory.vhd"

vhdl work "../../../rtl/vhdl/commons/properties_64bit.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"

vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"

vhdl work "../../../rtl/vhdl/commons/Reg.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"

/trunk/syn/XC3ES500/mod_exp/ModExp512.xst
0,0 → 1,57

set -tmpdir "xst/projnav.tmp"

set -xsthdpdir "xst"

run

-ifn ModExp512.prj

-ifmt mixed

-ofn ModExp

-ofmt NGC

-p xc3s500e-5-fg320

-top ModExp

-opt_mode Speed

-opt_level 1

-iuc NO

-keep_hierarchy Soft

-netlist_hierarchy As_Optimized

-rtlview Yes

-glob_opt AllClockNets

-read_cores YES

-sd {"../../../rtl/vhdl/mod_exp/blockMemory512" }

-write_timing_constraints NO

-cross_clock_analysis NO

-hierarchy_separator /

-bus_delimiter <>

-case Maintain

-slice_utilization_ratio 100

-bram_utilization_ratio 100

-verilog2001 YES

-fsm_extract YES -fsm_encoding Auto

-safe_implementation No

-fsm_style LUT

-ram_extract Yes

-ram_style Auto

-rom_extract Yes

-mux_style Auto

-decoder_extract YES

-priority_extract Yes

-shreg_extract YES

-shift_extract YES

-xor_collapse YES

-rom_style Auto

-auto_bram_packing NO

-mux_extract Yes

-resource_sharing YES

-async_to_sync NO

-mult_style Auto

-iobuf YES

-max_fanout 100000

-bufg 24

-register_duplication YES

-register_balancing No

-slice_packing YES

-optimize_primitives NO

-use_clock_enable Yes

-use_sync_set Yes

-use_sync_reset Yes

-iob Auto

-equivalent_register_removal YES

-slice_utilization_ratio_maxmargin 5

/trunk/syn/XC3ES500/mod_exp/ModExp.ut
0,0 → 1,22

-w

-g DebugBitstream:No

-g Binary:no

-g CRC:Enable

-g ConfigRate:1

-g ProgPin:PullUp

-g DonePin:PullUp

-g TckPin:PullUp

-g TdiPin:PullUp

-g TdoPin:PullUp

-g TmsPin:PullUp

-g UnusedPin:PullDown

-g UserID:0xFFFFFFFF

-g DCMShutdown:Disable

-g StartUpClk:CClk

-g DONE_cycle:4

-g GTS_cycle:5

-g GWE_cycle:6

-g LCK_cycle:NoWait

-g Security:None

-g DonePipe:Yes

-g DriveDone:No

/trunk/syn/XC3ES500/mod_exp/ModExp64.xst
0,0 → 1,57

set -tmpdir "xst/projnav.tmp"

set -xsthdpdir "xst"

run

-ifn ModExp64.prj

-ifmt mixed

-ofn ModExp

-ofmt NGC

-p xc3s500e-5-fg320

-top ModExp

-opt_mode Speed

-opt_level 1

-iuc NO

-keep_hierarchy Soft

-netlist_hierarchy As_Optimized

-rtlview Yes

-glob_opt AllClockNets

-read_cores YES

-sd {"../../../rtl/vhdl/mod_exp/blockMemory64" }

-write_timing_constraints NO

-cross_clock_analysis NO

-hierarchy_separator /

-bus_delimiter <>

-case Maintain

-slice_utilization_ratio 100

-bram_utilization_ratio 100

-verilog2001 YES

-fsm_extract YES -fsm_encoding Auto

-safe_implementation No

-fsm_style LUT

-ram_extract Yes

-ram_style Auto

-rom_extract Yes

-mux_style Auto

-decoder_extract YES

-priority_extract Yes

-shreg_extract YES

-shift_extract YES

-xor_collapse YES

-rom_style Auto

-auto_bram_packing NO

-mux_extract Yes

-resource_sharing YES

-async_to_sync NO

-mult_style Auto

-iobuf YES

-max_fanout 100000

-bufg 24

-register_duplication YES

-register_balancing No

-slice_packing YES

-optimize_primitives NO

-use_clock_enable Yes

-use_sync_set Yes

-use_sync_reset Yes

-iob Auto

-equivalent_register_removal YES

-slice_utilization_ratio_maxmargin 5

/trunk/syn/XC3ES500/mod_exp/ModExp32.prj
0,0 → 1,8

vhdl work "../../../rtl/vhdl/mod_exp/blockMemory32/blockMemory.vhd"

vhdl work "../../../rtl/vhdl/commons/properties_32bit.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"

vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"

vhdl work "../../../rtl/vhdl/commons/Reg.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"

/trunk/syn/XC3ES500/mod_exp/Makefile
0,0 → 1,58

PROJECT=mont-exp

RM=/bin/rm -rf

CP=/bin/cp

PLATFORM=xc3s500e-fg320-5

XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"

XST_DIR=$(XILINX_DIR)"xst.exe"

NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe"

MAP=$(XILINX_DIR)"map.exe"

PAR=$(XILINX_DIR)"par.exe"

TRCE=$(XILINX_DIR)"trce.exe"

BITGEN=$(XILINX_DIR)"bitgen.exe"

clean: clean_postgen

$(RM) "./out/"*.*

$(RM) "./log/"*.*

$(RM) "./out/"

$(RM) "./log/"

clean_postgen:

$(RM) "./_xmsgs"

$(RM) "./_ngo"

$(RM) "./xlnx_auto_0_xdb"

$(RM) "./xst"

$(RM) *_vhdl.prj *.bgn *.bld *.csv *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.ngr *.pad *.par *.pcf *.ptwx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt

synthesize: clean

mkdir "./xst"

mkdir "./xst/projnav.tmp"

mkdir "./out/"

mkdir "./log/"

$(XST_DIR) -intstyle ise -ifn "./ModExp$(word).xst" -ofn "./ModExp.syr"

translate: synthesize

$(NGDBUILD_DIR) -intstyle ise -dd _ngo -sd "../../../rtl/vhdl/mod_exp/blockMemory$(word)" -nt timestamp -i -p $(PLATFORM) "ModExp.ngc" ModExp.ngd

map: translate

$(MAP) -intstyle ise -p $(PLATFORM) -cm area -ir off -pr off -c 100 -o ModExp_map.ncd ModExp.ngd ModExp.pcf

par: map

$(PAR) -w -intstyle ise -ol high -t 1 ModExp_map.ncd ModExp.ncd ModExp.pcf

trce: par

$(TRCE) -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml ModExp.twx ModExp.ncd -o ModExp.twr ModExp.pcf

bitgen: trce

$(BITGEN) -intstyle ise -f ModExp.ut ModExp.ncd

postgen:

mv *.log ./log

mv *.xrpt ./log

mv *.txt ./log

mv *.xml ./log

mv *.html ./log

mv *.bit ./out

/trunk/syn/XC3ES500/mod_exp/ModExp512.prj
0,0 → 1,8

vhdl work "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd"

vhdl work "../../../rtl/vhdl/commons/properties.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"

vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"

vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"

vhdl work "../../../rtl/vhdl/commons/Reg.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"

vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"

/trunk/syn/XC3ES500/mod_exp/ModExp32.xst
0,0 → 1,57

set -tmpdir "xst/projnav.tmp"

set -xsthdpdir "xst"

run

-ifn ModExp32.prj

-ifmt mixed

-ofn ModExp

-ofmt NGC

-p xc3s500e-5-fg320

-top ModExp

-opt_mode Speed

-opt_level 1

-iuc NO

-keep_hierarchy Soft

-netlist_hierarchy As_Optimized

-rtlview Yes

-glob_opt AllClockNets

-read_cores YES

-sd {"../../../rtl/vhdl/mod_exp/blockMemory32" }

-write_timing_constraints NO

-cross_clock_analysis NO

-hierarchy_separator /

-bus_delimiter <>

-case Maintain

-slice_utilization_ratio 100

-bram_utilization_ratio 100

-verilog2001 YES

-fsm_extract YES -fsm_encoding Auto

-safe_implementation No

-fsm_style LUT

-ram_extract Yes

-ram_style Auto

-rom_extract Yes

-mux_style Auto

-decoder_extract YES

-priority_extract Yes

-shreg_extract YES

-shift_extract YES

-xor_collapse YES

-rom_style Auto

-auto_bram_packing NO

-mux_extract Yes

-resource_sharing YES

-async_to_sync NO

-mult_style Auto

-iobuf YES

-max_fanout 100000

-bufg 24

-register_duplication YES

-register_balancing No

-slice_packing YES

-optimize_primitives NO

-use_clock_enable Yes

-use_sync_set Yes

-use_sync_reset Yes

-iob Auto

-equivalent_register_removal YES

-slice_utilization_ratio_maxmargin 5

/trunk/syn/XC3ES500/mod_exp

trunk/syn/XC3ES500/mod_exp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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