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Rev 5 → Rev 6

/trunk/bench/vhdl/txt_util.vhd File deleted
/trunk/bench/vhdl/commons/ShiftRegTB.vhd
0,0 → 1,152
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator ----
---- https://opencores.org/projects/mod_mult_exp ----
---- ----
---- Description: ----
---- Test bench of shift register - nothing special. ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.properties.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ShiftRegTB IS
END ShiftRegTB;
ARCHITECTURE behavior OF ShiftRegTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ShiftReg
GENERIC (
length_1 : integer := BYTE;
length_2 : integer := WORD_LENGTH
);
PORT(
input : in STD_LOGIC_VECTOR(BYTE - 1 downto 0);
output : out STD_LOGIC_VECTOR(WORD_LENGTH - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
END COMPONENT;
 
--Inputs
signal input : STD_LOGIC_VECTOR(BYTE - 1 downto 0) := (others => '0');
signal en : STD_LOGIC := '0';
signal shift : STD_LOGIC := '0';
signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
 
--Outputs
signal output : STD_LOGIC_VECTOR(WORD_LENGTH - 1 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ShiftReg PORT MAP (
input => input,
output => output,
en => en,
shift => shift,
clk => clk,
reset => reset
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
reset <= '0';
shift <= '0';
input <= "10101010";
wait for 100 ns;
reset <= '1';
wait for clk_period*10;
reset <= '0';
en <= '1';
wait for clk_period*1;
en <= '0';
wait for clk_period*1;
 
------------- Test case 1 ------------------------
-- expected_output <= x"aa00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--------------------------------------------------
 
if output /= x"aa000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" then
report "RESULT MISMATCH! Test case 1 failed" severity ERROR;
assert false severity failure;
else
report "Test case 1 successful" severity note;
end if;
shift <= '1';
wait for clk_period*10;
------------- Test case 2 ------------------------
-- expected_output <= x"002a800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--------------------------------------------------
 
if output /= x"002a8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" then
report "RESULT MISMATCH! Test case 2 failed" severity ERROR;
assert false severity failure;
else
report "Test case 2 successful" severity note;
end if;
assert false severity failure;
end process;
 
END;
/trunk/bench/vhdl/commons/txt_util.vhd
0,0 → 1,586
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
 
 
package txt_util is
 
-- prints a message to the screen
procedure print(text: string);
 
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
 
-- converts std_logic into a character
function chr(sl: std_logic) return character;
 
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
 
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
 
-- converts boolean into a string
function str(b: boolean) return string;
 
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
 
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
 
-- converts integer to string, using base 10
function str(int: integer) return string;
 
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
 
 
-- functions to manipulate strings
-----------------------------------
 
-- convert a character to upper case
function to_upper(c: character) return character;
 
-- convert a character to lower case
function to_lower(c: character) return character;
 
-- convert a string to upper case
function to_upper(s: string) return string;
 
-- convert a string to lower case
function to_lower(s: string) return string;
 
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
 
 
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
 
 
 
 
package body txt_util is
 
 
 
 
-- prints text to the screen
 
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
 
 
 
 
-- prints text to the screen when active
 
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
 
 
-- converts std_logic into a character
 
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
 
 
 
-- converts std_logic into a string (1 to 1)
 
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
 
 
 
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
 
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
 
 
function str(b: boolean) return string is
 
begin
if b then
return "true";
else
return "false";
end if;
end str;
 
 
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
 
 
 
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
function str(int: integer; base: integer) return string is
 
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
 
begin
 
-- bug fix for negative numbers
abs_int := abs(int);
 
num := abs_int;
 
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
 
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
 
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
 
end str;
 
 
-- convert integer to string, using base 10
function str(int: integer) return string is
 
begin
 
return str(int, 10) ;
 
end str;
 
 
 
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
 
 
 
-- functions to manipulate strings
-----------------------------------
 
 
-- convert a character to upper case
 
function to_upper(c: character) return character is
 
variable u: character;
 
begin
 
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
 
return u;
 
end to_upper;
 
 
-- convert a character to lower case
 
function to_lower(c: character) return character is
 
variable l: character;
 
begin
 
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
 
return l;
 
end to_lower;
 
 
 
-- convert a string to upper case
 
function to_upper(s: string) return string is
 
variable uppercase: string (s'range);
 
begin
 
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
 
end to_upper;
 
 
 
-- convert a string to lower case
 
function to_lower(s: string) return string is
 
variable lowercase: string (s'range);
 
begin
 
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
 
end to_lower;
 
 
 
-- functions to convert strings into other types
 
 
-- converts a character into a std_logic
 
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
 
 
-- converts a string into std_logic_vector
 
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
 
 
 
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
 
 
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
 
 
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
 
 
 
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
 
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
 
 
 
 
end txt_util;
 
 
 
 
/trunk/bench/vhdl/commons
trunk/bench/vhdl/commons Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/bench/vhdl/communication/ModExpComm512bitTB.vhd =================================================================== --- trunk/bench/vhdl/communication/ModExpComm512bitTB.vhd (nonexistent) +++ trunk/bench/vhdl/communication/ModExpComm512bitTB.vhd (revision 6) @@ -0,0 +1,546 @@ +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator ---- +---- https://opencores.org/projects/mod_mult_exp ---- +---- ---- +---- Description: ---- +---- Test bench for Montgomery multiplier and exponentiator ---- +---- with 512 bit word length enclosed in RS232 communication ---- +---- with computer. Some kind of demo application of the ---- +---- project. Due to it uses serial communication, demo of ---- +---- this part is somewhat tricky. Most convienient way is to ---- +---- use graphical window. It is simulated all communication ---- +---- - sending data and exponentiation. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE std.textio.all; +USE work.txt_util.all; +USE ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY ModExpComm512bitTB IS +END ModExpComm512bitTB; + +ARCHITECTURE behavior OF ModExpComm512bitTB IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT ModExpComm + port ( + DATA_RXD : in STD_LOGIC; + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_TXD : out STD_LOGIC + ); + END COMPONENT; + + + --Inputs + signal DATA_RXD : STD_LOGIC := '0'; + signal CLK : STD_LOGIC := '0'; + signal RESET : STD_LOGIC := '0'; + + --Outputs + signal DATA_TXD : STD_LOGIC; + + -- Clock period definitions + constant CLK_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: ModExpComm + PORT MAP ( + DATA_RXD => DATA_RXD, + CLK => CLK, + RESET => RESET, + DATA_TXD => DATA_TXD + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + -- Stimulus process + stim_proc: process + + -- All data sent are prepared in files listed below. Data are stored + -- in sim/rtl_sim/bin folder . Data are grouped in packets of bytes. + -- Data from the files are explained in the Result.txt folder. + file BaseFile :text is in "testData512bit/Base.txt"; + file ModulusFile :text is in "testData512bit/Modulus.txt"; + file ExponentFile :text is in "testData512bit/Exponent.txt"; + file ResiduumFile :text is in "testData512bit/Residuum.txt"; + + variable line_in : line; + variable line_content : string(1 to 8); + variable data : STD_LOGIC; + + begin + DATA_RXD <= '1'; + RESET <= '1'; + wait for 1000 ns; + RESET <= '0'; + + wait for CLK_period*10; + + -- Data transmission + -- All data are sent in direction from LSB to MSB + -- 8.75 us is due to estimation of period of time needed for sending + -- one bit in RS-232 with 115 200 bps bandwith + + -- Command mn_read_base 00000 000 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + + -- READ base - 512-bit number from the file + + while not (endfile(BaseFile)) loop + readline(BaseFile, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(BaseFile, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Command mn_read_modulus 00000 001 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + + -- READ modulus - 512-bit number from the file + + while not (endfile(ModulusFile)) loop + readline(ModulusFile, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ModulusFile, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Command mn_read_exponent 00000 010 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + + -- READ exponent - 512-bit number from the file + + while not (endfile(ExponentFile)) loop + readline(ExponentFile, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ExponentFile, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Command mn_read_residuum 00000 011 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + + -- READ residuum - 512-bit number from the file + + while not (endfile(ResiduumFile)) loop + readline(ResiduumFile, line_in); -- info line + read(line_in, line_content); + report line_content; + + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; + wait for 8.75 us; + + readline(ResiduumFile, line_in); + read(line_in, data); + DATA_RXD <= data; -- parity bit + wait for 8.75 us; + + report "End of byte"; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + end loop; + + -- Command mn_count_power -- 00000 100 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 64 ms; + + -- Wait for exponentiation process + + -- Command mn_show_result -- 00000 101 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '1'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 15 ms; + + -- Command mn_prepare_for_data -- 00000 111 + DATA_RXD <= '0'; -- start bit + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '1'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; + wait for 8.75 us; + DATA_RXD <= '0'; -- parity bit + wait for 8.75 us; + DATA_RXD <= '1'; -- stop bit + wait for 100 us; + + assert false severity failure; + + end process; + +END; Index: trunk/bench/vhdl/communication =================================================================== --- trunk/bench/vhdl/communication (nonexistent) +++ trunk/bench/vhdl/communication (revision 6)
trunk/bench/vhdl/communication Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/commons/AsyncMux.vhd =================================================================== --- trunk/rtl/vhdl/commons/AsyncMux.vhd (nonexistent) +++ trunk/rtl/vhdl/commons/AsyncMux.vhd (revision 6) @@ -0,0 +1,75 @@ +----------------------------------------------------------------------- +---- ---- +---- Montgomery modular multiplier and exponentiator ---- +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator project ---- +---- http://opencores.org/project,mod_mult_exp ---- +---- ---- +---- Description: ---- +---- Asynchronous multiplexer - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.properties.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AsyncMux is + generic ( + word_size : integer := WORD_LENGTH + ); + port ( + input0 : in STD_LOGIC_VECTOR(word_size downto 0); + input1 : in STD_LOGIC_VECTOR(word_size downto 0); + ctrl : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(word_size downto 0) + ); +end AsyncMux; + +architecture Behavioral of AsyncMux is + +begin + output <= input0 when (ctrl = '0') else + input1; + +end Behavioral; + Index: trunk/rtl/vhdl/commons/RS232RefComp.vhd =================================================================== --- trunk/rtl/vhdl/commons/RS232RefComp.vhd (nonexistent) +++ trunk/rtl/vhdl/commons/RS232RefComp.vhd (revision 6) @@ -0,0 +1,406 @@ +------------------------------------------------------------------------ +-- RS232RefCom.vhd +------------------------------------------------------------------------ +-- Author: Dan Pederson +-- Copyright 2004 Digilent, Inc. +------------------------------------------------------------------------ +-- Description: This file defines a UART which tranfers data from +-- serial form to parallel form and vice versa. +------------------------------------------------------------------------ +-- Revision History: +-- 07/15/04 (Created) DanP +-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant +-- in the Clock Dividing Processes +------------------------------------------------------------------------ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Rs232RefComp is + Port ( + TXD : out std_logic := '1'; + RXD : in std_logic; + CLK : in std_logic; --Master Clock + DBIN : in std_logic_vector (7 downto 0); --Data Bus in + DBOUT : out std_logic_vector (7 downto 0); --Data Bus out + RDA : inout std_logic; --Read Data Available + TBE : inout std_logic := '1'; --Transfer Bus Empty + RD : in std_logic; --Read Strobe + WR : in std_logic; --Write Strobe + PE : out std_logic; --Parity Error Flag + FE : out std_logic; --Frame Error Flag + OE : out std_logic; --Overwrite Error Flag + RST : in std_logic := '0'); --Master Reset +end Rs232RefComp; + +architecture Behavioral of Rs232RefComp is +------------------------------------------------------------------------ +-- Component Declarations +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- Local Type Declarations +------------------------------------------------------------------------ + --Receive state machine + type rstate is ( + strIdle, --Idle state + strEightDelay, --Delays for 8 clock cycles + strGetData, --Shifts in the 8 data bits, and checks parity + strCheckStop --Sets framing error flag if Stop bit is wrong + ); + + type tstate is ( + sttIdle, --Idle state + sttTransfer, --Move data into shift register + sttShift --Shift out data + ); + + type TBEstate is ( + stbeIdle, + stbeSetTBE, + stbeWaitLoad, + stbeWaitWrite + ); + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ + constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600. + --Found by dividing 50MHz by 9600 and 16. + signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register + signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register + signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register + signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register + signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk + signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk + signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times + signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer + signal rClk : std_logic := '0'; --Receiving Clock + signal tClk : std_logic; --Transfering Clock + signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits + signal parError: std_logic; --Parity error bit + signal frameError: std_logic; --Frame error bit + signal CE : std_logic; --Clock enable for the latch + signal ctRst : std_logic := '0'; + signal load : std_logic := '0'; + signal shift : std_logic := '0'; + signal par : std_logic; + signal tClkRST : std_logic := '0'; + signal rShift : std_logic := '0'; + signal dataRST : std_logic := '0'; + signal dataIncr: std_logic := '0'; + + signal strCur : rstate := strIdle; --Current state in the Receive state machine + signal strNext : rstate; --Next state in the Receive state machine + signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine + signal sttNext : tstate; --Next state in the Transfer staet machine + signal stbeCur : TBEstate := stbeIdle; + signal stbeNext: TBEstate; + +------------------------------------------------------------------------ +-- Module Implementation +------------------------------------------------------------------------ + +begin + frameError <= not rdSReg(9); + parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); + DBOUT <= rdReg; + tfReg <= DBIN; + par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); + +--Clock Dividing Functions-- + + process (CLK, clkDiv) --set up clock divide for rClk + begin + if (Clk = '1' and Clk'event) then + if (clkDiv = baudDivide) then + clkDiv <= "000000000"; + else + clkDiv <= clkDiv +1; + end if; + end if; + end process; + + process (clkDiv, rClk, CLK) --Define rClk + begin + if CLK = '1' and CLK'Event then + if clkDiv = baudDivide then + rClk <= not rClk; + else + rClk <= rClk; + end if; + end if; + end process; + + process (rClk) --set up clock divide for tClk + begin + if (rClk = '1' and rClk'event) then + rClkDiv <= rClkDiv +1; + end if; + end process; + + tClk <= rClkDiv(3); --define tClk + + process (rClk, ctRst) --set up a counter based on rClk + begin + if rClk = '1' and rClk'Event then + if ctRst = '1' then + ctr <= "0000"; + else + ctr <= ctr +1; + end if; + end if; + end process; + + process (tClk, tClkRST) --set up a counter based on tClk + begin + if (tClk = '1' and tClk'event) then + if tClkRST = '1' then + tfCtr <= "0000"; + else + tfCtr <= tfCtr +1; + end if; + end if; + end process; + + --This process controls the error flags-- + process (rClk, RST, RD, CE) + begin + if RD = '1' or RST = '1' then + FE <= '0'; + OE <= '0'; + RDA <= '0'; + PE <= '0'; + elsif rClk = '1' and rClk'event then + if CE = '1' then + FE <= frameError; + OE <= RDA; + RDA <= '1'; + PE <= parError; + rdReg(7 downto 0) <= rdSReg (7 downto 0); + end if; + end if; + end process; + + --This process controls the receiving shift register-- + process (rClk, rShift) + begin + if rClk = '1' and rClk'Event then + if rShift = '1' then + rdSReg <= (RXD & rdSReg(9 downto 1)); + end if; + end if; + end process; + + --This process controls the dataCtr to keep track of shifted values-- + process (rClk, dataRST) + begin + if (rClk = '1' and rClk'event) then + if dataRST = '1' then + dataCtr <= "0000"; + elsif dataIncr = '1' then + dataCtr <= dataCtr +1; + end if; + end if; + end process; + + --Receiving State Machine-- + process (rClk, RST) + begin + if rClk = '1' and rClk'Event then + if RST = '1' then + strCur <= strIdle; + else + strCur <= strNext; + end if; + end if; + end process; + + --This process generates the sequence of steps needed receive the data + + process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) + begin + case strCur is + + when strIdle => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + + CE <= '0'; + if RXD = '0' then + ctRst <= '1'; + strNext <= strEightDelay; + else + ctRst <= '0'; + strNext <= strIdle; + end if; + + when strEightDelay => + dataIncr <= '0'; + rShift <= '0'; + CE <= '0'; + + if ctr(2 downto 0) = "111" then + ctRst <= '1'; + dataRST <= '1'; + strNext <= strGetData; + else + ctRst <= '0'; + dataRST <= '0'; + strNext <= strEightDelay; + end if; + + when strGetData => + CE <= '0'; + dataRst <= '0'; + if ctr(3 downto 0) = "1111" then + ctRst <= '1'; + dataIncr <= '1'; + rShift <= '1'; + else + ctRst <= '0'; + dataIncr <= '0'; + rShift <= '0'; + end if; + + if dataCtr = "1010" then + strNext <= strCheckStop; + else + strNext <= strGetData; + end if; + + when strCheckStop => + dataIncr <= '0'; + rShift <= '0'; + dataRst <= '0'; + ctRst <= '0'; + + CE <= '1'; + strNext <= strIdle; + + end case; + + end process; + + --TBE State Machine-- + process (CLK, RST) + begin + if CLK = '1' and CLK'Event then + if RST = '1' then + stbeCur <= stbeIdle; + else + stbeCur <= stbeNext; + end if; + end if; + end process; + + --This process gererates the sequence of events needed to control the TBE flag-- + process (stbeCur, CLK, WR, DBIN, load) + begin + + case stbeCur is + + when stbeIdle => + TBE <= '1'; + if WR = '1' then + stbeNext <= stbeSetTBE; + else + stbeNext <= stbeIdle; + end if; + + when stbeSetTBE => + TBE <= '0'; + if load = '1' then + stbeNext <= stbeWaitLoad; + else + stbeNext <= stbeSetTBE; + end if; + + when stbeWaitLoad => + if load = '0' then + stbeNext <= stbeWaitWrite; + else + stbeNext <= stbeWaitLoad; + end if; + + when stbeWaitWrite => + if WR = '0' then + stbeNext <= stbeIdle; + else + stbeNext <= stbeWaitWrite; + end if; + end case; + end process; + + --This process loads and shifts out the transfer shift register-- + process (load, shift, tClk, tfSReg) + begin + TXD <= tfsReg(0); + if tClk = '1' and tClk'Event then + if load = '1' then + tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); + end if; + if shift = '1' then + + tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); + end if; + end if; + end process; + + -- Transfer State Machine-- + process (tClk, RST) + begin + if (tClk = '1' and tClk'Event) then + if RST = '1' then + sttCur <= sttIdle; + else + sttCur <= sttNext; + end if; + end if; + end process; + + -- This process generates the sequence of steps needed transfer the data-- + process (sttCur, tfCtr, tfReg, TBE, tclk) + begin + + case sttCur is + + when sttIdle => + tClkRST <= '0'; + shift <= '0'; + load <= '0'; + if TBE = '1' then + sttNext <= sttIdle; + else + sttNext <= sttTransfer; + end if; + + when sttTransfer => + shift <= '0'; + load <= '1'; + tClkRST <= '1'; + sttNext <= sttShift; + + + when sttShift => + shift <= '1'; + load <= '0'; + tClkRST <= '0'; + if tfCtr = "1100" then + sttNext <= sttIdle; + else + sttNext <= sttShift; + end if; + end case; + end process; + +end Behavioral; \ No newline at end of file Index: trunk/rtl/vhdl/commons/ShiftReg.vhd =================================================================== --- trunk/rtl/vhdl/commons/ShiftReg.vhd (nonexistent) +++ trunk/rtl/vhdl/commons/ShiftReg.vhd (revision 6) @@ -0,0 +1,94 @@ +----------------------------------------------------------------------- +---- ---- +---- Montgomery modular multiplier and exponentiator ---- +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator project ---- +---- http://opencores.org/project,mod_mult_exp ---- +---- ---- +---- Description: ---- +---- Shift register - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.properties.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftReg is + generic ( + length_1 : integer := BYTE; + length_2 : integer := WORD_LENGTH; + internal_data : integer := WORD_LENGTH + ); + port ( + input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0); + output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0); + en : in STD_LOGIC; + shift : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end ShiftReg; + +architecture Behavioral of ShiftReg is + +signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0); + +begin + reg : process (clk, reset, data) + begin + if (reset = '1') then + data <= (others => '0'); + elsif (clk'event and clk = '1') then + if (en = '1') then + data(internal_data - 1 downto internal_data - length_1) <= input; + else + if (shift = '1') then + data <= '0' & data(internal_data - 1 downto 1); + end if; + end if; + end if; + output <= data(length_2 - 1 downto 0); + end process reg; + +end Behavioral; + Index: trunk/rtl/vhdl/commons/counter.vhd =================================================================== --- trunk/rtl/vhdl/commons/counter.vhd (nonexistent) +++ trunk/rtl/vhdl/commons/counter.vhd (revision 6) @@ -0,0 +1,89 @@ +----------------------------------------------------------------------- +---- ---- +---- Montgomery modular multiplier and exponentiator ---- +---- ---- +---- This file is part of the Montgomery modular multiplier ---- +---- and exponentiator project ---- +---- http://opencores.org/project,mod_mult_exp ---- +---- ---- +---- Description: ---- +---- Counter - nothing special. ---- +---- To Do: ---- +---- ---- +---- Author(s): ---- +---- - Krzysztof Gajewski, gajos@opencores.org ---- +---- k.gajewski@gmail.com ---- +---- ---- +----------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and-or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +----------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use work.properties.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter is + generic( + size : integer := 4 + ); + port ( + count : in STD_LOGIC; + zero : in STD_LOGIC; + output : out STD_LOGIC_VECTOR(size - 1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC + ); +end counter; + +architecture Behavioral of Counter is + signal c : STD_LOGIC_VECTOR(size - 1 downto 0); + begin + licznik: process (reset,clk) + begin + if (clk = '1' and clk'Event) then + if (reset = '1') then + c <= (others => '0'); + elsif count = '1' then + c <= c + 1; + elsif zero = '1' then + c <= (others => '0'); + else + c <= c; + end if; + end if; + end process licznik; + OUTPUT <= c; +end Behavioral; \ No newline at end of file Index: trunk/rtl/vhdl/commons/dcms/dcms.v =================================================================== --- trunk/rtl/vhdl/commons/dcms/dcms.v (nonexistent) +++ trunk/rtl/vhdl/commons/dcms/dcms.v (revision 6) @@ -0,0 +1,67 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : dcms.v +// /___/ /\ Timestamp : 03/24/2013 14:44:49 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle E:/spent i praca/OpenCores/fin_134above/dcms.xaw -st dcms.v +//Design Name: dcms +//Device: xc3s500e-5fg320 +// +// Module dcms +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +`timescale 1ns / 1ps + +module dcms(CLKIN_IN, + CLKDV_OUT, + CLK0_OUT); + + input CLKIN_IN; + output CLKDV_OUT; + output CLK0_OUT; + + wire CLKDV_BUF; + wire CLKFB_IN; + wire CLK0_BUF; + wire GND_BIT; + + assign GND_BIT = 0; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), + .O(CLKDV_OUT)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1), + .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), + .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), + .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) + DCM_SP_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IN), + .DSSEN(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKDV(CLKDV_BUF), + .CLKFX(), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(), + .PSDONE(), + .STATUS()); +endmodule Index: trunk/rtl/vhdl/commons/dcms/dcms.xaw =================================================================== --- trunk/rtl/vhdl/commons/dcms/dcms.xaw (nonexistent) +++ trunk/rtl/vhdl/commons/dcms/dcms.xaw (revision 6) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$83x4>7<881:86?;.3:853!oK92;>6?W6:03*56792>:78<45158EWEO_@P:;6O]W[]LJI_XKHYHMIGAG^AOO4>GPRVIGGO[I2^K\WLAIIDO:96OXZ^AOOGSA:VET_DIAALG27>GPRVIGGO[I3^@OOKGJM8?0MZTPCMIAQC5XAVYBKCOBE078ER\XKEAIYK=PO^QJCKGJM890MZTPCMIAQC2XJEAEM@K>5:CT^ZEKCK_M8RGPSHEMEHC6=2K\VRMCKCWE0ZIX[@MEM@Ki;@UY[FJLJ\L_U]K>f:CT^ZEKCK_MXT^J2048ER\XKEAIYKZVPD0\JJCCA]l0MZTPCMIAQCR^XL9m7LYU_BNHFP@SQYO?=>5NW[]@HNYH]]Z^XRZVPDa8ER\XNEE\XT^J8:CT^ZVFZ]n0MZTPSXLWLQIHD=1ICYF;;CWEC1=DDB:37NBD0^@VB`=DDB:TNXHH_HLPP==DDB:TCXZ9;BNH5=613JF@>:>:;BNH6]>4CMIGRZDRNNUBB^Z=119@HNBQWK_MKRGASU1`?FJLL_UOE[GKE89@HNBQWF__m6MCKET\KPR6i2IGGIXPOTV1e>EKCM\TCXZ<5:AOOCD?3JF@JOQFN49@HN@_02IGGKV>81a8GIMAPVNBZDJJe:AOOC^XE\F_E]BV5:AOOLH692IGGD@PDHTJ@@YEQV837NBDIO]JJf=DDBCES]K]INFf?FJLAGUX^NQ[YQG26>EKCF__S]FNSD]PLL@Sk2IGGRHJEE@BGN?1EIYY@RJ68JJHB92E37BHKDSASAg=W@HYNS^FFFU;8TLHOIZH^_l5_IOKPCKBBL11[ECYFDUJ;?UTNE]S[I<>4PSMS[UOIAZKHXDXJ5:RPGIM13YYOCCK;;QQFJ==W[@DHHHM<;SQWf>UNOLR_I_@NL79PMKAKMj1XXL\[UQ]TELR13Z^JXX]>2:QZWQCJWZSEOE\@NNWP7>RHX=1_^XK7;TQF[GSAO01^_HQMUGEP1>PNM^;i7UOX_WGQWLII9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON;2RXX;5Wdc]J`467V>50\78_5<0U=1j~zt<;eanf>pbzzcdb-?!059ulaja3qi88>?e,7ec647uIJ{9i5O@y7b>C<5:3;p_8>58b8;a?74;;3mj7=9434xj=>=92d35784$959<0=z[=l14n47e;3077?an39=8n<4S749h4S7494S749<[=l14n47e;300402l39:=k=4d9a94?7=9rY><76l:9g956551ol1?;:=6:tW<6<7280:64u\518;g?>b2898>4hi:24763=e?o0;6=49:8y'e?>c3-8265h4$3c9=5=#:k03:6*74;18f04=83;86=4?{%50>07<,k08;6*l:6`8 `<5m2.m6?k4$02977=#9809i6*>2;4f?!742>h0(<:52:&21?0d3-;=68m4$0596f=#7)=k:99'03<53-><6:5+4886g>"3j3<0(9m5659'0a<1k2.>?79j;%7:>7=#==0=46*:6;4;?!3?21:0(8l54:&6`?033-?m6;74$7392<=#>;0;7)8::728 3g=?2.=j7?4$6a91f=#0803>6*k:89'6=<2=2c?47>5$609!1521k0(::58198m2?=83.<>76n;%52>=6<3`=<6=4+738;e>"0932;76g88;29 24=0h1/;<470:9j30<72-=965o4$639<5=7b<,;?19h54o2494?"0:32j76a<2;29 24=0h1/>>4=d:9l76<72-=965o4;n14>5<#?;03m6*84;:3?!442;n0(<753d9'5f<4m2.9876?<,8h1?55+1g80a>"5>38o7)?k:2;8 4c=;11/>?474$3397==1<7*82;:b?>i4=3:1(:<58`98k12=83.<>76n;:m71?6=,>814l54o6f94?"0:32i7)9?:928?j00290/;?47a:9l33<72-=965o4;|`04?6=:3:1732e=h7>5$6095<#?;03m6*84;:3?>i1l3:1(:<58`9'31l50;094?6|,>91>i5f6283>!1521k0(::58198k3b=83.<>76n;%57>=6<3th8o7>52;294~"0;38o7d8<:18'37814l5+758;4>=z{=k1<7?t=4090==#?h0=?6s|4283>7}:=;0?>63<0;4g?!7?2:;0q~>5629~w6>=83?p18<5369>7<<1;278m78<;<1a>35<5:i1:>5rs2g94?7|5:31:i5+7`85`>{t;o0;6"0i3m1v>?50;2x 2g=>m1vqc:m:182xh3k3:1=vsa4e83>4}zf=o1<7?t}o6e>5<6std><7>51zm14<728qvb8<50;3xyk34290:wpsr}AB@0b=;=?=<:
trunk/rtl/vhdl/commons/dcms Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/commons/dcms.vhd =================================================================== --- trunk/rtl/vhdl/commons/dcms.vhd (nonexistent) +++ trunk/rtl/vhdl/commons/dcms.vhd (revision 6) @@ -0,0 +1,102 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 14.2 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcms.vhd +-- /___/ /\ Timestamp : 08/13/2019 22:16:29 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-intstyle E:/spent i praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/commons/dcms/dcms.xaw -st dcms.vhd +--Design Name: dcms +--Device: xc3s500e-5fg320 +-- +-- Module dcms +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcms is + port ( CLKIN_IN : in std_logic; + CLKDV_OUT : out std_logic; + CLKDV_OUT1 : out std_logic; + CLKDV_OUT2 : out std_logic; + CLKDV_OUT3 : out std_logic; + CLK0_OUT : out std_logic); +end dcms; + +architecture BEHAVIORAL of dcms is + signal CLKDV_BUF : std_logic; + signal CLKFB_IN : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKDV_BUFG_INST : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT); + + CLKDV_BUFG_INST1 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT1); + + CLKDV_BUFG_INST2 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT2); + + CLKDV_BUFG_INST3 : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT3); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 5.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>CLKDV_BUF, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: trunk/rtl/vhdl/commons/properties.vhd =================================================================== --- trunk/rtl/vhdl/commons/properties.vhd (revision 5) +++ trunk/rtl/vhdl/commons/properties.vhd (revision 6) @@ -17,7 +17,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- @@ -66,9 +66,9 @@ COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT, INFO_RESULT, SHOW_RESULT); -type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE, - DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE, - TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA); +type comm_ctrl_states is (NOP, DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_MOD_EXP, + OUTPUT_DATA, INFO_STATE, TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, + MOVE_DATA, MOVE_OUTPUT_DATA); ---- mnemonics for exponentiator constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000"; @@ -77,7 +77,6 @@ constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011"; constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100"; constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101"; -constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110"; constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111"; ---- addresses for memory data
/trunk/rtl/vhdl/communication/ModExpComm.vhd
0,0 → 1,351
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This module is example implementation of the Montgomery ----
---- modular exponentiator combined with the RS-232 communication----
---- with PC. All related to the communication logic was ----
---- inclueded here. Input data are retrieved by serial input ----
---- and converted into parallel data by the shift registers ----
---- After exponentiation in similar way parallel data are ----
---- converted into serial data. For the communication, the ----
---- RS232RefComp module made by Digilent was used and slightly ----
---- modified (increased data transfer speed to 115 200 bps). ----
---- ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
-- Definition of the component
entity ModExpComm is
generic (word_size : integer := WORD_LENGTH);
port (
DATA_RXD : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DATA_TXD : out STD_LOGIC
);
end ModExpComm;
 
architecture Behavioral of ModExpComm is
 
-- This is DCM component generated by the ISE. It was used due
-- to maximum clock speed available in the S3EBOARD served by
-- the Digilent (50 MHz) it is used in order to decrease speed
-- of exponentiator core. RS232 is working with 50 MHz and the
-- rest part of the core is working with 10 MHz. This is due
-- to timing estimation of ISE.
component dcms is
port (
CLKIN_IN : in STD_LOGIC;
CLKDV_OUT : out STD_LOGIC;
CLK0_OUT : out STD_LOGIC
);
end component dcms;
 
-- Montgomery modular exponentiator
component ModExp is
generic (
word_size : integer := WORD_LENGTH;
word_binary : integer := WORD_INTEGER
);
Port (
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
ctrl : in STD_LOGIC_VECTOR(2 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in_ready : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0)
);
end component ModExp;
 
-- RS232 component made by the Digilent
-- all checking was ignored but for communication
-- odd parity is used
component Rs232RefComp is
port (
TXD : out STD_LOGIC := '1';
RXD : in STD_LOGIC;
CLK : in STD_LOGIC; --Master Clock
DBIN : in STD_LOGIC_VECTOR(7 downto 0); --Data Bus in
DBOUT : out STD_LOGIC_VECTOR(7 downto 0); --Data Bus out
RDA : inout STD_LOGIC; --Read Data Available
TBE : inout STD_LOGIC := '1'; --Transfer Bus Empty
RD : in STD_LOGIC; --Read Strobe
WR : in STD_LOGIC; --Write Strobe
PE : out STD_LOGIC; --Parity Error Flag
FE : out STD_LOGIC; --Frame Error Flag
OE : out STD_LOGIC; --Overwrite Error Flag
RST : in STD_LOGIC := '0' --Master Reset
);
end component Rs232RefComp;
 
-- Register for storing control word for ModExpComm component
component Reg is
generic(word_size : integer := 8);
port(
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component Reg;
 
---- Shift registers for input and output data for the modular exponentiator
component ShiftReg is
generic (
length_1 : integer := BYTE;
length_2 : integer := WORD_LENGTH;
internal_data : integer := WORD_LENGTH
);
port (
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
en : in STD_LOGIC;
shift : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component ShiftReg;
 
---- some 'help' mux at the output of the component
component AsyncMux is
generic(
word_size : integer := WORD_LENGTH
);
port(
input0 : in STD_LOGIC_VECTOR(word_size downto 0);
input1 : in STD_LOGIC_VECTOR(word_size downto 0);
ctrl : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(word_size downto 0)
);
end component AsyncMux;
 
---- State machine
component ModExpDataCtrlSM is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
data_in_ready : out STD_LOGIC;
readySig : in STD_LOGIC;
modExpCtrlRegEn : out STD_LOGIC;
dataToModExpEn : out STD_LOGIC;
dataToModExpShift : out STD_LOGIC;
dataFromModExpEn : out STD_LOGIC;
dataFromModExpShift : out STD_LOGIC;
muxCtrl : out STD_LOGIC;
opcodes : in STD_LOGIC_VECTOR(2 downto 0);
controlStateOut : out STD_LOGIC_VECTOR(2 downto 0)
);
end component ModExpDataCtrlSM;
 
-- All signals needed in the implementation
signal clk_div : STD_LOGIC;
signal clk_0 : STD_LOGIC;
 
signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);
signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);
signal RDAsig : STD_LOGIC;
signal TBEsig : STD_LOGIC;
signal RDsig : STD_LOGIC;
signal WRsig : STD_LOGIC;
signal PEsig : STD_LOGIC;
signal FEsig : STD_LOGIC;
signal OEsig : STD_LOGIC;
 
signal modExpInput : STD_LOGIC_VECTOR(word_size - 1 downto 0);
signal modExpCtrl : STD_LOGIC_VECTOR(2 downto 0);
signal modExpCtrlRegEn : STD_LOGIC;
signal data_in_ready : STD_LOGIC;
signal readySig : STD_LOGIC;
signal modExpOutput : STD_LOGIC_VECTOR(word_size - 1 downto 0);
 
signal dataToModExpEn : STD_LOGIC;
signal dataToModExpShift : STD_LOGIC;
 
signal dataFromModExpEn : STD_LOGIC;
signal dataFromModExpShift : STD_LOGIC;
 
signal inputToMux : STD_LOGIC_VECTOR(BYTE - 1 downto 0);
signal controlStateOut : STD_LOGIC_VECTOR(2 downto 0);
signal muxCtrl : STD_LOGIC;
 
signal ctrl_zero : STD_LOGIC_VECTOR(4 downto 0) := "00000";
signal control_state_to_out : STD_LOGIC_VECTOR(7 downto 0);
begin
-- Architecture definition
ctrl_zero <= (others => '0');
control_state_to_out <= controlStateOut & ctrl_zero;
-- DCM
dcm_module : dcms
port map(
CLKIN_IN => CLK,
CLKDV_OUT => clk_div, --clk_null,
CLK0_OUT => clk_0
);
-- RS232 component
serialPort : Rs232RefComp
port map (
TXD => DATA_TXD,
RXD => DATA_RXD,
CLK => clk_0,
DBIN => dataTXD,
DBOUT => dataRXD,
RDA => RDAsig, --Read Data Available
TBE => TBEsig, --Transfer Bus Empty
RD => RDsig, --Read Strobe
WR => WRsig, --Write Strobe
PE => PEsig, --Parity Error Flag
FE => FEsig, --Frame Error Flag
OE => OEsig, --Overwrite Error Flag
RST => RESET --Master Reset
);
-- Shift register at input of the modular exponentiator
-- (convert data from 8 bit to 32 bit, 64 bit, 512 bit, etc.)
modExpCompIn : ShiftReg
generic map(
length_1 => BYTE,
length_2 => WORD_LENGTH,
internal_data => WORD_LENGTH
)
port map (
input => dataRXD,
output => modExpInput,
en => dataToModExpEn,
shift => dataToModExpShift,
clk => CLK_div,
reset => RESET
);
-- Control register
modCtrl : Reg
generic map(
word_size => 3
)
port map (
input => dataRXD(2 downto 0),
output => modExpCtrl,
enable => modExpCtrlRegEn,
clk => CLK_div,
reset => RESET
);
 
-- Modular exponentiator component
ModExpComp : ModExp
port map (
input => modExpInput,
ctrl => modExpCtrl,
clk => CLK_div,
reset => RESET,
data_in_ready => data_in_ready,
ready => readySig,
output => modExpOutput
);
-- Shift register at output of the modular exponentiator
-- (convert data from 32 bit, 64 bit, 512 bit, etc. to 8 bit)
dataFromModExpComponent : ShiftReg
generic map(
length_1 => WORD_LENGTH,
length_2 => BYTE,
internal_data => WORD_LENGTH
)
port map (
input => modExpOutput,
output => inputToMux,
en => dataFromModExpEn,
shift => dataFromModExpShift,
clk => CLK_div,
reset => RESET
);
-- Multiplexer at the output of the component
outMux : AsyncMux
generic map(
word_size => BYTE - 1
)
port map(
input0 => inputToMux,
input1 => control_state_to_out,
ctrl => muxCtrl,
output => dataTXD
);
 
-- State machine
stateMachine : ModExpDataCtrlSM
port map(
clk => CLK_div,
reset => RESET,
RDAsig => RDAsig,
TBEsig => TBEsig,
RDsig => RDsig,
WRsig => WRsig,
data_in_ready => data_in_ready,
readySig => readySig,
modExpCtrlRegEn => modExpCtrlRegEn,
dataToModExpEn => dataToModExpEn,
dataToModExpShift => dataToModExpShift,
dataFromModExpEn => dataFromModExpEn,
dataFromModExpShift => dataFromModExpShift,
muxCtrl => muxCtrl,
opcodes => dataRXD(2 downto 0),
controlStateOut => controlStateOut
);
 
end Behavioral;
/trunk/rtl/vhdl/communication/ModExpDataCtrlSM.vhd
0,0 → 1,563
-----------------------------------------------------------------------
---- ----
---- Montgomery modular multiplier and exponentiator ----
---- ----
---- This file is part of the Montgomery modular multiplier ----
---- and exponentiator project ----
---- http://opencores.org/project,mod_mult_exp ----
---- ----
---- Description: ----
---- This module is state machine for the example implementation ----
---- of the Montgomery modular exponentiatorcombined with the ----
---- RS-232 communication with PC. ----
---- ----
---- To Do: ----
---- ----
---- Author(s): ----
---- - Krzysztof Gajewski, gajos@opencores.org ----
---- k.gajewski@gmail.com ----
---- ----
-----------------------------------------------------------------------
---- ----
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and-or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.properties.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ModExpDataCtrlSM is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
RDAsig : in STD_LOGIC;
TBEsig : in STD_LOGIC;
RDsig : out STD_LOGIC;
WRsig : out STD_LOGIC;
data_in_ready : out STD_LOGIC;
readySig : in STD_LOGIC;
modExpCtrlRegEn : out STD_LOGIC;
dataToModExpEn : out STD_LOGIC;
dataToModExpShift : out STD_LOGIC;
dataFromModExpEn : out STD_LOGIC;
dataFromModExpShift : out STD_LOGIC;
muxCtrl : out STD_LOGIC;
opcodes : in STD_LOGIC_VECTOR(2 downto 0);
controlStateOut : out STD_LOGIC_VECTOR(2 downto 0)
);
end ModExpDataCtrlSM;
 
architecture Behavioral of ModExpDataCtrlSM is
 
-- Counters are used for both bit counting in byte
-- and composing full length word in exponentiator
component counter is
generic(
size : integer := 4
);
port (
count : in STD_LOGIC;
zero : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (size - 1 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component counter;
 
-- some constants for temp_state signal which is used in TEMPORARY_STATE.
-- This state is used as something like "wait" command due to data
-- propagation in the core
constant rd_data : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant mk_fin : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant dat_out_prop : STD_LOGIC_VECTOR(2 downto 0) := "010";
constant info_st : STD_LOGIC_VECTOR(2 downto 0) := "011";
constant mv_dat : STD_LOGIC_VECTOR(2 downto 0) := "100";
constant nothing : STD_LOGIC_VECTOR(2 downto 0) := "101";
 
signal state : comm_ctrl_states := NOP;
signal next_state : comm_ctrl_states := NOP;
 
signal temp_state : STD_LOGIC_VECTOR (2 downto 0) := nothing;
 
-- This signals are used for control the counters for data shifting
-- in shift registers (by bytes). This length have to be modified
-- with changing the used word size.
-- Modify for variable key size
-- In fact it is modified from the properties file
signal serialDataCtrCt : STD_LOGIC;
signal serialDataCtrZero : STD_LOGIC;
signal serialDataCtrOut : STD_LOGIC_VECTOR(WORD_INT_LOG downto 0);
 
-- This signals are used for control the counters for data shifting - bits in
-- bytes.
-- DO NOT MODIFY!!!
signal shiftDataCtrCt : STD_LOGIC;
signal shiftDataCtrZero : STD_LOGIC;
signal shiftDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
 
begin
-- State machine process
SM : process(state, RDAsig, TBEsig, shiftDataCtrOut,
serialDataCtrOut, opcodes, readySig)
begin
case state is
-- This state prepares whoole core before calculations
-- 'No operation' state
when NOP =>
WRsig <= '0';
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '1';
serialDataCtrCt <= '0';
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
RDsig <= '0';
-- This is something like 'info' word
if (readySig = '1') then
controlStateOut <= "100";
else
controlStateOut <= "000";
end if;
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- RDAsig = '1' means that some data
-- appeard in the RS-232 input
if (RDAsig = '1') then
next_state <= DECODE_IN;
else
next_state <= NOP;
end if;
when DECODE_IN =>
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '1';
serialDataCtrCt <= '0';
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
RDsig <= '1';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
modExpCtrlRegEn <= '1';
 
-- firstly from the RS-232 input comes OPCODE informing the core
-- what to do. Data can appeard in any order. This opcode are saved
-- in the suitable register at the input of the modular exponentiator
if (opcodes = mn_read_base) or (opcodes = mn_read_modulus) or
(opcodes = mn_read_exponent) or (opcodes = mn_read_residuum) then
next_state <= TEMPORARY_STATE;
temp_state <= rd_data;
elsif (opcodes = mn_count_power) then
next_state <= TEMPORARY_STATE;
temp_state <= mk_fin;
elsif (opcodes = mn_show_result) then
if (readySig = '1') then
next_state <= TEMPORARY_STATE;
temp_state <= dat_out_prop;
else
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
end if;
elsif (opcodes = mn_prepare_for_data) then
next_state <= TEMPORARY_STATE;
temp_state <= nothing;
else
next_state <= NOP;
temp_state <= nothing; -- not important
end if;
when READ_DATA =>
-- For now need to 'restart' all the flow of reading data
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpEn <= '1';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
if (RDAsig = '0') then
next_state <= READ_DATA;
else
next_state <= DECODE_READ;
end if;
-- This state is for the control of number of the 8-bit 'packets'
-- of the input data for the modular exponentiator
when DECODE_READ =>
modExpCtrlRegEn <= '0';
WRsig <= '0';
serialDataCtrCt <= '1';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
RDsig <= '1';
dataToModExpEn <= '1';
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
-- Data reading X times 8 bit -> modify for variable key length
-- In fact it is modified from the properties file
if (serialDataCtrOut(WORD_INT_LOG - 1 downto 0) = WORD_INT_LOG_STR) then
next_state <= DECODE_READ_PROP;
temp_state <= nothing; -- not important
else
next_state <= TEMPORARY_STATE;
temp_state <= mv_dat;
end if;
-- Some info state for the modular exponentiator core,
-- that some data are at the input - after the end of the
-- reading data
when DECODE_READ_PROP =>
modExpCtrlRegEn <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
RDsig <= '0';
dataToModExpEn <= '0';
serialDataCtrCt <= '0';
muxCtrl <= '1';
data_in_ready <= '1';
temp_state <= nothing; -- not important
controlStateOut <= "000";
next_state <= INFO_STATE;
-- This state is for moving bits in data word for the
-- modular exponentiator counter counts to 8 while data
-- are shifted
when MOVE_DATA =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '1';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '0';
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '1';
data_in_ready <= '0';
--- shifting data in register -> DO NOT MODIFY!!!
if (shiftDataCtrOut(2 downto 0) = "111") then
shiftDataCtrZero <= '1';
shiftDataCtrCt <= '0';
next_state <= READ_DATA;
else
shiftDataCtrZero <= '0';
shiftDataCtrCt <= '1';
next_state <= MOVE_DATA;
end if;
-- If all the needed data appeared at the input
-- and 'mn_count_power' command appeared modular exponentiation
-- is performed. This state is present until modular exponentiation
-- is calculated
when MAKE_MOD_EXP =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
muxCtrl <= '1';
data_in_ready <= '1';
-- Here
if (readySig = '1') then
controlStateOut <= "100";
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
else
controlStateOut <= "001";
next_state <= MAKE_MOD_EXP;
temp_state <= nothing;
end if;
-- When 'mn_show_result' command appears in the core input,
-- the result from the modular exponentiation feeds the output
-- Here and below state are also for 'data propagation'
when DATA_TO_OUT_PROPAGATE =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
dataFromModExpEn <= '1';
dataFromModExpShift <= '0';
next_state <= DATA_TO_OUT_PROPAGATE2;
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
when DATA_TO_OUT_PROPAGATE2 =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '1';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
next_state <= OUTPUT_DATA;
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- Here data from parallel form are transformed to serial form.
-- This state is for the control of number of the 8-bit 'packets'
-- of the input data for the modular exponentiator
when OUTPUT_DATA =>
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
serialDataCtrZero <= '0';
RDsig <= '0';
WRsig <= '1';
serialDataCtrCt <= '1';
temp_state <= nothing;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
if (serialDataCtrOut(WORD_INT_LOG) = '1') then
next_state <= NOP;
else
next_state <= MOVE_OUTPUT_DATA;
end if;
-- This state is for moving bits in data word for the
-- modular exponentiator counter counts to 8 while data
-- are shifted
when MOVE_OUTPUT_DATA =>
if (TBEsig = '0') then
-- Here we have to wait for the sending the previous serial data
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
next_state <= MOVE_OUTPUT_DATA;
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
else
-- Here data are shifted in the output data word
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
serialDataCtrCt <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '1';
shiftDataCtrCt <= '1';
serialDataCtrZero <= '0';
controlStateOut <= "000";
muxCtrl <= '0';
data_in_ready <= '0';
temp_state <= nothing; -- not important
-- Output register shifting DO NOT MODIFY!!!
if (shiftDataCtrOut(3) = '1') then
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '1';
dataFromModExpShift <= '0';
next_state <= DATA_TO_OUT_PROPAGATE2;
else
shiftDataCtrZero <= '0';
next_state <= MOVE_OUTPUT_DATA;
end if;
end if;
-- State for informing 'the world' about the end of
-- the modular exponentiation
when INFO_STATE =>
modExpCtrlRegEn <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
if (readySig = '1') then
controlStateOut <= "100";
else
controlStateOut <= "000";
end if;
muxCtrl <= '1';
data_in_ready <= '0';
temp_state <= nothing; -- not important
RDsig <= '0';
WRsig <= '1';
next_state <= NOP;
-- This state is mostly used for 'data propagation'
-- and control of work of the modular exponentiator
-- its work/state depends on the 'temp_state' signal.
-- temp_state = nothing means that this state is not used
when TEMPORARY_STATE =>
modExpCtrlRegEn <= '0';
RDsig <= '0';
WRsig <= '0';
dataToModExpEn <= '0';
dataToModExpShift <= '0';
dataFromModExpEn <= '0';
dataFromModExpShift <= '0';
serialDataCtrCt <= '0';
serialDataCtrZero <= '0';
shiftDataCtrCt <= '0';
shiftDataCtrZero <= '0';
if (readySig = '1') then
controlStateOut <= "100";
next_state <= TEMPORARY_STATE;
temp_state <= info_st;
else
controlStateOut <= "001";
next_state <= MAKE_MOD_EXP;
temp_state <= nothing;
end if;
if (temp_state = rd_data) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= READ_DATA;
temp_state <= rd_data;
elsif (temp_state = mk_fin) then
muxCtrl <= '0';
data_in_ready <= '1';
next_state <= MAKE_MOD_EXP;
temp_state <= mk_fin;
elsif (temp_state = dat_out_prop) then
muxCtrl <= '1';
data_in_ready <= '0';
next_state <= DATA_TO_OUT_PROPAGATE;
temp_state <= dat_out_prop;
elsif (temp_state = info_st) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= INFO_STATE;
temp_state <= info_st;
elsif (temp_state = mv_dat) then
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= MOVE_DATA;
temp_state <= mv_dat;
else
muxCtrl <= '0';
data_in_ready <= '0';
next_state <= NOP;
temp_state <= nothing;
end if;
end case;
end process SM;
 
state_modifier : process (clk, reset)
begin
if (clk = '1' and clk'Event) then
if (reset = '1') then
state <= NOP;
else
state <= next_state;
end if;
end if;
end process state_modifier;
 
-- modify for changing width of the hey
-- in fact it is modified from the properties file
dataCounter : counter
generic map(
size => WORD_INT_LOG + 1
)
port map (
count => serialDataCtrCt,
zero => serialDataCtrZero,
output => serialDataCtrOut,
clk => clk,
reset => reset
);
shiftCounter : counter
generic map(
size => 4
)
port map (
count => shiftDataCtrCt,
zero => shiftDataCtrZero,
output => shiftDataCtrOut,
clk => clk,
reset => reset
);
 
end Behavioral;
/trunk/rtl/vhdl/communication/ModExpDataCtrlUCF.ucf
0,0 → 1,8
NET "DATA_RXD" LOC= "R7" | IOSTANDARD= LVTTL | SLEW= FAST ;
NET "DATA_TXD" LOC= "M14" | IOSTANDARD= LVTTL | DRIVE= 8 | SLEW= FAST ;
NET "CLK" LOC= "C9" | IOSTANDARD= LVCMOS33 | SLEW= FAST ;
NET "CLK" TNM_NET = "clk_group";
TIMESPEC "TS_CLK" = PERIOD "clk_group" 20 ns HIGH 40%;
 
NET "RESET" LOC= "K17" | IOSTANDARD= LVTTL | PULLDOWN;
SYSTEM_JITTER = 1 ns;
/trunk/rtl/vhdl/communication
trunk/rtl/vhdl/communication Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/rtl/vhdl/mod_exp/ModExp.vhd =================================================================== --- trunk/rtl/vhdl/mod_exp/ModExp.vhd (revision 5) +++ trunk/rtl/vhdl/mod_exp/ModExp.vhd (revision 6) @@ -8,7 +8,7 @@ ---- ---- ---- Description: ---- ---- Montgomery modular exponentiator main module. It combines ---- ----- all subomponents. It takes four numbers as the input: ---- +---- all subcomponents. It takes four numbers as the input: ---- ---- base, power, modulus and Montgomery residuum ---- ---- (2^(2*word_length) mod N) and results the modular ---- ---- exponentiation A^B mod M. ---- @@ -22,7 +22,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- Index: trunk/rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd =================================================================== --- trunk/rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd (revision 5) +++ trunk/rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd (revision 6) @@ -14,7 +14,7 @@ ---- R*R^{-1} == 1 mod M ---- ---- R = 2^word_length mod M ---- ---- and word_length is the binary width of the ---- ----- operated word (in this case 64 bit) ---- +---- operated word (in this case 32, 64 or 512 bit) ---- ---- To Do: ---- ---- ---- ---- Author(s): ---- @@ -23,7 +23,7 @@ ---- ---- ----------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2014 Authors and OPENCORES.ORG ---- +---- Copyright (C) 2019 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- Index: trunk/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/sim/rtl_sim/bin/Makefile (revision 5) +++ trunk/sim/rtl_sim/bin/Makefile (revision 6) @@ -4,10 +4,10 @@ PLATFORM=xc3s500e-fg320-5 -XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" -FUSE=$(XILINX_DIR)"unwrapped/fuse.exe" +XILINX_DIR="c:/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" +FUSE=$(XILINX_DIR)"fuse.exe" VHPCOMP=$(XILINX_DIR)"vhpcomp.exe" -PATH=${XILINX}/bin/${SYSOP}:/cygdrive/D/Programy/Xilinx/14.2/ISE_DS/ISE/sysgen/bin/nt64/:/cygdrive/D/Programy/Xilinx/14.2/ISE_DS/ISE/lib/nt64/ +PATH=${XILINX}/bin/${SYSOP}:/cygdrive/C/Xilinx/14.2/ISE_DS/ISE/sysgen/bin/nt64/:/cygdrive/C/Xilinx/14.2/ISE_DS/ISE/lib/nt64/ clean: $(RM) ./isim @@ -20,7 +20,7 @@ exports: export DISPLAY=:0 - export XILINX=D:/Programy/Xilinx/14.2/ISE_DS/ISE + export XILINX=C:/Xilinx/14.2/ISE_DS/ISE export SYSOP=nt64 export PATH=${XILINX}/bin/${SYSOP} export LD_LIBRARY_PATH=${XILINX}/lib/${SYSOP} @@ -64,3 +64,17 @@ run_ModExp512: exports ModExp512 "./ModExp512bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModExp512bitTB_isim_beh.wdb" + +ModExpComm512bitTB: exports + $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ModExpComm512bitTB_stx_beh.prj + $(FUSE) -intstyle ise -incremental -o ModExpComm512bitTB_isim_beh.exe -prj ./ModExpComm512bitTB_beh.prj work.ModExpComm512bitTB + +run_ModExpComm512bitTB: exports ModExpComm512bitTB + "./ModExpComm512bitTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ModExpComm512bitTB_isim_beh.wdb" + +ShiftRegTB: exports + $(VHPCOMP) -work isim_temp -intstyle ise -prj ./ShiftRegTB_stx_beh.prj + $(FUSE) -intstyle ise -incremental -o ShiftRegTB_isim_beh.exe -prj ./ShiftRegTB_beh.prj work.ShiftRegTB + +run_ShiftRegTB: exports ShiftRegTB + "./ShiftRegTB_isim_beh.exe" -intstyle ise -tclbatch isim.cmd -wdb "./ShiftRegTB_isim_beh.wdb" \ No newline at end of file
/trunk/sim/rtl_sim/bin/ModExpComm512bitTB_beh.prj
0,0 → 1,17
vhdl work "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd"
vhdl work "../../../rtl/vhdl/commons/properties.vhd"
vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"
vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"
vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"
vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"
vhdl work "../../../rtl/vhdl/commons/Reg.vhd"
vhdl work "../../../rtl/vhdl/commons/counter.vhd"
vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"
vhdl work "../../../rtl/vhdl/communication/ModExpDataCtrlSM.vhd"
vhdl work "../../../rtl/vhdl/commons/ShiftReg.vhd"
vhdl work "../../../rtl/vhdl/commons/RS232RefComp.vhd"
vhdl work "../../../rtl/vhdl/commons/dcms.vhd"
vhdl work "../../../rtl/vhdl/commons/AsyncMux.vhd"
vhdl work "../../../rtl/vhdl/communication/ModExpComm.vhd"
vhdl work "../../../bench/vhdl/commons/txt_util.vhd"
vhdl work "../../../bench/vhdl/communication/ModExpComm512bitTB.vhd"
/trunk/sim/rtl_sim/bin/ModExpComm512bitTB_stx_beh.prj
0,0 → 1,17
vhdl isim_temp "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/properties.vhd"
vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/MontMult4inMux.vhd"
vhdl isim_temp "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"
vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/Reg.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/counter.vhd"
vhdl isim_temp "../../../rtl/vhdl/mod_exp/ModExp.vhd"
vhdl isim_temp "../../../rtl/vhdl/communication/ModExpDataCtrlSM.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/ShiftReg.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/RS232RefComp.vhd"
vhdl work "../../../rtl/vhdl/commons/dcms.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/AsyncMux.vhd"
vhdl isim_temp "../../../rtl/vhdl/communication/ModExpComm.vhd"
vhdl isim_temp "../../../bench/vhdl/commons/txt_util.vhd"
vhdl isim_temp "../../../bench/vhdl/communication/ModExpComm512bitTB.vhd"
/trunk/sim/rtl_sim/bin/ShiftRegTB_beh.prj
0,0 → 1,3
vhdl work "../../../rtl/vhdl/commons/properties.vhd"
vhdl work "../../../rtl/vhdl/commons/ShiftReg.vhd"
vhdl work "../../../bench/vhdl/commons/ShiftRegTB.vhd"
/trunk/sim/rtl_sim/bin/ShiftRegTB_stx_beh.prj
0,0 → 1,3
vhdl isim_temp "../../../rtl/vhdl/commons/properties.vhd"
vhdl isim_temp "../../../rtl/vhdl/commons/ShiftReg.vhd"
vhdl isim_temp "../../../bench/vhdl/commons/ShiftRegTB.vhd"
/trunk/sim/rtl_sim/bin/testData512bit/Base.txt
0,0 → 1,640
10101000
 
 
 
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1
 
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1
 
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1
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1
 
1
 
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1
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1
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1
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1
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1
 
 
 
 
 
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1
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10101000
 
 
 
1
 
1
 
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1
1
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11101111
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1
1
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01001110
 
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1
 
 
1
 
1
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1
 
1
1
1
 
1
 
10000011
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1
 
 
 
 
 
1
 
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1
 
 
 
1
 
1
 
10011010
 
1
 
1
1
 
 
1
1
10110010
 
1
 
 
1
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1
1
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1
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11111000
 
 
 
1
1
1
1
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10010011
1
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1
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10101010
 
1
 
1
 
1
 
1
1
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1
 
 
 
 
1
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1
 
1
 
 
1
 
 
 
10001010
 
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1
 
 
 
1
 
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1
 
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10111010
 
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1
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1
 
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10101010
 
1
 
1
 
1
 
1
1
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1
 
1
 
1
11100010
 
1
 
 
 
1
1
1
1
10111011
1
1
 
1
1
1
 
1
1
01011101
1
 
1
1
1
 
1
 
 
00011111
1
1
1
1
1
 
 
 
 
00100101
1
 
1
 
 
1
 
 
 
10101101
1
 
1
1
 
1
 
1
 
00100100
 
 
1
 
 
1
 
 
1
11010010
 
1
 
 
1
 
1
1
1
10100111
1
1
1
 
 
1
 
1
 
11000110
 
1
1
 
 
 
1
1
1
01101110
 
1
1
1
 
1
1
 
 
01101111
1
1
1
1
 
1
1
 
1
00010011
1
1
 
 
1
 
 
 
 
11110000
 
 
 
 
1
1
1
1
1
10000000
 
 
 
 
 
 
 
1
 
11100110
 
1
1
 
 
1
1
1
 
10100100
 
 
1
 
 
1
 
1
 
01000011
1
1
 
 
 
 
1
 
 
11001100
 
 
1
1
 
 
1
1
1
10000111
1
1
1
 
 
 
 
1
1
10010011
1
1
 
 
1
 
 
1
1
11010001
1
 
 
 
1
 
1
1
1
11001110
 
1
1
1
 
 
1
1
 
/trunk/sim/rtl_sim/bin/testData512bit/Exponent.txt
0,0 → 1,640
00010111
1
1
1
 
1
 
 
 
1
11011100
 
 
1
1
1
 
1
1
 
00000101
1
 
1
 
 
 
 
 
1
00010100
 
 
1
 
1
 
 
 
1
01000011
1
1
 
 
 
 
1
 
 
10000101
1
 
1
 
 
 
 
1
 
01111110
 
1
1
1
1
1
1
 
1
11111000
 
 
 
1
1
1
1
1
 
10011111
1
1
1
1
1
 
 
1
1
01101111
1
1
1
1
 
1
1
 
1
01010010
 
1
 
 
1
 
1
 
 
11110101
1
 
1
 
1
1
1
1
1
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1
 
 
1
1
 
1
 
1
00111010
 
1
 
1
1
1
 
 
1
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1
1
 
 
 
 
 
1
11110100
 
 
1
 
1
1
1
1
 
01110110
 
1
1
 
1
1
1
 
 
10111011
1
1
 
1
1
1
 
1
1
01000101
1
 
1
 
 
 
1
 
 
00111010
 
1
 
1
1
1
 
 
1
10101001
1
 
 
1
 
1
 
1
1
01101100
 
 
1
1
 
1
1
 
1
11000110
 
1
1
 
 
 
1
1
1
11111111
1
1
1
1
1
1
1
1
1
00001110
 
1
1
1
 
 
 
 
 
01010101
1
 
1
 
1
 
1
 
1
01011100
 
 
1
1
1
 
1
 
1
00110110
 
1
1
 
1
1
 
 
1
10111000
 
 
 
1
1
1
 
1
1
10010001
1
 
 
 
1
 
 
1
 
00011110
 
1
1
1
1
 
 
 
1
11101101
1
 
1
1
 
1
1
1
1
00111111
1
1
1
1
1
1
 
 
1
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1
1
 
 
 
1
01101100
 
 
1
1
 
1
1
 
1
10101111
1
1
1
1
 
1
 
1
1
00100111
1
1
1
 
 
1
 
 
1
10001010
 
1
 
1
 
 
 
1
 
11111101
1
 
1
1
1
1
1
1
 
11011101
1
 
1
1
1
 
1
1
1
01000100
 
 
1
 
 
 
1
 
1
10100100
 
 
1
 
 
1
 
1
 
10000011
1
1
 
 
 
 
 
1
 
00001010
 
1
 
1
 
 
 
 
1
00010111
1
1
1
 
1
 
 
 
1
10111011
1
1
 
1
1
1
 
1
1
11001001
1
 
 
1
 
 
1
1
1
11001000
 
 
 
1
 
 
1
1
 
01111010
 
1
 
1
1
1
1
 
 
10011101
1
 
1
1
1
 
 
1
 
10010001
1
 
 
 
1
 
 
1
 
00101001
1
 
 
1
 
1
 
 
 
01010011
1
1
 
 
1
 
1
 
1
01010100
 
 
1
 
1
 
1
 
 
01010101
1
 
1
 
1
 
1
 
1
11011101
1
 
1
1
1
 
1
1
1
10001110
 
1
1
1
 
 
 
1
1
00000001
1
 
 
 
 
 
 
 
 
10110010
 
1
 
 
1
1
 
1
1
00111100
 
 
1
1
1
1
 
 
1
00010100
 
 
1
 
1
 
 
 
1
10001110
 
1
1
1
 
 
 
1
1
00111010
 
1
 
1
1
1
 
 
1
00010110
 
1
1
 
1
 
 
 
 
/trunk/sim/rtl_sim/bin/testData512bit/Modulus.txt
0,0 → 1,640
00001111
1
1
1
1
 
 
 
 
1
01001010
 
1
 
1
 
 
1
 
 
01011001
1
 
 
1
1
 
1
 
1
00101110
 
1
1
1
 
1
 
 
1
00101101
1
 
1
1
 
1
 
 
1
10011101
1
 
1
1
1
 
 
1
 
01101000
 
 
 
1
 
1
1
 
 
10000100
 
 
1
 
 
 
 
1
1
11011110
 
1
1
1
1
 
1
1
1
00110111
1
1
1
 
1
1
 
 
 
11011100
 
 
1
1
1
 
1
1
 
00010001
1
 
 
 
1
 
 
 
1
10100010
 
1
 
 
 
1
 
1
 
11010001
1
 
 
 
1
 
1
1
1
01000011
1
1
 
 
 
 
1
 
 
10010101
1
 
1
 
1
 
 
1
1
01000011
1
1
 
 
 
 
1
 
 
10001000
 
 
 
1
 
 
 
1
1
11001001
1
 
 
1
 
 
1
1
1
01000111
1
1
1
 
 
 
1
 
1
10100000
 
 
 
 
 
1
 
1
1
10101000
 
 
 
1
 
1
 
1
 
01001111
1
1
1
1
 
 
1
 
 
11111100
 
 
1
1
1
1
1
1
1
00010100
 
 
1
 
1
 
 
 
1
11010011
1
1
 
 
1
 
1
1
 
01110001
1
 
 
 
1
1
1
 
1
10011011
1
1
 
1
1
 
 
1
 
10100111
1
1
1
 
 
1
 
1
 
11010001
1
 
 
 
1
 
1
1
1
01010001
1
 
 
 
1
 
1
 
 
10111100
 
 
1
1
1
1
 
1
 
11000001
1
 
 
 
 
 
1
1
 
10000111
1
1
1
 
 
 
 
1
1
10011010
 
1
 
1
1
 
 
1
1
01001000
 
 
 
1
 
 
1
 
1
11101011
1
1
 
1
 
1
1
1
1
10111000
 
 
 
1
1
1
 
1
1
01001110
 
1
1
1
 
 
1
 
1
01110111
1
1
1
 
1
1
1
 
1
01101000
 
 
 
1
 
1
1
 
 
11011000
 
 
 
1
1
 
1
1
1
00011110
 
1
1
1
1
 
 
 
1
01110000
 
 
 
 
1
1
1
 
 
11110111
1
1
1
 
1
1
1
1
 
10110000
 
 
 
 
1
1
 
1
 
10001101
1
 
1
1
 
 
 
1
1
10101011
1
1
 
1
 
1
 
1
 
01011010
 
1
 
1
1
 
1
 
1
10000101
1
 
1
 
 
 
 
1
 
10101000
 
 
 
1
 
1
 
1
 
10100101
1
 
1
 
 
1
 
1
1
01100111
1
1
1
 
 
1
1
 
 
10101001
1
 
 
1
 
1
 
1
1
01101111
1
1
1
1
 
1
1
 
1
01010010
 
1
 
 
1
 
1
 
 
00000111
1
1
1
 
 
 
 
 
 
01000000
 
 
 
 
 
 
1
 
 
11110101
1
 
1
 
1
1
1
1
1
01001011
1
1
 
1
 
 
1
 
1
00111101
1
 
1
1
1
1
 
 
 
00110010
 
1
 
 
1
1
 
 
 
00111011
1
1
 
1
1
1
 
 
 
11011110
 
1
1
1
1
 
1
1
1
/trunk/sim/rtl_sim/bin/testData512bit/Residuum.txt
0,0 → 1,640
00111100
 
 
1
1
1
1
 
 
1
01011001
1
 
 
1
1
 
1
 
1
11011010
 
1
 
1
1
 
1
1
 
00010101
1
 
1
 
1
 
 
 
 
10110100
 
 
1
 
1
1
 
1
1
01000011
1
1
 
 
 
 
1
 
 
01101010
 
1
 
1
 
1
1
 
1
11110101
1
 
1
 
1
1
1
1
1
00000111
1
1
1
 
 
 
 
 
 
01010010
 
1
 
 
1
 
1
 
 
11100001
1
 
 
 
 
1
1
1
1
11110001
1
 
 
 
1
1
1
1
 
10100001
1
 
 
 
 
1
 
1
 
01111011
1
1
 
1
1
1
1
 
1
10011010
 
1
 
1
1
 
 
1
1
00101001
1
 
 
1
 
1
 
 
 
11110000
 
 
 
 
1
1
1
1
1
00010000
 
 
 
 
1
 
 
 
 
10100111
1
1
1
 
 
1
 
1
 
10010001
1
 
 
 
1
 
 
1
 
11010011
1
1
 
 
1
 
1
1
 
00011000
 
 
 
1
1
 
 
 
1
00001011
1
1
 
1
 
 
 
 
 
00110101
1
 
1
 
1
1
 
 
1
10011111
1
1
1
1
1
 
 
1
1
11101110
 
1
1
1
 
1
1
1
1
00110001
1
 
 
 
1
1
 
 
 
00101001
1
 
 
1
 
1
 
 
 
11001100
 
 
1
1
 
 
1
1
1
11010100
 
 
1
 
1
 
1
1
1
10010000
 
 
 
 
1
 
 
1
1
11011101
1
 
1
1
1
 
1
1
1
10011010
 
1
 
1
1
 
 
1
1
11100110
 
1
1
 
 
1
1
1
 
01100000
 
 
 
 
 
1
1
 
1
11010011
1
1
 
 
1
 
1
1
 
01011101
1
 
1
1
1
 
1
 
 
10001001
1
 
 
1
 
 
 
1
 
11001011
1
1
 
1
 
 
1
1
 
00011100
 
 
1
1
1
 
 
 
 
10001000
 
 
 
1
 
 
 
1
1
01000010
 
1
 
 
 
 
1
 
1
00001100
 
 
1
1
 
 
 
 
1
11101000
 
 
 
1
 
1
1
1
1
10000000
 
 
 
 
 
 
 
1
 
00000100
 
 
1
 
 
 
 
 
 
11101111
1
1
1
1
 
1
1
1
 
10111011
1
1
 
1
1
1
 
1
1
10101010
 
1
 
1
 
1
 
1
1
10010100
 
 
1
 
1
 
 
1
 
11100000
 
 
 
 
 
1
1
1
 
00110110
 
1
1
 
1
1
 
 
1
10101101
1
 
1
1
 
1
 
1
 
00010010
 
1
 
 
1
 
 
 
1
01111010
 
1
 
1
1
1
1
 
 
10100111
1
1
1
 
 
1
 
1
 
11101101
1
 
1
1
 
1
1
1
1
00110110
 
1
1
 
1
1
 
 
1
10101100
 
 
1
1
 
1
 
1
1
10001110
 
1
1
1
 
 
 
1
1
01010001
1
 
 
 
1
 
1
 
 
01101111
1
1
1
1
 
1
1
 
1
10100110
 
1
1
 
 
1
 
1
1
00100000
 
 
 
 
 
1
 
 
 
/trunk/sim/rtl_sim/bin/testData512bit/Result.txt
0,0 → 1,21
Generated result file:
Base:
10831972010009692284864743082963908985928244572237504978567815597954452424901701848115907348099319027887255346705501542390228546770547307022309796259930536 in decimal
ced19387cc43a4e680f0136f6ec6a7d224ad251f5dbbe250aa3b7eba158a25c2aa934ff8f2b29aa283ba4eeff1a8310b77234abdda72ae7156c054c2b7e1a1a8 in hex
 
Modulus:
11639194216848075599002265489360912001411488135138961225285267565441921553320210324625995654671521634712013831000392536053201786146999373798311679376312847 in decimal
de3b323d4bf54007526fa967a5a8855aab8db0f7701ed868774eb8eb489a87c1bc51d1a79b71d314fc4fa8a047c988439543d1a211dc37de84689d2d2e594a0f in hex
 
Exponent:
1164213079911476522452523716613118512153792329806743382289257300977572318091588414675225325908322428116294194315992613761814533537627230020523566408522775 in decimal
163a8e143cb2018edd55545329919d7ac8c9bb170a83a444ddfd8a27af6c183fed1e91b8365c550effc66ca93a45bb76f4063a59f5526f9ff87e85431405dc17 in hex
 
Residuum:
1710026381007983649390259627245755642172838934666512596966326197048317423109472713444486555154343967450576033188072022772979735585191761951832684734601532 in decimal
20a66f518eac36eda77a12ad36e094aabbef0480e80c42881ccb895dd360e69add90d4cc2931ee9f350b18d391a710f0299a7ba1f1e15207f56a43b415da593c in hex
 
Expected result:
10215434590127773452736997130423262496733403688918174389107454937571941952783927288073293172190106158494574006191363817891568897784169824931779958064171842 in decimal
c30c01107478845324720b6a680fa53034b26a2bc58fceb3b8de8edb00abe2c17557cc9865fdbc1b9fc7700daa41c63c8480235342dba66d9601f1141abe4b42 in hex
 
/trunk/sim/rtl_sim/bin/testData512bit
trunk/sim/rtl_sim/bin/testData512bit Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/syn/XC3ES500/mod_exp/Makefile =================================================================== --- trunk/syn/XC3ES500/mod_exp/Makefile (revision 5) +++ trunk/syn/XC3ES500/mod_exp/Makefile (revision 6) @@ -5,7 +5,7 @@ PLATFORM=xc3s500e-fg320-5 -XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" +XILINX_DIR="c:/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" XST_DIR=$(XILINX_DIR)"xst.exe" NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe" MAP=$(XILINX_DIR)"map.exe"
/trunk/syn/XC3ES500/mod_exp_comm/Makefile
0,0 → 1,57
PROJECT=mont-mult
 
RM=/bin/rm -rf
 
PLATFORM=xc3s500e-fg320-5
UCF="../../../rtl/vhdl/communication/ModExpDataCtrlUCF.ucf"
 
XILINX_DIR="c:/Xilinx/14.2/ISE_DS/ISE/bin/nt64/"
XST_DIR=$(XILINX_DIR)"xst.exe"
NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe"
MAP=$(XILINX_DIR)"map.exe"
PAR=$(XILINX_DIR)"par.exe"
TRCE=$(XILINX_DIR)"trce.exe"
BITGEN=$(XILINX_DIR)"bitgen.exe"
 
clean: clean_postgen
$(RM) "./out/"*.*
$(RM) "./log/"*.*
$(RM) "./out/"
$(RM) "./log/"
 
clean_postgen:
$(RM) "./_xmsgs"
$(RM) "./_ngo"
$(RM) "./xlnx_auto_0_xdb"
$(RM) "./xst"
$(RM) *_vhdl.prj *.bgn *.bld *.csv *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.ngr *.pad *.par *.pcf *.ptwx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt
 
synthesize: clean
mkdir "./xst"
mkdir "./xst/projnav.tmp"
mkdir "./out/"
mkdir "./log/"
$(XST_DIR) -intstyle ise -ifn "./ModExpComm.xst" -ofn "./ModExpComm.syr"
 
translate: synthesize
$(NGDBUILD_DIR) -intstyle ise -dd _ngo -sd ../../../rtl/vhdl/mod_exp/blockMemory512 -nt timestamp -uc $(UCF) -p $(PLATFORM) "ModExpComm.ngc" ModExpComm.ngd
 
map: translate
$(MAP) -intstyle ise -p $(PLATFORM) -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o ModExpComm_map.ncd ModExpComm.ngd ModExpComm.pcf
 
par: map
$(PAR) -w -intstyle ise -pl high -rl high -xe n -t 1 ModExpComm_map.ncd ModExpComm.ncd ModExpComm.pcf
 
trce: par
$(TRCE) -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml ModExpComm.twx ModExpComm.ncd -o ModExpComm.twr ModExpComm.pcf
 
bitgen: trce
$(BITGEN) -intstyle ise -f ModExpComm.ut ModExpComm.ncd
 
postgen:
mv *.log ./log
mv *.xrpt ./log
mv *.txt ./log
mv *.xml ./log
mv *.html ./log
mv *.bit ./out
/trunk/syn/XC3ES500/mod_exp_comm/ModExpComm.prj
0,0 → 1,15
vhdl work "../../../rtl/vhdl/mod_exp/blockMemory512/blockMemory.vhd"
vhdl work "../../../rtl/vhdl/commons/properties.vhd"
vhdl work "../../../rtl/vhdl/mod_mult/ModMultIter_SM.vhd"
vhdl work "../../../rtl/vhdl/commons/MontMult4inMux.vhd"
vhdl work "../../../rtl/vhdl/mod_mult/ModularMultiplierIterative.vhd"
vhdl work "../../../rtl/vhdl/mod_exp/ModExpSM.vhd"
vhdl work "../../../rtl/vhdl/commons/Reg.vhd"
vhdl work "../../../rtl/vhdl/commons/counter.vhd"
vhdl work "../../../rtl/vhdl/mod_exp/ModExp.vhd"
vhdl work "../../../rtl/vhdl/communication/ModExpDataCtrlSM.vhd"
vhdl work "../../../rtl/vhdl/commons/ShiftReg.vhd"
vhdl work "../../../rtl/vhdl/commons/RS232RefComp.vhd"
vhdl work "../../../rtl/vhdl/commons/dcms.vhd"
vhdl work "../../../rtl/vhdl/commons/AsyncMux.vhd"
vhdl work "../../../rtl/vhdl/communication/ModExpComm.vhd"
/trunk/syn/XC3ES500/mod_exp_comm/ModExpComm.ut
0,0 → 1,22
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:1
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutdown:Disable
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
/trunk/syn/XC3ES500/mod_exp_comm/ModExpComm.xst
0,0 → 1,59
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn ModExpComm.prj
-ifmt mixed
-ofn ModExpComm
-ofmt NGC
-p xc3s500e-5-fg320
-top ModExpComm
-opt_mode Speed
-opt_level 2
-iuc NO
-keep_hierarchy Soft
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"../../../rtl/vhdl/mod_exp/blockMemory512" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-mult_style Auto
-iobuf YES
-max_fanout 100000
-bufg 24
-register_duplication YES
-register_balancing Yes
-move_first_stage YES
-move_last_stage YES
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob True
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
/trunk/syn/XC3ES500/mod_exp_comm
trunk/syn/XC3ES500/mod_exp_comm Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/syn/XC3ES500/mod_mult/Makefile =================================================================== --- trunk/syn/XC3ES500/mod_mult/Makefile (revision 5) +++ trunk/syn/XC3ES500/mod_mult/Makefile (revision 6) @@ -4,7 +4,7 @@ PLATFORM=xc3s500e-fg320-5 -XILINX_DIR="D:/Programy/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" +XILINX_DIR="c:/Xilinx/14.2/ISE_DS/ISE/bin/nt64/" XST_DIR=$(XILINX_DIR)"xst.exe" NGDBUILD_DIR=$(XILINX_DIR)"ngdbuild.exe" MAP=$(XILINX_DIR)"map.exe"

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